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610626af AL |
1 | /* |
2 | * ioapic.c IOAPIC emulation logic | |
3 | * | |
4 | * Copyright (c) 2004-2005 Fabrice Bellard | |
5 | * | |
6 | * Split the ioapic logic from apic.c | |
7 | * Xiantao Zhang <xiantao.zhang@intel.com> | |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
610626af AL |
21 | */ |
22 | ||
23 | #include "hw.h" | |
24 | #include "pc.h" | |
aa28b9bf | 25 | #include "apic.h" |
0280b571 | 26 | #include "ioapic.h" |
610626af AL |
27 | #include "qemu-timer.h" |
28 | #include "host-utils.h" | |
96051119 | 29 | #include "sysbus.h" |
610626af AL |
30 | |
31 | //#define DEBUG_IOAPIC | |
32 | ||
9af9b330 BS |
33 | #ifdef DEBUG_IOAPIC |
34 | #define DPRINTF(fmt, ...) \ | |
35 | do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0) | |
36 | #else | |
37 | #define DPRINTF(fmt, ...) | |
38 | #endif | |
39 | ||
0280b571 JK |
40 | #define MAX_IOAPICS 1 |
41 | ||
1f5e71a8 | 42 | #define IOAPIC_VERSION 0x11 |
610626af | 43 | |
1f5e71a8 JK |
44 | #define IOAPIC_LVT_DEST_SHIFT 56 |
45 | #define IOAPIC_LVT_MASKED_SHIFT 16 | |
46 | #define IOAPIC_LVT_TRIGGER_MODE_SHIFT 15 | |
47 | #define IOAPIC_LVT_REMOTE_IRR_SHIFT 14 | |
48 | #define IOAPIC_LVT_POLARITY_SHIFT 13 | |
49 | #define IOAPIC_LVT_DELIV_STATUS_SHIFT 12 | |
50 | #define IOAPIC_LVT_DEST_MODE_SHIFT 11 | |
51 | #define IOAPIC_LVT_DELIV_MODE_SHIFT 8 | |
52 | ||
53 | #define IOAPIC_LVT_MASKED (1 << IOAPIC_LVT_MASKED_SHIFT) | |
54 | #define IOAPIC_LVT_REMOTE_IRR (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT) | |
55 | ||
56 | #define IOAPIC_TRIGGER_EDGE 0 | |
57 | #define IOAPIC_TRIGGER_LEVEL 1 | |
610626af AL |
58 | |
59 | /*io{apic,sapic} delivery mode*/ | |
1f5e71a8 JK |
60 | #define IOAPIC_DM_FIXED 0x0 |
61 | #define IOAPIC_DM_LOWEST_PRIORITY 0x1 | |
62 | #define IOAPIC_DM_PMI 0x2 | |
63 | #define IOAPIC_DM_NMI 0x4 | |
64 | #define IOAPIC_DM_INIT 0x5 | |
65 | #define IOAPIC_DM_SIPI 0x6 | |
66 | #define IOAPIC_DM_EXTINT 0x7 | |
67 | #define IOAPIC_DM_MASK 0x7 | |
68 | ||
69 | #define IOAPIC_VECTOR_MASK 0xff | |
70 | ||
71 | #define IOAPIC_IOREGSEL 0x00 | |
72 | #define IOAPIC_IOWIN 0x10 | |
73 | ||
74 | #define IOAPIC_REG_ID 0x00 | |
75 | #define IOAPIC_REG_VER 0x01 | |
76 | #define IOAPIC_REG_ARB 0x02 | |
77 | #define IOAPIC_REG_REDTBL_BASE 0x10 | |
78 | #define IOAPIC_ID 0x00 | |
79 | ||
80 | #define IOAPIC_ID_SHIFT 24 | |
81 | #define IOAPIC_ID_MASK 0xf | |
82 | ||
83 | #define IOAPIC_VER_ENTRIES_SHIFT 16 | |
610626af | 84 | |
96051119 BS |
85 | typedef struct IOAPICState IOAPICState; |
86 | ||
610626af | 87 | struct IOAPICState { |
96051119 | 88 | SysBusDevice busdev; |
610626af AL |
89 | uint8_t id; |
90 | uint8_t ioregsel; | |
610626af AL |
91 | uint32_t irr; |
92 | uint64_t ioredtbl[IOAPIC_NUM_PINS]; | |
93 | }; | |
94 | ||
0280b571 JK |
95 | static IOAPICState *ioapics[MAX_IOAPICS]; |
96 | ||
610626af AL |
97 | static void ioapic_service(IOAPICState *s) |
98 | { | |
99 | uint8_t i; | |
100 | uint8_t trig_mode; | |
101 | uint8_t vector; | |
102 | uint8_t delivery_mode; | |
103 | uint32_t mask; | |
104 | uint64_t entry; | |
105 | uint8_t dest; | |
106 | uint8_t dest_mode; | |
107 | uint8_t polarity; | |
108 | ||
109 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
110 | mask = 1 << i; | |
111 | if (s->irr & mask) { | |
112 | entry = s->ioredtbl[i]; | |
113 | if (!(entry & IOAPIC_LVT_MASKED)) { | |
1f5e71a8 JK |
114 | trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1); |
115 | dest = entry >> IOAPIC_LVT_DEST_SHIFT; | |
116 | dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; | |
117 | delivery_mode = | |
118 | (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK; | |
119 | polarity = (entry >> IOAPIC_LVT_POLARITY_SHIFT) & 1; | |
0280b571 | 120 | if (trig_mode == IOAPIC_TRIGGER_EDGE) { |
610626af | 121 | s->irr &= ~mask; |
0280b571 JK |
122 | } else { |
123 | s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR; | |
124 | } | |
1f5e71a8 | 125 | if (delivery_mode == IOAPIC_DM_EXTINT) { |
610626af | 126 | vector = pic_read_irq(isa_pic); |
1f5e71a8 JK |
127 | } else { |
128 | vector = entry & IOAPIC_VECTOR_MASK; | |
129 | } | |
610626af AL |
130 | apic_deliver_irq(dest, dest_mode, delivery_mode, |
131 | vector, polarity, trig_mode); | |
132 | } | |
133 | } | |
134 | } | |
135 | } | |
136 | ||
7d0500c4 | 137 | static void ioapic_set_irq(void *opaque, int vector, int level) |
610626af AL |
138 | { |
139 | IOAPICState *s = opaque; | |
140 | ||
141 | /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps | |
142 | * to GSI 2. GSI maps to ioapic 1-1. This is not | |
143 | * the cleanest way of doing it but it should work. */ | |
144 | ||
1f5e71a8 JK |
145 | DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector); |
146 | if (vector == 0) { | |
610626af | 147 | vector = 2; |
1f5e71a8 | 148 | } |
610626af AL |
149 | if (vector >= 0 && vector < IOAPIC_NUM_PINS) { |
150 | uint32_t mask = 1 << vector; | |
151 | uint64_t entry = s->ioredtbl[vector]; | |
152 | ||
1f5e71a8 JK |
153 | if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) == |
154 | IOAPIC_TRIGGER_LEVEL) { | |
610626af AL |
155 | /* level triggered */ |
156 | if (level) { | |
157 | s->irr |= mask; | |
158 | ioapic_service(s); | |
159 | } else { | |
160 | s->irr &= ~mask; | |
161 | } | |
162 | } else { | |
163 | /* edge triggered */ | |
164 | if (level) { | |
165 | s->irr |= mask; | |
166 | ioapic_service(s); | |
167 | } | |
168 | } | |
169 | } | |
170 | } | |
171 | ||
0280b571 JK |
172 | void ioapic_eoi_broadcast(int vector) |
173 | { | |
174 | IOAPICState *s; | |
175 | uint64_t entry; | |
176 | int i, n; | |
177 | ||
178 | for (i = 0; i < MAX_IOAPICS; i++) { | |
179 | s = ioapics[i]; | |
180 | if (!s) { | |
181 | continue; | |
182 | } | |
183 | for (n = 0; n < IOAPIC_NUM_PINS; n++) { | |
184 | entry = s->ioredtbl[n]; | |
1f5e71a8 JK |
185 | if ((entry & IOAPIC_LVT_REMOTE_IRR) |
186 | && (entry & IOAPIC_VECTOR_MASK) == vector) { | |
0280b571 JK |
187 | s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR; |
188 | if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) { | |
189 | ioapic_service(s); | |
190 | } | |
191 | } | |
192 | } | |
193 | } | |
194 | } | |
195 | ||
c227f099 | 196 | static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr) |
610626af AL |
197 | { |
198 | IOAPICState *s = opaque; | |
199 | int index; | |
200 | uint32_t val = 0; | |
201 | ||
1f5e71a8 JK |
202 | switch (addr & 0xff) { |
203 | case IOAPIC_IOREGSEL: | |
610626af | 204 | val = s->ioregsel; |
1f5e71a8 JK |
205 | break; |
206 | case IOAPIC_IOWIN: | |
610626af | 207 | switch (s->ioregsel) { |
1f5e71a8 JK |
208 | case IOAPIC_REG_ID: |
209 | val = s->id << IOAPIC_ID_SHIFT; | |
210 | break; | |
211 | case IOAPIC_REG_VER: | |
212 | val = IOAPIC_VERSION | | |
213 | ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT); | |
214 | break; | |
215 | case IOAPIC_REG_ARB: | |
216 | val = 0; | |
217 | break; | |
218 | default: | |
219 | index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; | |
220 | if (index >= 0 && index < IOAPIC_NUM_PINS) { | |
221 | if (s->ioregsel & 1) { | |
222 | val = s->ioredtbl[index] >> 32; | |
223 | } else { | |
224 | val = s->ioredtbl[index] & 0xffffffff; | |
610626af | 225 | } |
1f5e71a8 | 226 | } |
610626af | 227 | } |
9af9b330 | 228 | DPRINTF("read: %08x = %08x\n", s->ioregsel, val); |
1f5e71a8 | 229 | break; |
610626af AL |
230 | } |
231 | return val; | |
232 | } | |
233 | ||
1f5e71a8 JK |
234 | static void |
235 | ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) | |
610626af AL |
236 | { |
237 | IOAPICState *s = opaque; | |
238 | int index; | |
239 | ||
1f5e71a8 JK |
240 | switch (addr & 0xff) { |
241 | case IOAPIC_IOREGSEL: | |
610626af | 242 | s->ioregsel = val; |
1f5e71a8 JK |
243 | break; |
244 | case IOAPIC_IOWIN: | |
9af9b330 | 245 | DPRINTF("write: %08x = %08x\n", s->ioregsel, val); |
610626af | 246 | switch (s->ioregsel) { |
1f5e71a8 JK |
247 | case IOAPIC_REG_ID: |
248 | s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK; | |
249 | break; | |
250 | case IOAPIC_REG_VER: | |
251 | case IOAPIC_REG_ARB: | |
252 | break; | |
253 | default: | |
254 | index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; | |
255 | if (index >= 0 && index < IOAPIC_NUM_PINS) { | |
256 | if (s->ioregsel & 1) { | |
257 | s->ioredtbl[index] &= 0xffffffff; | |
258 | s->ioredtbl[index] |= (uint64_t)val << 32; | |
259 | } else { | |
260 | s->ioredtbl[index] &= ~0xffffffffULL; | |
261 | s->ioredtbl[index] |= val; | |
610626af | 262 | } |
1f5e71a8 JK |
263 | ioapic_service(s); |
264 | } | |
610626af | 265 | } |
1f5e71a8 | 266 | break; |
610626af AL |
267 | } |
268 | } | |
269 | ||
35a74c5c JK |
270 | static int ioapic_post_load(void *opaque, int version_id) |
271 | { | |
272 | IOAPICState *s = opaque; | |
273 | ||
274 | if (version_id == 1) { | |
275 | /* set sane value */ | |
276 | s->irr = 0; | |
277 | } | |
278 | return 0; | |
279 | } | |
280 | ||
3e9e9888 JQ |
281 | static const VMStateDescription vmstate_ioapic = { |
282 | .name = "ioapic", | |
5dce4999 | 283 | .version_id = 3, |
35a74c5c | 284 | .post_load = ioapic_post_load, |
3e9e9888 JQ |
285 | .minimum_version_id = 1, |
286 | .minimum_version_id_old = 1, | |
1f5e71a8 | 287 | .fields = (VMStateField[]) { |
3e9e9888 JQ |
288 | VMSTATE_UINT8(id, IOAPICState), |
289 | VMSTATE_UINT8(ioregsel, IOAPICState), | |
5dce4999 | 290 | VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */ |
35a74c5c | 291 | VMSTATE_UINT32_V(irr, IOAPICState, 2), |
3e9e9888 JQ |
292 | VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS), |
293 | VMSTATE_END_OF_LIST() | |
610626af | 294 | } |
3e9e9888 | 295 | }; |
610626af | 296 | |
96051119 | 297 | static void ioapic_reset(DeviceState *d) |
610626af | 298 | { |
96051119 | 299 | IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d); |
610626af AL |
300 | int i; |
301 | ||
96051119 BS |
302 | s->id = 0; |
303 | s->ioregsel = 0; | |
304 | s->irr = 0; | |
1f5e71a8 JK |
305 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
306 | s->ioredtbl[i] = 1 << IOAPIC_LVT_MASKED_SHIFT; | |
307 | } | |
610626af AL |
308 | } |
309 | ||
d60efc6b | 310 | static CPUReadMemoryFunc * const ioapic_mem_read[3] = { |
610626af AL |
311 | ioapic_mem_readl, |
312 | ioapic_mem_readl, | |
313 | ioapic_mem_readl, | |
314 | }; | |
315 | ||
d60efc6b | 316 | static CPUWriteMemoryFunc * const ioapic_mem_write[3] = { |
610626af AL |
317 | ioapic_mem_writel, |
318 | ioapic_mem_writel, | |
319 | ioapic_mem_writel, | |
320 | }; | |
321 | ||
96051119 | 322 | static int ioapic_init1(SysBusDevice *dev) |
610626af | 323 | { |
96051119 | 324 | IOAPICState *s = FROM_SYSBUS(IOAPICState, dev); |
610626af | 325 | int io_memory; |
0280b571 JK |
326 | static int ioapic_no; |
327 | ||
328 | if (ioapic_no >= MAX_IOAPICS) { | |
329 | return -1; | |
330 | } | |
610626af | 331 | |
1eed09cb | 332 | io_memory = cpu_register_io_memory(ioapic_mem_read, |
2507c12a AG |
333 | ioapic_mem_write, s, |
334 | DEVICE_NATIVE_ENDIAN); | |
96051119 | 335 | sysbus_init_mmio(dev, 0x1000, io_memory); |
610626af | 336 | |
96051119 | 337 | qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS); |
610626af | 338 | |
0280b571 JK |
339 | ioapics[ioapic_no++] = s; |
340 | ||
96051119 | 341 | return 0; |
610626af | 342 | } |
96051119 BS |
343 | |
344 | static SysBusDeviceInfo ioapic_info = { | |
345 | .init = ioapic_init1, | |
346 | .qdev.name = "ioapic", | |
347 | .qdev.size = sizeof(IOAPICState), | |
348 | .qdev.vmsd = &vmstate_ioapic, | |
349 | .qdev.reset = ioapic_reset, | |
350 | .qdev.no_user = 1, | |
351 | }; | |
352 | ||
353 | static void ioapic_register_devices(void) | |
354 | { | |
355 | sysbus_register_withprop(&ioapic_info); | |
356 | } | |
357 | ||
358 | device_init(ioapic_register_devices) |