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610626af AL |
1 | /* |
2 | * ioapic.c IOAPIC emulation logic | |
3 | * | |
4 | * Copyright (c) 2004-2005 Fabrice Bellard | |
5 | * | |
6 | * Split the ioapic logic from apic.c | |
7 | * Xiantao Zhang <xiantao.zhang@intel.com> | |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
610626af AL |
21 | */ |
22 | ||
23 | #include "hw.h" | |
24 | #include "pc.h" | |
aa28b9bf | 25 | #include "apic.h" |
610626af AL |
26 | #include "qemu-timer.h" |
27 | #include "host-utils.h" | |
28 | ||
29 | //#define DEBUG_IOAPIC | |
30 | ||
9af9b330 BS |
31 | #ifdef DEBUG_IOAPIC |
32 | #define DPRINTF(fmt, ...) \ | |
33 | do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0) | |
34 | #else | |
35 | #define DPRINTF(fmt, ...) | |
36 | #endif | |
37 | ||
610626af AL |
38 | #define IOAPIC_NUM_PINS 0x18 |
39 | #define IOAPIC_LVT_MASKED (1<<16) | |
40 | ||
41 | #define IOAPIC_TRIGGER_EDGE 0 | |
42 | #define IOAPIC_TRIGGER_LEVEL 1 | |
43 | ||
44 | /*io{apic,sapic} delivery mode*/ | |
45 | #define IOAPIC_DM_FIXED 0x0 | |
46 | #define IOAPIC_DM_LOWEST_PRIORITY 0x1 | |
47 | #define IOAPIC_DM_PMI 0x2 | |
48 | #define IOAPIC_DM_NMI 0x4 | |
49 | #define IOAPIC_DM_INIT 0x5 | |
50 | #define IOAPIC_DM_SIPI 0x5 | |
51 | #define IOAPIC_DM_EXTINT 0x7 | |
52 | ||
53 | struct IOAPICState { | |
54 | uint8_t id; | |
55 | uint8_t ioregsel; | |
56 | ||
57 | uint32_t irr; | |
58 | uint64_t ioredtbl[IOAPIC_NUM_PINS]; | |
59 | }; | |
60 | ||
61 | static void ioapic_service(IOAPICState *s) | |
62 | { | |
63 | uint8_t i; | |
64 | uint8_t trig_mode; | |
65 | uint8_t vector; | |
66 | uint8_t delivery_mode; | |
67 | uint32_t mask; | |
68 | uint64_t entry; | |
69 | uint8_t dest; | |
70 | uint8_t dest_mode; | |
71 | uint8_t polarity; | |
72 | ||
73 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
74 | mask = 1 << i; | |
75 | if (s->irr & mask) { | |
76 | entry = s->ioredtbl[i]; | |
77 | if (!(entry & IOAPIC_LVT_MASKED)) { | |
78 | trig_mode = ((entry >> 15) & 1); | |
79 | dest = entry >> 56; | |
80 | dest_mode = (entry >> 11) & 1; | |
81 | delivery_mode = (entry >> 8) & 7; | |
82 | polarity = (entry >> 13) & 1; | |
83 | if (trig_mode == IOAPIC_TRIGGER_EDGE) | |
84 | s->irr &= ~mask; | |
85 | if (delivery_mode == IOAPIC_DM_EXTINT) | |
86 | vector = pic_read_irq(isa_pic); | |
87 | else | |
88 | vector = entry & 0xff; | |
89 | ||
90 | apic_deliver_irq(dest, dest_mode, delivery_mode, | |
91 | vector, polarity, trig_mode); | |
92 | } | |
93 | } | |
94 | } | |
95 | } | |
96 | ||
7d0500c4 | 97 | static void ioapic_set_irq(void *opaque, int vector, int level) |
610626af AL |
98 | { |
99 | IOAPICState *s = opaque; | |
100 | ||
101 | /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps | |
102 | * to GSI 2. GSI maps to ioapic 1-1. This is not | |
103 | * the cleanest way of doing it but it should work. */ | |
104 | ||
9af9b330 | 105 | DPRINTF("%s: %s vec %x\n", __func__, level? "raise" : "lower", vector); |
610626af AL |
106 | if (vector == 0) |
107 | vector = 2; | |
108 | ||
109 | if (vector >= 0 && vector < IOAPIC_NUM_PINS) { | |
110 | uint32_t mask = 1 << vector; | |
111 | uint64_t entry = s->ioredtbl[vector]; | |
112 | ||
113 | if ((entry >> 15) & 1) { | |
114 | /* level triggered */ | |
115 | if (level) { | |
116 | s->irr |= mask; | |
117 | ioapic_service(s); | |
118 | } else { | |
119 | s->irr &= ~mask; | |
120 | } | |
121 | } else { | |
122 | /* edge triggered */ | |
123 | if (level) { | |
124 | s->irr |= mask; | |
125 | ioapic_service(s); | |
126 | } | |
127 | } | |
128 | } | |
129 | } | |
130 | ||
c227f099 | 131 | static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr) |
610626af AL |
132 | { |
133 | IOAPICState *s = opaque; | |
134 | int index; | |
135 | uint32_t val = 0; | |
136 | ||
137 | addr &= 0xff; | |
138 | if (addr == 0x00) { | |
139 | val = s->ioregsel; | |
140 | } else if (addr == 0x10) { | |
141 | switch (s->ioregsel) { | |
142 | case 0x00: | |
143 | val = s->id << 24; | |
144 | break; | |
145 | case 0x01: | |
146 | val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */ | |
147 | break; | |
148 | case 0x02: | |
149 | val = 0; | |
150 | break; | |
151 | default: | |
152 | index = (s->ioregsel - 0x10) >> 1; | |
153 | if (index >= 0 && index < IOAPIC_NUM_PINS) { | |
154 | if (s->ioregsel & 1) | |
155 | val = s->ioredtbl[index] >> 32; | |
156 | else | |
157 | val = s->ioredtbl[index] & 0xffffffff; | |
158 | } | |
159 | } | |
9af9b330 | 160 | DPRINTF("read: %08x = %08x\n", s->ioregsel, val); |
610626af AL |
161 | } |
162 | return val; | |
163 | } | |
164 | ||
c227f099 | 165 | static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
610626af AL |
166 | { |
167 | IOAPICState *s = opaque; | |
168 | int index; | |
169 | ||
170 | addr &= 0xff; | |
171 | if (addr == 0x00) { | |
172 | s->ioregsel = val; | |
173 | return; | |
174 | } else if (addr == 0x10) { | |
9af9b330 | 175 | DPRINTF("write: %08x = %08x\n", s->ioregsel, val); |
610626af AL |
176 | switch (s->ioregsel) { |
177 | case 0x00: | |
178 | s->id = (val >> 24) & 0xff; | |
179 | return; | |
180 | case 0x01: | |
181 | case 0x02: | |
182 | return; | |
183 | default: | |
184 | index = (s->ioregsel - 0x10) >> 1; | |
185 | if (index >= 0 && index < IOAPIC_NUM_PINS) { | |
186 | if (s->ioregsel & 1) { | |
187 | s->ioredtbl[index] &= 0xffffffff; | |
188 | s->ioredtbl[index] |= (uint64_t)val << 32; | |
189 | } else { | |
190 | s->ioredtbl[index] &= ~0xffffffffULL; | |
191 | s->ioredtbl[index] |= val; | |
192 | } | |
193 | ioapic_service(s); | |
194 | } | |
195 | } | |
196 | } | |
197 | } | |
198 | ||
3e9e9888 JQ |
199 | static const VMStateDescription vmstate_ioapic = { |
200 | .name = "ioapic", | |
201 | .version_id = 1, | |
202 | .minimum_version_id = 1, | |
203 | .minimum_version_id_old = 1, | |
204 | .fields = (VMStateField []) { | |
205 | VMSTATE_UINT8(id, IOAPICState), | |
206 | VMSTATE_UINT8(ioregsel, IOAPICState), | |
207 | VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS), | |
208 | VMSTATE_END_OF_LIST() | |
610626af | 209 | } |
3e9e9888 | 210 | }; |
610626af AL |
211 | |
212 | static void ioapic_reset(void *opaque) | |
213 | { | |
214 | IOAPICState *s = opaque; | |
215 | int i; | |
216 | ||
217 | memset(s, 0, sizeof(*s)); | |
218 | for(i = 0; i < IOAPIC_NUM_PINS; i++) | |
219 | s->ioredtbl[i] = 1 << 16; /* mask LVT */ | |
220 | } | |
221 | ||
d60efc6b | 222 | static CPUReadMemoryFunc * const ioapic_mem_read[3] = { |
610626af AL |
223 | ioapic_mem_readl, |
224 | ioapic_mem_readl, | |
225 | ioapic_mem_readl, | |
226 | }; | |
227 | ||
d60efc6b | 228 | static CPUWriteMemoryFunc * const ioapic_mem_write[3] = { |
610626af AL |
229 | ioapic_mem_writel, |
230 | ioapic_mem_writel, | |
231 | ioapic_mem_writel, | |
232 | }; | |
233 | ||
1632dc6a | 234 | qemu_irq *ioapic_init(void) |
610626af AL |
235 | { |
236 | IOAPICState *s; | |
1632dc6a | 237 | qemu_irq *irq; |
610626af AL |
238 | int io_memory; |
239 | ||
240 | s = qemu_mallocz(sizeof(IOAPICState)); | |
241 | ioapic_reset(s); | |
242 | ||
1eed09cb | 243 | io_memory = cpu_register_io_memory(ioapic_mem_read, |
610626af AL |
244 | ioapic_mem_write, s); |
245 | cpu_register_physical_memory(0xfec00000, 0x1000, io_memory); | |
246 | ||
3e9e9888 | 247 | vmstate_register(0, &vmstate_ioapic, s); |
a08d4367 | 248 | qemu_register_reset(ioapic_reset, s); |
1632dc6a | 249 | irq = qemu_allocate_irqs(ioapic_set_irq, s, IOAPIC_NUM_PINS); |
610626af | 250 | |
1632dc6a | 251 | return irq; |
610626af | 252 | } |