[qemu.git] / hw / iommu.c

/*
 * QEMU SPARC iommu emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sun4m.h"

/* debug iommu */
//#define DEBUG_IOMMU

#ifdef DEBUG_IOMMU
#define DPRINTF(fmt, ...)                                       \
    do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif

#define IOMMU_NREGS         (4*4096/4)
#define IOMMU_CTRL          (0x0000 >> 2)
#define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS     0x0f000000 /* Version */
#define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
#define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
#define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
#define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
#define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
#define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
#define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
#define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
#define IOMMU_CTRL_MASK     0x0000001d

#define IOMMU_BASE          (0x0004 >> 2)
#define IOMMU_BASE_MASK     0x07fffc00

#define IOMMU_TLBFLUSH      (0x0014 >> 2)
#define IOMMU_TLBFLUSH_MASK 0xffffffff

#define IOMMU_PGFLUSH       (0x0018 >> 2)
#define IOMMU_PGFLUSH_MASK  0xffffffff

#define IOMMU_AFSR          (0x1000 >> 2)
#define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
#define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
                                          transaction */
#define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
                                          12.8 us. */
#define IOMMU_AFSR_BE       0x10000000 /* Write access received error
                                          acknowledge */
#define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
#define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
                                          hardware */
#define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
#define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
#define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
#define IOMMU_AFSR_MASK     0xff0fffff

#define IOMMU_AFAR          (0x1004 >> 2)

#define IOMMU_AER           (0x1008 >> 2) /* Arbiter Enable Register */
#define IOMMU_AER_EN_P0_ARB 0x00000001    /* MBus master 0x8 (Always 1) */
#define IOMMU_AER_EN_P1_ARB 0x00000002    /* MBus master 0x9 */
#define IOMMU_AER_EN_P2_ARB 0x00000004    /* MBus master 0xa */
#define IOMMU_AER_EN_P3_ARB 0x00000008    /* MBus master 0xb */
#define IOMMU_AER_EN_0      0x00010000    /* SBus slot 0 */
#define IOMMU_AER_EN_1      0x00020000    /* SBus slot 1 */
#define IOMMU_AER_EN_2      0x00040000    /* SBus slot 2 */
#define IOMMU_AER_EN_3      0x00080000    /* SBus slot 3 */
#define IOMMU_AER_EN_F      0x00100000    /* SBus on-board */
#define IOMMU_AER_SBW       0x80000000    /* S-to-M asynchronous writes */
#define IOMMU_AER_MASK      0x801f000f

#define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
                                          bypass enabled */
#define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
                                          produced by this device as pure
                                          physical. */
#define IOMMU_SBCFG_MASK    0x00010003

#define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
#define IOMMU_ARBEN_MASK    0x001f0000
#define IOMMU_MID           0x00000008

#define IOMMU_MASK_ID       (0x3018 >> 2) /* Mask ID */
#define IOMMU_MASK_ID_MASK  0x00ffffff

#define IOMMU_MSII_MASK     0x26000000 /* microSPARC II mask number */
#define IOMMU_TS_MASK       0x23000000 /* turboSPARC mask number */

/* The format of an iopte in the page tables */
#define IOPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12]) */
#define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
                                          Viking/MXCC) */
#define IOPTE_WRITE         0x00000004 /* Writeable */
#define IOPTE_VALID         0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ           0x00000001 /* Write as zeros */

#define IOMMU_PAGE_SHIFT    12
#define IOMMU_PAGE_SIZE     (1 << IOMMU_PAGE_SHIFT)
#define IOMMU_PAGE_MASK     ~(IOMMU_PAGE_SIZE - 1)

typedef struct IOMMUState {
    uint32_t regs[IOMMU_NREGS];
    target_phys_addr_t iostart;
    uint32_t version;
    qemu_irq irq;
} IOMMUState;

static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
{
    IOMMUState *s = opaque;
    target_phys_addr_t saddr;
    uint32_t ret;

    saddr = addr >> 2;
    switch (saddr) {
    default:
        ret = s->regs[saddr];
        break;
    case IOMMU_AFAR:
    case IOMMU_AFSR:
        ret = s->regs[saddr];
        qemu_irq_lower(s->irq);
        break;
    }
    DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
    return ret;
}

static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
                             uint32_t val)
{
    IOMMUState *s = opaque;
    target_phys_addr_t saddr;

    saddr = addr >> 2;
    DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
    switch (saddr) {
    case IOMMU_CTRL:
        switch (val & IOMMU_CTRL_RNGE) {
        case IOMMU_RNGE_16MB:
            s->iostart = 0xffffffffff000000ULL;
            break;
        case IOMMU_RNGE_32MB:
            s->iostart = 0xfffffffffe000000ULL;
            break;
        case IOMMU_RNGE_64MB:
            s->iostart = 0xfffffffffc000000ULL;
            break;
        case IOMMU_RNGE_128MB:
            s->iostart = 0xfffffffff8000000ULL;
            break;
        case IOMMU_RNGE_256MB:
            s->iostart = 0xfffffffff0000000ULL;
            break;
        case IOMMU_RNGE_512MB:
            s->iostart = 0xffffffffe0000000ULL;
            break;
        case IOMMU_RNGE_1GB:
            s->iostart = 0xffffffffc0000000ULL;
            break;
        default:
        case IOMMU_RNGE_2GB:
            s->iostart = 0xffffffff80000000ULL;
            break;
        }
        DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
        s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
        break;
    case IOMMU_BASE:
        s->regs[saddr] = val & IOMMU_BASE_MASK;
        break;
    case IOMMU_TLBFLUSH:
        DPRINTF("tlb flush %x\n", val);
        s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
        break;
    case IOMMU_PGFLUSH:
        DPRINTF("page flush %x\n", val);
        s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
        break;
    case IOMMU_AFAR:
        s->regs[saddr] = val;
        qemu_irq_lower(s->irq);
        break;
    case IOMMU_AER:
        s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
        break;
    case IOMMU_AFSR:
        s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
        qemu_irq_lower(s->irq);
        break;
    case IOMMU_SBCFG0:
    case IOMMU_SBCFG1:
    case IOMMU_SBCFG2:
    case IOMMU_SBCFG3:
        s->regs[saddr] = val & IOMMU_SBCFG_MASK;
        break;
    case IOMMU_ARBEN:
        // XXX implement SBus probing: fault when reading unmapped
        // addresses, fault cause and address stored to MMU/IOMMU
        s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
        break;
    case IOMMU_MASK_ID:
        s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
        break;
    default:
        s->regs[saddr] = val;
        break;
    }
}

static CPUReadMemoryFunc *iommu_mem_read[3] = {
    NULL,
    NULL,
    iommu_mem_readl,
};

static CPUWriteMemoryFunc *iommu_mem_write[3] = {
    NULL,
    NULL,
    iommu_mem_writel,
};

static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
{
    uint32_t ret;
    target_phys_addr_t iopte;
#ifdef DEBUG_IOMMU
    target_phys_addr_t pa = addr;
#endif

    iopte = s->regs[IOMMU_BASE] << 4;
    addr &= ~s->iostart;
    iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
    cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
    tswap32s(&ret);
    DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
            ", *pte = %x\n", pa, iopte, ret);

    return ret;
}

static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
                                             uint32_t pte)
{
    uint32_t tmppte;
    target_phys_addr_t pa;

    tmppte = pte;
    pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
    DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
            " (iopte = %x)\n", addr, pa, tmppte);

    return pa;
}

static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
                           int is_write)
{
    DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
    s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
        IOMMU_AFSR_FAV;
    if (!is_write)
        s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
    s->regs[IOMMU_AFAR] = addr;
    qemu_irq_raise(s->irq);
}

void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
                           uint8_t *buf, int len, int is_write)
{
    int l;
    uint32_t flags;
    target_phys_addr_t page, phys_addr;

    while (len > 0) {
        page = addr & IOMMU_PAGE_MASK;
        l = (page + IOMMU_PAGE_SIZE) - addr;
        if (l > len)
            l = len;
        flags = iommu_page_get_flags(opaque, page);
        if (!(flags & IOPTE_VALID)) {
            iommu_bad_addr(opaque, page, is_write);
            return;
        }
        phys_addr = iommu_translate_pa(addr, flags);
        if (is_write) {
            if (!(flags & IOPTE_WRITE)) {
                iommu_bad_addr(opaque, page, is_write);
                return;
            }
            cpu_physical_memory_write(phys_addr, buf, l);
        } else {
            cpu_physical_memory_read(phys_addr, buf, l);
        }
        len -= l;
        buf += l;
        addr += l;
    }
}

static void iommu_save(QEMUFile *f, void *opaque)
{
    IOMMUState *s = opaque;
    int i;

    for (i = 0; i < IOMMU_NREGS; i++)
        qemu_put_be32s(f, &s->regs[i]);
    qemu_put_be64s(f, &s->iostart);
}

static int iommu_load(QEMUFile *f, void *opaque, int version_id)
{
    IOMMUState *s = opaque;
    int i;

    if (version_id != 2)
        return -EINVAL;

    for (i = 0; i < IOMMU_NREGS; i++)
        qemu_get_be32s(f, &s->regs[i]);
    qemu_get_be64s(f, &s->iostart);

    return 0;
}

static void iommu_reset(void *opaque)
{
    IOMMUState *s = opaque;

    memset(s->regs, 0, IOMMU_NREGS * 4);
    s->iostart = 0;
    s->regs[IOMMU_CTRL] = s->version;
    s->regs[IOMMU_ARBEN] = IOMMU_MID;
    s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
    s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
    s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
    qemu_irq_lower(s->irq);
}

void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
{
    IOMMUState *s;
    int iommu_io_memory;

    s = qemu_mallocz(sizeof(IOMMUState));

    s->version = version;
    s->irq = irq;

    iommu_io_memory = cpu_register_io_memory(iommu_mem_read,
                                             iommu_mem_write, s);
    cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);

    register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
    qemu_register_reset(iommu_reset, 0, s);
    iommu_reset(s);
    return s;
}
Commit	Line	Data
420557e8 FB	1	/*
	2	* QEMU SPARC iommu emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
420557e8 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
87ecb68b PB	25	#include "sun4m.h"
420557e8 FB	26
	27	/* debug iommu */
	28	//#define DEBUG_IOMMU
	29
66321a11	30	#ifdef DEBUG_IOMMU
001faf32 BS	31	#define DPRINTF(fmt, ...) \
001faf32 BS	32	do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
66321a11	33	#else
001faf32	34	#define DPRINTF(fmt, ...)
66321a11	35	#endif
420557e8	36
e5e38121	37	#define IOMMU_NREGS (4*4096/4)
4e3b1ea1	38	#define IOMMU_CTRL (0x0000 >> 2)
420557e8 FB	39	#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
	40	#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
	41	#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
	42	#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
	43	#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
	44	#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
	45	#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
	46	#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
	47	#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
	48	#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
	49	#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
	50	#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
4e3b1ea1 FB	51	#define IOMMU_CTRL_MASK 0x0000001d
	52
	53	#define IOMMU_BASE (0x0004 >> 2)
	54	#define IOMMU_BASE_MASK 0x07fffc00
	55
	56	#define IOMMU_TLBFLUSH (0x0014 >> 2)
	57	#define IOMMU_TLBFLUSH_MASK 0xffffffff
	58
	59	#define IOMMU_PGFLUSH (0x0018 >> 2)
	60	#define IOMMU_PGFLUSH_MASK 0xffffffff
	61
225d4be7 BS	62	#define IOMMU_AFSR (0x1000 >> 2)
225d4be7 BS	63	#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
5ad6bb97 BS	64	#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
	65	transaction */
	66	#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
	67	12.8 us. */
	68	#define IOMMU_AFSR_BE 0x10000000 /* Write access received error
	69	acknowledge */
225d4be7 BS	70	#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
225d4be7 BS	71	#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
5ad6bb97 BS	72	#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
5ad6bb97 BS	73	hardware */
225d4be7 BS	74	#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
	75	#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
	76	#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
c52428fc	77	#define IOMMU_AFSR_MASK 0xff0fffff
225d4be7 BS	78
	79	#define IOMMU_AFAR (0x1004 >> 2)
	80
7b169687 BS	81	#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
	82	#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
	83	#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
	84	#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
	85	#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
	86	#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
	87	#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
	88	#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
	89	#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
	90	#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
	91	#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
	92	#define IOMMU_AER_MASK 0x801f000f
	93
4e3b1ea1 FB	94	#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
	95	#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
	96	#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
	97	#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
5ad6bb97 BS	98	#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
5ad6bb97 BS	99	bypass enabled */
4e3b1ea1 FB	100	#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
	101	#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
	102	#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
f930d07e	103	produced by this device as pure
4e3b1ea1 FB	104	physical. */
	105	#define IOMMU_SBCFG_MASK 0x00010003
	106
	107	#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
	108	#define IOMMU_ARBEN_MASK 0x001f0000
	109	#define IOMMU_MID 0x00000008
420557e8	110
e5e38121 BS	111	#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
	112	#define IOMMU_MASK_ID_MASK 0x00ffffff
	113
	114	#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
	115	#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
	116
420557e8	117	/* The format of an iopte in the page tables */
498fbd8a	118	#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
5ad6bb97 BS	119	#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
5ad6bb97 BS	120	Viking/MXCC) */
420557e8 FB	121	#define IOPTE_WRITE 0x00000004 /* Writeable */
	122	#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
	123	#define IOPTE_WAZ 0x00000001 /* Write as zeros */
	124
8b0de438 BS	125	#define IOMMU_PAGE_SHIFT 12
	126	#define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT)
	127	#define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1)
420557e8 FB	128
420557e8 FB	129	typedef struct IOMMUState {
66321a11	130	uint32_t regs[IOMMU_NREGS];
5dcb6b91	131	target_phys_addr_t iostart;
7fbfb139	132	uint32_t version;
ff403da6	133	qemu_irq irq;
420557e8 FB	134	} IOMMUState;
420557e8 FB	135
7c560456	136	static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
420557e8 FB	137	{
420557e8 FB	138	IOMMUState *s = opaque;
5dcb6b91	139	target_phys_addr_t saddr;
ff403da6	140	uint32_t ret;
420557e8	141
8da3ff18	142	saddr = addr >> 2;
420557e8 FB	143	switch (saddr) {
420557e8 FB	144	default:
ff403da6 BS	145	ret = s->regs[saddr];
	146	break;
	147	case IOMMU_AFAR:
	148	case IOMMU_AFSR:
	149	ret = s->regs[saddr];
	150	qemu_irq_lower(s->irq);
f930d07e	151	break;
420557e8	152	}
ff403da6 BS	153	DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
ff403da6 BS	154	return ret;
420557e8 FB	155	}
420557e8 FB	156
7c560456	157	static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
5ad6bb97	158	uint32_t val)
420557e8 FB	159	{
420557e8 FB	160	IOMMUState *s = opaque;
5dcb6b91	161	target_phys_addr_t saddr;
420557e8	162
8da3ff18	163	saddr = addr >> 2;
981a2e99	164	DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
420557e8	165	switch (saddr) {
4e3b1ea1	166	case IOMMU_CTRL:
f930d07e BS	167	switch (val & IOMMU_CTRL_RNGE) {
	168	case IOMMU_RNGE_16MB:
	169	s->iostart = 0xffffffffff000000ULL;
	170	break;
	171	case IOMMU_RNGE_32MB:
	172	s->iostart = 0xfffffffffe000000ULL;
	173	break;
	174	case IOMMU_RNGE_64MB:
	175	s->iostart = 0xfffffffffc000000ULL;
	176	break;
	177	case IOMMU_RNGE_128MB:
	178	s->iostart = 0xfffffffff8000000ULL;
	179	break;
	180	case IOMMU_RNGE_256MB:
	181	s->iostart = 0xfffffffff0000000ULL;
	182	break;
	183	case IOMMU_RNGE_512MB:
	184	s->iostart = 0xffffffffe0000000ULL;
	185	break;
	186	case IOMMU_RNGE_1GB:
	187	s->iostart = 0xffffffffc0000000ULL;
	188	break;
	189	default:
	190	case IOMMU_RNGE_2GB:
	191	s->iostart = 0xffffffff80000000ULL;
	192	break;
	193	}
	194	DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
7fbfb139	195	s->regs[saddr] = ((val & IOMMU_CTRL_MASK) \| s->version);
f930d07e	196	break;
4e3b1ea1	197	case IOMMU_BASE:
f930d07e BS	198	s->regs[saddr] = val & IOMMU_BASE_MASK;
f930d07e BS	199	break;
4e3b1ea1	200	case IOMMU_TLBFLUSH:
f930d07e BS	201	DPRINTF("tlb flush %x\n", val);
	202	s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
	203	break;
4e3b1ea1	204	case IOMMU_PGFLUSH:
f930d07e BS	205	DPRINTF("page flush %x\n", val);
	206	s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
	207	break;
ff403da6 BS	208	case IOMMU_AFAR:
	209	s->regs[saddr] = val;
	210	qemu_irq_lower(s->irq);
	211	break;
7b169687 BS	212	case IOMMU_AER:
	213	s->regs[saddr] = (val & IOMMU_AER_MASK) \| IOMMU_AER_EN_P0_ARB;
	214	break;
c52428fc BS	215	case IOMMU_AFSR:
c52428fc BS	216	s->regs[saddr] = (val & IOMMU_AFSR_MASK) \| IOMMU_AFSR_RESV;
ff403da6	217	qemu_irq_lower(s->irq);
c52428fc	218	break;
4e3b1ea1 FB	219	case IOMMU_SBCFG0:
	220	case IOMMU_SBCFG1:
	221	case IOMMU_SBCFG2:
	222	case IOMMU_SBCFG3:
f930d07e BS	223	s->regs[saddr] = val & IOMMU_SBCFG_MASK;
f930d07e BS	224	break;
4e3b1ea1 FB	225	case IOMMU_ARBEN:
	226	// XXX implement SBus probing: fault when reading unmapped
	227	// addresses, fault cause and address stored to MMU/IOMMU
f930d07e BS	228	s->regs[saddr] = (val & IOMMU_ARBEN_MASK) \| IOMMU_MID;
f930d07e BS	229	break;
e5e38121 BS	230	case IOMMU_MASK_ID:
	231	s->regs[saddr] \|= val & IOMMU_MASK_ID_MASK;
	232	break;
420557e8	233	default:
f930d07e BS	234	s->regs[saddr] = val;
f930d07e BS	235	break;
420557e8 FB	236	}
	237	}
	238
	239	static CPUReadMemoryFunc *iommu_mem_read[3] = {
7c560456 BS	240	NULL,
	241	NULL,
	242	iommu_mem_readl,
420557e8 FB	243	};
	244
	245	static CPUWriteMemoryFunc *iommu_mem_write[3] = {
7c560456 BS	246	NULL,
	247	NULL,
	248	iommu_mem_writel,
420557e8 FB	249	};
420557e8 FB	250
5dcb6b91	251	static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
420557e8	252	{
5e3b100b BS	253	uint32_t ret;
5e3b100b BS	254	target_phys_addr_t iopte;
981a2e99 BS	255	#ifdef DEBUG_IOMMU
	256	target_phys_addr_t pa = addr;
	257	#endif
420557e8	258
981a2e99	259	iopte = s->regs[IOMMU_BASE] << 4;
66321a11	260	addr &= ~s->iostart;
8b0de438	261	iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
5e3b100b	262	cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
748e4993	263	tswap32s(&ret);
5e3b100b BS	264	DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
5e3b100b BS	265	", *pte = %x\n", pa, iopte, ret);
981a2e99 BS	266
981a2e99 BS	267	return ret;
a917d384 PB	268	}
a917d384 PB	269
22548760	270	static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
5dcb6b91	271	uint32_t pte)
a917d384 PB	272	{
a917d384 PB	273	uint32_t tmppte;
5dcb6b91 BS	274	target_phys_addr_t pa;
	275
	276	tmppte = pte;
8b0de438	277	pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
5dcb6b91 BS	278	DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
5dcb6b91 BS	279	" (iopte = %x)\n", addr, pa, tmppte);
a917d384	280
66321a11	281	return pa;
420557e8 FB	282	}
420557e8 FB	283
5ad6bb97 BS	284	static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
5ad6bb97 BS	285	int is_write)
225d4be7 BS	286	{
225d4be7 BS	287	DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
5ad6bb97	288	s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR \| IOMMU_AFSR_LE \| IOMMU_AFSR_RESV \|
225d4be7 BS	289	IOMMU_AFSR_FAV;
	290	if (!is_write)
	291	s->regs[IOMMU_AFSR] \|= IOMMU_AFSR_RD;
	292	s->regs[IOMMU_AFAR] = addr;
ff403da6	293	qemu_irq_raise(s->irq);
225d4be7 BS	294	}
225d4be7 BS	295
67e999be FB	296	void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
67e999be FB	297	uint8_t *buf, int len, int is_write)
a917d384	298	{
5dcb6b91 BS	299	int l;
	300	uint32_t flags;
	301	target_phys_addr_t page, phys_addr;
a917d384 PB	302
a917d384 PB	303	while (len > 0) {
8b0de438 BS	304	page = addr & IOMMU_PAGE_MASK;
8b0de438 BS	305	l = (page + IOMMU_PAGE_SIZE) - addr;
a917d384 PB	306	if (l > len)
	307	l = len;
	308	flags = iommu_page_get_flags(opaque, page);
225d4be7 BS	309	if (!(flags & IOPTE_VALID)) {
225d4be7 BS	310	iommu_bad_addr(opaque, page, is_write);
a917d384	311	return;
225d4be7	312	}
22548760	313	phys_addr = iommu_translate_pa(addr, flags);
a917d384	314	if (is_write) {
225d4be7 BS	315	if (!(flags & IOPTE_WRITE)) {
225d4be7 BS	316	iommu_bad_addr(opaque, page, is_write);
a917d384	317	return;
225d4be7	318	}
a5cdf952	319	cpu_physical_memory_write(phys_addr, buf, l);
a917d384	320	} else {
a5cdf952	321	cpu_physical_memory_read(phys_addr, buf, l);
a917d384 PB	322	}
	323	len -= l;
	324	buf += l;
	325	addr += l;
	326	}
	327	}
	328
e80cfcfc FB	329	static void iommu_save(QEMUFile f, void opaque)
	330	{
	331	IOMMUState *s = opaque;
	332	int i;
3b46e624	333
66321a11	334	for (i = 0; i < IOMMU_NREGS; i++)
f930d07e	335	qemu_put_be32s(f, &s->regs[i]);
5dcb6b91	336	qemu_put_be64s(f, &s->iostart);
e80cfcfc FB	337	}
	338
	339	static int iommu_load(QEMUFile f, void opaque, int version_id)
	340	{
	341	IOMMUState *s = opaque;
	342	int i;
3b46e624	343
5dcb6b91	344	if (version_id != 2)
e80cfcfc FB	345	return -EINVAL;
e80cfcfc FB	346
66321a11	347	for (i = 0; i < IOMMU_NREGS; i++)
fda77c2d	348	qemu_get_be32s(f, &s->regs[i]);
5dcb6b91	349	qemu_get_be64s(f, &s->iostart);
e80cfcfc FB	350
	351	return 0;
	352	}
	353
	354	static void iommu_reset(void *opaque)
	355	{
	356	IOMMUState *s = opaque;
	357
66321a11	358	memset(s->regs, 0, IOMMU_NREGS * 4);
e80cfcfc	359	s->iostart = 0;
7fbfb139 BS	360	s->regs[IOMMU_CTRL] = s->version;
7fbfb139 BS	361	s->regs[IOMMU_ARBEN] = IOMMU_MID;
5ad6bb97	362	s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
7b169687	363	s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB \| IOMMU_AER_EN_P1_ARB;
e5e38121	364	s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
ff403da6	365	qemu_irq_lower(s->irq);
e80cfcfc FB	366	}
e80cfcfc FB	367
ff403da6	368	void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
420557e8 FB	369	{
420557e8 FB	370	IOMMUState *s;
8d5f07fa	371	int iommu_io_memory;
420557e8 FB	372
420557e8 FB	373	s = qemu_mallocz(sizeof(IOMMUState));
420557e8	374
7fbfb139	375	s->version = version;
ff403da6	376	s->irq = irq;
8d5f07fa	377
1eed09cb	378	iommu_io_memory = cpu_register_io_memory(iommu_mem_read,
5ad6bb97	379	iommu_mem_write, s);
66321a11	380	cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
3b46e624	381
5dcb6b91	382	register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
8217606e	383	qemu_register_reset(iommu_reset, 0, s);
7fbfb139	384	iommu_reset(s);
e80cfcfc	385	return s;
420557e8	386	}