[qemu.git] / hw / iommu.c

/*
 * QEMU SPARC iommu emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

/* debug iommu */
//#define DEBUG_IOMMU

#ifdef DEBUG_IOMMU
#define DPRINTF(fmt, args...) \
do { printf("IOMMU: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

#define IOMMU_NREGS (3*4096/4)
#define IOMMU_CTRL          (0x0000 >> 2)
#define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS     0x0f000000 /* Version */
#define IOMMU_VERSION       0x04000000
#define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
#define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
#define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
#define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
#define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
#define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
#define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
#define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
#define IOMMU_CTRL_MASK     0x0000001d

#define IOMMU_BASE          (0x0004 >> 2)
#define IOMMU_BASE_MASK     0x07fffc00

#define IOMMU_TLBFLUSH      (0x0014 >> 2)
#define IOMMU_TLBFLUSH_MASK 0xffffffff

#define IOMMU_PGFLUSH       (0x0018 >> 2)
#define IOMMU_PGFLUSH_MASK  0xffffffff

#define IOMMU_AFSR          (0x1000 >> 2)
#define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
#define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after transaction */
#define IOMMU_AFSR_TO       0x20000000 /* Write access took more than 12.8 us. */
#define IOMMU_AFSR_BE       0x10000000 /* Write access received error acknowledge */
#define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
#define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_AFSR_RESV     0x00f00000 /* Reserved, forced to 0x8 by hardware */
#define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
#define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
#define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */

#define IOMMU_AFAR          (0x1004 >> 2)

#define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when bypass enabled */
#define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
                                          produced by this device as pure
                                          physical. */
#define IOMMU_SBCFG_MASK    0x00010003

#define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
#define IOMMU_ARBEN_MASK    0x001f0000
#define IOMMU_MID           0x00000008

/* The format of an iopte in the page tables */
#define IOPTE_PAGE          0x07ffff00 /* Physical page number (PA[30:12]) */
#define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
#define IOPTE_WRITE         0x00000004 /* Writeable */
#define IOPTE_VALID         0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ           0x00000001 /* Write as zeros */

#define PAGE_SHIFT      12
#define PAGE_SIZE       (1 << PAGE_SHIFT)
#define PAGE_MASK       (PAGE_SIZE - 1)

typedef struct IOMMUState {
    target_phys_addr_t addr;
    uint32_t regs[IOMMU_NREGS];
    target_phys_addr_t iostart;
} IOMMUState;

static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
{
    IOMMUState *s = opaque;
    target_phys_addr_t saddr;

    saddr = (addr - s->addr) >> 2;
    switch (saddr) {
    default:
        DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
        return s->regs[saddr];
        break;
    }
    return 0;
}

static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    IOMMUState *s = opaque;
    target_phys_addr_t saddr;

    saddr = (addr - s->addr) >> 2;
    DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
    switch (saddr) {
    case IOMMU_CTRL:
        switch (val & IOMMU_CTRL_RNGE) {
        case IOMMU_RNGE_16MB:
            s->iostart = 0xffffffffff000000ULL;
            break;
        case IOMMU_RNGE_32MB:
            s->iostart = 0xfffffffffe000000ULL;
            break;
        case IOMMU_RNGE_64MB:
            s->iostart = 0xfffffffffc000000ULL;
            break;
        case IOMMU_RNGE_128MB:
            s->iostart = 0xfffffffff8000000ULL;
            break;
        case IOMMU_RNGE_256MB:
            s->iostart = 0xfffffffff0000000ULL;
            break;
        case IOMMU_RNGE_512MB:
            s->iostart = 0xffffffffe0000000ULL;
            break;
        case IOMMU_RNGE_1GB:
            s->iostart = 0xffffffffc0000000ULL;
            break;
        default:
        case IOMMU_RNGE_2GB:
            s->iostart = 0xffffffff80000000ULL;
            break;
        }
        DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
        s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
        break;
    case IOMMU_BASE:
        s->regs[saddr] = val & IOMMU_BASE_MASK;
        break;
    case IOMMU_TLBFLUSH:
        DPRINTF("tlb flush %x\n", val);
        s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
        break;
    case IOMMU_PGFLUSH:
        DPRINTF("page flush %x\n", val);
        s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
        break;
    case IOMMU_SBCFG0:
    case IOMMU_SBCFG1:
    case IOMMU_SBCFG2:
    case IOMMU_SBCFG3:
        s->regs[saddr] = val & IOMMU_SBCFG_MASK;
        break;
    case IOMMU_ARBEN:
        // XXX implement SBus probing: fault when reading unmapped
        // addresses, fault cause and address stored to MMU/IOMMU
        s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
        break;
    default:
        s->regs[saddr] = val;
        break;
    }
}

static CPUReadMemoryFunc *iommu_mem_read[3] = {
    iommu_mem_readw,
    iommu_mem_readw,
    iommu_mem_readw,
};

static CPUWriteMemoryFunc *iommu_mem_write[3] = {
    iommu_mem_writew,
    iommu_mem_writew,
    iommu_mem_writew,
};

static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
{
    uint32_t ret;
    target_phys_addr_t iopte;
#ifdef DEBUG_IOMMU
    target_phys_addr_t pa = addr;
#endif

    iopte = s->regs[IOMMU_BASE] << 4;
    addr &= ~s->iostart;
    iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
    cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
    tswap32s(&ret);
    DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
            ", *pte = %x\n", pa, iopte, ret);

    return ret;
}

static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
                                             target_phys_addr_t addr,
                                             uint32_t pte)
{
    uint32_t tmppte;
    target_phys_addr_t pa;

    tmppte = pte;
    pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
    DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
            " (iopte = %x)\n", addr, pa, tmppte);

    return pa;
}

static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, int is_write)
{
    DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
    s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | (8 << 20) |
        IOMMU_AFSR_FAV;
    if (!is_write)
        s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
    s->regs[IOMMU_AFAR] = addr;
}

void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
                           uint8_t *buf, int len, int is_write)
{
    int l;
    uint32_t flags;
    target_phys_addr_t page, phys_addr;

    while (len > 0) {
        page = addr & TARGET_PAGE_MASK;
        l = (page + TARGET_PAGE_SIZE) - addr;
        if (l > len)
            l = len;
        flags = iommu_page_get_flags(opaque, page);
        if (!(flags & IOPTE_VALID)) {
            iommu_bad_addr(opaque, page, is_write);
            return;
        }
        phys_addr = iommu_translate_pa(opaque, addr, flags);
        if (is_write) {
            if (!(flags & IOPTE_WRITE)) {
                iommu_bad_addr(opaque, page, is_write);
                return;
            }
            cpu_physical_memory_write(phys_addr, buf, len);
        } else {
            cpu_physical_memory_read(phys_addr, buf, len);
        }
        len -= l;
        buf += l;
        addr += l;
    }
}

static void iommu_save(QEMUFile *f, void *opaque)
{
    IOMMUState *s = opaque;
    int i;

    for (i = 0; i < IOMMU_NREGS; i++)
        qemu_put_be32s(f, &s->regs[i]);
    qemu_put_be64s(f, &s->iostart);
}

static int iommu_load(QEMUFile *f, void *opaque, int version_id)
{
    IOMMUState *s = opaque;
    int i;

    if (version_id != 2)
        return -EINVAL;

    for (i = 0; i < IOMMU_NREGS; i++)
        qemu_get_be32s(f, &s->regs[i]);
    qemu_get_be64s(f, &s->iostart);

    return 0;
}

static void iommu_reset(void *opaque)
{
    IOMMUState *s = opaque;

    memset(s->regs, 0, IOMMU_NREGS * 4);
    s->iostart = 0;
    s->regs[IOMMU_CTRL] = IOMMU_VERSION;
}

void *iommu_init(target_phys_addr_t addr)
{
    IOMMUState *s;
    int iommu_io_memory;

    s = qemu_mallocz(sizeof(IOMMUState));
    if (!s)
        return NULL;

    s->addr = addr;

    iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
    cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);

    register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
    qemu_register_reset(iommu_reset, s);
    return s;
}
Commit	Line	Data
420557e8 FB	1	/*
	2	* QEMU SPARC iommu emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
420557e8 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
	26	/* debug iommu */
	27	//#define DEBUG_IOMMU
	28
66321a11 FB	29	#ifdef DEBUG_IOMMU
	30	#define DPRINTF(fmt, args...) \
	31	do { printf("IOMMU: " fmt , ##args); } while (0)
	32	#else
	33	#define DPRINTF(fmt, args...)
	34	#endif
420557e8	35
4e3b1ea1 FB	36	#define IOMMU_NREGS (3*4096/4)
4e3b1ea1 FB	37	#define IOMMU_CTRL (0x0000 >> 2)
420557e8 FB	38	#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
420557e8 FB	39	#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
4e3b1ea1	40	#define IOMMU_VERSION 0x04000000
420557e8 FB	41	#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
	42	#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
	43	#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
	44	#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
	45	#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
	46	#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
	47	#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
	48	#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
	49	#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
	50	#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
4e3b1ea1 FB	51	#define IOMMU_CTRL_MASK 0x0000001d
	52
	53	#define IOMMU_BASE (0x0004 >> 2)
	54	#define IOMMU_BASE_MASK 0x07fffc00
	55
	56	#define IOMMU_TLBFLUSH (0x0014 >> 2)
	57	#define IOMMU_TLBFLUSH_MASK 0xffffffff
	58
	59	#define IOMMU_PGFLUSH (0x0018 >> 2)
	60	#define IOMMU_PGFLUSH_MASK 0xffffffff
	61
225d4be7 BS	62	#define IOMMU_AFSR (0x1000 >> 2)
	63	#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
	64	#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
	65	#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
	66	#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
	67	#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
	68	#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
	69	#define IOMMU_AFSR_RESV 0x00f00000 /* Reserved, forced to 0x8 by hardware */
	70	#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
	71	#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
	72	#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
	73
	74	#define IOMMU_AFAR (0x1004 >> 2)
	75
4e3b1ea1 FB	76	#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
	77	#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
	78	#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
	79	#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
	80	#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
	81	#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
	82	#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
	83	#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
f930d07e	84	produced by this device as pure
4e3b1ea1 FB	85	physical. */
	86	#define IOMMU_SBCFG_MASK 0x00010003
	87
	88	#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
	89	#define IOMMU_ARBEN_MASK 0x001f0000
	90	#define IOMMU_MID 0x00000008
420557e8	91
420557e8 FB	92	/* The format of an iopte in the page tables */
	93	#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
	94	#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
	95	#define IOPTE_WRITE 0x00000004 /* Writeable */
	96	#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
	97	#define IOPTE_WAZ 0x00000001 /* Write as zeros */
	98
420557e8 FB	99	#define PAGE_SHIFT 12
420557e8 FB	100	#define PAGE_SIZE (1 << PAGE_SHIFT)
f930d07e	101	#define PAGE_MASK (PAGE_SIZE - 1)
420557e8 FB	102
420557e8 FB	103	typedef struct IOMMUState {
5dcb6b91	104	target_phys_addr_t addr;
66321a11	105	uint32_t regs[IOMMU_NREGS];
5dcb6b91	106	target_phys_addr_t iostart;
420557e8 FB	107	} IOMMUState;
420557e8 FB	108
420557e8 FB	109	static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
	110	{
	111	IOMMUState *s = opaque;
5dcb6b91	112	target_phys_addr_t saddr;
420557e8	113
8d5f07fa	114	saddr = (addr - s->addr) >> 2;
420557e8 FB	115	switch (saddr) {
420557e8 FB	116	default:
f930d07e BS	117	DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
	118	return s->regs[saddr];
	119	break;
420557e8 FB	120	}
	121	return 0;
	122	}
	123
	124	static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
	125	{
	126	IOMMUState *s = opaque;
5dcb6b91	127	target_phys_addr_t saddr;
420557e8	128
8d5f07fa	129	saddr = (addr - s->addr) >> 2;
981a2e99	130	DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
420557e8	131	switch (saddr) {
4e3b1ea1	132	case IOMMU_CTRL:
f930d07e BS	133	switch (val & IOMMU_CTRL_RNGE) {
	134	case IOMMU_RNGE_16MB:
	135	s->iostart = 0xffffffffff000000ULL;
	136	break;
	137	case IOMMU_RNGE_32MB:
	138	s->iostart = 0xfffffffffe000000ULL;
	139	break;
	140	case IOMMU_RNGE_64MB:
	141	s->iostart = 0xfffffffffc000000ULL;
	142	break;
	143	case IOMMU_RNGE_128MB:
	144	s->iostart = 0xfffffffff8000000ULL;
	145	break;
	146	case IOMMU_RNGE_256MB:
	147	s->iostart = 0xfffffffff0000000ULL;
	148	break;
	149	case IOMMU_RNGE_512MB:
	150	s->iostart = 0xffffffffe0000000ULL;
	151	break;
	152	case IOMMU_RNGE_1GB:
	153	s->iostart = 0xffffffffc0000000ULL;
	154	break;
	155	default:
	156	case IOMMU_RNGE_2GB:
	157	s->iostart = 0xffffffff80000000ULL;
	158	break;
	159	}
	160	DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
	161	s->regs[saddr] = ((val & IOMMU_CTRL_MASK) \| IOMMU_VERSION);
	162	break;
4e3b1ea1	163	case IOMMU_BASE:
f930d07e BS	164	s->regs[saddr] = val & IOMMU_BASE_MASK;
f930d07e BS	165	break;
4e3b1ea1	166	case IOMMU_TLBFLUSH:
f930d07e BS	167	DPRINTF("tlb flush %x\n", val);
	168	s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
	169	break;
4e3b1ea1	170	case IOMMU_PGFLUSH:
f930d07e BS	171	DPRINTF("page flush %x\n", val);
	172	s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
	173	break;
4e3b1ea1 FB	174	case IOMMU_SBCFG0:
	175	case IOMMU_SBCFG1:
	176	case IOMMU_SBCFG2:
	177	case IOMMU_SBCFG3:
f930d07e BS	178	s->regs[saddr] = val & IOMMU_SBCFG_MASK;
f930d07e BS	179	break;
4e3b1ea1 FB	180	case IOMMU_ARBEN:
	181	// XXX implement SBus probing: fault when reading unmapped
	182	// addresses, fault cause and address stored to MMU/IOMMU
f930d07e BS	183	s->regs[saddr] = (val & IOMMU_ARBEN_MASK) \| IOMMU_MID;
f930d07e BS	184	break;
420557e8	185	default:
f930d07e BS	186	s->regs[saddr] = val;
f930d07e BS	187	break;
420557e8 FB	188	}
	189	}
	190
	191	static CPUReadMemoryFunc *iommu_mem_read[3] = {
	192	iommu_mem_readw,
	193	iommu_mem_readw,
	194	iommu_mem_readw,
	195	};
	196
	197	static CPUWriteMemoryFunc *iommu_mem_write[3] = {
	198	iommu_mem_writew,
	199	iommu_mem_writew,
	200	iommu_mem_writew,
	201	};
	202
5dcb6b91	203	static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
420557e8	204	{
5e3b100b BS	205	uint32_t ret;
5e3b100b BS	206	target_phys_addr_t iopte;
981a2e99 BS	207	#ifdef DEBUG_IOMMU
	208	target_phys_addr_t pa = addr;
	209	#endif
420557e8	210
981a2e99	211	iopte = s->regs[IOMMU_BASE] << 4;
66321a11 FB	212	addr &= ~s->iostart;
66321a11 FB	213	iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
5e3b100b	214	cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
748e4993	215	tswap32s(&ret);
5e3b100b BS	216	DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
5e3b100b BS	217	", *pte = %x\n", pa, iopte, ret);
981a2e99 BS	218
981a2e99 BS	219	return ret;
a917d384 PB	220	}
a917d384 PB	221
5dcb6b91 BS	222	static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
	223	target_phys_addr_t addr,
	224	uint32_t pte)
a917d384 PB	225	{
a917d384 PB	226	uint32_t tmppte;
5dcb6b91 BS	227	target_phys_addr_t pa;
	228
	229	tmppte = pte;
	230	pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
	231	DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
	232	" (iopte = %x)\n", addr, pa, tmppte);
a917d384	233
66321a11	234	return pa;
420557e8 FB	235	}
420557e8 FB	236
225d4be7 BS	237	static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, int is_write)
	238	{
	239	DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
	240	s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR \| IOMMU_AFSR_LE \| (8 << 20) \|
	241	IOMMU_AFSR_FAV;
	242	if (!is_write)
	243	s->regs[IOMMU_AFSR] \|= IOMMU_AFSR_RD;
	244	s->regs[IOMMU_AFAR] = addr;
	245	}
	246
67e999be FB	247	void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
67e999be FB	248	uint8_t *buf, int len, int is_write)
a917d384	249	{
5dcb6b91 BS	250	int l;
	251	uint32_t flags;
	252	target_phys_addr_t page, phys_addr;
a917d384 PB	253
	254	while (len > 0) {
	255	page = addr & TARGET_PAGE_MASK;
	256	l = (page + TARGET_PAGE_SIZE) - addr;
	257	if (l > len)
	258	l = len;
	259	flags = iommu_page_get_flags(opaque, page);
225d4be7 BS	260	if (!(flags & IOPTE_VALID)) {
225d4be7 BS	261	iommu_bad_addr(opaque, page, is_write);
a917d384	262	return;
225d4be7	263	}
a917d384 PB	264	phys_addr = iommu_translate_pa(opaque, addr, flags);
a917d384 PB	265	if (is_write) {
225d4be7 BS	266	if (!(flags & IOPTE_WRITE)) {
225d4be7 BS	267	iommu_bad_addr(opaque, page, is_write);
a917d384	268	return;
225d4be7	269	}
a917d384 PB	270	cpu_physical_memory_write(phys_addr, buf, len);
	271	} else {
	272	cpu_physical_memory_read(phys_addr, buf, len);
	273	}
	274	len -= l;
	275	buf += l;
	276	addr += l;
	277	}
	278	}
	279
e80cfcfc FB	280	static void iommu_save(QEMUFile f, void opaque)
	281	{
	282	IOMMUState *s = opaque;
	283	int i;
3b46e624	284
66321a11	285	for (i = 0; i < IOMMU_NREGS; i++)
f930d07e	286	qemu_put_be32s(f, &s->regs[i]);
5dcb6b91	287	qemu_put_be64s(f, &s->iostart);
e80cfcfc FB	288	}
	289
	290	static int iommu_load(QEMUFile f, void opaque, int version_id)
	291	{
	292	IOMMUState *s = opaque;
	293	int i;
3b46e624	294
5dcb6b91	295	if (version_id != 2)
e80cfcfc FB	296	return -EINVAL;
e80cfcfc FB	297
66321a11	298	for (i = 0; i < IOMMU_NREGS; i++)
fda77c2d	299	qemu_get_be32s(f, &s->regs[i]);
5dcb6b91	300	qemu_get_be64s(f, &s->iostart);
e80cfcfc FB	301
	302	return 0;
	303	}
	304
	305	static void iommu_reset(void *opaque)
	306	{
	307	IOMMUState *s = opaque;
	308
66321a11	309	memset(s->regs, 0, IOMMU_NREGS * 4);
e80cfcfc	310	s->iostart = 0;
981a2e99	311	s->regs[IOMMU_CTRL] = IOMMU_VERSION;
e80cfcfc FB	312	}
e80cfcfc FB	313
5dcb6b91	314	void *iommu_init(target_phys_addr_t addr)
420557e8 FB	315	{
420557e8 FB	316	IOMMUState *s;
8d5f07fa	317	int iommu_io_memory;
420557e8 FB	318
	319	s = qemu_mallocz(sizeof(IOMMUState));
	320	if (!s)
e80cfcfc	321	return NULL;
420557e8	322
8d5f07fa FB	323	s->addr = addr;
8d5f07fa FB	324
420557e8	325	iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
66321a11	326	cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
3b46e624	327
5dcb6b91	328	register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
e80cfcfc FB	329	qemu_register_reset(iommu_reset, s);
e80cfcfc FB	330	return s;
420557e8 FB	331	}
420557e8 FB	332