[qemu.git] / hw / iommu.c

/*
 * QEMU SPARC iommu emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sun4m.h"

/* debug iommu */
//#define DEBUG_IOMMU

#ifdef DEBUG_IOMMU
#define DPRINTF(fmt, args...) \
do { printf("IOMMU: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

#define IOMMU_NREGS (3*4096/4)
#define IOMMU_CTRL          (0x0000 >> 2)
#define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS     0x0f000000 /* Version */
#define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
#define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
#define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
#define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
#define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
#define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
#define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
#define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
#define IOMMU_CTRL_MASK     0x0000001d

#define IOMMU_BASE          (0x0004 >> 2)
#define IOMMU_BASE_MASK     0x07fffc00

#define IOMMU_TLBFLUSH      (0x0014 >> 2)
#define IOMMU_TLBFLUSH_MASK 0xffffffff

#define IOMMU_PGFLUSH       (0x0018 >> 2)
#define IOMMU_PGFLUSH_MASK  0xffffffff

#define IOMMU_AFSR          (0x1000 >> 2)
#define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
#define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
                                          transaction */
#define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
                                          12.8 us. */
#define IOMMU_AFSR_BE       0x10000000 /* Write access received error
                                          acknowledge */
#define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
#define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
                                          hardware */
#define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
#define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
#define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
#define IOMMU_AFSR_MASK     0xff0fffff

#define IOMMU_AFAR          (0x1004 >> 2)

#define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
                                          bypass enabled */
#define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
                                          produced by this device as pure
                                          physical. */
#define IOMMU_SBCFG_MASK    0x00010003

#define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
#define IOMMU_ARBEN_MASK    0x001f0000
#define IOMMU_MID           0x00000008

/* The format of an iopte in the page tables */
#define IOPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12]) */
#define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
                                          Viking/MXCC) */
#define IOPTE_WRITE         0x00000004 /* Writeable */
#define IOPTE_VALID         0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ           0x00000001 /* Write as zeros */

#define PAGE_SHIFT      12
#define PAGE_SIZE       (1 << PAGE_SHIFT)
#define PAGE_MASK       (PAGE_SIZE - 1)

typedef struct IOMMUState {
    target_phys_addr_t addr;
    uint32_t regs[IOMMU_NREGS];
    target_phys_addr_t iostart;
    uint32_t version;
    qemu_irq irq;
} IOMMUState;

static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
{
    IOMMUState *s = opaque;
    target_phys_addr_t saddr;
    uint32_t ret;

    saddr = (addr - s->addr) >> 2;
    switch (saddr) {
    default:
        ret = s->regs[saddr];
        break;
    case IOMMU_AFAR:
    case IOMMU_AFSR:
        ret = s->regs[saddr];
        qemu_irq_lower(s->irq);
        break;
    }
    DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
    return ret;
}

static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
                             uint32_t val)
{
    IOMMUState *s = opaque;
    target_phys_addr_t saddr;

    saddr = (addr - s->addr) >> 2;
    DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
    switch (saddr) {
    case IOMMU_CTRL:
        switch (val & IOMMU_CTRL_RNGE) {
        case IOMMU_RNGE_16MB:
            s->iostart = 0xffffffffff000000ULL;
            break;
        case IOMMU_RNGE_32MB:
            s->iostart = 0xfffffffffe000000ULL;
            break;
        case IOMMU_RNGE_64MB:
            s->iostart = 0xfffffffffc000000ULL;
            break;
        case IOMMU_RNGE_128MB:
            s->iostart = 0xfffffffff8000000ULL;
            break;
        case IOMMU_RNGE_256MB:
            s->iostart = 0xfffffffff0000000ULL;
            break;
        case IOMMU_RNGE_512MB:
            s->iostart = 0xffffffffe0000000ULL;
            break;
        case IOMMU_RNGE_1GB:
            s->iostart = 0xffffffffc0000000ULL;
            break;
        default:
        case IOMMU_RNGE_2GB:
            s->iostart = 0xffffffff80000000ULL;
            break;
        }
        DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
        s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
        break;
    case IOMMU_BASE:
        s->regs[saddr] = val & IOMMU_BASE_MASK;
        break;
    case IOMMU_TLBFLUSH:
        DPRINTF("tlb flush %x\n", val);
        s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
        break;
    case IOMMU_PGFLUSH:
        DPRINTF("page flush %x\n", val);
        s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
        break;
    case IOMMU_AFAR:
        s->regs[saddr] = val;
        qemu_irq_lower(s->irq);
        break;
    case IOMMU_AFSR:
        s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
        qemu_irq_lower(s->irq);
        break;
    case IOMMU_SBCFG0:
    case IOMMU_SBCFG1:
    case IOMMU_SBCFG2:
    case IOMMU_SBCFG3:
        s->regs[saddr] = val & IOMMU_SBCFG_MASK;
        break;
    case IOMMU_ARBEN:
        // XXX implement SBus probing: fault when reading unmapped
        // addresses, fault cause and address stored to MMU/IOMMU
        s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
        break;
    default:
        s->regs[saddr] = val;
        break;
    }
}

static CPUReadMemoryFunc *iommu_mem_read[3] = {
    NULL,
    NULL,
    iommu_mem_readl,
};

static CPUWriteMemoryFunc *iommu_mem_write[3] = {
    NULL,
    NULL,
    iommu_mem_writel,
};

static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
{
    uint32_t ret;
    target_phys_addr_t iopte;
#ifdef DEBUG_IOMMU
    target_phys_addr_t pa = addr;
#endif

    iopte = s->regs[IOMMU_BASE] << 4;
    addr &= ~s->iostart;
    iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
    cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
    tswap32s(&ret);
    DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
            ", *pte = %x\n", pa, iopte, ret);

    return ret;
}

static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
                                             target_phys_addr_t addr,
                                             uint32_t pte)
{
    uint32_t tmppte;
    target_phys_addr_t pa;

    tmppte = pte;
    pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
    DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
            " (iopte = %x)\n", addr, pa, tmppte);

    return pa;
}

static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
                           int is_write)
{
    DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
    s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
        IOMMU_AFSR_FAV;
    if (!is_write)
        s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
    s->regs[IOMMU_AFAR] = addr;
    qemu_irq_raise(s->irq);
}

void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
                           uint8_t *buf, int len, int is_write)
{
    int l;
    uint32_t flags;
    target_phys_addr_t page, phys_addr;

    while (len > 0) {
        page = addr & TARGET_PAGE_MASK;
        l = (page + TARGET_PAGE_SIZE) - addr;
        if (l > len)
            l = len;
        flags = iommu_page_get_flags(opaque, page);
        if (!(flags & IOPTE_VALID)) {
            iommu_bad_addr(opaque, page, is_write);
            return;
        }
        phys_addr = iommu_translate_pa(opaque, addr, flags);
        if (is_write) {
            if (!(flags & IOPTE_WRITE)) {
                iommu_bad_addr(opaque, page, is_write);
                return;
            }
            cpu_physical_memory_write(phys_addr, buf, len);
        } else {
            cpu_physical_memory_read(phys_addr, buf, len);
        }
        len -= l;
        buf += l;
        addr += l;
    }
}

static void iommu_save(QEMUFile *f, void *opaque)
{
    IOMMUState *s = opaque;
    int i;

    for (i = 0; i < IOMMU_NREGS; i++)
        qemu_put_be32s(f, &s->regs[i]);
    qemu_put_be64s(f, &s->iostart);
}

static int iommu_load(QEMUFile *f, void *opaque, int version_id)
{
    IOMMUState *s = opaque;
    int i;

    if (version_id != 2)
        return -EINVAL;

    for (i = 0; i < IOMMU_NREGS; i++)
        qemu_get_be32s(f, &s->regs[i]);
    qemu_get_be64s(f, &s->iostart);

    return 0;
}

static void iommu_reset(void *opaque)
{
    IOMMUState *s = opaque;

    memset(s->regs, 0, IOMMU_NREGS * 4);
    s->iostart = 0;
    s->regs[IOMMU_CTRL] = s->version;
    s->regs[IOMMU_ARBEN] = IOMMU_MID;
    s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
    qemu_irq_lower(s->irq);
}

void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
{
    IOMMUState *s;
    int iommu_io_memory;

    s = qemu_mallocz(sizeof(IOMMUState));
    if (!s)
        return NULL;

    s->addr = addr;
    s->version = version;
    s->irq = irq;

    iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
                                             iommu_mem_write, s);
    cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);

    register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
    qemu_register_reset(iommu_reset, s);
    iommu_reset(s);
    return s;
}
Commit	Line	Data
420557e8 FB	1	/*
	2	* QEMU SPARC iommu emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
420557e8 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
87ecb68b PB	25	#include "sun4m.h"
420557e8 FB	26
	27	/* debug iommu */
	28	//#define DEBUG_IOMMU
	29
66321a11 FB	30	#ifdef DEBUG_IOMMU
	31	#define DPRINTF(fmt, args...) \
	32	do { printf("IOMMU: " fmt , ##args); } while (0)
	33	#else
	34	#define DPRINTF(fmt, args...)
	35	#endif
420557e8	36
4e3b1ea1 FB	37	#define IOMMU_NREGS (3*4096/4)
4e3b1ea1 FB	38	#define IOMMU_CTRL (0x0000 >> 2)
420557e8 FB	39	#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
	40	#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
	41	#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
	42	#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
	43	#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
	44	#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
	45	#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
	46	#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
	47	#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
	48	#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
	49	#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
	50	#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
4e3b1ea1 FB	51	#define IOMMU_CTRL_MASK 0x0000001d
	52
	53	#define IOMMU_BASE (0x0004 >> 2)
	54	#define IOMMU_BASE_MASK 0x07fffc00
	55
	56	#define IOMMU_TLBFLUSH (0x0014 >> 2)
	57	#define IOMMU_TLBFLUSH_MASK 0xffffffff
	58
	59	#define IOMMU_PGFLUSH (0x0018 >> 2)
	60	#define IOMMU_PGFLUSH_MASK 0xffffffff
	61
225d4be7 BS	62	#define IOMMU_AFSR (0x1000 >> 2)
225d4be7 BS	63	#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
5ad6bb97 BS	64	#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
	65	transaction */
	66	#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
	67	12.8 us. */
	68	#define IOMMU_AFSR_BE 0x10000000 /* Write access received error
	69	acknowledge */
225d4be7 BS	70	#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
225d4be7 BS	71	#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
5ad6bb97 BS	72	#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
5ad6bb97 BS	73	hardware */
225d4be7 BS	74	#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
	75	#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
	76	#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
c52428fc	77	#define IOMMU_AFSR_MASK 0xff0fffff
225d4be7 BS	78
	79	#define IOMMU_AFAR (0x1004 >> 2)
	80
4e3b1ea1 FB	81	#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
	82	#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
	83	#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
	84	#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
5ad6bb97 BS	85	#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
5ad6bb97 BS	86	bypass enabled */
4e3b1ea1 FB	87	#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
	88	#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
	89	#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
f930d07e	90	produced by this device as pure
4e3b1ea1 FB	91	physical. */
	92	#define IOMMU_SBCFG_MASK 0x00010003
	93
	94	#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
	95	#define IOMMU_ARBEN_MASK 0x001f0000
	96	#define IOMMU_MID 0x00000008
420557e8	97
420557e8	98	/* The format of an iopte in the page tables */
498fbd8a	99	#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
5ad6bb97 BS	100	#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
5ad6bb97 BS	101	Viking/MXCC) */
420557e8 FB	102	#define IOPTE_WRITE 0x00000004 /* Writeable */
	103	#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
	104	#define IOPTE_WAZ 0x00000001 /* Write as zeros */
	105
420557e8 FB	106	#define PAGE_SHIFT 12
420557e8 FB	107	#define PAGE_SIZE (1 << PAGE_SHIFT)
f930d07e	108	#define PAGE_MASK (PAGE_SIZE - 1)
420557e8 FB	109
420557e8 FB	110	typedef struct IOMMUState {
5dcb6b91	111	target_phys_addr_t addr;
66321a11	112	uint32_t regs[IOMMU_NREGS];
5dcb6b91	113	target_phys_addr_t iostart;
7fbfb139	114	uint32_t version;
ff403da6	115	qemu_irq irq;
420557e8 FB	116	} IOMMUState;
420557e8 FB	117
7c560456	118	static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
420557e8 FB	119	{
420557e8 FB	120	IOMMUState *s = opaque;
5dcb6b91	121	target_phys_addr_t saddr;
ff403da6	122	uint32_t ret;
420557e8	123
8d5f07fa	124	saddr = (addr - s->addr) >> 2;
420557e8 FB	125	switch (saddr) {
420557e8 FB	126	default:
ff403da6 BS	127	ret = s->regs[saddr];
	128	break;
	129	case IOMMU_AFAR:
	130	case IOMMU_AFSR:
	131	ret = s->regs[saddr];
	132	qemu_irq_lower(s->irq);
f930d07e	133	break;
420557e8	134	}
ff403da6 BS	135	DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
ff403da6 BS	136	return ret;
420557e8 FB	137	}
420557e8 FB	138
7c560456	139	static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
5ad6bb97	140	uint32_t val)
420557e8 FB	141	{
420557e8 FB	142	IOMMUState *s = opaque;
5dcb6b91	143	target_phys_addr_t saddr;
420557e8	144
8d5f07fa	145	saddr = (addr - s->addr) >> 2;
981a2e99	146	DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
420557e8	147	switch (saddr) {
4e3b1ea1	148	case IOMMU_CTRL:
f930d07e BS	149	switch (val & IOMMU_CTRL_RNGE) {
	150	case IOMMU_RNGE_16MB:
	151	s->iostart = 0xffffffffff000000ULL;
	152	break;
	153	case IOMMU_RNGE_32MB:
	154	s->iostart = 0xfffffffffe000000ULL;
	155	break;
	156	case IOMMU_RNGE_64MB:
	157	s->iostart = 0xfffffffffc000000ULL;
	158	break;
	159	case IOMMU_RNGE_128MB:
	160	s->iostart = 0xfffffffff8000000ULL;
	161	break;
	162	case IOMMU_RNGE_256MB:
	163	s->iostart = 0xfffffffff0000000ULL;
	164	break;
	165	case IOMMU_RNGE_512MB:
	166	s->iostart = 0xffffffffe0000000ULL;
	167	break;
	168	case IOMMU_RNGE_1GB:
	169	s->iostart = 0xffffffffc0000000ULL;
	170	break;
	171	default:
	172	case IOMMU_RNGE_2GB:
	173	s->iostart = 0xffffffff80000000ULL;
	174	break;
	175	}
	176	DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
7fbfb139	177	s->regs[saddr] = ((val & IOMMU_CTRL_MASK) \| s->version);
f930d07e	178	break;
4e3b1ea1	179	case IOMMU_BASE:
f930d07e BS	180	s->regs[saddr] = val & IOMMU_BASE_MASK;
f930d07e BS	181	break;
4e3b1ea1	182	case IOMMU_TLBFLUSH:
f930d07e BS	183	DPRINTF("tlb flush %x\n", val);
	184	s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
	185	break;
4e3b1ea1	186	case IOMMU_PGFLUSH:
f930d07e BS	187	DPRINTF("page flush %x\n", val);
	188	s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
	189	break;
ff403da6 BS	190	case IOMMU_AFAR:
	191	s->regs[saddr] = val;
	192	qemu_irq_lower(s->irq);
	193	break;
c52428fc BS	194	case IOMMU_AFSR:
c52428fc BS	195	s->regs[saddr] = (val & IOMMU_AFSR_MASK) \| IOMMU_AFSR_RESV;
ff403da6	196	qemu_irq_lower(s->irq);
c52428fc	197	break;
4e3b1ea1 FB	198	case IOMMU_SBCFG0:
	199	case IOMMU_SBCFG1:
	200	case IOMMU_SBCFG2:
	201	case IOMMU_SBCFG3:
f930d07e BS	202	s->regs[saddr] = val & IOMMU_SBCFG_MASK;
f930d07e BS	203	break;
4e3b1ea1 FB	204	case IOMMU_ARBEN:
	205	// XXX implement SBus probing: fault when reading unmapped
	206	// addresses, fault cause and address stored to MMU/IOMMU
f930d07e BS	207	s->regs[saddr] = (val & IOMMU_ARBEN_MASK) \| IOMMU_MID;
f930d07e BS	208	break;
420557e8	209	default:
f930d07e BS	210	s->regs[saddr] = val;
f930d07e BS	211	break;
420557e8 FB	212	}
	213	}
	214
	215	static CPUReadMemoryFunc *iommu_mem_read[3] = {
7c560456 BS	216	NULL,
	217	NULL,
	218	iommu_mem_readl,
420557e8 FB	219	};
	220
	221	static CPUWriteMemoryFunc *iommu_mem_write[3] = {
7c560456 BS	222	NULL,
	223	NULL,
	224	iommu_mem_writel,
420557e8 FB	225	};
420557e8 FB	226
5dcb6b91	227	static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
420557e8	228	{
5e3b100b BS	229	uint32_t ret;
5e3b100b BS	230	target_phys_addr_t iopte;
981a2e99 BS	231	#ifdef DEBUG_IOMMU
	232	target_phys_addr_t pa = addr;
	233	#endif
420557e8	234
981a2e99	235	iopte = s->regs[IOMMU_BASE] << 4;
66321a11 FB	236	addr &= ~s->iostart;
66321a11 FB	237	iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
5e3b100b	238	cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
748e4993	239	tswap32s(&ret);
5e3b100b BS	240	DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
5e3b100b BS	241	", *pte = %x\n", pa, iopte, ret);
981a2e99 BS	242
981a2e99 BS	243	return ret;
a917d384 PB	244	}
a917d384 PB	245
5dcb6b91 BS	246	static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
	247	target_phys_addr_t addr,
	248	uint32_t pte)
a917d384 PB	249	{
a917d384 PB	250	uint32_t tmppte;
5dcb6b91 BS	251	target_phys_addr_t pa;
	252
	253	tmppte = pte;
	254	pa = ((pte & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
	255	DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
	256	" (iopte = %x)\n", addr, pa, tmppte);
a917d384	257
66321a11	258	return pa;
420557e8 FB	259	}
420557e8 FB	260
5ad6bb97 BS	261	static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
5ad6bb97 BS	262	int is_write)
225d4be7 BS	263	{
225d4be7 BS	264	DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
5ad6bb97	265	s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR \| IOMMU_AFSR_LE \| IOMMU_AFSR_RESV \|
225d4be7 BS	266	IOMMU_AFSR_FAV;
	267	if (!is_write)
	268	s->regs[IOMMU_AFSR] \|= IOMMU_AFSR_RD;
	269	s->regs[IOMMU_AFAR] = addr;
ff403da6	270	qemu_irq_raise(s->irq);
225d4be7 BS	271	}
225d4be7 BS	272
67e999be FB	273	void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
67e999be FB	274	uint8_t *buf, int len, int is_write)
a917d384	275	{
5dcb6b91 BS	276	int l;
	277	uint32_t flags;
	278	target_phys_addr_t page, phys_addr;
a917d384 PB	279
	280	while (len > 0) {
	281	page = addr & TARGET_PAGE_MASK;
	282	l = (page + TARGET_PAGE_SIZE) - addr;
	283	if (l > len)
	284	l = len;
	285	flags = iommu_page_get_flags(opaque, page);
225d4be7 BS	286	if (!(flags & IOPTE_VALID)) {
225d4be7 BS	287	iommu_bad_addr(opaque, page, is_write);
a917d384	288	return;
225d4be7	289	}
a917d384 PB	290	phys_addr = iommu_translate_pa(opaque, addr, flags);
a917d384 PB	291	if (is_write) {
225d4be7 BS	292	if (!(flags & IOPTE_WRITE)) {
225d4be7 BS	293	iommu_bad_addr(opaque, page, is_write);
a917d384	294	return;
225d4be7	295	}
a917d384 PB	296	cpu_physical_memory_write(phys_addr, buf, len);
	297	} else {
	298	cpu_physical_memory_read(phys_addr, buf, len);
	299	}
	300	len -= l;
	301	buf += l;
	302	addr += l;
	303	}
	304	}
	305
e80cfcfc FB	306	static void iommu_save(QEMUFile f, void opaque)
	307	{
	308	IOMMUState *s = opaque;
	309	int i;
3b46e624	310
66321a11	311	for (i = 0; i < IOMMU_NREGS; i++)
f930d07e	312	qemu_put_be32s(f, &s->regs[i]);
5dcb6b91	313	qemu_put_be64s(f, &s->iostart);
e80cfcfc FB	314	}
	315
	316	static int iommu_load(QEMUFile f, void opaque, int version_id)
	317	{
	318	IOMMUState *s = opaque;
	319	int i;
3b46e624	320
5dcb6b91	321	if (version_id != 2)
e80cfcfc FB	322	return -EINVAL;
e80cfcfc FB	323
66321a11	324	for (i = 0; i < IOMMU_NREGS; i++)
fda77c2d	325	qemu_get_be32s(f, &s->regs[i]);
5dcb6b91	326	qemu_get_be64s(f, &s->iostart);
e80cfcfc FB	327
	328	return 0;
	329	}
	330
	331	static void iommu_reset(void *opaque)
	332	{
	333	IOMMUState *s = opaque;
	334
66321a11	335	memset(s->regs, 0, IOMMU_NREGS * 4);
e80cfcfc	336	s->iostart = 0;
7fbfb139 BS	337	s->regs[IOMMU_CTRL] = s->version;
7fbfb139 BS	338	s->regs[IOMMU_ARBEN] = IOMMU_MID;
5ad6bb97	339	s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
ff403da6	340	qemu_irq_lower(s->irq);
e80cfcfc FB	341	}
e80cfcfc FB	342
ff403da6	343	void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
420557e8 FB	344	{
420557e8 FB	345	IOMMUState *s;
8d5f07fa	346	int iommu_io_memory;
420557e8 FB	347
	348	s = qemu_mallocz(sizeof(IOMMUState));
	349	if (!s)
e80cfcfc	350	return NULL;
420557e8	351
8d5f07fa	352	s->addr = addr;
7fbfb139	353	s->version = version;
ff403da6	354	s->irq = irq;
8d5f07fa	355
5ad6bb97 BS	356	iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
5ad6bb97 BS	357	iommu_mem_write, s);
66321a11	358	cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
3b46e624	359
5dcb6b91	360	register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
e80cfcfc	361	qemu_register_reset(iommu_reset, s);
7fbfb139	362	iommu_reset(s);
e80cfcfc	363	return s;
420557e8	364	}