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4d00636e | 1 | /* |
6f918e40 JB |
2 | * QEMU ICH9 Emulation |
3 | * | |
4d00636e | 4 | * Copyright (c) 2006 Fabrice Bellard |
6f918e40 JB |
5 | * Copyright (c) 2009, 2010, 2011 |
6 | * Isaku Yamahata <yamahata at valinux co jp> | |
7 | * VA Linux Systems Japan K.K. | |
8 | * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> | |
9 | * | |
10 | * This is based on piix_pci.c, but heavily modified. | |
4d00636e JB |
11 | * |
12 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
13 | * of this software and associated documentation files (the "Software"), to deal | |
14 | * in the Software without restriction, including without limitation the rights | |
15 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
16 | * copies of the Software, and to permit persons to whom the Software is | |
17 | * furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice shall be included in | |
20 | * all copies or substantial portions of the Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
27 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
28 | * THE SOFTWARE. | |
29 | */ | |
4d00636e | 30 | #include "qemu-common.h" |
83c9f4ca | 31 | #include "hw/hw.h" |
1de7afc9 | 32 | #include "qemu/range.h" |
0d09e41a | 33 | #include "hw/isa/isa.h" |
83c9f4ca | 34 | #include "hw/sysbus.h" |
0d09e41a PB |
35 | #include "hw/i386/pc.h" |
36 | #include "hw/isa/apm.h" | |
37 | #include "hw/i386/ioapic.h" | |
83c9f4ca PB |
38 | #include "hw/pci/pci.h" |
39 | #include "hw/pci/pcie_host.h" | |
40 | #include "hw/pci/pci_bridge.h" | |
0d09e41a PB |
41 | #include "hw/i386/ich9.h" |
42 | #include "hw/acpi/acpi.h" | |
43 | #include "hw/acpi/ich9.h" | |
83c9f4ca | 44 | #include "hw/pci/pci_bus.h" |
022c62cb | 45 | #include "exec/address-spaces.h" |
9c17d615 | 46 | #include "sysemu/sysemu.h" |
4d00636e JB |
47 | |
48 | static int ich9_lpc_sci_irq(ICH9LPCState *lpc); | |
49 | ||
50 | /*****************************************************************************/ | |
51 | /* ICH9 LPC PCI to ISA bridge */ | |
52 | ||
53 | static void ich9_lpc_reset(DeviceState *qdev); | |
54 | ||
55 | /* chipset configuration register | |
56 | * to access chipset configuration registers, pci_[sg]et_{byte, word, long} | |
57 | * are used. | |
58 | * Although it's not pci configuration space, it's little endian as Intel. | |
59 | */ | |
60 | ||
61 | static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) | |
62 | { | |
63 | int intx; | |
64 | for (intx = 0; intx < PCI_NUM_PINS; intx++) { | |
65 | irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; | |
66 | } | |
67 | } | |
68 | ||
69 | static void ich9_cc_update(ICH9LPCState *lpc) | |
70 | { | |
71 | int slot; | |
72 | int pci_intx; | |
73 | ||
74 | const int reg_offsets[] = { | |
75 | ICH9_CC_D25IR, | |
76 | ICH9_CC_D26IR, | |
77 | ICH9_CC_D27IR, | |
78 | ICH9_CC_D28IR, | |
79 | ICH9_CC_D29IR, | |
80 | ICH9_CC_D30IR, | |
81 | ICH9_CC_D31IR, | |
82 | }; | |
83 | const int *offset; | |
84 | ||
85 | /* D{25 - 31}IR, but D30IR is read only to 0. */ | |
86 | for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { | |
87 | if (slot == 30) { | |
88 | continue; | |
89 | } | |
90 | ich9_cc_update_ir(lpc->irr[slot], | |
91 | pci_get_word(lpc->chip_config + *offset)); | |
92 | } | |
93 | ||
94 | /* | |
95 | * D30: DMI2PCI bridge | |
96 | * It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge | |
97 | * are connected to pirq lines. Our choice is PIRQ[E-H]. | |
98 | * INT[A-D] are connected to PIRQ[E-H] | |
99 | */ | |
100 | for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { | |
101 | lpc->irr[30][pci_intx] = pci_intx + 4; | |
102 | } | |
103 | } | |
104 | ||
105 | static void ich9_cc_init(ICH9LPCState *lpc) | |
106 | { | |
107 | int slot; | |
108 | int intx; | |
109 | ||
110 | /* the default irq routing is arbitrary as long as it matches with | |
111 | * acpi irq routing table. | |
112 | * The one that is incompatible with piix_pci(= bochs) one is | |
113 | * intentionally chosen to let the users know that the different | |
114 | * board is used. | |
115 | * | |
116 | * int[A-D] -> pirq[E-F] | |
117 | * avoid pirq A-D because they are used for pci express port | |
118 | */ | |
119 | for (slot = 0; slot < PCI_SLOT_MAX; slot++) { | |
120 | for (intx = 0; intx < PCI_NUM_PINS; intx++) { | |
121 | lpc->irr[slot][intx] = (slot + intx) % 4 + 4; | |
122 | } | |
123 | } | |
124 | ich9_cc_update(lpc); | |
125 | } | |
126 | ||
127 | static void ich9_cc_reset(ICH9LPCState *lpc) | |
128 | { | |
129 | uint8_t *c = lpc->chip_config; | |
130 | ||
131 | memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); | |
132 | ||
133 | pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); | |
134 | pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); | |
135 | pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); | |
136 | pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); | |
137 | pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); | |
138 | pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); | |
139 | pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); | |
140 | ||
141 | ich9_cc_update(lpc); | |
142 | } | |
143 | ||
144 | static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) | |
145 | { | |
146 | *addr &= ICH9_CC_ADDR_MASK; | |
147 | if (*addr + *len >= ICH9_CC_SIZE) { | |
148 | *len = ICH9_CC_SIZE - *addr; | |
149 | } | |
150 | } | |
151 | ||
152 | /* val: little endian */ | |
153 | static void ich9_cc_write(void *opaque, hwaddr addr, | |
154 | uint64_t val, unsigned len) | |
155 | { | |
156 | ICH9LPCState *lpc = (ICH9LPCState *)opaque; | |
157 | ||
158 | ich9_cc_addr_len(&addr, &len); | |
159 | memcpy(lpc->chip_config + addr, &val, len); | |
91c3f2f0 | 160 | pci_bus_fire_intx_routing_notifier(lpc->d.bus); |
4d00636e JB |
161 | ich9_cc_update(lpc); |
162 | } | |
163 | ||
164 | /* return value: little endian */ | |
165 | static uint64_t ich9_cc_read(void *opaque, hwaddr addr, | |
166 | unsigned len) | |
167 | { | |
168 | ICH9LPCState *lpc = (ICH9LPCState *)opaque; | |
169 | ||
170 | uint32_t val = 0; | |
171 | ich9_cc_addr_len(&addr, &len); | |
172 | memcpy(&val, lpc->chip_config + addr, len); | |
173 | return val; | |
174 | } | |
175 | ||
176 | /* IRQ routing */ | |
177 | /* */ | |
178 | static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) | |
179 | { | |
180 | *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; | |
181 | *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; | |
182 | } | |
183 | ||
184 | static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, | |
185 | int *pic_irq, int *pic_dis) | |
186 | { | |
187 | switch (pirq_num) { | |
188 | case 0 ... 3: /* A-D */ | |
189 | ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], | |
190 | pic_irq, pic_dis); | |
191 | return; | |
192 | case 4 ... 7: /* E-H */ | |
193 | ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], | |
194 | pic_irq, pic_dis); | |
195 | return; | |
196 | default: | |
197 | break; | |
198 | } | |
199 | abort(); | |
200 | } | |
201 | ||
202 | /* pic_irq: i8254 irq 0-15 */ | |
203 | static void ich9_lpc_update_pic(ICH9LPCState *lpc, int pic_irq) | |
204 | { | |
205 | int i, pic_level; | |
206 | ||
207 | /* The pic level is the logical OR of all the PCI irqs mapped to it */ | |
208 | pic_level = 0; | |
209 | for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { | |
210 | int tmp_irq; | |
211 | int tmp_dis; | |
212 | ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); | |
213 | if (!tmp_dis && pic_irq == tmp_irq) { | |
214 | pic_level |= pci_bus_get_irq_level(lpc->d.bus, i); | |
215 | } | |
216 | } | |
217 | if (pic_irq == ich9_lpc_sci_irq(lpc)) { | |
218 | pic_level |= lpc->sci_level; | |
219 | } | |
220 | ||
221 | qemu_set_irq(lpc->pic[pic_irq], pic_level); | |
222 | } | |
223 | ||
224 | /* pirq: pirq[A-H] 0-7*/ | |
225 | static void ich9_lpc_update_by_pirq(ICH9LPCState *lpc, int pirq) | |
226 | { | |
227 | int pic_irq; | |
228 | int pic_dis; | |
229 | ||
230 | ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); | |
231 | assert(pic_irq < ICH9_LPC_PIC_NUM_PINS); | |
232 | if (pic_dis) { | |
233 | return; | |
234 | } | |
235 | ||
236 | ich9_lpc_update_pic(lpc, pic_irq); | |
237 | } | |
238 | ||
239 | /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ | |
240 | static int ich9_pirq_to_gsi(int pirq) | |
241 | { | |
242 | return pirq + ICH9_LPC_PIC_NUM_PINS; | |
243 | } | |
244 | ||
245 | static int ich9_gsi_to_pirq(int gsi) | |
246 | { | |
247 | return gsi - ICH9_LPC_PIC_NUM_PINS; | |
248 | } | |
249 | ||
250 | static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) | |
251 | { | |
243b9511 | 252 | int level = 0; |
4d00636e | 253 | |
243b9511 JK |
254 | if (gsi >= ICH9_LPC_PIC_NUM_PINS) { |
255 | level |= pci_bus_get_irq_level(lpc->d.bus, ich9_gsi_to_pirq(gsi)); | |
256 | } | |
4d00636e JB |
257 | if (gsi == ich9_lpc_sci_irq(lpc)) { |
258 | level |= lpc->sci_level; | |
259 | } | |
260 | ||
261 | qemu_set_irq(lpc->ioapic[gsi], level); | |
262 | } | |
263 | ||
264 | void ich9_lpc_set_irq(void *opaque, int pirq, int level) | |
265 | { | |
266 | ICH9LPCState *lpc = opaque; | |
267 | ||
268 | assert(0 <= pirq); | |
269 | assert(pirq < ICH9_LPC_NB_PIRQS); | |
270 | ||
271 | ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); | |
272 | ich9_lpc_update_by_pirq(lpc, pirq); | |
273 | } | |
274 | ||
275 | /* return the pirq number (PIRQ[A-H]:0-7) corresponding to | |
276 | * a given device irq pin. | |
277 | */ | |
278 | int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) | |
279 | { | |
280 | BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); | |
281 | PCIBus *pci_bus = PCI_BUS(bus); | |
282 | PCIDevice *lpc_pdev = | |
283 | pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; | |
284 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); | |
285 | ||
286 | return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; | |
287 | } | |
288 | ||
91c3f2f0 JB |
289 | PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) |
290 | { | |
291 | ICH9LPCState *lpc = opaque; | |
292 | PCIINTxRoute route; | |
293 | int pic_irq; | |
294 | int pic_dis; | |
295 | ||
296 | assert(0 <= pirq_pin); | |
297 | assert(pirq_pin < ICH9_LPC_NB_PIRQS); | |
298 | ||
299 | route.mode = PCI_INTX_ENABLED; | |
300 | ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); | |
301 | if (!pic_dis) { | |
302 | if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { | |
303 | route.irq = pic_irq; | |
304 | } else { | |
305 | route.mode = PCI_INTX_DISABLED; | |
306 | route.irq = -1; | |
307 | } | |
308 | } else { | |
309 | route.irq = ich9_pirq_to_gsi(pirq_pin); | |
310 | } | |
311 | ||
312 | return route; | |
313 | } | |
314 | ||
4d00636e JB |
315 | static int ich9_lpc_sci_irq(ICH9LPCState *lpc) |
316 | { | |
317 | switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] & | |
318 | ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) { | |
319 | case ICH9_LPC_ACPI_CTRL_9: | |
320 | return 9; | |
321 | case ICH9_LPC_ACPI_CTRL_10: | |
322 | return 10; | |
323 | case ICH9_LPC_ACPI_CTRL_11: | |
324 | return 11; | |
325 | case ICH9_LPC_ACPI_CTRL_20: | |
326 | return 20; | |
327 | case ICH9_LPC_ACPI_CTRL_21: | |
328 | return 21; | |
329 | default: | |
330 | /* reserved */ | |
331 | break; | |
332 | } | |
333 | return -1; | |
334 | } | |
335 | ||
336 | static void ich9_set_sci(void *opaque, int irq_num, int level) | |
337 | { | |
338 | ICH9LPCState *lpc = opaque; | |
339 | int irq; | |
340 | ||
341 | assert(irq_num == 0); | |
342 | level = !!level; | |
343 | if (level == lpc->sci_level) { | |
344 | return; | |
345 | } | |
346 | lpc->sci_level = level; | |
347 | ||
348 | irq = ich9_lpc_sci_irq(lpc); | |
349 | if (irq < 0) { | |
350 | return; | |
351 | } | |
352 | ||
353 | ich9_lpc_update_apic(lpc, irq); | |
354 | if (irq < ICH9_LPC_PIC_NUM_PINS) { | |
355 | ich9_lpc_update_pic(lpc, irq); | |
356 | } | |
357 | } | |
358 | ||
a3ac6b53 | 359 | void ich9_lpc_pm_init(PCIDevice *lpc_pci) |
4d00636e JB |
360 | { |
361 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); | |
362 | qemu_irq *sci_irq; | |
363 | ||
364 | sci_irq = qemu_allocate_irqs(ich9_set_sci, lpc, 1); | |
a3ac6b53 | 365 | ich9_pm_init(lpc_pci, &lpc->pm, sci_irq[0]); |
4d00636e JB |
366 | |
367 | ich9_lpc_reset(&lpc->d.qdev); | |
368 | } | |
369 | ||
370 | /* APM */ | |
371 | ||
372 | static void ich9_apm_ctrl_changed(uint32_t val, void *arg) | |
373 | { | |
374 | ICH9LPCState *lpc = arg; | |
375 | ||
376 | /* ACPI specs 3.0, 4.7.2.5 */ | |
377 | acpi_pm1_cnt_update(&lpc->pm.acpi_regs, | |
378 | val == ICH9_APM_ACPI_ENABLE, | |
379 | val == ICH9_APM_ACPI_DISABLE); | |
380 | ||
381 | /* SMI_EN = PMBASE + 30. SMI control and enable register */ | |
382 | if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { | |
182735ef | 383 | cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); |
4d00636e JB |
384 | } |
385 | } | |
386 | ||
387 | /* config:PMBASE */ | |
388 | static void | |
389 | ich9_lpc_pmbase_update(ICH9LPCState *lpc) | |
390 | { | |
391 | uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); | |
392 | pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; | |
393 | ||
394 | ich9_pm_iospace_update(&lpc->pm, pm_io_base); | |
395 | } | |
396 | ||
397 | /* config:RBCA */ | |
398 | static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rbca_old) | |
399 | { | |
400 | uint32_t rbca = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); | |
401 | ||
402 | if (rbca_old & ICH9_LPC_RCBA_EN) { | |
403 | memory_region_del_subregion(get_system_memory(), &lpc->rbca_mem); | |
404 | } | |
405 | if (rbca & ICH9_LPC_RCBA_EN) { | |
406 | memory_region_add_subregion_overlap(get_system_memory(), | |
407 | rbca & ICH9_LPC_RCBA_BA_MASK, | |
408 | &lpc->rbca_mem, 1); | |
409 | } | |
410 | } | |
411 | ||
412 | static int ich9_lpc_post_load(void *opaque, int version_id) | |
413 | { | |
414 | ICH9LPCState *lpc = opaque; | |
415 | ||
416 | ich9_lpc_pmbase_update(lpc); | |
417 | ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RBCA_EN */); | |
418 | return 0; | |
419 | } | |
420 | ||
421 | static void ich9_lpc_config_write(PCIDevice *d, | |
422 | uint32_t addr, uint32_t val, int len) | |
423 | { | |
424 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); | |
425 | uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA); | |
426 | ||
427 | pci_default_write_config(d, addr, val, len); | |
428 | if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4)) { | |
429 | ich9_lpc_pmbase_update(lpc); | |
430 | } | |
431 | if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { | |
432 | ich9_lpc_rcba_update(lpc, rbca_old); | |
433 | } | |
91c3f2f0 JB |
434 | if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { |
435 | pci_bus_fire_intx_routing_notifier(lpc->d.bus); | |
436 | } | |
437 | if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { | |
438 | pci_bus_fire_intx_routing_notifier(lpc->d.bus); | |
439 | } | |
4d00636e JB |
440 | } |
441 | ||
442 | static void ich9_lpc_reset(DeviceState *qdev) | |
443 | { | |
444 | PCIDevice *d = PCI_DEVICE(qdev); | |
445 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); | |
446 | uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA); | |
447 | int i; | |
448 | ||
449 | for (i = 0; i < 4; i++) { | |
450 | pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, | |
451 | ICH9_LPC_PIRQ_ROUT_DEFAULT); | |
452 | } | |
453 | for (i = 0; i < 4; i++) { | |
454 | pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, | |
455 | ICH9_LPC_PIRQ_ROUT_DEFAULT); | |
456 | } | |
457 | pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); | |
458 | ||
459 | pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); | |
460 | pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); | |
461 | ||
462 | ich9_cc_reset(lpc); | |
463 | ||
464 | ich9_lpc_pmbase_update(lpc); | |
465 | ich9_lpc_rcba_update(lpc, rbca_old); | |
466 | ||
467 | lpc->sci_level = 0; | |
0e98b436 | 468 | lpc->rst_cnt = 0; |
4d00636e JB |
469 | } |
470 | ||
471 | static const MemoryRegionOps rbca_mmio_ops = { | |
472 | .read = ich9_cc_read, | |
473 | .write = ich9_cc_write, | |
474 | .endianness = DEVICE_LITTLE_ENDIAN, | |
475 | }; | |
476 | ||
3f5bc9e8 GH |
477 | static void ich9_lpc_machine_ready(Notifier *n, void *opaque) |
478 | { | |
479 | ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); | |
b6f32962 | 480 | MemoryRegion *io_as = pci_address_space_io(&s->d); |
3f5bc9e8 GH |
481 | uint8_t *pci_conf; |
482 | ||
483 | pci_conf = s->d.config; | |
3ce10901 | 484 | if (memory_region_present(io_as, 0x3f8)) { |
3f5bc9e8 GH |
485 | /* com1 */ |
486 | pci_conf[0x82] |= 0x01; | |
487 | } | |
3ce10901 | 488 | if (memory_region_present(io_as, 0x2f8)) { |
3f5bc9e8 GH |
489 | /* com2 */ |
490 | pci_conf[0x82] |= 0x02; | |
491 | } | |
3ce10901 | 492 | if (memory_region_present(io_as, 0x378)) { |
3f5bc9e8 GH |
493 | /* lpt */ |
494 | pci_conf[0x82] |= 0x04; | |
495 | } | |
3ce10901 | 496 | if (memory_region_present(io_as, 0x3f0)) { |
3f5bc9e8 GH |
497 | /* floppy */ |
498 | pci_conf[0x82] |= 0x08; | |
499 | } | |
500 | } | |
501 | ||
0e98b436 LE |
502 | /* reset control */ |
503 | static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, | |
504 | unsigned len) | |
505 | { | |
506 | ICH9LPCState *lpc = opaque; | |
507 | ||
508 | if (val & 4) { | |
509 | qemu_system_reset_request(); | |
510 | return; | |
511 | } | |
512 | lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ | |
513 | } | |
514 | ||
515 | static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) | |
516 | { | |
517 | ICH9LPCState *lpc = opaque; | |
518 | ||
519 | return lpc->rst_cnt; | |
520 | } | |
521 | ||
522 | static const MemoryRegionOps ich9_rst_cnt_ops = { | |
523 | .read = ich9_rst_cnt_read, | |
524 | .write = ich9_rst_cnt_write, | |
525 | .endianness = DEVICE_LITTLE_ENDIAN | |
526 | }; | |
527 | ||
4d00636e JB |
528 | static int ich9_lpc_initfn(PCIDevice *d) |
529 | { | |
530 | ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); | |
531 | ISABus *isa_bus; | |
532 | ||
533 | isa_bus = isa_bus_new(&d->qdev, get_system_io()); | |
534 | ||
535 | pci_set_long(d->wmask + ICH9_LPC_PMBASE, | |
536 | ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); | |
537 | ||
1437c94b | 538 | memory_region_init_io(&lpc->rbca_mem, OBJECT(d), &rbca_mmio_ops, lpc, |
4d00636e JB |
539 | "lpc-rbca-mmio", ICH9_CC_SIZE); |
540 | ||
541 | lpc->isa_bus = isa_bus; | |
542 | ||
543 | ich9_cc_init(lpc); | |
42d8a3cf | 544 | apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); |
3f5bc9e8 GH |
545 | |
546 | lpc->machine_ready.notify = ich9_lpc_machine_ready; | |
547 | qemu_add_machine_init_done_notifier(&lpc->machine_ready); | |
548 | ||
1437c94b | 549 | memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, |
0e98b436 LE |
550 | "lpc-reset-control", 1); |
551 | memory_region_add_subregion_overlap(pci_address_space_io(d), | |
552 | ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, | |
553 | 1); | |
554 | ||
4d00636e JB |
555 | return 0; |
556 | } | |
557 | ||
0e98b436 LE |
558 | static bool ich9_rst_cnt_needed(void *opaque) |
559 | { | |
560 | ICH9LPCState *lpc = opaque; | |
561 | ||
562 | return (lpc->rst_cnt != 0); | |
563 | } | |
564 | ||
565 | static const VMStateDescription vmstate_ich9_rst_cnt = { | |
566 | .name = "ICH9LPC/rst_cnt", | |
567 | .version_id = 1, | |
568 | .minimum_version_id = 1, | |
569 | .fields = (VMStateField[]) { | |
570 | VMSTATE_UINT8(rst_cnt, ICH9LPCState), | |
571 | VMSTATE_END_OF_LIST() | |
572 | } | |
573 | }; | |
574 | ||
4d00636e JB |
575 | static const VMStateDescription vmstate_ich9_lpc = { |
576 | .name = "ICH9LPC", | |
577 | .version_id = 1, | |
578 | .minimum_version_id = 1, | |
579 | .minimum_version_id_old = 1, | |
580 | .post_load = ich9_lpc_post_load, | |
581 | .fields = (VMStateField[]) { | |
582 | VMSTATE_PCI_DEVICE(d, ICH9LPCState), | |
583 | VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), | |
584 | VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), | |
585 | VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), | |
586 | VMSTATE_UINT32(sci_level, ICH9LPCState), | |
587 | VMSTATE_END_OF_LIST() | |
0e98b436 LE |
588 | }, |
589 | .subsections = (VMStateSubsection[]) { | |
590 | { | |
591 | .vmsd = &vmstate_ich9_rst_cnt, | |
592 | .needed = ich9_rst_cnt_needed | |
593 | }, | |
594 | { 0 } | |
4d00636e JB |
595 | } |
596 | }; | |
597 | ||
598 | static void ich9_lpc_class_init(ObjectClass *klass, void *data) | |
599 | { | |
600 | DeviceClass *dc = DEVICE_CLASS(klass); | |
601 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
602 | ||
603 | dc->reset = ich9_lpc_reset; | |
604 | k->init = ich9_lpc_initfn; | |
605 | dc->vmsd = &vmstate_ich9_lpc; | |
606 | dc->no_user = 1; | |
607 | k->config_write = ich9_lpc_config_write; | |
608 | dc->desc = "ICH9 LPC bridge"; | |
609 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
610 | k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; | |
611 | k->revision = ICH9_A2_LPC_REVISION; | |
612 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
613 | ||
614 | } | |
615 | ||
616 | static const TypeInfo ich9_lpc_info = { | |
617 | .name = TYPE_ICH9_LPC_DEVICE, | |
618 | .parent = TYPE_PCI_DEVICE, | |
619 | .instance_size = sizeof(struct ICH9LPCState), | |
620 | .class_init = ich9_lpc_class_init, | |
621 | }; | |
622 | ||
623 | static void ich9_lpc_register(void) | |
624 | { | |
625 | type_register_static(&ich9_lpc_info); | |
626 | } | |
627 | ||
628 | type_init(ich9_lpc_register); |