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94e1a912 GH |
1 | /* |
2 | * QEMU AMD PC-Net II (Am79C970A) emulation | |
3 | * | |
4 | * Copyright (c) 2004 Antony T Curtis | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | /* This software was written to be compatible with the specification: | |
26 | * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet | |
27 | * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 | |
28 | */ | |
29 | ||
30 | /* | |
31 | * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also | |
32 | * produced as NCR89C100. See | |
33 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt | |
34 | * and | |
35 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt | |
36 | */ | |
37 | ||
38 | #include "sysbus.h" | |
39 | #include "net.h" | |
40 | #include "qemu-timer.h" | |
41 | #include "qemu_socket.h" | |
42 | #include "sun4m.h" | |
43 | ||
44 | #include "pcnet.h" | |
45 | ||
46 | typedef struct { | |
47 | SysBusDevice busdev; | |
48 | PCNetState state; | |
49 | } SysBusPCNetState; | |
50 | ||
51 | static void parent_lance_reset(void *opaque, int irq, int level) | |
52 | { | |
53 | SysBusPCNetState *d = opaque; | |
54 | if (level) | |
55 | pcnet_h_reset(&d->state); | |
56 | } | |
57 | ||
58 | static void lance_mem_writew(void *opaque, target_phys_addr_t addr, | |
59 | uint32_t val) | |
60 | { | |
61 | SysBusPCNetState *d = opaque; | |
62 | #ifdef PCNET_DEBUG_IO | |
63 | printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr, | |
64 | val & 0xffff); | |
65 | #endif | |
66 | pcnet_ioport_writew(&d->state, addr, val & 0xffff); | |
67 | } | |
68 | ||
69 | static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr) | |
70 | { | |
71 | SysBusPCNetState *d = opaque; | |
72 | uint32_t val; | |
73 | ||
74 | val = pcnet_ioport_readw(&d->state, addr); | |
75 | #ifdef PCNET_DEBUG_IO | |
76 | printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr, | |
77 | val & 0xffff); | |
78 | #endif | |
79 | ||
80 | return val & 0xffff; | |
81 | } | |
82 | ||
83 | static CPUReadMemoryFunc * const lance_mem_read[3] = { | |
84 | NULL, | |
85 | lance_mem_readw, | |
86 | NULL, | |
87 | }; | |
88 | ||
89 | static CPUWriteMemoryFunc * const lance_mem_write[3] = { | |
90 | NULL, | |
91 | lance_mem_writew, | |
92 | NULL, | |
93 | }; | |
94 | ||
1fa51482 | 95 | static void lance_cleanup(VLANClientState *nc) |
94e1a912 | 96 | { |
1fa51482 | 97 | PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque; |
94e1a912 | 98 | |
3d865059 | 99 | vmstate_unregister(&vmstate_pcnet, d); |
94e1a912 GH |
100 | pcnet_common_cleanup(d); |
101 | } | |
102 | ||
1fa51482 MM |
103 | static NetClientInfo net_lance_info = { |
104 | .type = NET_CLIENT_TYPE_NIC, | |
105 | .size = sizeof(NICState), | |
106 | .can_receive = pcnet_can_receive, | |
107 | .receive = pcnet_receive, | |
108 | .cleanup = lance_cleanup, | |
109 | }; | |
110 | ||
94e1a912 GH |
111 | static int lance_init(SysBusDevice *dev) |
112 | { | |
113 | SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev); | |
114 | PCNetState *s = &d->state; | |
115 | ||
116 | s->mmio_index = | |
117 | cpu_register_io_memory(lance_mem_read, lance_mem_write, d); | |
118 | ||
119 | qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1); | |
120 | ||
121 | sysbus_init_mmio(dev, 4, s->mmio_index); | |
122 | ||
123 | sysbus_init_irq(dev, &s->irq); | |
124 | ||
125 | s->phys_mem_read = ledma_memory_read; | |
126 | s->phys_mem_write = ledma_memory_write; | |
127 | ||
3d865059 | 128 | vmstate_register(-1, &vmstate_pcnet, d); |
1fa51482 | 129 | return pcnet_common_init(&dev->qdev, s, &net_lance_info); |
94e1a912 GH |
130 | } |
131 | ||
132 | static void lance_reset(DeviceState *dev) | |
133 | { | |
134 | SysBusPCNetState *d = DO_UPCAST(SysBusPCNetState, busdev.qdev, dev); | |
135 | ||
136 | pcnet_h_reset(&d->state); | |
137 | } | |
138 | ||
139 | static SysBusDeviceInfo lance_info = { | |
140 | .init = lance_init, | |
141 | .qdev.name = "lance", | |
142 | .qdev.size = sizeof(SysBusPCNetState), | |
143 | .qdev.reset = lance_reset, | |
144 | .qdev.props = (Property[]) { | |
145 | DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque), | |
146 | DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf), | |
147 | DEFINE_PROP_END_OF_LIST(), | |
148 | } | |
149 | }; | |
150 | ||
151 | static void lance_register_devices(void) | |
152 | { | |
153 | sysbus_register_withprop(&lance_info); | |
154 | } | |
155 | device_init(lance_register_devices) |