[qemu.git] / hw / lm32_boards.c

/*
 *  QEMU models for LatticeMico32 uclinux and evr32 boards.
 *
 *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "sysbus.h"
#include "hw.h"
#include "net.h"
#include "flash.h"
#include "devices.h"
#include "boards.h"
#include "loader.h"
#include "blockdev.h"
#include "elf.h"
#include "lm32_hwsetup.h"
#include "lm32.h"

typedef struct {
    CPUState *env;
    target_phys_addr_t bootstrap_pc;
    target_phys_addr_t flash_base;
    target_phys_addr_t hwsetup_base;
    target_phys_addr_t initrd_base;
    size_t initrd_size;
    target_phys_addr_t cmdline_base;
} ResetInfo;

static void cpu_irq_handler(void *opaque, int irq, int level)
{
    CPUState *env = opaque;

    if (level) {
        cpu_interrupt(env, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
    }
}

static void main_cpu_reset(void *opaque)
{
    ResetInfo *reset_info = opaque;
    CPUState *env = reset_info->env;

    cpu_reset(env);

    /* init defaults */
    env->pc = (uint32_t)reset_info->bootstrap_pc;
    env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
    env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
    env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
    env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
        reset_info->initrd_size);
    env->eba = reset_info->flash_base;
    env->deba = reset_info->flash_base;
}

static void lm32_evr_init(ram_addr_t ram_size_not_used,
                          const char *boot_device,
                          const char *kernel_filename,
                          const char *kernel_cmdline,
                          const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    DriveInfo *dinfo;
    ram_addr_t phys_ram;
    qemu_irq *cpu_irq, irq[32];
    ResetInfo *reset_info;
    int i;

    /* memory map */
    target_phys_addr_t flash_base  = 0x04000000;
    size_t flash_sector_size       = 256 * 1024;
    size_t flash_size              = 32 * 1024 * 1024;
    target_phys_addr_t ram_base    = 0x08000000;
    size_t ram_size                = 64 * 1024 * 1024;
    target_phys_addr_t timer0_base = 0x80002000;
    target_phys_addr_t uart0_base  = 0x80006000;
    target_phys_addr_t timer1_base = 0x8000a000;
    int uart0_irq                  = 0;
    int timer0_irq                 = 1;
    int timer1_irq                 = 3;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    env = cpu_init(cpu_model);
    reset_info->env = env;

    reset_info->flash_base = flash_base;

    phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size);
    cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
                          dinfo ? dinfo->bdrv : NULL, flash_sector_size,
                          flash_size / flash_sector_size, 1, 2,
                          0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
    env->pic_state = lm32_pic_init(*cpu_irq);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, ELF_MACHINE, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
                          const char *boot_device,
                          const char *kernel_filename,
                          const char *kernel_cmdline,
                          const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    DriveInfo *dinfo;
    ram_addr_t phys_ram;
    qemu_irq *cpu_irq, irq[32];
    HWSetup *hw;
    ResetInfo *reset_info;
    int i;

    /* memory map */
    target_phys_addr_t flash_base   = 0x04000000;
    size_t flash_sector_size        = 256 * 1024;
    size_t flash_size               = 32 * 1024 * 1024;
    target_phys_addr_t ram_base     = 0x08000000;
    size_t ram_size                 = 64 * 1024 * 1024;
    target_phys_addr_t uart0_base   = 0x80000000;
    target_phys_addr_t timer0_base  = 0x80002000;
    target_phys_addr_t timer1_base  = 0x80010000;
    target_phys_addr_t timer2_base  = 0x80012000;
    int uart0_irq                   = 0;
    int timer0_irq                  = 1;
    int timer1_irq                  = 20;
    int timer2_irq                  = 21;
    target_phys_addr_t hwsetup_base = 0x0bffe000;
    target_phys_addr_t cmdline_base = 0x0bfff000;
    target_phys_addr_t initrd_base  = 0x08400000;
    size_t initrd_max               = 0x01000000;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    env = cpu_init(cpu_model);
    reset_info->env = env;

    reset_info->flash_base = flash_base;

    phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size);
    cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
                          dinfo ? dinfo->bdrv : NULL, flash_sector_size,
                          flash_size / flash_sector_size, 1, 2,
                          0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
    env->pic_state = lm32_pic_init(*cpu_irq);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
    sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, ELF_MACHINE, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    /* generate a rom with the hardware description */
    hw = hwsetup_init();
    hwsetup_add_cpu(hw, "LM32", 75000000);
    hwsetup_add_flash(hw, "flash", flash_base, flash_size);
    hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
    hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
    hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
    hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
    hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
    hwsetup_add_trailer(hw);
    hwsetup_create_rom(hw, hwsetup_base);
    hwsetup_free(hw);

    reset_info->hwsetup_base = hwsetup_base;

    if (kernel_cmdline && strlen(kernel_cmdline)) {
        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
                kernel_cmdline);
        reset_info->cmdline_base = cmdline_base;
    }

    if (initrd_filename) {
        size_t initrd_size;
        initrd_size = load_image_targphys(initrd_filename, initrd_base,
                initrd_max);
        reset_info->initrd_base = initrd_base;
        reset_info->initrd_size = initrd_size;
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static QEMUMachine lm32_evr_machine = {
    .name = "lm32-evr",
    .desc = "LatticeMico32 EVR32 eval system",
    .init = lm32_evr_init,
    .is_default = 1
};

static QEMUMachine lm32_uclinux_machine = {
    .name = "lm32-uclinux",
    .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
    .init = lm32_uclinux_init,
    .is_default = 0
};

static void lm32_machine_init(void)
{
    qemu_register_machine(&lm32_uclinux_machine);
    qemu_register_machine(&lm32_evr_machine);
}

machine_init(lm32_machine_init);
Commit	Line	Data
d821732a MW	1	/*
	2	* QEMU models for LatticeMico32 uclinux and evr32 boards.
	3	*
	4	* Copyright (c) 2010 Michael Walle <michael@walle.cc>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "sysbus.h"
	21	#include "hw.h"
	22	#include "net.h"
	23	#include "flash.h"
d821732a MW	24	#include "devices.h"
	25	#include "boards.h"
	26	#include "loader.h"
	27	#include "blockdev.h"
	28	#include "elf.h"
	29	#include "lm32_hwsetup.h"
	30	#include "lm32.h"
	31
	32	typedef struct {
	33	CPUState *env;
	34	target_phys_addr_t bootstrap_pc;
	35	target_phys_addr_t flash_base;
	36	target_phys_addr_t hwsetup_base;
	37	target_phys_addr_t initrd_base;
	38	size_t initrd_size;
	39	target_phys_addr_t cmdline_base;
	40	} ResetInfo;
	41
	42	static void cpu_irq_handler(void *opaque, int irq, int level)
	43	{
	44	CPUState *env = opaque;
	45
	46	if (level) {
	47	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	48	} else {
	49	cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
	50	}
	51	}
	52
	53	static void main_cpu_reset(void *opaque)
	54	{
	55	ResetInfo *reset_info = opaque;
	56	CPUState *env = reset_info->env;
	57
	58	cpu_reset(env);
	59
	60	/* init defaults */
	61	env->pc = (uint32_t)reset_info->bootstrap_pc;
	62	env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
	63	env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
	64	env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
	65	env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
	66	reset_info->initrd_size);
	67	env->eba = reset_info->flash_base;
	68	env->deba = reset_info->flash_base;
	69	}
	70
	71	static void lm32_evr_init(ram_addr_t ram_size_not_used,
	72	const char *boot_device,
	73	const char *kernel_filename,
	74	const char *kernel_cmdline,
	75	const char initrd_filename, const char cpu_model)
	76	{
	77	CPUState *env;
	78	DriveInfo *dinfo;
01e0451a	79	ram_addr_t phys_ram;
d821732a MW	80	qemu_irq *cpu_irq, irq[32];
	81	ResetInfo *reset_info;
	82	int i;
	83
	84	/* memory map */
	85	target_phys_addr_t flash_base = 0x04000000;
	86	size_t flash_sector_size = 256 * 1024;
	87	size_t flash_size = 32 * 1024 * 1024;
	88	target_phys_addr_t ram_base = 0x08000000;
	89	size_t ram_size = 64 * 1024 * 1024;
	90	target_phys_addr_t timer0_base = 0x80002000;
	91	target_phys_addr_t uart0_base = 0x80006000;
	92	target_phys_addr_t timer1_base = 0x8000a000;
	93	int uart0_irq = 0;
	94	int timer0_irq = 1;
	95	int timer1_irq = 3;
	96
7267c094	97	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	98
	99	if (cpu_model == NULL) {
	100	cpu_model = "lm32-full";
	101	}
	102	env = cpu_init(cpu_model);
	103	reset_info->env = env;
	104
	105	reset_info->flash_base = flash_base;
	106
01e0451a AL	107	phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size);
01e0451a AL	108	cpu_register_physical_memory(ram_base, ram_size, phys_ram \| IO_MEM_RAM);
d821732a	109
d821732a MW	110	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	111	/* Spansion S29NS128P */
cfe5f011	112	pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
d821732a MW	113	dinfo ? dinfo->bdrv : NULL, flash_sector_size,
d821732a MW	114	flash_size / flash_sector_size, 1, 2,
01e0451a	115	0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	116
	117	/* create irq lines */
	118	cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
	119	env->pic_state = lm32_pic_init(*cpu_irq);
	120	for (i = 0; i < 32; i++) {
	121	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	122	}
	123
	124	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
	125	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	126	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	127
	128	/* make sure juart isn't the first chardev */
	129	env->juart_state = lm32_juart_init();
	130
	131	reset_info->bootstrap_pc = flash_base;
	132
	133	if (kernel_filename) {
	134	uint64_t entry;
	135	int kernel_size;
	136
	137	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
	138	1, ELF_MACHINE, 0);
	139	reset_info->bootstrap_pc = entry;
	140
	141	if (kernel_size < 0) {
	142	kernel_size = load_image_targphys(kernel_filename, ram_base,
	143	ram_size);
	144	reset_info->bootstrap_pc = ram_base;
	145	}
	146
	147	if (kernel_size < 0) {
	148	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	149	kernel_filename);
	150	exit(1);
	151	}
	152	}
	153
	154	qemu_register_reset(main_cpu_reset, reset_info);
	155	}
	156
	157	static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
	158	const char *boot_device,
	159	const char *kernel_filename,
	160	const char *kernel_cmdline,
	161	const char initrd_filename, const char cpu_model)
	162	{
	163	CPUState *env;
	164	DriveInfo *dinfo;
01e0451a	165	ram_addr_t phys_ram;
d821732a MW	166	qemu_irq *cpu_irq, irq[32];
	167	HWSetup *hw;
	168	ResetInfo *reset_info;
	169	int i;
	170
	171	/* memory map */
	172	target_phys_addr_t flash_base = 0x04000000;
	173	size_t flash_sector_size = 256 * 1024;
	174	size_t flash_size = 32 * 1024 * 1024;
	175	target_phys_addr_t ram_base = 0x08000000;
	176	size_t ram_size = 64 * 1024 * 1024;
	177	target_phys_addr_t uart0_base = 0x80000000;
	178	target_phys_addr_t timer0_base = 0x80002000;
	179	target_phys_addr_t timer1_base = 0x80010000;
	180	target_phys_addr_t timer2_base = 0x80012000;
	181	int uart0_irq = 0;
	182	int timer0_irq = 1;
	183	int timer1_irq = 20;
	184	int timer2_irq = 21;
	185	target_phys_addr_t hwsetup_base = 0x0bffe000;
	186	target_phys_addr_t cmdline_base = 0x0bfff000;
	187	target_phys_addr_t initrd_base = 0x08400000;
	188	size_t initrd_max = 0x01000000;
	189
7267c094	190	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	191
	192	if (cpu_model == NULL) {
	193	cpu_model = "lm32-full";
	194	}
	195	env = cpu_init(cpu_model);
	196	reset_info->env = env;
	197
	198	reset_info->flash_base = flash_base;
	199
01e0451a AL	200	phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size);
01e0451a AL	201	cpu_register_physical_memory(ram_base, ram_size, phys_ram \| IO_MEM_RAM);
d821732a	202
d821732a MW	203	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	204	/* Spansion S29NS128P */
cfe5f011	205	pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
d821732a MW	206	dinfo ? dinfo->bdrv : NULL, flash_sector_size,
d821732a MW	207	flash_size / flash_sector_size, 1, 2,
01e0451a	208	0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	209
	210	/* create irq lines */
	211	cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
	212	env->pic_state = lm32_pic_init(*cpu_irq);
	213	for (i = 0; i < 32; i++) {
	214	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	215	}
	216
	217	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
	218	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	219	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	220	sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
	221
	222	/* make sure juart isn't the first chardev */
	223	env->juart_state = lm32_juart_init();
	224
	225	reset_info->bootstrap_pc = flash_base;
	226
	227	if (kernel_filename) {
	228	uint64_t entry;
	229	int kernel_size;
	230
	231	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
	232	1, ELF_MACHINE, 0);
	233	reset_info->bootstrap_pc = entry;
	234
	235	if (kernel_size < 0) {
	236	kernel_size = load_image_targphys(kernel_filename, ram_base,
	237	ram_size);
	238	reset_info->bootstrap_pc = ram_base;
	239	}
	240
	241	if (kernel_size < 0) {
	242	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	243	kernel_filename);
	244	exit(1);
	245	}
	246	}
	247
	248	/* generate a rom with the hardware description */
	249	hw = hwsetup_init();
	250	hwsetup_add_cpu(hw, "LM32", 75000000);
	251	hwsetup_add_flash(hw, "flash", flash_base, flash_size);
	252	hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
	253	hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
	254	hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
	255	hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
	256	hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
	257	hwsetup_add_trailer(hw);
	258	hwsetup_create_rom(hw, hwsetup_base);
	259	hwsetup_free(hw);
	260
	261	reset_info->hwsetup_base = hwsetup_base;
	262
	263	if (kernel_cmdline && strlen(kernel_cmdline)) {
	264	pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
	265	kernel_cmdline);
	266	reset_info->cmdline_base = cmdline_base;
	267	}
	268
	269	if (initrd_filename) {
	270	size_t initrd_size;
	271	initrd_size = load_image_targphys(initrd_filename, initrd_base,
	272	initrd_max);
273	reset_info->initrd_base = initrd_base;
274	reset_info->initrd_size = initrd_size;
275	}
276
277	qemu_register_reset(main_cpu_reset, reset_info);
278	}
279
280	static QEMUMachine lm32_evr_machine = {
281	.name = "lm32-evr",
282	.desc = "LatticeMico32 EVR32 eval system",
283	.init = lm32_evr_init,
284	.is_default = 1
285	};
286
287	static QEMUMachine lm32_uclinux_machine = {
288	.name = "lm32-uclinux",
289	.desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
290	.init = lm32_uclinux_init,
291	.is_default = 0
292	};
293
294	static void lm32_machine_init(void)
295	{
296	qemu_register_machine(&lm32_uclinux_machine);
297	qemu_register_machine(&lm32_evr_machine);
298	}
299
300	machine_init(lm32_machine_init);