[qemu.git] / hw / m25p80.c

/*
 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
 * set. Known devices table current as of Jun/2012 and taken from linux.
 * See drivers/mtd/devices/m25p80.c.
 *
 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
 * Copyright (C) 2012 PetaLogix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) a later version of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "hw.h"
#include "sysemu/blockdev.h"
#include "ssi.h"
#include "devices.h"

#ifdef M25P80_ERR_DEBUG
#define DB_PRINT(...) do { \
    fprintf(stderr,  ": %s: ", __func__); \
    fprintf(stderr, ## __VA_ARGS__); \
    } while (0);
#else
    #define DB_PRINT(...)
#endif

/* Fields for FlashPartInfo->flags */

/* erase capabilities */
#define ER_4K 1
#define ER_32K 2
/* set to allow the page program command to write 0s back to 1. Useful for
 * modelling EEPROM with SPI flash command set
 */
#define WR_1 0x100

typedef struct FlashPartInfo {
    const char *part_name;
    /* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */
    uint32_t jedec;
    /* extended jedec code */
    uint16_t ext_jedec;
    /* there is confusion between manufacturers as to what a sector is. In this
     * device model, a "sector" is the size that is erased by the ERASE_SECTOR
     * command (opcode 0xd8).
     */
    uint32_t sector_size;
    uint32_t n_sectors;
    uint32_t page_size;
    uint8_t flags;
} FlashPartInfo;

/* adapted from linux */

#define INFO(_part_name, _jedec, _ext_jedec, _sector_size, _n_sectors, _flags)\
    .part_name = (_part_name),\
    .jedec = (_jedec),\
    .ext_jedec = (_ext_jedec),\
    .sector_size = (_sector_size),\
    .n_sectors = (_n_sectors),\
    .page_size = 256,\
    .flags = (_flags),\

#define JEDEC_NUMONYX 0x20
#define JEDEC_WINBOND 0xEF
#define JEDEC_SPANSION 0x01

static const FlashPartInfo known_devices[] = {
    /* Atmel -- some are (confusingly) marketed as "DataFlash" */
    { INFO("at25fs010",   0x1f6601,      0,  32 << 10,   4, ER_4K) },
    { INFO("at25fs040",   0x1f6604,      0,  64 << 10,   8, ER_4K) },

    { INFO("at25df041a",  0x1f4401,      0,  64 << 10,   8, ER_4K) },
    { INFO("at25df321a",  0x1f4701,      0,  64 << 10,  64, ER_4K) },
    { INFO("at25df641",   0x1f4800,      0,  64 << 10, 128, ER_4K) },

    { INFO("at26f004",    0x1f0400,      0,  64 << 10,   8, ER_4K) },
    { INFO("at26df081a",  0x1f4501,      0,  64 << 10,  16, ER_4K) },
    { INFO("at26df161a",  0x1f4601,      0,  64 << 10,  32, ER_4K) },
    { INFO("at26df321",   0x1f4700,      0,  64 << 10,  64, ER_4K) },

    /* EON -- en25xxx */
    { INFO("en25f32",     0x1c3116,      0,  64 << 10,  64, ER_4K) },
    { INFO("en25p32",     0x1c2016,      0,  64 << 10,  64, 0) },
    { INFO("en25q32b",    0x1c3016,      0,  64 << 10,  64, 0) },
    { INFO("en25p64",     0x1c2017,      0,  64 << 10, 128, 0) },

    /* Intel/Numonyx -- xxxs33b */
    { INFO("160s33b",     0x898911,      0,  64 << 10,  32, 0) },
    { INFO("320s33b",     0x898912,      0,  64 << 10,  64, 0) },
    { INFO("640s33b",     0x898913,      0,  64 << 10, 128, 0) },

    /* Macronix */
    { INFO("mx25l4005a",  0xc22013,      0,  64 << 10,   8, ER_4K) },
    { INFO("mx25l8005",   0xc22014,      0,  64 << 10,  16, 0) },
    { INFO("mx25l1606e",  0xc22015,      0,  64 << 10,  32, ER_4K) },
    { INFO("mx25l3205d",  0xc22016,      0,  64 << 10,  64, 0) },
    { INFO("mx25l6405d",  0xc22017,      0,  64 << 10, 128, 0) },
    { INFO("mx25l12805d", 0xc22018,      0,  64 << 10, 256, 0) },
    { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
    { INFO("mx25l25635e", 0xc22019,      0,  64 << 10, 512, 0) },
    { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },

    /* Spansion -- single (large) sector size only, at least
     * for the chips listed here (without boot sectors).
     */
    { INFO("s25sl004a",   0x010212,      0,  64 << 10,   8, 0) },
    { INFO("s25sl008a",   0x010213,      0,  64 << 10,  16, 0) },
    { INFO("s25sl016a",   0x010214,      0,  64 << 10,  32, 0) },
    { INFO("s25sl032a",   0x010215,      0,  64 << 10,  64, 0) },
    { INFO("s25sl032p",   0x010215, 0x4d00,  64 << 10,  64, ER_4K) },
    { INFO("s25sl064a",   0x010216,      0,  64 << 10, 128, 0) },
    { INFO("s25fl256s0",  0x010219, 0x4d00, 256 << 10, 128, 0) },
    { INFO("s25fl256s1",  0x010219, 0x4d01,  64 << 10, 512, 0) },
    { INFO("s25fl512s",   0x010220, 0x4d00, 256 << 10, 256, 0) },
    { INFO("s70fl01gs",   0x010221, 0x4d00, 256 << 10, 256, 0) },
    { INFO("s25sl12800",  0x012018, 0x0300, 256 << 10,  64, 0) },
    { INFO("s25sl12801",  0x012018, 0x0301,  64 << 10, 256, 0) },
    { INFO("s25fl129p0",  0x012018, 0x4d00, 256 << 10,  64, 0) },
    { INFO("s25fl129p1",  0x012018, 0x4d01,  64 << 10, 256, 0) },
    { INFO("s25fl016k",   0xef4015,      0,  64 << 10,  32, ER_4K | ER_32K) },
    { INFO("s25fl064k",   0xef4017,      0,  64 << 10, 128, ER_4K | ER_32K) },

    /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
    { INFO("sst25vf040b", 0xbf258d,      0,  64 << 10,   8, ER_4K) },
    { INFO("sst25vf080b", 0xbf258e,      0,  64 << 10,  16, ER_4K) },
    { INFO("sst25vf016b", 0xbf2541,      0,  64 << 10,  32, ER_4K) },
    { INFO("sst25vf032b", 0xbf254a,      0,  64 << 10,  64, ER_4K) },
    { INFO("sst25wf512",  0xbf2501,      0,  64 << 10,   1, ER_4K) },
    { INFO("sst25wf010",  0xbf2502,      0,  64 << 10,   2, ER_4K) },
    { INFO("sst25wf020",  0xbf2503,      0,  64 << 10,   4, ER_4K) },
    { INFO("sst25wf040",  0xbf2504,      0,  64 << 10,   8, ER_4K) },

    /* ST Microelectronics -- newer production may have feature updates */
    { INFO("m25p05",      0x202010,      0,  32 << 10,   2, 0) },
    { INFO("m25p10",      0x202011,      0,  32 << 10,   4, 0) },
    { INFO("m25p20",      0x202012,      0,  64 << 10,   4, 0) },
    { INFO("m25p40",      0x202013,      0,  64 << 10,   8, 0) },
    { INFO("m25p80",      0x202014,      0,  64 << 10,  16, 0) },
    { INFO("m25p16",      0x202015,      0,  64 << 10,  32, 0) },
    { INFO("m25p32",      0x202016,      0,  64 << 10,  64, 0) },
    { INFO("m25p64",      0x202017,      0,  64 << 10, 128, 0) },
    { INFO("m25p128",     0x202018,      0, 256 << 10,  64, 0) },

    { INFO("m45pe10",     0x204011,      0,  64 << 10,   2, 0) },
    { INFO("m45pe80",     0x204014,      0,  64 << 10,  16, 0) },
    { INFO("m45pe16",     0x204015,      0,  64 << 10,  32, 0) },

    { INFO("m25pe80",     0x208014,      0,  64 << 10,  16, 0) },
    { INFO("m25pe16",     0x208015,      0,  64 << 10,  32, ER_4K) },

    { INFO("m25px32",     0x207116,      0,  64 << 10,  64, ER_4K) },
    { INFO("m25px32-s0",  0x207316,      0,  64 << 10,  64, ER_4K) },
    { INFO("m25px32-s1",  0x206316,      0,  64 << 10,  64, ER_4K) },
    { INFO("m25px64",     0x207117,      0,  64 << 10, 128, 0) },

    /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
    { INFO("w25x10",      0xef3011,      0,  64 << 10,   2, ER_4K) },
    { INFO("w25x20",      0xef3012,      0,  64 << 10,   4, ER_4K) },
    { INFO("w25x40",      0xef3013,      0,  64 << 10,   8, ER_4K) },
    { INFO("w25x80",      0xef3014,      0,  64 << 10,  16, ER_4K) },
    { INFO("w25x16",      0xef3015,      0,  64 << 10,  32, ER_4K) },
    { INFO("w25x32",      0xef3016,      0,  64 << 10,  64, ER_4K) },
    { INFO("w25q32",      0xef4016,      0,  64 << 10,  64, ER_4K) },
    { INFO("w25x64",      0xef3017,      0,  64 << 10, 128, ER_4K) },
    { INFO("w25q64",      0xef4017,      0,  64 << 10, 128, ER_4K) },

    /* Numonyx -- n25q128 */
    { INFO("n25q128",      0x20ba18,      0,  64 << 10, 256, 0) },

    { },
};

typedef enum {
    NOP = 0,
    WRSR = 0x1,
    WRDI = 0x4,
    RDSR = 0x5,
    WREN = 0x6,
    JEDEC_READ = 0x9f,
    BULK_ERASE = 0xc7,

    READ = 0x3,
    FAST_READ = 0xb,
    DOR = 0x3b,
    QOR = 0x6b,
    DIOR = 0xbb,
    QIOR = 0xeb,

    PP = 0x2,
    DPP = 0xa2,
    QPP = 0x32,

    ERASE_4K = 0x20,
    ERASE_32K = 0x52,
    ERASE_SECTOR = 0xd8,
} FlashCMD;

typedef enum {
    STATE_IDLE,
    STATE_PAGE_PROGRAM,
    STATE_READ,
    STATE_COLLECTING_DATA,
    STATE_READING_DATA,
} CMDState;

typedef struct Flash {
    SSISlave ssidev;
    uint32_t r;

    BlockDriverState *bdrv;

    uint8_t *storage;
    uint32_t size;
    int page_size;

    uint8_t state;
    uint8_t data[16];
    uint32_t len;
    uint32_t pos;
    uint8_t needed_bytes;
    uint8_t cmd_in_progress;
    uint64_t cur_addr;
    bool write_enable;

    int64_t dirty_page;

    char *part_name;
    const FlashPartInfo *pi;

} Flash;

static void bdrv_sync_complete(void *opaque, int ret)
{
    /* do nothing. Masters do not directly interact with the backing store,
     * only the working copy so no mutexing required.
     */
}

static void flash_sync_page(Flash *s, int page)
{
    if (s->bdrv) {
        int bdrv_sector, nb_sectors;
        QEMUIOVector iov;

        bdrv_sector = (page * s->pi->page_size) / BDRV_SECTOR_SIZE;
        nb_sectors = DIV_ROUND_UP(s->pi->page_size, BDRV_SECTOR_SIZE);
        qemu_iovec_init(&iov, 1);
        qemu_iovec_add(&iov, s->storage + bdrv_sector * BDRV_SECTOR_SIZE,
                                                nb_sectors * BDRV_SECTOR_SIZE);
        bdrv_aio_writev(s->bdrv, bdrv_sector, &iov, nb_sectors,
                                                bdrv_sync_complete, NULL);
    }
}

static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
{
    int64_t start, end, nb_sectors;
    QEMUIOVector iov;

    if (!s->bdrv) {
        return;
    }

    assert(!(len % BDRV_SECTOR_SIZE));
    start = off / BDRV_SECTOR_SIZE;
    end = (off + len) / BDRV_SECTOR_SIZE;
    nb_sectors = end - start;
    qemu_iovec_init(&iov, 1);
    qemu_iovec_add(&iov, s->storage + (start * BDRV_SECTOR_SIZE),
                                        nb_sectors * BDRV_SECTOR_SIZE);
    bdrv_aio_writev(s->bdrv, start, &iov, nb_sectors, bdrv_sync_complete, NULL);
}

static void flash_erase(Flash *s, int offset, FlashCMD cmd)
{
    uint32_t len;
    uint8_t capa_to_assert = 0;

    switch (cmd) {
    case ERASE_4K:
        len = 4 << 10;
        capa_to_assert = ER_4K;
        break;
    case ERASE_32K:
        len = 32 << 10;
        capa_to_assert = ER_32K;
        break;
    case ERASE_SECTOR:
        len = s->pi->sector_size;
        break;
    case BULK_ERASE:
        len = s->size;
        break;
    default:
        abort();
    }

    DB_PRINT("offset = %#x, len = %d\n", offset, len);
    if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
        hw_error("m25p80: %dk erase size not supported by device\n", len);
    }

    if (!s->write_enable) {
        DB_PRINT("erase with write protect!\n");
        return;
    }
    memset(s->storage + offset, 0xff, len);
    flash_sync_area(s, offset, len);
}

static inline void flash_sync_dirty(Flash *s, int64_t newpage)
{
    if (s->dirty_page >= 0 && s->dirty_page != newpage) {
        flash_sync_page(s, s->dirty_page);
        s->dirty_page = newpage;
    }
}

static inline
void flash_write8(Flash *s, uint64_t addr, uint8_t data)
{
    int64_t page = addr / s->pi->page_size;
    uint8_t prev = s->storage[s->cur_addr];

    if (!s->write_enable) {
        DB_PRINT("write with write protect!\n");
    }

    if ((prev ^ data) & data) {
        DB_PRINT("programming zero to one! addr=%lx  %x -> %x\n",
                  addr, prev, data);
    }

    if (s->pi->flags & WR_1) {
        s->storage[s->cur_addr] = data;
    } else {
        s->storage[s->cur_addr] &= data;
    }

    flash_sync_dirty(s, page);
    s->dirty_page = page;
}

static void complete_collecting_data(Flash *s)
{
    s->cur_addr = s->data[0] << 16;
    s->cur_addr |= s->data[1] << 8;
    s->cur_addr |= s->data[2];

    s->state = STATE_IDLE;

    switch (s->cmd_in_progress) {
    case DPP:
    case QPP:
    case PP:
        s->state = STATE_PAGE_PROGRAM;
        break;
    case READ:
    case FAST_READ:
    case DOR:
    case QOR:
    case DIOR:
    case QIOR:
        s->state = STATE_READ;
        break;
    case ERASE_4K:
    case ERASE_32K:
    case ERASE_SECTOR:
        flash_erase(s, s->cur_addr, s->cmd_in_progress);
        break;
    case WRSR:
        if (s->write_enable) {
            s->write_enable = false;
        }
        break;
    default:
        break;
    }
}

static void decode_new_cmd(Flash *s, uint32_t value)
{
    s->cmd_in_progress = value;
    DB_PRINT("decoded new command:%x\n", value);

    switch (value) {

    case ERASE_4K:
    case ERASE_32K:
    case ERASE_SECTOR:
    case READ:
    case DPP:
    case QPP:
    case PP:
        s->needed_bytes = 3;
        s->pos = 0;
        s->len = 0;
        s->state = STATE_COLLECTING_DATA;
        break;

    case FAST_READ:
    case DOR:
    case QOR:
        s->needed_bytes = 4;
        s->pos = 0;
        s->len = 0;
        s->state = STATE_COLLECTING_DATA;
        break;

    case DIOR:
        switch ((s->pi->jedec >> 16) & 0xFF) {
        case JEDEC_WINBOND:
        case JEDEC_SPANSION:
            s->needed_bytes = 4;
            break;
        case JEDEC_NUMONYX:
        default:
            s->needed_bytes = 5;
        }
        s->pos = 0;
        s->len = 0;
        s->state = STATE_COLLECTING_DATA;
        break;

    case QIOR:
        switch ((s->pi->jedec >> 16) & 0xFF) {
        case JEDEC_WINBOND:
        case JEDEC_SPANSION:
            s->needed_bytes = 6;
            break;
        case JEDEC_NUMONYX:
        default:
            s->needed_bytes = 8;
        }
        s->pos = 0;
        s->len = 0;
        s->state = STATE_COLLECTING_DATA;
        break;

    case WRSR:
        if (s->write_enable) {
            s->needed_bytes = 1;
            s->pos = 0;
            s->len = 0;
            s->state = STATE_COLLECTING_DATA;
        }
        break;

    case WRDI:
        s->write_enable = false;
        break;
    case WREN:
        s->write_enable = true;
        break;

    case RDSR:
        s->data[0] = (!!s->write_enable) << 1;
        s->pos = 0;
        s->len = 1;
        s->state = STATE_READING_DATA;
        break;

    case JEDEC_READ:
        DB_PRINT("populated jedec code\n");
        s->data[0] = (s->pi->jedec >> 16) & 0xff;
        s->data[1] = (s->pi->jedec >> 8) & 0xff;
        s->data[2] = s->pi->jedec & 0xff;
        if (s->pi->ext_jedec) {
            s->data[3] = (s->pi->ext_jedec >> 8) & 0xff;
            s->data[4] = s->pi->ext_jedec & 0xff;
            s->len = 5;
        } else {
            s->len = 3;
        }
        s->pos = 0;
        s->state = STATE_READING_DATA;
        break;

    case BULK_ERASE:
        if (s->write_enable) {
            DB_PRINT("chip erase\n");
            flash_erase(s, 0, BULK_ERASE);
        } else {
            DB_PRINT("chip erase with write protect!\n");
        }
        break;
    case NOP:
        break;
    default:
        DB_PRINT("Unknown cmd %x\n", value);
        break;
    }
}

static int m25p80_cs(SSISlave *ss, bool select)
{
    Flash *s = FROM_SSI_SLAVE(Flash, ss);

    if (select) {
        s->len = 0;
        s->pos = 0;
        s->state = STATE_IDLE;
        flash_sync_dirty(s, -1);
    }

    DB_PRINT("%sselect\n", select ? "de" : "");

    return 0;
}

static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
{
    Flash *s = FROM_SSI_SLAVE(Flash, ss);
    uint32_t r = 0;

    switch (s->state) {

    case STATE_PAGE_PROGRAM:
        DB_PRINT("page program cur_addr=%lx data=%x\n", s->cur_addr,
                 (uint8_t)tx);
        flash_write8(s, s->cur_addr, (uint8_t)tx);
        s->cur_addr++;
        break;

    case STATE_READ:
        r = s->storage[s->cur_addr];
        DB_PRINT("READ 0x%lx=%x\n", s->cur_addr, r);
        s->cur_addr = (s->cur_addr + 1) % s->size;
        break;

    case STATE_COLLECTING_DATA:
        s->data[s->len] = (uint8_t)tx;
        s->len++;

        if (s->len == s->needed_bytes) {
            complete_collecting_data(s);
        }
        break;

    case STATE_READING_DATA:
        r = s->data[s->pos];
        s->pos++;
        if (s->pos == s->len) {
            s->pos = 0;
            s->state = STATE_IDLE;
        }
        break;

    default:
    case STATE_IDLE:
        decode_new_cmd(s, (uint8_t)tx);
        break;
    }

    return r;
}

static int m25p80_init(SSISlave *ss)
{
    DriveInfo *dinfo;
    Flash *s = FROM_SSI_SLAVE(Flash, ss);
    const FlashPartInfo *i;

    if (!s->part_name) { /* default to actual m25p80 if no partname given */
        s->part_name = (char *)"m25p80";
    }

    i = known_devices;
    for (i = known_devices;; i++) {
        assert(i);
        if (!i->part_name) {
            fprintf(stderr, "Unknown SPI flash part: \"%s\"\n", s->part_name);
            return 1;
        } else if (!strcmp(i->part_name, s->part_name)) {
            s->pi = i;
            break;
        }
    }

    s->size = s->pi->sector_size * s->pi->n_sectors;
    s->dirty_page = -1;
    s->storage = qemu_blockalign(s->bdrv, s->size);

    dinfo = drive_get_next(IF_MTD);

    if (dinfo && dinfo->bdrv) {
        DB_PRINT("Binding to IF_MTD drive\n");
        s->bdrv = dinfo->bdrv;
        /* FIXME: Move to late init */
        if (bdrv_read(s->bdrv, 0, s->storage, DIV_ROUND_UP(s->size,
                                                    BDRV_SECTOR_SIZE))) {
            fprintf(stderr, "Failed to initialize SPI flash!\n");
            return 1;
        }
    } else {
        memset(s->storage, 0xFF, s->size);
    }

    return 0;
}

static void m25p80_pre_save(void *opaque)
{
    flash_sync_dirty((Flash *)opaque, -1);
}

static const VMStateDescription vmstate_m25p80 = {
    .name = "xilinx_spi",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .pre_save = m25p80_pre_save,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8(state, Flash),
        VMSTATE_UINT8_ARRAY(data, Flash, 16),
        VMSTATE_UINT32(len, Flash),
        VMSTATE_UINT32(pos, Flash),
        VMSTATE_UINT8(needed_bytes, Flash),
        VMSTATE_UINT8(cmd_in_progress, Flash),
        VMSTATE_UINT64(cur_addr, Flash),
        VMSTATE_BOOL(write_enable, Flash),
        VMSTATE_END_OF_LIST()
    }
};

static Property m25p80_properties[] = {
    DEFINE_PROP_STRING("partname", Flash, part_name),
    DEFINE_PROP_END_OF_LIST(),
};

static void m25p80_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SSISlaveClass *k = SSI_SLAVE_CLASS(klass);

    k->init = m25p80_init;
    k->transfer = m25p80_transfer8;
    k->set_cs = m25p80_cs;
    k->cs_polarity = SSI_CS_LOW;
    dc->props = m25p80_properties;
    dc->vmsd = &vmstate_m25p80;
}

static const TypeInfo m25p80_info = {
    .name           = "m25p80",
    .parent         = TYPE_SSI_SLAVE,
    .instance_size  = sizeof(Flash),
    .class_init     = m25p80_class_init,
};

static void m25p80_register_types(void)
{
    type_register_static(&m25p80_info);
}

type_init(m25p80_register_types)
Commit	Line	Data
82a24990 PC	1	/*
	2	* ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
	3	* set. Known devices table current as of Jun/2012 and taken from linux.
	4	* See drivers/mtd/devices/m25p80.c.
	5	*
	6	* Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
	7	* Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
	8	* Copyright (C) 2012 PetaLogix
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 or
	13	* (at your option) a later version of the License.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License along
	21	* with this program; if not, see <http://www.gnu.org/licenses/>.
	22	*/
	23
	24	#include "hw.h"
9c17d615	25	#include "sysemu/blockdev.h"
82a24990 PC	26	#include "ssi.h"
	27	#include "devices.h"
	28
	29	#ifdef M25P80_ERR_DEBUG
	30	#define DB_PRINT(...) do { \
	31	fprintf(stderr, ": %s: ", __func__); \
	32	fprintf(stderr, ## __VA_ARGS__); \
	33	} while (0);
	34	#else
	35	#define DB_PRINT(...)
	36	#endif
	37
	38	/* Fields for FlashPartInfo->flags */
	39
	40	/* erase capabilities */
	41	#define ER_4K 1
	42	#define ER_32K 2
	43	/* set to allow the page program command to write 0s back to 1. Useful for
	44	* modelling EEPROM with SPI flash command set
	45	*/
	46	#define WR_1 0x100
	47
	48	typedef struct FlashPartInfo {
	49	const char *part_name;
	50	/* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */
	51	uint32_t jedec;
	52	/* extended jedec code */
	53	uint16_t ext_jedec;
	54	/* there is confusion between manufacturers as to what a sector is. In this
	55	* device model, a "sector" is the size that is erased by the ERASE_SECTOR
	56	* command (opcode 0xd8).
	57	*/
	58	uint32_t sector_size;
	59	uint32_t n_sectors;
	60	uint32_t page_size;
	61	uint8_t flags;
	62	} FlashPartInfo;
	63
	64	/* adapted from linux */
	65
	66	#define INFO(_part_name, _jedec, _ext_jedec, _sector_size, _n_sectors, _flags)\
	67	.part_name = (_part_name),\
	68	.jedec = (_jedec),\
	69	.ext_jedec = (_ext_jedec),\
	70	.sector_size = (_sector_size),\
	71	.n_sectors = (_n_sectors),\
	72	.page_size = 256,\
	73	.flags = (_flags),\
	74
419336a9 PC	75	#define JEDEC_NUMONYX 0x20
	76	#define JEDEC_WINBOND 0xEF
	77	#define JEDEC_SPANSION 0x01
	78
82a24990 PC	79	static const FlashPartInfo known_devices[] = {
	80	/* Atmel -- some are (confusingly) marketed as "DataFlash" */
	81	{ INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
	82	{ INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
	83
	84	{ INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
	85	{ INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
	86	{ INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
	87
	88	{ INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
	89	{ INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
	90	{ INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
	91	{ INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
	92
	93	/* EON -- en25xxx */
	94	{ INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
	95	{ INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
	96	{ INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
	97	{ INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
	98
	99	/* Intel/Numonyx -- xxxs33b */
	100	{ INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
	101	{ INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
	102	{ INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
	103
	104	/* Macronix */
	105	{ INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
	106	{ INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
	107	{ INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
	108	{ INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
	109	{ INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
	110	{ INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
	111	{ INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
	112	{ INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
	113	{ INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
	114
	115	/* Spansion -- single (large) sector size only, at least
	116	* for the chips listed here (without boot sectors).
	117	*/
	118	{ INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
	119	{ INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
	120	{ INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
	121	{ INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
	122	{ INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
	123	{ INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
	124	{ INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
	125	{ INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
	126	{ INFO("s25fl512s", 0x010220, 0x4d00, 256 << 10, 256, 0) },
	127	{ INFO("s70fl01gs", 0x010221, 0x4d00, 256 << 10, 256, 0) },
	128	{ INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
	129	{ INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
	130	{ INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
	131	{ INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
	132	{ INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K \| ER_32K) },
	133	{ INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K \| ER_32K) },
	134
	135	/* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
	136	{ INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
	137	{ INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
	138	{ INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
	139	{ INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
	140	{ INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
	141	{ INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
	142	{ INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
143	{ INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
144
145	/* ST Microelectronics -- newer production may have feature updates */
146	{ INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
147	{ INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
148	{ INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
149	{ INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
150	{ INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
151	{ INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
152	{ INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
153	{ INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
154	{ INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
155
156	{ INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
157	{ INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
158	{ INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
159
160	{ INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
161	{ INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
162
163	{ INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
164	{ INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
165	{ INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
166	{ INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
167
168	/* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
169	{ INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
170	{ INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
171	{ INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
172	{ INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
173	{ INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
174	{ INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
175	{ INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
176	{ INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
177	{ INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
178
179	/* Numonyx -- n25q128 */
180	{ INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
181
182	{ },
183	};
184
185	typedef enum {
186	NOP = 0,
03ec2f83	187	WRSR = 0x1,
82a24990 PC	188	WRDI = 0x4,
	189	RDSR = 0x5,
	190	WREN = 0x6,
419336a9 PC	191	JEDEC_READ = 0x9f,
	192	BULK_ERASE = 0xc7,
	193
	194	READ = 0x3,
82a24990	195	FAST_READ = 0xb,
419336a9 PC	196	DOR = 0x3b,
	197	QOR = 0x6b,
	198	DIOR = 0xbb,
	199	QIOR = 0xeb,
	200
	201	PP = 0x2,
	202	DPP = 0xa2,
	203	QPP = 0x32,
	204
82a24990 PC	205	ERASE_4K = 0x20,
	206	ERASE_32K = 0x52,
	207	ERASE_SECTOR = 0xd8,
82a24990 PC	208	} FlashCMD;
	209
	210	typedef enum {
	211	STATE_IDLE,
	212	STATE_PAGE_PROGRAM,
	213	STATE_READ,
	214	STATE_COLLECTING_DATA,
	215	STATE_READING_DATA,
	216	} CMDState;
	217
	218	typedef struct Flash {
	219	SSISlave ssidev;
	220	uint32_t r;
	221
	222	BlockDriverState *bdrv;
	223
	224	uint8_t *storage;
	225	uint32_t size;
	226	int page_size;
	227
	228	uint8_t state;
	229	uint8_t data[16];
	230	uint32_t len;
	231	uint32_t pos;
	232	uint8_t needed_bytes;
	233	uint8_t cmd_in_progress;
	234	uint64_t cur_addr;
	235	bool write_enable;
	236
	237	int64_t dirty_page;
	238
	239	char *part_name;
	240	const FlashPartInfo *pi;
	241
	242	} Flash;
	243
	244	static void bdrv_sync_complete(void *opaque, int ret)
	245	{
	246	/* do nothing. Masters do not directly interact with the backing store,
	247	* only the working copy so no mutexing required.
	248	*/
	249	}
	250
	251	static void flash_sync_page(Flash *s, int page)
	252	{
	253	if (s->bdrv) {
	254	int bdrv_sector, nb_sectors;
	255	QEMUIOVector iov;
	256
	257	bdrv_sector = (page * s->pi->page_size) / BDRV_SECTOR_SIZE;
	258	nb_sectors = DIV_ROUND_UP(s->pi->page_size, BDRV_SECTOR_SIZE);
	259	qemu_iovec_init(&iov, 1);
	260	qemu_iovec_add(&iov, s->storage + bdrv_sector * BDRV_SECTOR_SIZE,
	261	nb_sectors * BDRV_SECTOR_SIZE);
	262	bdrv_aio_writev(s->bdrv, bdrv_sector, &iov, nb_sectors,
	263	bdrv_sync_complete, NULL);
	264	}
	265	}
	266
	267	static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
	268	{
	269	int64_t start, end, nb_sectors;
	270	QEMUIOVector iov;
	271
272	if (!s->bdrv) {
273	return;
274	}
275
276	assert(!(len % BDRV_SECTOR_SIZE));
277	start = off / BDRV_SECTOR_SIZE;
278	end = (off + len) / BDRV_SECTOR_SIZE;
279	nb_sectors = end - start;
280	qemu_iovec_init(&iov, 1);
281	qemu_iovec_add(&iov, s->storage + (start * BDRV_SECTOR_SIZE),
282	nb_sectors * BDRV_SECTOR_SIZE);
283	bdrv_aio_writev(s->bdrv, start, &iov, nb_sectors, bdrv_sync_complete, NULL);
284	}
285
286	static void flash_erase(Flash *s, int offset, FlashCMD cmd)
287	{
288	uint32_t len;
289	uint8_t capa_to_assert = 0;
290
291	switch (cmd) {
292	case ERASE_4K:
293	len = 4 << 10;
294	capa_to_assert = ER_4K;
295	break;
296	case ERASE_32K:
297	len = 32 << 10;
298	capa_to_assert = ER_32K;
299	break;
300	case ERASE_SECTOR:
301	len = s->pi->sector_size;
302	break;
303	case BULK_ERASE:
304	len = s->size;
305	break;
306	default:
307	abort();
308	}
309
310	DB_PRINT("offset = %#x, len = %d\n", offset, len);
311	if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
312	hw_error("m25p80: %dk erase size not supported by device\n", len);
313	}
314
315	if (!s->write_enable) {
316	DB_PRINT("erase with write protect!\n");
317	return;
318	}
319	memset(s->storage + offset, 0xff, len);
320	flash_sync_area(s, offset, len);
321	}
322
323	static inline void flash_sync_dirty(Flash *s, int64_t newpage)
324	{
325	if (s->dirty_page >= 0 && s->dirty_page != newpage) {
326	flash_sync_page(s, s->dirty_page);
327	s->dirty_page = newpage;
328	}
329	}
330
331	static inline
332	void flash_write8(Flash *s, uint64_t addr, uint8_t data)
333	{
334	int64_t page = addr / s->pi->page_size;
335	uint8_t prev = s->storage[s->cur_addr];
336
337	if (!s->write_enable) {
338	DB_PRINT("write with write protect!\n");
339	}
340
341	if ((prev ^ data) & data) {
342	DB_PRINT("programming zero to one! addr=%lx %x -> %x\n",
343	addr, prev, data);
344	}
345
346	if (s->pi->flags & WR_1) {
347	s->storage[s->cur_addr] = data;
348	} else {
349	s->storage[s->cur_addr] &= data;
350	}
351
352	flash_sync_dirty(s, page);
353	s->dirty_page = page;
354	}
355
356	static void complete_collecting_data(Flash *s)
357	{
358	s->cur_addr = s->data[0] << 16;
359	s->cur_addr \|= s->data[1] << 8;
360	s->cur_addr \|= s->data[2];
361
a56d305a PC	362	s->state = STATE_IDLE;
a56d305a PC	363
82a24990	364	switch (s->cmd_in_progress) {
419336a9 PC	365	case DPP:
419336a9 PC	366	case QPP:
82a24990 PC	367	case PP:
	368	s->state = STATE_PAGE_PROGRAM;
	369	break;
	370	case READ:
	371	case FAST_READ:
419336a9 PC	372	case DOR:
	373	case QOR:
	374	case DIOR:
	375	case QIOR:
82a24990 PC	376	s->state = STATE_READ;
	377	break;
	378	case ERASE_4K:
	379	case ERASE_32K:
	380	case ERASE_SECTOR:
	381	flash_erase(s, s->cur_addr, s->cmd_in_progress);
	382	break;
03ec2f83 KJS	383	case WRSR:
	384	if (s->write_enable) {
	385	s->write_enable = false;
	386	}
	387	break;
82a24990 PC	388	default:
	389	break;
	390	}
	391	}
	392
	393	static void decode_new_cmd(Flash *s, uint32_t value)
	394	{
	395	s->cmd_in_progress = value;
	396	DB_PRINT("decoded new command:%x\n", value);
	397
	398	switch (value) {
	399
	400	case ERASE_4K:
	401	case ERASE_32K:
	402	case ERASE_SECTOR:
	403	case READ:
419336a9 PC	404	case DPP:
419336a9 PC	405	case QPP:
82a24990 PC	406	case PP:
	407	s->needed_bytes = 3;
	408	s->pos = 0;
	409	s->len = 0;
	410	s->state = STATE_COLLECTING_DATA;
	411	break;
	412
	413	case FAST_READ:
419336a9 PC	414	case DOR:
419336a9 PC	415	case QOR:
82a24990 PC	416	s->needed_bytes = 4;
	417	s->pos = 0;
	418	s->len = 0;
	419	s->state = STATE_COLLECTING_DATA;
	420	break;
	421
419336a9 PC	422	case DIOR:
	423	switch ((s->pi->jedec >> 16) & 0xFF) {
	424	case JEDEC_WINBOND:
	425	case JEDEC_SPANSION:
	426	s->needed_bytes = 4;
	427	break;
	428	case JEDEC_NUMONYX:
	429	default:
	430	s->needed_bytes = 5;
	431	}
	432	s->pos = 0;
	433	s->len = 0;
	434	s->state = STATE_COLLECTING_DATA;
	435	break;
	436
	437	case QIOR:
	438	switch ((s->pi->jedec >> 16) & 0xFF) {
	439	case JEDEC_WINBOND:
	440	case JEDEC_SPANSION:
	441	s->needed_bytes = 6;
	442	break;
	443	case JEDEC_NUMONYX:
	444	default:
	445	s->needed_bytes = 8;
	446	}
	447	s->pos = 0;
	448	s->len = 0;
	449	s->state = STATE_COLLECTING_DATA;
	450	break;
	451
03ec2f83 KJS	452	case WRSR:
	453	if (s->write_enable) {
	454	s->needed_bytes = 1;
	455	s->pos = 0;
	456	s->len = 0;
	457	s->state = STATE_COLLECTING_DATA;
	458	}
	459	break;
	460
82a24990 PC	461	case WRDI:
	462	s->write_enable = false;
	463	break;
	464	case WREN:
	465	s->write_enable = true;
	466	break;
	467
	468	case RDSR:
	469	s->data[0] = (!!s->write_enable) << 1;
	470	s->pos = 0;
	471	s->len = 1;
	472	s->state = STATE_READING_DATA;
	473	break;
	474
	475	case JEDEC_READ:
	476	DB_PRINT("populated jedec code\n");
	477	s->data[0] = (s->pi->jedec >> 16) & 0xff;
	478	s->data[1] = (s->pi->jedec >> 8) & 0xff;
	479	s->data[2] = s->pi->jedec & 0xff;
	480	if (s->pi->ext_jedec) {
	481	s->data[3] = (s->pi->ext_jedec >> 8) & 0xff;
	482	s->data[4] = s->pi->ext_jedec & 0xff;
	483	s->len = 5;
	484	} else {
	485	s->len = 3;
	486	}
	487	s->pos = 0;
	488	s->state = STATE_READING_DATA;
	489	break;
	490
	491	case BULK_ERASE:
	492	if (s->write_enable) {
	493	DB_PRINT("chip erase\n");
	494	flash_erase(s, 0, BULK_ERASE);
	495	} else {
	496	DB_PRINT("chip erase with write protect!\n");
	497	}
	498	break;
	499	case NOP:
	500	break;
	501	default:
	502	DB_PRINT("Unknown cmd %x\n", value);
	503	break;
	504	}
	505	}
	506
	507	static int m25p80_cs(SSISlave *ss, bool select)
	508	{
	509	Flash *s = FROM_SSI_SLAVE(Flash, ss);
	510
	511	if (select) {
	512	s->len = 0;
	513	s->pos = 0;
	514	s->state = STATE_IDLE;
	515	flash_sync_dirty(s, -1);
	516	}
	517
	518	DB_PRINT("%sselect\n", select ? "de" : "");
	519
	520	return 0;
	521	}
	522
	523	static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
	524	{
525	Flash *s = FROM_SSI_SLAVE(Flash, ss);
526	uint32_t r = 0;
527
528	switch (s->state) {
529
530	case STATE_PAGE_PROGRAM:
531	DB_PRINT("page program cur_addr=%lx data=%x\n", s->cur_addr,
532	(uint8_t)tx);
533	flash_write8(s, s->cur_addr, (uint8_t)tx);
534	s->cur_addr++;
535	break;
536
537	case STATE_READ:
538	r = s->storage[s->cur_addr];
539	DB_PRINT("READ 0x%lx=%x\n", s->cur_addr, r);
540	s->cur_addr = (s->cur_addr + 1) % s->size;
541	break;
542
543	case STATE_COLLECTING_DATA:
544	s->data[s->len] = (uint8_t)tx;
545	s->len++;
546
547	if (s->len == s->needed_bytes) {
548	complete_collecting_data(s);
549	}
550	break;
551
552	case STATE_READING_DATA:
553	r = s->data[s->pos];
554	s->pos++;
555	if (s->pos == s->len) {
556	s->pos = 0;
557	s->state = STATE_IDLE;
558	}
559	break;
560
561	default:
562	case STATE_IDLE:
563	decode_new_cmd(s, (uint8_t)tx);
564	break;
565	}
566
567	return r;
568	}
569
570	static int m25p80_init(SSISlave *ss)
571	{
572	DriveInfo *dinfo;
573	Flash *s = FROM_SSI_SLAVE(Flash, ss);
574	const FlashPartInfo *i;
575
576	if (!s->part_name) { /* default to actual m25p80 if no partname given */
577	s->part_name = (char *)"m25p80";
578	}
579
580	i = known_devices;
581	for (i = known_devices;; i++) {
582	assert(i);
583	if (!i->part_name) {
584	fprintf(stderr, "Unknown SPI flash part: \"%s\"\n", s->part_name);
585	return 1;
586	} else if (!strcmp(i->part_name, s->part_name)) {
587	s->pi = i;
588	break;
589	}
590	}
591
592	s->size = s->pi->sector_size * s->pi->n_sectors;
593	s->dirty_page = -1;
594	s->storage = qemu_blockalign(s->bdrv, s->size);
595
596	dinfo = drive_get_next(IF_MTD);
597
598	if (dinfo && dinfo->bdrv) {
599	DB_PRINT("Binding to IF_MTD drive\n");
600	s->bdrv = dinfo->bdrv;
601	/* FIXME: Move to late init */
602	if (bdrv_read(s->bdrv, 0, s->storage, DIV_ROUND_UP(s->size,
603	BDRV_SECTOR_SIZE))) {
604	fprintf(stderr, "Failed to initialize SPI flash!\n");
605	return 1;
606	}
607	} else {
608	memset(s->storage, 0xFF, s->size);
609	}
610
611	return 0;
612	}
613
614	static void m25p80_pre_save(void *opaque)
615	{
616	flash_sync_dirty((Flash *)opaque, -1);
617	}
618
619	static const VMStateDescription vmstate_m25p80 = {
620	.name = "xilinx_spi",
621	.version_id = 1,
622	.minimum_version_id = 1,
623	.minimum_version_id_old = 1,
624	.pre_save = m25p80_pre_save,
625	.fields = (VMStateField[]) {
626	VMSTATE_UINT8(state, Flash),
627	VMSTATE_UINT8_ARRAY(data, Flash, 16),
628	VMSTATE_UINT32(len, Flash),
629	VMSTATE_UINT32(pos, Flash),
630	VMSTATE_UINT8(needed_bytes, Flash),
631	VMSTATE_UINT8(cmd_in_progress, Flash),
632	VMSTATE_UINT64(cur_addr, Flash),
633	VMSTATE_BOOL(write_enable, Flash),
634	VMSTATE_END_OF_LIST()
635	}
636	};
637
638	static Property m25p80_properties[] = {
639	DEFINE_PROP_STRING("partname", Flash, part_name),
640	DEFINE_PROP_END_OF_LIST(),
641	};
642
643	static void m25p80_class_init(ObjectClass klass, void data)
644	{
645	DeviceClass *dc = DEVICE_CLASS(klass);
646	SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
647
648	k->init = m25p80_init;
649	k->transfer = m25p80_transfer8;
650	k->set_cs = m25p80_cs;
651	k->cs_polarity = SSI_CS_LOW;
652	dc->props = m25p80_properties;
653	dc->vmsd = &vmstate_m25p80;
654	}
655
656	static const TypeInfo m25p80_info = {
657	.name = "m25p80",
658	.parent = TYPE_SSI_SLAVE,
659	.instance_size = sizeof(Flash),
660	.class_init = m25p80_class_init,
661	};
662
663	static void m25p80_register_types(void)
664	{
665	type_register_static(&m25p80_info);
666	}
667
668	type_init(m25p80_register_types)