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Commit | Line | Data |
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a541f297 | 1 | /* |
819385c5 | 2 | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms |
5fafdf24 | 3 | * |
3ccacc4a | 4 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "nvram.h" | |
87ecb68b PB |
26 | #include "qemu-timer.h" |
27 | #include "sysemu.h" | |
d27cf0ae | 28 | #include "sysbus.h" |
f80237d4 | 29 | #include "isa.h" |
a541f297 | 30 | |
13ab5daa | 31 | //#define DEBUG_NVRAM |
a541f297 | 32 | |
13ab5daa | 33 | #if defined(DEBUG_NVRAM) |
001faf32 | 34 | #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
a541f297 | 35 | #else |
001faf32 | 36 | #define NVRAM_PRINTF(fmt, ...) do { } while (0) |
a541f297 FB |
37 | #endif |
38 | ||
819385c5 | 39 | /* |
4aed2c33 | 40 | * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has |
819385c5 FB |
41 | * alarm and a watchdog timer and related control registers. In the |
42 | * PPC platform there is also a nvram lock function. | |
43 | */ | |
930f3fe1 BS |
44 | |
45 | /* | |
46 | * Chipset docs: | |
47 | * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf | |
48 | * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf | |
49 | * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf | |
50 | */ | |
51 | ||
43a34704 | 52 | struct M48t59State { |
a541f297 | 53 | /* Hardware parameters */ |
d537cf6c | 54 | qemu_irq IRQ; |
a541f297 | 55 | uint32_t io_base; |
ee6847d1 | 56 | uint32_t size; |
a541f297 FB |
57 | /* RTC management */ |
58 | time_t time_offset; | |
59 | time_t stop_time; | |
60 | /* Alarm & watchdog */ | |
f6503059 | 61 | struct tm alarm; |
a541f297 FB |
62 | struct QEMUTimer *alrm_timer; |
63 | struct QEMUTimer *wd_timer; | |
64 | /* NVRAM storage */ | |
a541f297 | 65 | uint8_t *buffer; |
42c812b9 BS |
66 | /* Model parameters */ |
67 | uint32_t type; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */ | |
68 | /* NVRAM storage */ | |
69 | uint16_t addr; | |
70 | uint8_t lock; | |
c5df018e | 71 | }; |
a541f297 | 72 | |
f80237d4 BS |
73 | typedef struct M48t59ISAState { |
74 | ISADevice busdev; | |
43a34704 | 75 | M48t59State state; |
f80237d4 BS |
76 | } M48t59ISAState; |
77 | ||
78 | typedef struct M48t59SysBusState { | |
79 | SysBusDevice busdev; | |
43a34704 | 80 | M48t59State state; |
f80237d4 BS |
81 | } M48t59SysBusState; |
82 | ||
a541f297 | 83 | /* Fake timer functions */ |
a541f297 | 84 | |
a541f297 FB |
85 | /* Alarm management */ |
86 | static void alarm_cb (void *opaque) | |
87 | { | |
f6503059 | 88 | struct tm tm; |
a541f297 | 89 | uint64_t next_time; |
43a34704 | 90 | M48t59State *NVRAM = opaque; |
a541f297 | 91 | |
d537cf6c | 92 | qemu_set_irq(NVRAM->IRQ, 1); |
5fafdf24 | 93 | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
a541f297 FB |
94 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
95 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
96 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
97 | /* Repeat once a month */ |
98 | qemu_get_timedate(&tm, NVRAM->time_offset); | |
99 | tm.tm_mon++; | |
100 | if (tm.tm_mon == 13) { | |
101 | tm.tm_mon = 1; | |
102 | tm.tm_year++; | |
103 | } | |
104 | next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; | |
a541f297 FB |
105 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
106 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && | |
107 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
108 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
109 | /* Repeat once a day */ |
110 | next_time = 24 * 60 * 60; | |
a541f297 FB |
111 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
112 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && | |
113 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
114 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
115 | /* Repeat once an hour */ |
116 | next_time = 60 * 60; | |
a541f297 FB |
117 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
118 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && | |
119 | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && | |
120 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
121 | /* Repeat once a minute */ |
122 | next_time = 60; | |
a541f297 | 123 | } else { |
f6503059 AZ |
124 | /* Repeat once a second */ |
125 | next_time = 1; | |
a541f297 | 126 | } |
74475455 | 127 | qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(vm_clock) + |
f6503059 | 128 | next_time * 1000); |
d537cf6c | 129 | qemu_set_irq(NVRAM->IRQ, 0); |
a541f297 FB |
130 | } |
131 | ||
43a34704 | 132 | static void set_alarm(M48t59State *NVRAM) |
f6503059 AZ |
133 | { |
134 | int diff; | |
135 | if (NVRAM->alrm_timer != NULL) { | |
136 | qemu_del_timer(NVRAM->alrm_timer); | |
137 | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; | |
138 | if (diff > 0) | |
139 | qemu_mod_timer(NVRAM->alrm_timer, diff * 1000); | |
140 | } | |
141 | } | |
a541f297 | 142 | |
f6503059 | 143 | /* RTC management helpers */ |
43a34704 | 144 | static inline void get_time(M48t59State *NVRAM, struct tm *tm) |
a541f297 | 145 | { |
f6503059 | 146 | qemu_get_timedate(tm, NVRAM->time_offset); |
a541f297 FB |
147 | } |
148 | ||
43a34704 | 149 | static void set_time(M48t59State *NVRAM, struct tm *tm) |
a541f297 | 150 | { |
f6503059 AZ |
151 | NVRAM->time_offset = qemu_timedate_diff(tm); |
152 | set_alarm(NVRAM); | |
a541f297 FB |
153 | } |
154 | ||
155 | /* Watchdog management */ | |
156 | static void watchdog_cb (void *opaque) | |
157 | { | |
43a34704 | 158 | M48t59State *NVRAM = opaque; |
a541f297 FB |
159 | |
160 | NVRAM->buffer[0x1FF0] |= 0x80; | |
161 | if (NVRAM->buffer[0x1FF7] & 0x80) { | |
162 | NVRAM->buffer[0x1FF7] = 0x00; | |
163 | NVRAM->buffer[0x1FFC] &= ~0x40; | |
13ab5daa | 164 | /* May it be a hw CPU Reset instead ? */ |
d7d02e3c | 165 | qemu_system_reset_request(); |
a541f297 | 166 | } else { |
d537cf6c PB |
167 | qemu_set_irq(NVRAM->IRQ, 1); |
168 | qemu_set_irq(NVRAM->IRQ, 0); | |
a541f297 FB |
169 | } |
170 | } | |
171 | ||
43a34704 | 172 | static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) |
a541f297 FB |
173 | { |
174 | uint64_t interval; /* in 1/16 seconds */ | |
175 | ||
868d585a | 176 | NVRAM->buffer[0x1FF0] &= ~0x80; |
a541f297 FB |
177 | if (NVRAM->wd_timer != NULL) { |
178 | qemu_del_timer(NVRAM->wd_timer); | |
868d585a JM |
179 | if (value != 0) { |
180 | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); | |
181 | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + | |
182 | ((interval * 1000) >> 4)); | |
183 | } | |
a541f297 FB |
184 | } |
185 | } | |
186 | ||
187 | /* Direct access to NVRAM */ | |
897b4c6c | 188 | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
a541f297 | 189 | { |
43a34704 | 190 | M48t59State *NVRAM = opaque; |
a541f297 FB |
191 | struct tm tm; |
192 | int tmp; | |
193 | ||
819385c5 FB |
194 | if (addr > 0x1FF8 && addr < 0x2000) |
195 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); | |
4aed2c33 BS |
196 | |
197 | /* check for NVRAM access */ | |
198 | if ((NVRAM->type == 2 && addr < 0x7f8) || | |
199 | (NVRAM->type == 8 && addr < 0x1ff8) || | |
200 | (NVRAM->type == 59 && addr < 0x1ff0)) | |
819385c5 | 201 | goto do_write; |
4aed2c33 BS |
202 | |
203 | /* TOD access */ | |
819385c5 | 204 | switch (addr) { |
a541f297 FB |
205 | case 0x1FF0: |
206 | /* flags register : read-only */ | |
207 | break; | |
208 | case 0x1FF1: | |
209 | /* unused */ | |
210 | break; | |
211 | case 0x1FF2: | |
212 | /* alarm seconds */ | |
abd0c6bd | 213 | tmp = from_bcd(val & 0x7F); |
819385c5 | 214 | if (tmp >= 0 && tmp <= 59) { |
f6503059 | 215 | NVRAM->alarm.tm_sec = tmp; |
819385c5 | 216 | NVRAM->buffer[0x1FF2] = val; |
f6503059 | 217 | set_alarm(NVRAM); |
819385c5 | 218 | } |
a541f297 FB |
219 | break; |
220 | case 0x1FF3: | |
221 | /* alarm minutes */ | |
abd0c6bd | 222 | tmp = from_bcd(val & 0x7F); |
819385c5 | 223 | if (tmp >= 0 && tmp <= 59) { |
f6503059 | 224 | NVRAM->alarm.tm_min = tmp; |
819385c5 | 225 | NVRAM->buffer[0x1FF3] = val; |
f6503059 | 226 | set_alarm(NVRAM); |
819385c5 | 227 | } |
a541f297 FB |
228 | break; |
229 | case 0x1FF4: | |
230 | /* alarm hours */ | |
abd0c6bd | 231 | tmp = from_bcd(val & 0x3F); |
819385c5 | 232 | if (tmp >= 0 && tmp <= 23) { |
f6503059 | 233 | NVRAM->alarm.tm_hour = tmp; |
819385c5 | 234 | NVRAM->buffer[0x1FF4] = val; |
f6503059 | 235 | set_alarm(NVRAM); |
819385c5 | 236 | } |
a541f297 FB |
237 | break; |
238 | case 0x1FF5: | |
239 | /* alarm date */ | |
abd0c6bd | 240 | tmp = from_bcd(val & 0x1F); |
819385c5 | 241 | if (tmp != 0) { |
f6503059 | 242 | NVRAM->alarm.tm_mday = tmp; |
819385c5 | 243 | NVRAM->buffer[0x1FF5] = val; |
f6503059 | 244 | set_alarm(NVRAM); |
819385c5 | 245 | } |
a541f297 FB |
246 | break; |
247 | case 0x1FF6: | |
248 | /* interrupts */ | |
819385c5 | 249 | NVRAM->buffer[0x1FF6] = val; |
a541f297 FB |
250 | break; |
251 | case 0x1FF7: | |
252 | /* watchdog */ | |
819385c5 FB |
253 | NVRAM->buffer[0x1FF7] = val; |
254 | set_up_watchdog(NVRAM, val); | |
a541f297 FB |
255 | break; |
256 | case 0x1FF8: | |
4aed2c33 | 257 | case 0x07F8: |
a541f297 | 258 | /* control */ |
4aed2c33 | 259 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
a541f297 FB |
260 | break; |
261 | case 0x1FF9: | |
4aed2c33 | 262 | case 0x07F9: |
a541f297 | 263 | /* seconds (BCD) */ |
abd0c6bd | 264 | tmp = from_bcd(val & 0x7F); |
a541f297 FB |
265 | if (tmp >= 0 && tmp <= 59) { |
266 | get_time(NVRAM, &tm); | |
267 | tm.tm_sec = tmp; | |
268 | set_time(NVRAM, &tm); | |
269 | } | |
f6503059 | 270 | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
a541f297 FB |
271 | if (val & 0x80) { |
272 | NVRAM->stop_time = time(NULL); | |
273 | } else { | |
274 | NVRAM->time_offset += NVRAM->stop_time - time(NULL); | |
275 | NVRAM->stop_time = 0; | |
276 | } | |
277 | } | |
f6503059 | 278 | NVRAM->buffer[addr] = val & 0x80; |
a541f297 FB |
279 | break; |
280 | case 0x1FFA: | |
4aed2c33 | 281 | case 0x07FA: |
a541f297 | 282 | /* minutes (BCD) */ |
abd0c6bd | 283 | tmp = from_bcd(val & 0x7F); |
a541f297 FB |
284 | if (tmp >= 0 && tmp <= 59) { |
285 | get_time(NVRAM, &tm); | |
286 | tm.tm_min = tmp; | |
287 | set_time(NVRAM, &tm); | |
288 | } | |
289 | break; | |
290 | case 0x1FFB: | |
4aed2c33 | 291 | case 0x07FB: |
a541f297 | 292 | /* hours (BCD) */ |
abd0c6bd | 293 | tmp = from_bcd(val & 0x3F); |
a541f297 FB |
294 | if (tmp >= 0 && tmp <= 23) { |
295 | get_time(NVRAM, &tm); | |
296 | tm.tm_hour = tmp; | |
297 | set_time(NVRAM, &tm); | |
298 | } | |
299 | break; | |
300 | case 0x1FFC: | |
4aed2c33 | 301 | case 0x07FC: |
a541f297 | 302 | /* day of the week / century */ |
abd0c6bd | 303 | tmp = from_bcd(val & 0x07); |
a541f297 FB |
304 | get_time(NVRAM, &tm); |
305 | tm.tm_wday = tmp; | |
306 | set_time(NVRAM, &tm); | |
4aed2c33 | 307 | NVRAM->buffer[addr] = val & 0x40; |
a541f297 FB |
308 | break; |
309 | case 0x1FFD: | |
4aed2c33 | 310 | case 0x07FD: |
a541f297 | 311 | /* date */ |
abd0c6bd | 312 | tmp = from_bcd(val & 0x1F); |
a541f297 FB |
313 | if (tmp != 0) { |
314 | get_time(NVRAM, &tm); | |
315 | tm.tm_mday = tmp; | |
316 | set_time(NVRAM, &tm); | |
317 | } | |
318 | break; | |
319 | case 0x1FFE: | |
4aed2c33 | 320 | case 0x07FE: |
a541f297 | 321 | /* month */ |
abd0c6bd | 322 | tmp = from_bcd(val & 0x1F); |
a541f297 FB |
323 | if (tmp >= 1 && tmp <= 12) { |
324 | get_time(NVRAM, &tm); | |
325 | tm.tm_mon = tmp - 1; | |
326 | set_time(NVRAM, &tm); | |
327 | } | |
328 | break; | |
329 | case 0x1FFF: | |
4aed2c33 | 330 | case 0x07FF: |
a541f297 | 331 | /* year */ |
abd0c6bd | 332 | tmp = from_bcd(val); |
a541f297 FB |
333 | if (tmp >= 0 && tmp <= 99) { |
334 | get_time(NVRAM, &tm); | |
180b700d | 335 | if (NVRAM->type == 8) |
abd0c6bd | 336 | tm.tm_year = from_bcd(val) + 68; // Base year is 1968 |
180b700d | 337 | else |
abd0c6bd | 338 | tm.tm_year = from_bcd(val); |
a541f297 FB |
339 | set_time(NVRAM, &tm); |
340 | } | |
341 | break; | |
342 | default: | |
13ab5daa | 343 | /* Check lock registers state */ |
819385c5 | 344 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
13ab5daa | 345 | break; |
819385c5 | 346 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
13ab5daa | 347 | break; |
819385c5 FB |
348 | do_write: |
349 | if (addr < NVRAM->size) { | |
350 | NVRAM->buffer[addr] = val & 0xFF; | |
a541f297 FB |
351 | } |
352 | break; | |
353 | } | |
354 | } | |
355 | ||
897b4c6c | 356 | uint32_t m48t59_read (void *opaque, uint32_t addr) |
a541f297 | 357 | { |
43a34704 | 358 | M48t59State *NVRAM = opaque; |
a541f297 FB |
359 | struct tm tm; |
360 | uint32_t retval = 0xFF; | |
361 | ||
4aed2c33 BS |
362 | /* check for NVRAM access */ |
363 | if ((NVRAM->type == 2 && addr < 0x078f) || | |
364 | (NVRAM->type == 8 && addr < 0x1ff8) || | |
365 | (NVRAM->type == 59 && addr < 0x1ff0)) | |
819385c5 | 366 | goto do_read; |
4aed2c33 BS |
367 | |
368 | /* TOD access */ | |
819385c5 | 369 | switch (addr) { |
a541f297 FB |
370 | case 0x1FF0: |
371 | /* flags register */ | |
372 | goto do_read; | |
373 | case 0x1FF1: | |
374 | /* unused */ | |
375 | retval = 0; | |
376 | break; | |
377 | case 0x1FF2: | |
378 | /* alarm seconds */ | |
379 | goto do_read; | |
380 | case 0x1FF3: | |
381 | /* alarm minutes */ | |
382 | goto do_read; | |
383 | case 0x1FF4: | |
384 | /* alarm hours */ | |
385 | goto do_read; | |
386 | case 0x1FF5: | |
387 | /* alarm date */ | |
388 | goto do_read; | |
389 | case 0x1FF6: | |
390 | /* interrupts */ | |
391 | goto do_read; | |
392 | case 0x1FF7: | |
393 | /* A read resets the watchdog */ | |
394 | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]); | |
395 | goto do_read; | |
396 | case 0x1FF8: | |
4aed2c33 | 397 | case 0x07F8: |
a541f297 FB |
398 | /* control */ |
399 | goto do_read; | |
400 | case 0x1FF9: | |
4aed2c33 | 401 | case 0x07F9: |
a541f297 FB |
402 | /* seconds (BCD) */ |
403 | get_time(NVRAM, &tm); | |
abd0c6bd | 404 | retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec); |
a541f297 FB |
405 | break; |
406 | case 0x1FFA: | |
4aed2c33 | 407 | case 0x07FA: |
a541f297 FB |
408 | /* minutes (BCD) */ |
409 | get_time(NVRAM, &tm); | |
abd0c6bd | 410 | retval = to_bcd(tm.tm_min); |
a541f297 FB |
411 | break; |
412 | case 0x1FFB: | |
4aed2c33 | 413 | case 0x07FB: |
a541f297 FB |
414 | /* hours (BCD) */ |
415 | get_time(NVRAM, &tm); | |
abd0c6bd | 416 | retval = to_bcd(tm.tm_hour); |
a541f297 FB |
417 | break; |
418 | case 0x1FFC: | |
4aed2c33 | 419 | case 0x07FC: |
a541f297 FB |
420 | /* day of the week / century */ |
421 | get_time(NVRAM, &tm); | |
4aed2c33 | 422 | retval = NVRAM->buffer[addr] | tm.tm_wday; |
a541f297 FB |
423 | break; |
424 | case 0x1FFD: | |
4aed2c33 | 425 | case 0x07FD: |
a541f297 FB |
426 | /* date */ |
427 | get_time(NVRAM, &tm); | |
abd0c6bd | 428 | retval = to_bcd(tm.tm_mday); |
a541f297 FB |
429 | break; |
430 | case 0x1FFE: | |
4aed2c33 | 431 | case 0x07FE: |
a541f297 FB |
432 | /* month */ |
433 | get_time(NVRAM, &tm); | |
abd0c6bd | 434 | retval = to_bcd(tm.tm_mon + 1); |
a541f297 FB |
435 | break; |
436 | case 0x1FFF: | |
4aed2c33 | 437 | case 0x07FF: |
a541f297 FB |
438 | /* year */ |
439 | get_time(NVRAM, &tm); | |
5fafdf24 | 440 | if (NVRAM->type == 8) |
abd0c6bd | 441 | retval = to_bcd(tm.tm_year - 68); // Base year is 1968 |
180b700d | 442 | else |
abd0c6bd | 443 | retval = to_bcd(tm.tm_year); |
a541f297 FB |
444 | break; |
445 | default: | |
13ab5daa | 446 | /* Check lock registers state */ |
819385c5 | 447 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
13ab5daa | 448 | break; |
819385c5 | 449 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
13ab5daa | 450 | break; |
819385c5 FB |
451 | do_read: |
452 | if (addr < NVRAM->size) { | |
453 | retval = NVRAM->buffer[addr]; | |
a541f297 FB |
454 | } |
455 | break; | |
456 | } | |
819385c5 | 457 | if (addr > 0x1FF9 && addr < 0x2000) |
9ed1e667 | 458 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); |
a541f297 FB |
459 | |
460 | return retval; | |
461 | } | |
462 | ||
897b4c6c | 463 | void m48t59_set_addr (void *opaque, uint32_t addr) |
a541f297 | 464 | { |
43a34704 | 465 | M48t59State *NVRAM = opaque; |
897b4c6c | 466 | |
a541f297 FB |
467 | NVRAM->addr = addr; |
468 | } | |
469 | ||
897b4c6c | 470 | void m48t59_toggle_lock (void *opaque, int lock) |
13ab5daa | 471 | { |
43a34704 | 472 | M48t59State *NVRAM = opaque; |
897b4c6c | 473 | |
13ab5daa FB |
474 | NVRAM->lock ^= 1 << lock; |
475 | } | |
476 | ||
a541f297 FB |
477 | /* IO access to NVRAM */ |
478 | static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) | |
479 | { | |
43a34704 | 480 | M48t59State *NVRAM = opaque; |
a541f297 FB |
481 | |
482 | addr -= NVRAM->io_base; | |
9ed1e667 | 483 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); |
a541f297 FB |
484 | switch (addr) { |
485 | case 0: | |
486 | NVRAM->addr &= ~0x00FF; | |
487 | NVRAM->addr |= val; | |
488 | break; | |
489 | case 1: | |
490 | NVRAM->addr &= ~0xFF00; | |
491 | NVRAM->addr |= val << 8; | |
492 | break; | |
493 | case 3: | |
819385c5 | 494 | m48t59_write(NVRAM, val, NVRAM->addr); |
a541f297 FB |
495 | NVRAM->addr = 0x0000; |
496 | break; | |
497 | default: | |
498 | break; | |
499 | } | |
500 | } | |
501 | ||
502 | static uint32_t NVRAM_readb (void *opaque, uint32_t addr) | |
503 | { | |
43a34704 | 504 | M48t59State *NVRAM = opaque; |
13ab5daa | 505 | uint32_t retval; |
a541f297 | 506 | |
13ab5daa FB |
507 | addr -= NVRAM->io_base; |
508 | switch (addr) { | |
509 | case 3: | |
819385c5 | 510 | retval = m48t59_read(NVRAM, NVRAM->addr); |
13ab5daa FB |
511 | break; |
512 | default: | |
513 | retval = -1; | |
514 | break; | |
515 | } | |
9ed1e667 | 516 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); |
a541f297 | 517 | |
13ab5daa | 518 | return retval; |
a541f297 FB |
519 | } |
520 | ||
c227f099 | 521 | static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
e1bb04f7 | 522 | { |
43a34704 | 523 | M48t59State *NVRAM = opaque; |
3b46e624 | 524 | |
819385c5 | 525 | m48t59_write(NVRAM, addr, value & 0xff); |
e1bb04f7 FB |
526 | } |
527 | ||
c227f099 | 528 | static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
e1bb04f7 | 529 | { |
43a34704 | 530 | M48t59State *NVRAM = opaque; |
3b46e624 | 531 | |
819385c5 FB |
532 | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
533 | m48t59_write(NVRAM, addr + 1, value & 0xff); | |
e1bb04f7 FB |
534 | } |
535 | ||
c227f099 | 536 | static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
e1bb04f7 | 537 | { |
43a34704 | 538 | M48t59State *NVRAM = opaque; |
3b46e624 | 539 | |
819385c5 FB |
540 | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
541 | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); | |
542 | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); | |
543 | m48t59_write(NVRAM, addr + 3, value & 0xff); | |
e1bb04f7 FB |
544 | } |
545 | ||
c227f099 | 546 | static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) |
e1bb04f7 | 547 | { |
43a34704 | 548 | M48t59State *NVRAM = opaque; |
819385c5 | 549 | uint32_t retval; |
3b46e624 | 550 | |
819385c5 | 551 | retval = m48t59_read(NVRAM, addr); |
e1bb04f7 FB |
552 | return retval; |
553 | } | |
554 | ||
c227f099 | 555 | static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) |
e1bb04f7 | 556 | { |
43a34704 | 557 | M48t59State *NVRAM = opaque; |
819385c5 | 558 | uint32_t retval; |
3b46e624 | 559 | |
819385c5 FB |
560 | retval = m48t59_read(NVRAM, addr) << 8; |
561 | retval |= m48t59_read(NVRAM, addr + 1); | |
e1bb04f7 FB |
562 | return retval; |
563 | } | |
564 | ||
c227f099 | 565 | static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) |
e1bb04f7 | 566 | { |
43a34704 | 567 | M48t59State *NVRAM = opaque; |
819385c5 | 568 | uint32_t retval; |
e1bb04f7 | 569 | |
819385c5 FB |
570 | retval = m48t59_read(NVRAM, addr) << 24; |
571 | retval |= m48t59_read(NVRAM, addr + 1) << 16; | |
572 | retval |= m48t59_read(NVRAM, addr + 2) << 8; | |
573 | retval |= m48t59_read(NVRAM, addr + 3); | |
e1bb04f7 FB |
574 | return retval; |
575 | } | |
576 | ||
d60efc6b | 577 | static CPUWriteMemoryFunc * const nvram_write[] = { |
e1bb04f7 FB |
578 | &nvram_writeb, |
579 | &nvram_writew, | |
580 | &nvram_writel, | |
581 | }; | |
582 | ||
d60efc6b | 583 | static CPUReadMemoryFunc * const nvram_read[] = { |
e1bb04f7 FB |
584 | &nvram_readb, |
585 | &nvram_readw, | |
586 | &nvram_readl, | |
587 | }; | |
819385c5 | 588 | |
fd484ae4 JQ |
589 | static const VMStateDescription vmstate_m48t59 = { |
590 | .name = "m48t59", | |
591 | .version_id = 1, | |
592 | .minimum_version_id = 1, | |
593 | .minimum_version_id_old = 1, | |
594 | .fields = (VMStateField[]) { | |
595 | VMSTATE_UINT8(lock, M48t59State), | |
596 | VMSTATE_UINT16(addr, M48t59State), | |
597 | VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size), | |
598 | VMSTATE_END_OF_LIST() | |
599 | } | |
600 | }; | |
3ccacc4a | 601 | |
43a34704 | 602 | static void m48t59_reset_common(M48t59State *NVRAM) |
3ccacc4a | 603 | { |
6e6b7363 BS |
604 | NVRAM->addr = 0; |
605 | NVRAM->lock = 0; | |
3ccacc4a BS |
606 | if (NVRAM->alrm_timer != NULL) |
607 | qemu_del_timer(NVRAM->alrm_timer); | |
608 | ||
609 | if (NVRAM->wd_timer != NULL) | |
610 | qemu_del_timer(NVRAM->wd_timer); | |
611 | } | |
612 | ||
285e468d BS |
613 | static void m48t59_reset_isa(DeviceState *d) |
614 | { | |
615 | M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev); | |
43a34704 | 616 | M48t59State *NVRAM = &isa->state; |
285e468d BS |
617 | |
618 | m48t59_reset_common(NVRAM); | |
619 | } | |
620 | ||
621 | static void m48t59_reset_sysbus(DeviceState *d) | |
622 | { | |
623 | M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); | |
43a34704 | 624 | M48t59State *NVRAM = &sys->state; |
285e468d BS |
625 | |
626 | m48t59_reset_common(NVRAM); | |
627 | } | |
628 | ||
a541f297 | 629 | /* Initialisation routine */ |
43a34704 BS |
630 | M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base, |
631 | uint32_t io_base, uint16_t size, int type) | |
a541f297 | 632 | { |
d27cf0ae BS |
633 | DeviceState *dev; |
634 | SysBusDevice *s; | |
f80237d4 | 635 | M48t59SysBusState *d; |
51f9b84e | 636 | M48t59State *state; |
d27cf0ae BS |
637 | |
638 | dev = qdev_create(NULL, "m48t59"); | |
ee6847d1 GH |
639 | qdev_prop_set_uint32(dev, "type", type); |
640 | qdev_prop_set_uint32(dev, "size", size); | |
641 | qdev_prop_set_uint32(dev, "io_base", io_base); | |
e23a1b33 | 642 | qdev_init_nofail(dev); |
d27cf0ae | 643 | s = sysbus_from_qdev(dev); |
51f9b84e HP |
644 | d = FROM_SYSBUS(M48t59SysBusState, s); |
645 | state = &d->state; | |
d27cf0ae | 646 | sysbus_connect_irq(s, 0, IRQ); |
819385c5 | 647 | if (io_base != 0) { |
51f9b84e HP |
648 | register_ioport_read(io_base, 0x04, 1, NVRAM_readb, state); |
649 | register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, state); | |
819385c5 | 650 | } |
e1bb04f7 | 651 | if (mem_base != 0) { |
d27cf0ae | 652 | sysbus_mmio_map(s, 0, mem_base); |
e1bb04f7 | 653 | } |
d27cf0ae | 654 | |
51f9b84e | 655 | return state; |
d27cf0ae BS |
656 | } |
657 | ||
43a34704 | 658 | M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type) |
d27cf0ae | 659 | { |
f80237d4 BS |
660 | M48t59ISAState *d; |
661 | ISADevice *dev; | |
43a34704 | 662 | M48t59State *s; |
f80237d4 BS |
663 | |
664 | dev = isa_create("m48t59_isa"); | |
665 | qdev_prop_set_uint32(&dev->qdev, "type", type); | |
666 | qdev_prop_set_uint32(&dev->qdev, "size", size); | |
667 | qdev_prop_set_uint32(&dev->qdev, "io_base", io_base); | |
e23a1b33 | 668 | qdev_init_nofail(&dev->qdev); |
f80237d4 BS |
669 | d = DO_UPCAST(M48t59ISAState, busdev, dev); |
670 | s = &d->state; | |
d27cf0ae | 671 | |
f80237d4 BS |
672 | if (io_base != 0) { |
673 | register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s); | |
674 | register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s); | |
dee41d58 | 675 | isa_init_ioport_range(dev, io_base, 4); |
f80237d4 | 676 | } |
d27cf0ae | 677 | |
f80237d4 BS |
678 | return s; |
679 | } | |
d27cf0ae | 680 | |
43a34704 | 681 | static void m48t59_init_common(M48t59State *s) |
f80237d4 | 682 | { |
7267c094 | 683 | s->buffer = g_malloc0(s->size); |
d27cf0ae | 684 | if (s->type == 59) { |
74475455 PB |
685 | s->alrm_timer = qemu_new_timer_ns(vm_clock, &alarm_cb, s); |
686 | s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s); | |
819385c5 | 687 | } |
f6503059 | 688 | qemu_get_timedate(&s->alarm, 0); |
13ab5daa | 689 | |
fd484ae4 | 690 | vmstate_register(NULL, -1, &vmstate_m48t59, s); |
f80237d4 BS |
691 | } |
692 | ||
693 | static int m48t59_init_isa1(ISADevice *dev) | |
694 | { | |
695 | M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); | |
43a34704 | 696 | M48t59State *s = &d->state; |
f80237d4 BS |
697 | |
698 | isa_init_irq(dev, &s->IRQ, 8); | |
699 | m48t59_init_common(s); | |
700 | ||
81a322d4 | 701 | return 0; |
d27cf0ae | 702 | } |
3ccacc4a | 703 | |
f80237d4 BS |
704 | static int m48t59_init1(SysBusDevice *dev) |
705 | { | |
706 | M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); | |
43a34704 | 707 | M48t59State *s = &d->state; |
f80237d4 BS |
708 | int mem_index; |
709 | ||
710 | sysbus_init_irq(dev, &s->IRQ); | |
711 | ||
2507c12a AG |
712 | mem_index = cpu_register_io_memory(nvram_read, nvram_write, s, |
713 | DEVICE_NATIVE_ENDIAN); | |
f80237d4 BS |
714 | sysbus_init_mmio(dev, s->size, mem_index); |
715 | m48t59_init_common(s); | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
720 | static ISADeviceInfo m48t59_isa_info = { | |
721 | .init = m48t59_init_isa1, | |
722 | .qdev.name = "m48t59_isa", | |
723 | .qdev.size = sizeof(M48t59ISAState), | |
285e468d | 724 | .qdev.reset = m48t59_reset_isa, |
f80237d4 BS |
725 | .qdev.no_user = 1, |
726 | .qdev.props = (Property[]) { | |
727 | DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), | |
728 | DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1), | |
729 | DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), | |
730 | DEFINE_PROP_END_OF_LIST(), | |
731 | } | |
732 | }; | |
733 | ||
ee6847d1 GH |
734 | static SysBusDeviceInfo m48t59_info = { |
735 | .init = m48t59_init1, | |
736 | .qdev.name = "m48t59", | |
f80237d4 | 737 | .qdev.size = sizeof(M48t59SysBusState), |
285e468d | 738 | .qdev.reset = m48t59_reset_sysbus, |
ee6847d1 | 739 | .qdev.props = (Property[]) { |
f80237d4 BS |
740 | DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), |
741 | DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1), | |
742 | DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), | |
01274424 | 743 | DEFINE_PROP_END_OF_LIST(), |
ee6847d1 GH |
744 | } |
745 | }; | |
746 | ||
d27cf0ae BS |
747 | static void m48t59_register_devices(void) |
748 | { | |
ee6847d1 | 749 | sysbus_register_withprop(&m48t59_info); |
f80237d4 | 750 | isa_qdev_register(&m48t59_isa_info); |
a541f297 | 751 | } |
d27cf0ae BS |
752 | |
753 | device_init(m48t59_register_devices) |