[qemu.git] / hw / m48t59.c

/*
 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
 *
 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "nvram.h"
#include "isa.h"
#include "qemu-timer.h"
#include "sysemu.h"

//#define DEBUG_NVRAM

#if defined(DEBUG_NVRAM)
#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
#else
#define NVRAM_PRINTF(fmt, args...) do { } while (0)
#endif

/*
 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
 * alarm and a watchdog timer and related control registers. In the
 * PPC platform there is also a nvram lock function.
 */
struct m48t59_t {
    /* Model parameters */
    int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
    /* Hardware parameters */
    qemu_irq IRQ;
    int mem_index;
    target_phys_addr_t mem_base;
    uint32_t io_base;
    uint16_t size;
    /* RTC management */
    time_t   time_offset;
    time_t   stop_time;
    /* Alarm & watchdog */
    struct tm alarm;
    struct QEMUTimer *alrm_timer;
    struct QEMUTimer *wd_timer;
    /* NVRAM storage */
    uint8_t  lock;
    uint16_t addr;
    uint8_t *buffer;
};

/* Fake timer functions */
/* Generic helpers for BCD */
static inline uint8_t toBCD (uint8_t value)
{
    return (((value / 10) % 10) << 4) | (value % 10);
}

static inline uint8_t fromBCD (uint8_t BCD)
{
    return ((BCD >> 4) * 10) + (BCD & 0x0F);
}

/* Alarm management */
static void alarm_cb (void *opaque)
{
    struct tm tm;
    uint64_t next_time;
    m48t59_t *NVRAM = opaque;

    qemu_set_irq(NVRAM->IRQ, 1);
    if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
        /* Repeat once a month */
        qemu_get_timedate(&tm, NVRAM->time_offset);
        tm.tm_mon++;
        if (tm.tm_mon == 13) {
            tm.tm_mon = 1;
            tm.tm_year++;
        }
        next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	       (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
        /* Repeat once a day */
        next_time = 24 * 60 * 60;
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
        /* Repeat once an hour */
        next_time = 60 * 60;
    } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
	       (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
        /* Repeat once a minute */
        next_time = 60;
    } else {
        /* Repeat once a second */
        next_time = 1;
    }
    qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) +
                    next_time * 1000);
    qemu_set_irq(NVRAM->IRQ, 0);
}

static void set_alarm (m48t59_t *NVRAM)
{
    int diff;
    if (NVRAM->alrm_timer != NULL) {
        qemu_del_timer(NVRAM->alrm_timer);
        diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
        if (diff > 0)
            qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
    }
}

/* RTC management helpers */
static inline void get_time (m48t59_t *NVRAM, struct tm *tm)
{
    qemu_get_timedate(tm, NVRAM->time_offset);
}

static void set_time (m48t59_t *NVRAM, struct tm *tm)
{
    NVRAM->time_offset = qemu_timedate_diff(tm);
    set_alarm(NVRAM);
}

/* Watchdog management */
static void watchdog_cb (void *opaque)
{
    m48t59_t *NVRAM = opaque;

    NVRAM->buffer[0x1FF0] |= 0x80;
    if (NVRAM->buffer[0x1FF7] & 0x80) {
	NVRAM->buffer[0x1FF7] = 0x00;
	NVRAM->buffer[0x1FFC] &= ~0x40;
        /* May it be a hw CPU Reset instead ? */
        qemu_system_reset_request();
    } else {
	qemu_set_irq(NVRAM->IRQ, 1);
	qemu_set_irq(NVRAM->IRQ, 0);
    }
}

static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
{
    uint64_t interval; /* in 1/16 seconds */

    NVRAM->buffer[0x1FF0] &= ~0x80;
    if (NVRAM->wd_timer != NULL) {
        qemu_del_timer(NVRAM->wd_timer);
        if (value != 0) {
            interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
            qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
                           ((interval * 1000) >> 4));
        }
    }
}

/* Direct access to NVRAM */
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
{
    m48t59_t *NVRAM = opaque;
    struct tm tm;
    int tmp;

    if (addr > 0x1FF8 && addr < 0x2000)
	NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);

    /* check for NVRAM access */
    if ((NVRAM->type == 2 && addr < 0x7f8) ||
        (NVRAM->type == 8 && addr < 0x1ff8) ||
        (NVRAM->type == 59 && addr < 0x1ff0))
        goto do_write;

    /* TOD access */
    switch (addr) {
    case 0x1FF0:
        /* flags register : read-only */
        break;
    case 0x1FF1:
        /* unused */
        break;
    case 0x1FF2:
        /* alarm seconds */
        tmp = fromBCD(val & 0x7F);
        if (tmp >= 0 && tmp <= 59) {
            NVRAM->alarm.tm_sec = tmp;
            NVRAM->buffer[0x1FF2] = val;
            set_alarm(NVRAM);
        }
        break;
    case 0x1FF3:
        /* alarm minutes */
        tmp = fromBCD(val & 0x7F);
        if (tmp >= 0 && tmp <= 59) {
            NVRAM->alarm.tm_min = tmp;
            NVRAM->buffer[0x1FF3] = val;
            set_alarm(NVRAM);
        }
        break;
    case 0x1FF4:
        /* alarm hours */
        tmp = fromBCD(val & 0x3F);
        if (tmp >= 0 && tmp <= 23) {
            NVRAM->alarm.tm_hour = tmp;
            NVRAM->buffer[0x1FF4] = val;
            set_alarm(NVRAM);
        }
        break;
    case 0x1FF5:
        /* alarm date */
        tmp = fromBCD(val & 0x1F);
        if (tmp != 0) {
            NVRAM->alarm.tm_mday = tmp;
            NVRAM->buffer[0x1FF5] = val;
            set_alarm(NVRAM);
        }
        break;
    case 0x1FF6:
        /* interrupts */
        NVRAM->buffer[0x1FF6] = val;
        break;
    case 0x1FF7:
        /* watchdog */
        NVRAM->buffer[0x1FF7] = val;
        set_up_watchdog(NVRAM, val);
        break;
    case 0x1FF8:
    case 0x07F8:
        /* control */
       NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
        break;
    case 0x1FF9:
    case 0x07F9:
        /* seconds (BCD) */
	tmp = fromBCD(val & 0x7F);
	if (tmp >= 0 && tmp <= 59) {
	    get_time(NVRAM, &tm);
	    tm.tm_sec = tmp;
	    set_time(NVRAM, &tm);
	}
        if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
	    if (val & 0x80) {
		NVRAM->stop_time = time(NULL);
	    } else {
		NVRAM->time_offset += NVRAM->stop_time - time(NULL);
		NVRAM->stop_time = 0;
	    }
	}
        NVRAM->buffer[addr] = val & 0x80;
        break;
    case 0x1FFA:
    case 0x07FA:
        /* minutes (BCD) */
	tmp = fromBCD(val & 0x7F);
	if (tmp >= 0 && tmp <= 59) {
	    get_time(NVRAM, &tm);
	    tm.tm_min = tmp;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFB:
    case 0x07FB:
        /* hours (BCD) */
	tmp = fromBCD(val & 0x3F);
	if (tmp >= 0 && tmp <= 23) {
	    get_time(NVRAM, &tm);
	    tm.tm_hour = tmp;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFC:
    case 0x07FC:
        /* day of the week / century */
	tmp = fromBCD(val & 0x07);
	get_time(NVRAM, &tm);
	tm.tm_wday = tmp;
	set_time(NVRAM, &tm);
        NVRAM->buffer[addr] = val & 0x40;
        break;
    case 0x1FFD:
    case 0x07FD:
        /* date */
	tmp = fromBCD(val & 0x1F);
	if (tmp != 0) {
	    get_time(NVRAM, &tm);
	    tm.tm_mday = tmp;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFE:
    case 0x07FE:
        /* month */
	tmp = fromBCD(val & 0x1F);
	if (tmp >= 1 && tmp <= 12) {
	    get_time(NVRAM, &tm);
	    tm.tm_mon = tmp - 1;
	    set_time(NVRAM, &tm);
	}
        break;
    case 0x1FFF:
    case 0x07FF:
        /* year */
	tmp = fromBCD(val);
	if (tmp >= 0 && tmp <= 99) {
	    get_time(NVRAM, &tm);
            if (NVRAM->type == 8)
                tm.tm_year = fromBCD(val) + 68; // Base year is 1968
            else
                tm.tm_year = fromBCD(val);
	    set_time(NVRAM, &tm);
	}
        break;
    default:
        /* Check lock registers state */
        if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
            break;
        if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
            break;
    do_write:
        if (addr < NVRAM->size) {
            NVRAM->buffer[addr] = val & 0xFF;
	}
        break;
    }
}

uint32_t m48t59_read (void *opaque, uint32_t addr)
{
    m48t59_t *NVRAM = opaque;
    struct tm tm;
    uint32_t retval = 0xFF;

    /* check for NVRAM access */
    if ((NVRAM->type == 2 && addr < 0x078f) ||
        (NVRAM->type == 8 && addr < 0x1ff8) ||
        (NVRAM->type == 59 && addr < 0x1ff0))
        goto do_read;

    /* TOD access */
    switch (addr) {
    case 0x1FF0:
        /* flags register */
	goto do_read;
    case 0x1FF1:
        /* unused */
	retval = 0;
        break;
    case 0x1FF2:
        /* alarm seconds */
	goto do_read;
    case 0x1FF3:
        /* alarm minutes */
	goto do_read;
    case 0x1FF4:
        /* alarm hours */
	goto do_read;
    case 0x1FF5:
        /* alarm date */
	goto do_read;
    case 0x1FF6:
        /* interrupts */
	goto do_read;
    case 0x1FF7:
	/* A read resets the watchdog */
	set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
	goto do_read;
    case 0x1FF8:
    case 0x07F8:
        /* control */
	goto do_read;
    case 0x1FF9:
    case 0x07F9:
        /* seconds (BCD) */
        get_time(NVRAM, &tm);
        retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
        break;
    case 0x1FFA:
    case 0x07FA:
        /* minutes (BCD) */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_min);
        break;
    case 0x1FFB:
    case 0x07FB:
        /* hours (BCD) */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_hour);
        break;
    case 0x1FFC:
    case 0x07FC:
        /* day of the week / century */
        get_time(NVRAM, &tm);
        retval = NVRAM->buffer[addr] | tm.tm_wday;
        break;
    case 0x1FFD:
    case 0x07FD:
        /* date */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_mday);
        break;
    case 0x1FFE:
    case 0x07FE:
        /* month */
        get_time(NVRAM, &tm);
        retval = toBCD(tm.tm_mon + 1);
        break;
    case 0x1FFF:
    case 0x07FF:
        /* year */
        get_time(NVRAM, &tm);
        if (NVRAM->type == 8)
            retval = toBCD(tm.tm_year - 68); // Base year is 1968
        else
            retval = toBCD(tm.tm_year);
        break;
    default:
        /* Check lock registers state */
        if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
            break;
        if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
            break;
    do_read:
        if (addr < NVRAM->size) {
            retval = NVRAM->buffer[addr];
	}
        break;
    }
    if (addr > 0x1FF9 && addr < 0x2000)
       NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);

    return retval;
}

void m48t59_set_addr (void *opaque, uint32_t addr)
{
    m48t59_t *NVRAM = opaque;

    NVRAM->addr = addr;
}

void m48t59_toggle_lock (void *opaque, int lock)
{
    m48t59_t *NVRAM = opaque;

    NVRAM->lock ^= 1 << lock;
}

/* IO access to NVRAM */
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
{
    m48t59_t *NVRAM = opaque;

    addr -= NVRAM->io_base;
    NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
    switch (addr) {
    case 0:
        NVRAM->addr &= ~0x00FF;
        NVRAM->addr |= val;
        break;
    case 1:
        NVRAM->addr &= ~0xFF00;
        NVRAM->addr |= val << 8;
        break;
    case 3:
        m48t59_write(NVRAM, val, NVRAM->addr);
        NVRAM->addr = 0x0000;
        break;
    default:
        break;
    }
}

static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    addr -= NVRAM->io_base;
    switch (addr) {
    case 3:
        retval = m48t59_read(NVRAM, NVRAM->addr);
        break;
    default:
        retval = -1;
        break;
    }
    NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);

    return retval;
}

static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    m48t59_t *NVRAM = opaque;

    addr -= NVRAM->mem_base;
    m48t59_write(NVRAM, addr, value & 0xff);
}

static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    m48t59_t *NVRAM = opaque;

    addr -= NVRAM->mem_base;
    m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
    m48t59_write(NVRAM, addr + 1, value & 0xff);
}

static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    m48t59_t *NVRAM = opaque;

    addr -= NVRAM->mem_base;
    m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
    m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
    m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
    m48t59_write(NVRAM, addr + 3, value & 0xff);
}

static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    addr -= NVRAM->mem_base;
    retval = m48t59_read(NVRAM, addr);
    return retval;
}

static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    addr -= NVRAM->mem_base;
    retval = m48t59_read(NVRAM, addr) << 8;
    retval |= m48t59_read(NVRAM, addr + 1);
    return retval;
}

static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
    m48t59_t *NVRAM = opaque;
    uint32_t retval;

    addr -= NVRAM->mem_base;
    retval = m48t59_read(NVRAM, addr) << 24;
    retval |= m48t59_read(NVRAM, addr + 1) << 16;
    retval |= m48t59_read(NVRAM, addr + 2) << 8;
    retval |= m48t59_read(NVRAM, addr + 3);
    return retval;
}

static CPUWriteMemoryFunc *nvram_write[] = {
    &nvram_writeb,
    &nvram_writew,
    &nvram_writel,
};

static CPUReadMemoryFunc *nvram_read[] = {
    &nvram_readb,
    &nvram_readw,
    &nvram_readl,
};

static void m48t59_save(QEMUFile *f, void *opaque)
{
    m48t59_t *s = opaque;

    qemu_put_8s(f, &s->lock);
    qemu_put_be16s(f, &s->addr);
    qemu_put_buffer(f, s->buffer, s->size);
}

static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
{
    m48t59_t *s = opaque;

    if (version_id != 1)
        return -EINVAL;

    qemu_get_8s(f, &s->lock);
    qemu_get_be16s(f, &s->addr);
    qemu_get_buffer(f, s->buffer, s->size);

    return 0;
}

static void m48t59_reset(void *opaque)
{
    m48t59_t *NVRAM = opaque;

    if (NVRAM->alrm_timer != NULL)
        qemu_del_timer(NVRAM->alrm_timer);

    if (NVRAM->wd_timer != NULL)
        qemu_del_timer(NVRAM->wd_timer);
}

/* Initialisation routine */
m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
                       uint32_t io_base, uint16_t size,
                       int type)
{
    m48t59_t *s;
    target_phys_addr_t save_base;

    s = qemu_mallocz(sizeof(m48t59_t));
    if (!s)
	return NULL;
    s->buffer = qemu_mallocz(size);
    if (!s->buffer) {
        qemu_free(s);
        return NULL;
    }
    s->IRQ = IRQ;
    s->size = size;
    s->mem_base = mem_base;
    s->io_base = io_base;
    s->addr = 0;
    s->type = type;
    if (io_base != 0) {
        register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
        register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
    }
    if (mem_base != 0) {
        s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
        cpu_register_physical_memory(mem_base, size, s->mem_index);
    }
    if (type == 59) {
        s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
        s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
    }
    s->lock = 0;
    qemu_get_timedate(&s->alarm, 0);

    qemu_register_reset(m48t59_reset, s);
    save_base = mem_base ? mem_base : io_base;
    register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);

    return s;
}
Commit	Line	Data
a541f297	1	/*
819385c5	2	* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
5fafdf24	3	*
3ccacc4a	4	* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
5fafdf24	5	*
a541f297 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "nvram.h"
	26	#include "isa.h"
	27	#include "qemu-timer.h"
	28	#include "sysemu.h"
a541f297	29
13ab5daa	30	//#define DEBUG_NVRAM
a541f297	31
13ab5daa	32	#if defined(DEBUG_NVRAM)
a541f297 FB	33	#define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
	34	#else
	35	#define NVRAM_PRINTF(fmt, args...) do { } while (0)
	36	#endif
	37
819385c5	38	/*
4aed2c33	39	* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
819385c5 FB	40	* alarm and a watchdog timer and related control registers. In the
	41	* PPC platform there is also a nvram lock function.
	42	*/
c5df018e	43	struct m48t59_t {
819385c5	44	/* Model parameters */
4aed2c33	45	int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
a541f297	46	/* Hardware parameters */
d537cf6c	47	qemu_irq IRQ;
e1bb04f7	48	int mem_index;
5dcb6b91	49	target_phys_addr_t mem_base;
a541f297 FB	50	uint32_t io_base;
	51	uint16_t size;
	52	/* RTC management */
	53	time_t time_offset;
	54	time_t stop_time;
	55	/* Alarm & watchdog */
f6503059	56	struct tm alarm;
a541f297 FB	57	struct QEMUTimer *alrm_timer;
	58	struct QEMUTimer *wd_timer;
	59	/* NVRAM storage */
13ab5daa	60	uint8_t lock;
a541f297 FB	61	uint16_t addr;
a541f297 FB	62	uint8_t *buffer;
c5df018e	63	};
a541f297 FB	64
	65	/* Fake timer functions */
	66	/* Generic helpers for BCD */
	67	static inline uint8_t toBCD (uint8_t value)
	68	{
	69	return (((value / 10) % 10) << 4) \| (value % 10);
	70	}
	71
	72	static inline uint8_t fromBCD (uint8_t BCD)
	73	{
	74	return ((BCD >> 4) * 10) + (BCD & 0x0F);
	75	}
	76
a541f297 FB	77	/* Alarm management */
	78	static void alarm_cb (void *opaque)
	79	{
f6503059	80	struct tm tm;
a541f297 FB	81	uint64_t next_time;
	82	m48t59_t *NVRAM = opaque;
	83
d537cf6c	84	qemu_set_irq(NVRAM->IRQ, 1);
5fafdf24	85	if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
a541f297 FB	86	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	87	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	88	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
f6503059 AZ	89	/* Repeat once a month */
	90	qemu_get_timedate(&tm, NVRAM->time_offset);
	91	tm.tm_mon++;
	92	if (tm.tm_mon == 13) {
	93	tm.tm_mon = 1;
	94	tm.tm_year++;
	95	}
	96	next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
a541f297 FB	97	} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	98	(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
	99	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	100	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
f6503059 AZ	101	/* Repeat once a day */
f6503059 AZ	102	next_time = 24 * 60 * 60;
a541f297 FB	103	} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	104	(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	105	(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
	106	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
f6503059 AZ	107	/* Repeat once an hour */
f6503059 AZ	108	next_time = 60 * 60;
a541f297 FB	109	} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
	110	(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
	111	(NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
	112	(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
f6503059 AZ	113	/* Repeat once a minute */
f6503059 AZ	114	next_time = 60;
a541f297	115	} else {
f6503059 AZ	116	/* Repeat once a second */
f6503059 AZ	117	next_time = 1;
a541f297	118	}
f6503059 AZ	119	qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) +
f6503059 AZ	120	next_time * 1000);
d537cf6c	121	qemu_set_irq(NVRAM->IRQ, 0);
a541f297 FB	122	}
a541f297 FB	123
f6503059 AZ	124	static void set_alarm (m48t59_t *NVRAM)
	125	{
	126	int diff;
	127	if (NVRAM->alrm_timer != NULL) {
	128	qemu_del_timer(NVRAM->alrm_timer);
	129	diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
	130	if (diff > 0)
	131	qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
	132	}
	133	}
a541f297	134
f6503059 AZ	135	/* RTC management helpers */
f6503059 AZ	136	static inline void get_time (m48t59_t NVRAM, struct tm tm)
a541f297	137	{
f6503059	138	qemu_get_timedate(tm, NVRAM->time_offset);
a541f297 FB	139	}
a541f297 FB	140
f6503059	141	static void set_time (m48t59_t NVRAM, struct tm tm)
a541f297	142	{
f6503059 AZ	143	NVRAM->time_offset = qemu_timedate_diff(tm);
f6503059 AZ	144	set_alarm(NVRAM);
a541f297 FB	145	}
	146
	147	/* Watchdog management */
	148	static void watchdog_cb (void *opaque)
	149	{
	150	m48t59_t *NVRAM = opaque;
	151
	152	NVRAM->buffer[0x1FF0] \|= 0x80;
	153	if (NVRAM->buffer[0x1FF7] & 0x80) {
	154	NVRAM->buffer[0x1FF7] = 0x00;
	155	NVRAM->buffer[0x1FFC] &= ~0x40;
13ab5daa	156	/* May it be a hw CPU Reset instead ? */
d7d02e3c	157	qemu_system_reset_request();
a541f297	158	} else {
d537cf6c PB	159	qemu_set_irq(NVRAM->IRQ, 1);
d537cf6c PB	160	qemu_set_irq(NVRAM->IRQ, 0);
a541f297 FB	161	}
	162	}
	163
	164	static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
	165	{
	166	uint64_t interval; /* in 1/16 seconds */
	167
868d585a	168	NVRAM->buffer[0x1FF0] &= ~0x80;
a541f297 FB	169	if (NVRAM->wd_timer != NULL) {
a541f297 FB	170	qemu_del_timer(NVRAM->wd_timer);
868d585a JM	171	if (value != 0) {
	172	interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
	173	qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
	174	((interval * 1000) >> 4));
	175	}
a541f297 FB	176	}
	177	}
	178
	179	/* Direct access to NVRAM */
897b4c6c	180	void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
a541f297	181	{
897b4c6c	182	m48t59_t *NVRAM = opaque;
a541f297 FB	183	struct tm tm;
	184	int tmp;
	185
819385c5 FB	186	if (addr > 0x1FF8 && addr < 0x2000)
819385c5 FB	187	NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
4aed2c33 BS	188
	189	/* check for NVRAM access */
	190	if ((NVRAM->type == 2 && addr < 0x7f8) \|\|
	191	(NVRAM->type == 8 && addr < 0x1ff8) \|\|
	192	(NVRAM->type == 59 && addr < 0x1ff0))
819385c5	193	goto do_write;
4aed2c33 BS	194
4aed2c33 BS	195	/* TOD access */
819385c5	196	switch (addr) {
a541f297 FB	197	case 0x1FF0:
	198	/* flags register : read-only */
	199	break;
	200	case 0x1FF1:
	201	/* unused */
	202	break;
	203	case 0x1FF2:
	204	/* alarm seconds */
819385c5 FB	205	tmp = fromBCD(val & 0x7F);
819385c5 FB	206	if (tmp >= 0 && tmp <= 59) {
f6503059	207	NVRAM->alarm.tm_sec = tmp;
819385c5	208	NVRAM->buffer[0x1FF2] = val;
f6503059	209	set_alarm(NVRAM);
819385c5	210	}
a541f297 FB	211	break;
	212	case 0x1FF3:
	213	/* alarm minutes */
819385c5 FB	214	tmp = fromBCD(val & 0x7F);
819385c5 FB	215	if (tmp >= 0 && tmp <= 59) {
f6503059	216	NVRAM->alarm.tm_min = tmp;
819385c5	217	NVRAM->buffer[0x1FF3] = val;
f6503059	218	set_alarm(NVRAM);
819385c5	219	}
a541f297 FB	220	break;
	221	case 0x1FF4:
	222	/* alarm hours */
819385c5 FB	223	tmp = fromBCD(val & 0x3F);
819385c5 FB	224	if (tmp >= 0 && tmp <= 23) {
f6503059	225	NVRAM->alarm.tm_hour = tmp;
819385c5	226	NVRAM->buffer[0x1FF4] = val;
f6503059	227	set_alarm(NVRAM);
819385c5	228	}
a541f297 FB	229	break;
	230	case 0x1FF5:
	231	/* alarm date */
819385c5 FB	232	tmp = fromBCD(val & 0x1F);
819385c5 FB	233	if (tmp != 0) {
f6503059	234	NVRAM->alarm.tm_mday = tmp;
819385c5	235	NVRAM->buffer[0x1FF5] = val;
f6503059	236	set_alarm(NVRAM);
819385c5	237	}
a541f297 FB	238	break;
	239	case 0x1FF6:
	240	/* interrupts */
819385c5	241	NVRAM->buffer[0x1FF6] = val;
a541f297 FB	242	break;
	243	case 0x1FF7:
	244	/* watchdog */
819385c5 FB	245	NVRAM->buffer[0x1FF7] = val;
819385c5 FB	246	set_up_watchdog(NVRAM, val);
a541f297 FB	247	break;
a541f297 FB	248	case 0x1FF8:
4aed2c33	249	case 0x07F8:
a541f297	250	/* control */
4aed2c33	251	NVRAM->buffer[addr] = (val & ~0xA0) \| 0x90;
a541f297 FB	252	break;
a541f297 FB	253	case 0x1FF9:
4aed2c33	254	case 0x07F9:
a541f297 FB	255	/* seconds (BCD) */
	256	tmp = fromBCD(val & 0x7F);
	257	if (tmp >= 0 && tmp <= 59) {
	258	get_time(NVRAM, &tm);
	259	tm.tm_sec = tmp;
	260	set_time(NVRAM, &tm);
	261	}
f6503059	262	if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
a541f297 FB	263	if (val & 0x80) {
	264	NVRAM->stop_time = time(NULL);
	265	} else {
	266	NVRAM->time_offset += NVRAM->stop_time - time(NULL);
	267	NVRAM->stop_time = 0;
	268	}
	269	}
f6503059	270	NVRAM->buffer[addr] = val & 0x80;
a541f297 FB	271	break;
a541f297 FB	272	case 0x1FFA:
4aed2c33	273	case 0x07FA:
a541f297 FB	274	/* minutes (BCD) */
	275	tmp = fromBCD(val & 0x7F);
	276	if (tmp >= 0 && tmp <= 59) {
	277	get_time(NVRAM, &tm);
	278	tm.tm_min = tmp;
	279	set_time(NVRAM, &tm);
	280	}
	281	break;
	282	case 0x1FFB:
4aed2c33	283	case 0x07FB:
a541f297 FB	284	/* hours (BCD) */
	285	tmp = fromBCD(val & 0x3F);
	286	if (tmp >= 0 && tmp <= 23) {
	287	get_time(NVRAM, &tm);
	288	tm.tm_hour = tmp;
	289	set_time(NVRAM, &tm);
	290	}
	291	break;
	292	case 0x1FFC:
4aed2c33	293	case 0x07FC:
a541f297 FB	294	/* day of the week / century */
	295	tmp = fromBCD(val & 0x07);
	296	get_time(NVRAM, &tm);
	297	tm.tm_wday = tmp;
	298	set_time(NVRAM, &tm);
4aed2c33	299	NVRAM->buffer[addr] = val & 0x40;
a541f297 FB	300	break;
a541f297 FB	301	case 0x1FFD:
4aed2c33	302	case 0x07FD:
a541f297 FB	303	/* date */
	304	tmp = fromBCD(val & 0x1F);
	305	if (tmp != 0) {
	306	get_time(NVRAM, &tm);
	307	tm.tm_mday = tmp;
	308	set_time(NVRAM, &tm);
	309	}
	310	break;
	311	case 0x1FFE:
4aed2c33	312	case 0x07FE:
a541f297 FB	313	/* month */
	314	tmp = fromBCD(val & 0x1F);
	315	if (tmp >= 1 && tmp <= 12) {
	316	get_time(NVRAM, &tm);
	317	tm.tm_mon = tmp - 1;
	318	set_time(NVRAM, &tm);
	319	}
	320	break;
	321	case 0x1FFF:
4aed2c33	322	case 0x07FF:
a541f297 FB	323	/* year */
	324	tmp = fromBCD(val);
	325	if (tmp >= 0 && tmp <= 99) {
	326	get_time(NVRAM, &tm);
180b700d FB	327	if (NVRAM->type == 8)
	328	tm.tm_year = fromBCD(val) + 68; // Base year is 1968
	329	else
	330	tm.tm_year = fromBCD(val);
a541f297 FB	331	set_time(NVRAM, &tm);
	332	}
	333	break;
	334	default:
13ab5daa	335	/* Check lock registers state */
819385c5	336	if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
13ab5daa	337	break;
819385c5	338	if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
13ab5daa	339	break;
819385c5 FB	340	do_write:
	341	if (addr < NVRAM->size) {
	342	NVRAM->buffer[addr] = val & 0xFF;
a541f297 FB	343	}
	344	break;
	345	}
	346	}
	347
897b4c6c	348	uint32_t m48t59_read (void *opaque, uint32_t addr)
a541f297	349	{
897b4c6c	350	m48t59_t *NVRAM = opaque;
a541f297 FB	351	struct tm tm;
	352	uint32_t retval = 0xFF;
	353
4aed2c33 BS	354	/* check for NVRAM access */
	355	if ((NVRAM->type == 2 && addr < 0x078f) \|\|
	356	(NVRAM->type == 8 && addr < 0x1ff8) \|\|
	357	(NVRAM->type == 59 && addr < 0x1ff0))
819385c5	358	goto do_read;
4aed2c33 BS	359
4aed2c33 BS	360	/* TOD access */
819385c5	361	switch (addr) {
a541f297 FB	362	case 0x1FF0:
	363	/* flags register */
	364	goto do_read;
	365	case 0x1FF1:
	366	/* unused */
	367	retval = 0;
	368	break;
	369	case 0x1FF2:
	370	/* alarm seconds */
	371	goto do_read;
	372	case 0x1FF3:
	373	/* alarm minutes */
	374	goto do_read;
	375	case 0x1FF4:
	376	/* alarm hours */
	377	goto do_read;
	378	case 0x1FF5:
	379	/* alarm date */
	380	goto do_read;
	381	case 0x1FF6:
	382	/* interrupts */
	383	goto do_read;
	384	case 0x1FF7:
	385	/* A read resets the watchdog */
	386	set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
	387	goto do_read;
	388	case 0x1FF8:
4aed2c33	389	case 0x07F8:
a541f297 FB	390	/* control */
	391	goto do_read;
	392	case 0x1FF9:
4aed2c33	393	case 0x07F9:
a541f297 FB	394	/* seconds (BCD) */
a541f297 FB	395	get_time(NVRAM, &tm);
4aed2c33	396	retval = (NVRAM->buffer[addr] & 0x80) \| toBCD(tm.tm_sec);
a541f297 FB	397	break;
a541f297 FB	398	case 0x1FFA:
4aed2c33	399	case 0x07FA:
a541f297 FB	400	/* minutes (BCD) */
	401	get_time(NVRAM, &tm);
	402	retval = toBCD(tm.tm_min);
	403	break;
	404	case 0x1FFB:
4aed2c33	405	case 0x07FB:
a541f297 FB	406	/* hours (BCD) */
	407	get_time(NVRAM, &tm);
	408	retval = toBCD(tm.tm_hour);
	409	break;
	410	case 0x1FFC:
4aed2c33	411	case 0x07FC:
a541f297 FB	412	/* day of the week / century */
a541f297 FB	413	get_time(NVRAM, &tm);
4aed2c33	414	retval = NVRAM->buffer[addr] \| tm.tm_wday;
a541f297 FB	415	break;
a541f297 FB	416	case 0x1FFD:
4aed2c33	417	case 0x07FD:
a541f297 FB	418	/* date */
	419	get_time(NVRAM, &tm);
	420	retval = toBCD(tm.tm_mday);
	421	break;
	422	case 0x1FFE:
4aed2c33	423	case 0x07FE:
a541f297 FB	424	/* month */
	425	get_time(NVRAM, &tm);
	426	retval = toBCD(tm.tm_mon + 1);
	427	break;
	428	case 0x1FFF:
4aed2c33	429	case 0x07FF:
a541f297 FB	430	/* year */
a541f297 FB	431	get_time(NVRAM, &tm);
5fafdf24	432	if (NVRAM->type == 8)
180b700d FB	433	retval = toBCD(tm.tm_year - 68); // Base year is 1968
	434	else
	435	retval = toBCD(tm.tm_year);
a541f297 FB	436	break;
a541f297 FB	437	default:
13ab5daa	438	/* Check lock registers state */
819385c5	439	if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
13ab5daa	440	break;
819385c5	441	if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
13ab5daa	442	break;
819385c5 FB	443	do_read:
	444	if (addr < NVRAM->size) {
	445	retval = NVRAM->buffer[addr];
a541f297 FB	446	}
	447	break;
	448	}
819385c5	449	if (addr > 0x1FF9 && addr < 0x2000)
9ed1e667	450	NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
a541f297 FB	451
	452	return retval;
	453	}
	454
897b4c6c	455	void m48t59_set_addr (void *opaque, uint32_t addr)
a541f297	456	{
897b4c6c JM	457	m48t59_t *NVRAM = opaque;
897b4c6c JM	458
a541f297 FB	459	NVRAM->addr = addr;
	460	}
	461
897b4c6c	462	void m48t59_toggle_lock (void *opaque, int lock)
13ab5daa	463	{
897b4c6c JM	464	m48t59_t *NVRAM = opaque;
897b4c6c JM	465
13ab5daa FB	466	NVRAM->lock ^= 1 << lock;
	467	}
	468
a541f297 FB	469	/* IO access to NVRAM */
	470	static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
	471	{
	472	m48t59_t *NVRAM = opaque;
	473
	474	addr -= NVRAM->io_base;
9ed1e667	475	NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
a541f297 FB	476	switch (addr) {
	477	case 0:
	478	NVRAM->addr &= ~0x00FF;
	479	NVRAM->addr \|= val;
	480	break;
	481	case 1:
	482	NVRAM->addr &= ~0xFF00;
	483	NVRAM->addr \|= val << 8;
	484	break;
	485	case 3:
819385c5	486	m48t59_write(NVRAM, val, NVRAM->addr);
a541f297 FB	487	NVRAM->addr = 0x0000;
	488	break;
	489	default:
	490	break;
	491	}
	492	}
	493
	494	static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
	495	{
	496	m48t59_t *NVRAM = opaque;
13ab5daa	497	uint32_t retval;
a541f297	498
13ab5daa FB	499	addr -= NVRAM->io_base;
	500	switch (addr) {
	501	case 3:
819385c5	502	retval = m48t59_read(NVRAM, NVRAM->addr);
13ab5daa FB	503	break;
	504	default:
	505	retval = -1;
	506	break;
	507	}
9ed1e667	508	NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
a541f297	509
13ab5daa	510	return retval;
a541f297 FB	511	}
a541f297 FB	512
e1bb04f7 FB	513	static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
	514	{
	515	m48t59_t *NVRAM = opaque;
3b46e624	516
e1bb04f7	517	addr -= NVRAM->mem_base;
819385c5	518	m48t59_write(NVRAM, addr, value & 0xff);
e1bb04f7 FB	519	}
	520
	521	static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
	522	{
	523	m48t59_t *NVRAM = opaque;
3b46e624	524
e1bb04f7	525	addr -= NVRAM->mem_base;
819385c5 FB	526	m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
819385c5 FB	527	m48t59_write(NVRAM, addr + 1, value & 0xff);
e1bb04f7 FB	528	}
	529
	530	static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	531	{
	532	m48t59_t *NVRAM = opaque;
3b46e624	533
e1bb04f7	534	addr -= NVRAM->mem_base;
819385c5 FB	535	m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
	536	m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
	537	m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
	538	m48t59_write(NVRAM, addr + 3, value & 0xff);
e1bb04f7 FB	539	}
	540
	541	static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
	542	{
	543	m48t59_t *NVRAM = opaque;
819385c5	544	uint32_t retval;
3b46e624	545
e1bb04f7	546	addr -= NVRAM->mem_base;
819385c5	547	retval = m48t59_read(NVRAM, addr);
e1bb04f7 FB	548	return retval;
	549	}
	550
	551	static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
	552	{
	553	m48t59_t *NVRAM = opaque;
819385c5	554	uint32_t retval;
3b46e624	555
e1bb04f7	556	addr -= NVRAM->mem_base;
819385c5 FB	557	retval = m48t59_read(NVRAM, addr) << 8;
819385c5 FB	558	retval \|= m48t59_read(NVRAM, addr + 1);
e1bb04f7 FB	559	return retval;
	560	}
	561
	562	static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
	563	{
	564	m48t59_t *NVRAM = opaque;
819385c5	565	uint32_t retval;
e1bb04f7	566
819385c5 FB	567	addr -= NVRAM->mem_base;
	568	retval = m48t59_read(NVRAM, addr) << 24;
	569	retval \|= m48t59_read(NVRAM, addr + 1) << 16;
	570	retval \|= m48t59_read(NVRAM, addr + 2) << 8;
	571	retval \|= m48t59_read(NVRAM, addr + 3);
e1bb04f7 FB	572	return retval;
	573	}
	574
	575	static CPUWriteMemoryFunc *nvram_write[] = {
	576	&nvram_writeb,
	577	&nvram_writew,
	578	&nvram_writel,
	579	};
	580
	581	static CPUReadMemoryFunc *nvram_read[] = {
	582	&nvram_readb,
	583	&nvram_readw,
	584	&nvram_readl,
	585	};
819385c5	586
3ccacc4a BS	587	static void m48t59_save(QEMUFile f, void opaque)
	588	{
	589	m48t59_t *s = opaque;
	590
	591	qemu_put_8s(f, &s->lock);
	592	qemu_put_be16s(f, &s->addr);
	593	qemu_put_buffer(f, s->buffer, s->size);
	594	}
	595
	596	static int m48t59_load(QEMUFile f, void opaque, int version_id)
	597	{
	598	m48t59_t *s = opaque;
	599
	600	if (version_id != 1)
	601	return -EINVAL;
	602
	603	qemu_get_8s(f, &s->lock);
	604	qemu_get_be16s(f, &s->addr);
	605	qemu_get_buffer(f, s->buffer, s->size);
	606
	607	return 0;
	608	}
	609
	610	static void m48t59_reset(void *opaque)
	611	{
	612	m48t59_t *NVRAM = opaque;
	613
	614	if (NVRAM->alrm_timer != NULL)
	615	qemu_del_timer(NVRAM->alrm_timer);
	616
	617	if (NVRAM->wd_timer != NULL)
	618	qemu_del_timer(NVRAM->wd_timer);
	619	}
	620
a541f297	621	/* Initialisation routine */
5dcb6b91	622	m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
819385c5 FB	623	uint32_t io_base, uint16_t size,
819385c5 FB	624	int type)
a541f297	625	{
c5df018e	626	m48t59_t *s;
5dcb6b91	627	target_phys_addr_t save_base;
a541f297	628
c5df018e FB	629	s = qemu_mallocz(sizeof(m48t59_t));
c5df018e FB	630	if (!s)
a541f297	631	return NULL;
c5df018e FB	632	s->buffer = qemu_mallocz(size);
	633	if (!s->buffer) {
	634	qemu_free(s);
	635	return NULL;
	636	}
	637	s->IRQ = IRQ;
	638	s->size = size;
e1bb04f7	639	s->mem_base = mem_base;
c5df018e FB	640	s->io_base = io_base;
c5df018e FB	641	s->addr = 0;
819385c5 FB	642	s->type = type;
	643	if (io_base != 0) {
	644	register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
	645	register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
	646	}
e1bb04f7 FB	647	if (mem_base != 0) {
e1bb04f7 FB	648	s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
4aed2c33	649	cpu_register_physical_memory(mem_base, size, s->mem_index);
e1bb04f7	650	}
819385c5 FB	651	if (type == 59) {
	652	s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
	653	s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
	654	}
13ab5daa	655	s->lock = 0;
f6503059	656	qemu_get_timedate(&s->alarm, 0);
13ab5daa	657
3ccacc4a BS	658	qemu_register_reset(m48t59_reset, s);
	659	save_base = mem_base ? mem_base : io_base;
	660	register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);
	661
c5df018e	662	return s;
a541f297	663	}