[qemu.git] / hw / m68k / mcf5208.c

/*
 * Motorola ColdFire MCF5208 SoC emulation.
 *
 * Copyright (c) 2007 CodeSourcery.
 *
 * This code is licensed under the GPL
 */
#include "hw/hw.h"
#include "hw/m68k/mcf.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
#include "net/net.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "elf.h"
#include "exec/address-spaces.h"

#define SYS_FREQ 66000000

#define PCSR_EN         0x0001
#define PCSR_RLD        0x0002
#define PCSR_PIF        0x0004
#define PCSR_PIE        0x0008
#define PCSR_OVW        0x0010
#define PCSR_DBG        0x0020
#define PCSR_DOZE       0x0040
#define PCSR_PRE_SHIFT  8
#define PCSR_PRE_MASK   0x0f00

typedef struct {
    MemoryRegion iomem;
    qemu_irq irq;
    ptimer_state *timer;
    uint16_t pcsr;
    uint16_t pmr;
    uint16_t pcntr;
} m5208_timer_state;

static void m5208_timer_update(m5208_timer_state *s)
{
    if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void m5208_timer_write(void *opaque, hwaddr offset,
                              uint64_t value, unsigned size)
{
    m5208_timer_state *s = (m5208_timer_state *)opaque;
    int prescale;
    int limit;
    switch (offset) {
    case 0:
        /* The PIF bit is set-to-clear.  */
        if (value & PCSR_PIF) {
            s->pcsr &= ~PCSR_PIF;
            value &= ~PCSR_PIF;
        }
        /* Avoid frobbing the timer if we're just twiddling IRQ bits. */
        if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) {
            s->pcsr = value;
            m5208_timer_update(s);
            return;
        }

        if (s->pcsr & PCSR_EN)
            ptimer_stop(s->timer);

        s->pcsr = value;

        prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
        ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
        if (s->pcsr & PCSR_RLD)
            limit = s->pmr;
        else
            limit = 0xffff;
        ptimer_set_limit(s->timer, limit, 0);

        if (s->pcsr & PCSR_EN)
            ptimer_run(s->timer, 0);
        break;
    case 2:
        s->pmr = value;
        s->pcsr &= ~PCSR_PIF;
        if ((s->pcsr & PCSR_RLD) == 0) {
            if (s->pcsr & PCSR_OVW)
                ptimer_set_count(s->timer, value);
        } else {
            ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
        }
        break;
    case 4:
        break;
    default:
        hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);
        break;
    }
    m5208_timer_update(s);
}

static void m5208_timer_trigger(void *opaque)
{
    m5208_timer_state *s = (m5208_timer_state *)opaque;
    s->pcsr |= PCSR_PIF;
    m5208_timer_update(s);
}

static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
                                 unsigned size)
{
    m5208_timer_state *s = (m5208_timer_state *)opaque;
    switch (addr) {
    case 0:
        return s->pcsr;
    case 2:
        return s->pmr;
    case 4:
        return ptimer_get_count(s->timer);
    default:
        hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
        return 0;
    }
}

static const MemoryRegionOps m5208_timer_ops = {
    .read = m5208_timer_read,
    .write = m5208_timer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
                               unsigned size)
{
    switch (addr) {
    case 0x110: /* SDCS0 */
        {
            int n;
            for (n = 0; n < 32; n++) {
                if (ram_size < (2u << n))
                    break;
            }
            return (n - 1)  | 0x40000000;
        }
    case 0x114: /* SDCS1 */
        return 0;

    default:
        hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
        return 0;
    }
}

static void m5208_sys_write(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size)
{
    hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
}

static const MemoryRegionOps m5208_sys_ops = {
    .read = m5208_sys_read,
    .write = m5208_sys_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
{
    MemoryRegion *iomem = g_new(MemoryRegion, 1);
    m5208_timer_state *s;
    QEMUBH *bh;
    int i;

    /* SDRAMC.  */
    memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
    memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
    /* Timers.  */
    for (i = 0; i < 2; i++) {
        s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state));
        bh = qemu_bh_new(m5208_timer_trigger, s);
        s->timer = ptimer_init(bh);
        memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s,
                              "m5208-timer", 0x00004000);
        memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
                                    &s->iomem);
        s->irq = pic[4 + i];
    }
}

static void mcf5208evb_init(QEMUMachineInitArgs *args)
{
    ram_addr_t ram_size = args->ram_size;
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    M68kCPU *cpu;
    CPUM68KState *env;
    int kernel_size;
    uint64_t elf_entry;
    hwaddr entry;
    qemu_irq *pic;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *ram = g_new(MemoryRegion, 1);
    MemoryRegion *sram = g_new(MemoryRegion, 1);

    if (!cpu_model) {
        cpu_model = "m5208";
    }
    cpu = cpu_m68k_init(cpu_model);
    if (!cpu) {
        fprintf(stderr, "Unable to find m68k CPU definition\n");
        exit(1);
    }
    env = &cpu->env;

    /* Initialize CPU registers.  */
    env->vbr = 0;
    /* TODO: Configure BARs.  */

    /* DRAM at 0x40000000 */
    memory_region_init_ram(ram, NULL, "mcf5208.ram", ram_size);
    vmstate_register_ram_global(ram);
    memory_region_add_subregion(address_space_mem, 0x40000000, ram);

    /* Internal SRAM.  */
    memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384);
    vmstate_register_ram_global(sram);
    memory_region_add_subregion(address_space_mem, 0x80000000, sram);

    /* Internal peripherals.  */
    pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu);

    mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]);
    mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]);
    mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]);

    mcf5208_sys_init(address_space_mem, pic);

    if (nb_nics > 1) {
        fprintf(stderr, "Too many NICs\n");
        exit(1);
    }
    if (nd_table[0].used)
        mcf_fec_init(address_space_mem, &nd_table[0],
                     0xfc030000, pic + 36);

    /*  0xfc000000 SCM.  */
    /*  0xfc004000 XBS.  */
    /*  0xfc008000 FlexBus CS.  */
    /* 0xfc030000 FEC.  */
    /*  0xfc040000 SCM + Power management.  */
    /*  0xfc044000 eDMA.  */
    /* 0xfc048000 INTC.  */
    /*  0xfc058000 I2C.  */
    /*  0xfc05c000 QSPI.  */
    /* 0xfc060000 UART0.  */
    /* 0xfc064000 UART0.  */
    /* 0xfc068000 UART0.  */
    /*  0xfc070000 DMA timers.  */
    /* 0xfc080000 PIT0.  */
    /* 0xfc084000 PIT1.  */
    /*  0xfc088000 EPORT.  */
    /*  0xfc08c000 Watchdog.  */
    /*  0xfc090000 clock module.  */
    /*  0xfc0a0000 CCM + reset.  */
    /*  0xfc0a4000 GPIO.  */
    /* 0xfc0a8000 SDRAM controller.  */

    /* Load kernel.  */
    if (!kernel_filename) {
        if (qtest_enabled()) {
            return;
        }
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }

    kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
                           NULL, NULL, 1, ELF_MACHINE, 0);
    entry = elf_entry;
    if (kernel_size < 0) {
        kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
    }
    if (kernel_size < 0) {
        kernel_size = load_image_targphys(kernel_filename, 0x40000000,
                                          ram_size);
        entry = 0x40000000;
    }
    if (kernel_size < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
        exit(1);
    }

    env->pc = entry;
}

static QEMUMachine mcf5208evb_machine = {
    .name = "mcf5208evb",
    .desc = "MCF5206EVB",
    .init = mcf5208evb_init,
    .is_default = 1,
};

static void mcf5208evb_machine_init(void)
{
    qemu_register_machine(&mcf5208evb_machine);
}

machine_init(mcf5208evb_machine_init);
Commit	Line	Data
5fafdf24	1	/*
20dcee94 PB	2	* Motorola ColdFire MCF5208 SoC emulation.
	3	*
	4	* Copyright (c) 2007 CodeSourcery.
	5	*
8e31bf38	6	* This code is licensed under the GPL
20dcee94	7	*/
83c9f4ca	8	#include "hw/hw.h"
0d09e41a	9	#include "hw/m68k/mcf.h"
1de7afc9	10	#include "qemu/timer.h"
83c9f4ca	11	#include "hw/ptimer.h"
9c17d615	12	#include "sysemu/sysemu.h"
5c12762c	13	#include "sysemu/qtest.h"
1422e32d	14	#include "net/net.h"
83c9f4ca PB	15	#include "hw/boards.h"
83c9f4ca PB	16	#include "hw/loader.h"
ca20cf32	17	#include "elf.h"
022c62cb	18	#include "exec/address-spaces.h"
20dcee94 PB	19
	20	#define SYS_FREQ 66000000
	21
	22	#define PCSR_EN 0x0001
	23	#define PCSR_RLD 0x0002
	24	#define PCSR_PIF 0x0004
	25	#define PCSR_PIE 0x0008
	26	#define PCSR_OVW 0x0010
	27	#define PCSR_DBG 0x0020
	28	#define PCSR_DOZE 0x0040
	29	#define PCSR_PRE_SHIFT 8
	30	#define PCSR_PRE_MASK 0x0f00
	31
	32	typedef struct {
c378b364	33	MemoryRegion iomem;
20dcee94 PB	34	qemu_irq irq;
	35	ptimer_state *timer;
	36	uint16_t pcsr;
	37	uint16_t pmr;
	38	uint16_t pcntr;
	39	} m5208_timer_state;
	40
	41	static void m5208_timer_update(m5208_timer_state *s)
	42	{
	43	if ((s->pcsr & (PCSR_PIE \| PCSR_PIF)) == (PCSR_PIE \| PCSR_PIF))
	44	qemu_irq_raise(s->irq);
	45	else
	46	qemu_irq_lower(s->irq);
	47	}
	48
a8170e5e	49	static void m5208_timer_write(void *opaque, hwaddr offset,
c378b364	50	uint64_t value, unsigned size)
20dcee94	51	{
8da3ff18	52	m5208_timer_state s = (m5208_timer_state )opaque;
20dcee94 PB	53	int prescale;
	54	int limit;
	55	switch (offset) {
	56	case 0:
	57	/* The PIF bit is set-to-clear. */
	58	if (value & PCSR_PIF) {
	59	s->pcsr &= ~PCSR_PIF;
	60	value &= ~PCSR_PIF;
	61	}
	62	/* Avoid frobbing the timer if we're just twiddling IRQ bits. */
	63	if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) {
	64	s->pcsr = value;
	65	m5208_timer_update(s);
	66	return;
	67	}
	68
	69	if (s->pcsr & PCSR_EN)
	70	ptimer_stop(s->timer);
	71
	72	s->pcsr = value;
	73
	74	prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
	75	ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
	76	if (s->pcsr & PCSR_RLD)
20dcee94	77	limit = s->pmr;
6d9db39c PB	78	else
6d9db39c PB	79	limit = 0xffff;
20dcee94 PB	80	ptimer_set_limit(s->timer, limit, 0);
	81
	82	if (s->pcsr & PCSR_EN)
	83	ptimer_run(s->timer, 0);
	84	break;
	85	case 2:
	86	s->pmr = value;
	87	s->pcsr &= ~PCSR_PIF;
6d9db39c PB	88	if ((s->pcsr & PCSR_RLD) == 0) {
	89	if (s->pcsr & PCSR_OVW)
	90	ptimer_set_count(s->timer, value);
	91	} else {
	92	ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
	93	}
20dcee94 PB	94	break;
	95	case 4:
	96	break;
	97	default:
2ac71179	98	hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);
8da3ff18	99	break;
20dcee94 PB	100	}
	101	m5208_timer_update(s);
	102	}
	103
	104	static void m5208_timer_trigger(void *opaque)
	105	{
	106	m5208_timer_state s = (m5208_timer_state )opaque;
	107	s->pcsr \|= PCSR_PIF;
	108	m5208_timer_update(s);
	109	}
	110
a8170e5e	111	static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
c378b364	112	unsigned size)
8da3ff18 PB	113	{
	114	m5208_timer_state s = (m5208_timer_state )opaque;
	115	switch (addr) {
	116	case 0:
	117	return s->pcsr;
	118	case 2:
	119	return s->pmr;
	120	case 4:
	121	return ptimer_get_count(s->timer);
	122	default:
2ac71179	123	hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
8da3ff18 PB	124	return 0;
	125	}
	126	}
	127
c378b364 AK	128	static const MemoryRegionOps m5208_timer_ops = {
	129	.read = m5208_timer_read,
	130	.write = m5208_timer_write,
	131	.endianness = DEVICE_NATIVE_ENDIAN,
8da3ff18 PB	132	};
8da3ff18 PB	133
a8170e5e	134	static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
c378b364	135	unsigned size)
20dcee94	136	{
20dcee94	137	switch (addr) {
8da3ff18	138	case 0x110: /* SDCS0 */
20dcee94 PB	139	{
	140	int n;
	141	for (n = 0; n < 32; n++) {
	142	if (ram_size < (2u << n))
	143	break;
	144	}
	145	return (n - 1) \| 0x40000000;
	146	}
8da3ff18	147	case 0x114: /* SDCS1 */
20dcee94 PB	148	return 0;
	149
	150	default:
2ac71179	151	hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
20dcee94 PB	152	return 0;
	153	}
	154	}
	155
a8170e5e	156	static void m5208_sys_write(void *opaque, hwaddr addr,
c378b364	157	uint64_t value, unsigned size)
20dcee94	158	{
2ac71179	159	hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
20dcee94 PB	160	}
20dcee94 PB	161
c378b364 AK	162	static const MemoryRegionOps m5208_sys_ops = {
	163	.read = m5208_sys_read,
	164	.write = m5208_sys_write,
	165	.endianness = DEVICE_NATIVE_ENDIAN,
20dcee94 PB	166	};
20dcee94 PB	167
c378b364	168	static void mcf5208_sys_init(MemoryRegion address_space, qemu_irq pic)
20dcee94	169	{
c378b364	170	MemoryRegion *iomem = g_new(MemoryRegion, 1);
8da3ff18	171	m5208_timer_state *s;
20dcee94 PB	172	QEMUBH *bh;
	173	int i;
	174
20dcee94	175	/* SDRAMC. */
2c9b15ca	176	memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
c378b364	177	memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
20dcee94 PB	178	/* Timers. */
20dcee94 PB	179	for (i = 0; i < 2; i++) {
7267c094	180	s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state));
8da3ff18 PB	181	bh = qemu_bh_new(m5208_timer_trigger, s);
8da3ff18 PB	182	s->timer = ptimer_init(bh);
2c9b15ca	183	memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s,
c378b364 AK	184	"m5208-timer", 0x00004000);
	185	memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
	186	&s->iomem);
8da3ff18	187	s->irq = pic[4 + i];
20dcee94 PB	188	}
	189	}
	190
5f072e1f	191	static void mcf5208evb_init(QEMUMachineInitArgs *args)
20dcee94	192	{
5f072e1f EH	193	ram_addr_t ram_size = args->ram_size;
	194	const char *cpu_model = args->cpu_model;
	195	const char *kernel_filename = args->kernel_filename;
9a6ee9fd	196	M68kCPU *cpu;
7927df3a	197	CPUM68KState *env;
20dcee94 PB	198	int kernel_size;
20dcee94 PB	199	uint64_t elf_entry;
a8170e5e	200	hwaddr entry;
20dcee94	201	qemu_irq *pic;
c378b364 AK	202	MemoryRegion *address_space_mem = get_system_memory();
	203	MemoryRegion *ram = g_new(MemoryRegion, 1);
	204	MemoryRegion *sram = g_new(MemoryRegion, 1);
20dcee94	205
9a6ee9fd	206	if (!cpu_model) {
20dcee94	207	cpu_model = "m5208";
9a6ee9fd AF	208	}
	209	cpu = cpu_m68k_init(cpu_model);
	210	if (!cpu) {
aaed909a FB	211	fprintf(stderr, "Unable to find m68k CPU definition\n");
aaed909a FB	212	exit(1);
20dcee94	213	}
9a6ee9fd	214	env = &cpu->env;
20dcee94 PB	215
	216	/* Initialize CPU registers. */
	217	env->vbr = 0;
	218	/* TODO: Configure BARs. */
	219
dcac9679	220	/* DRAM at 0x40000000 */
2c9b15ca	221	memory_region_init_ram(ram, NULL, "mcf5208.ram", ram_size);
c5705a77	222	vmstate_register_ram_global(ram);
c378b364	223	memory_region_add_subregion(address_space_mem, 0x40000000, ram);
20dcee94 PB	224
20dcee94 PB	225	/* Internal SRAM. */
2c9b15ca	226	memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384);
c5705a77	227	vmstate_register_ram_global(sram);
c378b364	228	memory_region_add_subregion(address_space_mem, 0x80000000, sram);
20dcee94 PB	229
20dcee94 PB	230	/* Internal peripherals. */
9a6ee9fd	231	pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu);
20dcee94	232
aa6e4986 BC	233	mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]);
	234	mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]);
	235	mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]);
20dcee94	236
c378b364	237	mcf5208_sys_init(address_space_mem, pic);
20dcee94	238
7e049b8a PB	239	if (nb_nics > 1) {
	240	fprintf(stderr, "Too many NICs\n");
	241	exit(1);
	242	}
a005d073	243	if (nd_table[0].used)
c65fc1df BC	244	mcf_fec_init(address_space_mem, &nd_table[0],
c65fc1df BC	245	0xfc030000, pic + 36);
7e049b8a	246
20dcee94 PB	247	/* 0xfc000000 SCM. */
	248	/* 0xfc004000 XBS. */
	249	/* 0xfc008000 FlexBus CS. */
7e049b8a	250	/* 0xfc030000 FEC. */
20dcee94 PB	251	/* 0xfc040000 SCM + Power management. */
	252	/* 0xfc044000 eDMA. */
	253	/* 0xfc048000 INTC. */
	254	/* 0xfc058000 I2C. */
	255	/* 0xfc05c000 QSPI. */
	256	/* 0xfc060000 UART0. */
	257	/* 0xfc064000 UART0. */
	258	/* 0xfc068000 UART0. */
	259	/* 0xfc070000 DMA timers. */
	260	/* 0xfc080000 PIT0. */
	261	/* 0xfc084000 PIT1. */
	262	/* 0xfc088000 EPORT. */
	263	/* 0xfc08c000 Watchdog. */
	264	/* 0xfc090000 clock module. */
	265	/* 0xfc0a0000 CCM + reset. */
	266	/* 0xfc0a4000 GPIO. */
	267	/* 0xfc0a8000 SDRAM controller. */
	268
	269	/* Load kernel. */
	270	if (!kernel_filename) {
5c12762c AF	271	if (qtest_enabled()) {
	272	return;
	273	}
20dcee94 PB	274	fprintf(stderr, "Kernel image must be specified\n");
	275	exit(1);
	276	}
	277
409dbce5 AJ	278	kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
409dbce5 AJ	279	NULL, NULL, 1, ELF_MACHINE, 0);
20dcee94 PB	280	entry = elf_entry;
20dcee94 PB	281	if (kernel_size < 0) {
5a9154e0	282	kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
20dcee94 PB	283	}
20dcee94 PB	284	if (kernel_size < 0) {
dcac9679 PB	285	kernel_size = load_image_targphys(kernel_filename, 0x40000000,
	286	ram_size);
	287	entry = 0x40000000;
20dcee94 PB	288	}
	289	if (kernel_size < 0) {
	290	fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
	291	exit(1);
	292	}
	293
	294	env->pc = entry;
	295	}
	296
f80f9ec9	297	static QEMUMachine mcf5208evb_machine = {
4b32e168 AL	298	.name = "mcf5208evb",
	299	.desc = "MCF5206EVB",
	300	.init = mcf5208evb_init,
0c257437	301	.is_default = 1,
20dcee94	302	};
f80f9ec9 AL	303
	304	static void mcf5208evb_machine_init(void)
	305	{
	306	qemu_register_machine(&mcf5208evb_machine);
	307	}
	308
	309	machine_init(mcf5208evb_machine_init);