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macio: QOM'ify some more
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1/*
2 * PowerMac MacIO device emulation
3 *
4 * Copyright (c) 2005-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
87ecb68b 25#include "hw.h"
baec1910 26#include "ppc/mac.h"
a2cb15b0 27#include "pci/pci.h"
7fa9ae1a 28#include "escc.h"
3cbee15b 29
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30#define TYPE_MACIO "macio"
31#define MACIO(obj) OBJECT_CHECK(MacIOState, (obj), TYPE_MACIO)
32
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33typedef struct MacIOState
34{
fcf1bbab 35 /*< private >*/
d8c51b05 36 PCIDevice parent;
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37 /*< public >*/
38
3cbee15b 39 int is_oldworld;
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40 MemoryRegion bar;
41 MemoryRegion *pic_mem;
42 MemoryRegion *dbdma_mem;
43 MemoryRegion *cuda_mem;
44 MemoryRegion *escc_mem;
74e91155 45 void *nvram;
3cbee15b 46 int nb_ide;
23c5e4ca 47 MemoryRegion *ide_mem[4];
d8c51b05 48} MacIOState;
3cbee15b 49
d8c51b05 50static void macio_bar_setup(MacIOState *macio_state)
3cbee15b 51{
3cbee15b 52 int i;
23c5e4ca 53 MemoryRegion *bar = &macio_state->bar;
3cbee15b 54
23c5e4ca 55 if (macio_state->pic_mem) {
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56 if (macio_state->is_oldworld) {
57 /* Heathrow PIC */
23c5e4ca 58 memory_region_add_subregion(bar, 0x00000, macio_state->pic_mem);
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59 } else {
60 /* OpenPIC */
23c5e4ca 61 memory_region_add_subregion(bar, 0x40000, macio_state->pic_mem);
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62 }
63 }
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64 if (macio_state->dbdma_mem) {
65 memory_region_add_subregion(bar, 0x08000, macio_state->dbdma_mem);
3cbee15b 66 }
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67 if (macio_state->escc_mem) {
68 memory_region_add_subregion(bar, 0x13000, macio_state->escc_mem);
7fa9ae1a 69 }
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70 if (macio_state->cuda_mem) {
71 memory_region_add_subregion(bar, 0x16000, macio_state->cuda_mem);
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72 }
73 for (i = 0; i < macio_state->nb_ide; i++) {
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74 if (macio_state->ide_mem[i]) {
75 memory_region_add_subregion(bar, 0x1f000 + (i * 0x1000),
76 macio_state->ide_mem[i]);
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77 }
78 }
74e91155 79 if (macio_state->nvram != NULL)
23c5e4ca 80 macio_nvram_setup_bar(macio_state->nvram, bar, 0x60000);
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81}
82
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83static int macio_initfn(PCIDevice *d)
84{
85 d->config[0x3d] = 0x01; // interrupt on pin 1
86 return 0;
87}
88
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89static void macio_instance_init(Object *obj)
90{
91 MacIOState *s = MACIO(obj);
92
93 memory_region_init(&s->bar, "macio", 0x80000);
94}
95
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96static void macio_class_init(ObjectClass *klass, void *data)
97{
98 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
99
100 k->init = macio_initfn;
101 k->vendor_id = PCI_VENDOR_ID_APPLE;
102 k->class_id = PCI_CLASS_OTHERS << 8;
103}
104
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105static const TypeInfo macio_type_info = {
106 .name = TYPE_MACIO,
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107 .parent = TYPE_PCI_DEVICE,
108 .instance_size = sizeof(MacIOState),
fcf1bbab 109 .instance_init = macio_instance_init,
39bffca2 110 .class_init = macio_class_init,
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111};
112
83f7d43a 113static void macio_register_types(void)
d8c51b05 114{
fcf1bbab 115 type_register_static(&macio_type_info);
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116}
117
83f7d43a 118type_init(macio_register_types)
d8c51b05 119
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120void macio_init (PCIBus *bus, int device_id, int is_oldworld,
121 MemoryRegion *pic_mem, MemoryRegion *dbdma_mem,
122 MemoryRegion *cuda_mem, void *nvram,
123 int nb_ide, MemoryRegion **ide_mem,
124 MemoryRegion *escc_mem)
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125{
126 PCIDevice *d;
d8c51b05 127 MacIOState *macio_state;
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128 int i;
129
fcf1bbab 130 d = pci_create_simple(bus, -1, TYPE_MACIO);
d8c51b05 131
fcf1bbab 132 macio_state = MACIO(d);
3cbee15b 133 macio_state->is_oldworld = is_oldworld;
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134 macio_state->pic_mem = pic_mem;
135 macio_state->dbdma_mem = dbdma_mem;
136 macio_state->cuda_mem = cuda_mem;
137 macio_state->escc_mem = escc_mem;
74e91155 138 macio_state->nvram = nvram;
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139 if (nb_ide > 4)
140 nb_ide = 4;
141 macio_state->nb_ide = nb_ide;
142 for (i = 0; i < nb_ide; i++)
23c5e4ca 143 macio_state->ide_mem[i] = ide_mem[i];
3cbee15b 144 for (; i < 4; i++)
23c5e4ca 145 macio_state->ide_mem[i] = NULL;
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146 /* Note: this code is strongly inspirated from the corresponding code
147 in PearPC */
deb54399 148
deb54399 149 pci_config_set_device_id(d->config, device_id);
3cbee15b 150
23c5e4ca 151 macio_bar_setup(macio_state);
e824b2cc 152 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &macio_state->bar);
3cbee15b 153}