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1/*
2 * PXA270-based Intel Mainstone platforms.
3 *
4 * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
5 * <akuster@mvista.com>
6 *
7 * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
8 *
9 * This code is licensed under the GNU GPL v2.
10 */
11#include "hw.h"
12#include "pxa.h"
13#include "arm-misc.h"
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14#include "net.h"
15#include "devices.h"
16#include "boards.h"
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17#include "mainstone.h"
18#include "sysemu.h"
19#include "flash.h"
ef056e43 20
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21static struct keymap map[0xE0] = {
22 [0 ... 0xDF] = { -1, -1 },
23 [0x1e] = {0,0}, /* a */
24 [0x30] = {0,1}, /* b */
25 [0x2e] = {0,2}, /* c */
26 [0x20] = {0,3}, /* d */
27 [0x12] = {0,4}, /* e */
28 [0x21] = {0,5}, /* f */
29 [0x22] = {1,0}, /* g */
30 [0x23] = {1,1}, /* h */
31 [0x17] = {1,2}, /* i */
32 [0x24] = {1,3}, /* j */
33 [0x25] = {1,4}, /* k */
34 [0x26] = {1,5}, /* l */
35 [0x32] = {2,0}, /* m */
36 [0x31] = {2,1}, /* n */
37 [0x18] = {2,2}, /* o */
38 [0x19] = {2,3}, /* p */
39 [0x10] = {2,4}, /* q */
40 [0x13] = {2,5}, /* r */
41 [0x1f] = {3,0}, /* s */
42 [0x14] = {3,1}, /* t */
43 [0x16] = {3,2}, /* u */
44 [0x2f] = {3,3}, /* v */
45 [0x11] = {3,4}, /* w */
46 [0x2d] = {3,5}, /* x */
47 [0x15] = {4,2}, /* y */
48 [0x2c] = {4,3}, /* z */
49 [0xc7] = {5,0}, /* Home */
50 [0x2a] = {5,1}, /* shift */
51 [0x39] = {5,2}, /* space */
52 [0x39] = {5,3}, /* space */
53 [0x1c] = {5,5}, /* enter */
54 [0xc8] = {6,0}, /* up */
55 [0xd0] = {6,1}, /* down */
56 [0xcb] = {6,2}, /* left */
57 [0xcd] = {6,3}, /* right */
58};
59
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60enum mainstone_model_e { mainstone };
61
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62#define MAINSTONE_RAM 0x04000000
63#define MAINSTONE_ROM 0x00800000
64#define MAINSTONE_FLASH 0x02000000
65
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66static struct arm_boot_info mainstone_binfo = {
67 .loader_start = PXA2XX_SDRAM_BASE,
68 .ram_size = 0x04000000,
69};
70
c227f099 71static void mainstone_common_init(ram_addr_t ram_size,
3023f332 72 const char *kernel_filename,
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73 const char *kernel_cmdline, const char *initrd_filename,
74 const char *cpu_model, enum mainstone_model_e model, int arm_id)
75{
6d1f1778 76 uint32_t sector_len = 256 * 1024;
c227f099 77 target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
bc24a225 78 PXA2xxState *cpu;
ef056e43 79 qemu_irq *mst_irq;
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80 DriveInfo *dinfo;
81 int i;
3d08ff69 82 int be;
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83
84 if (!cpu_model)
85 cpu_model = "pxa270-c5";
86
87 /* Setup CPU & memory */
3023f332 88 cpu = pxa270_init(mainstone_binfo.ram_size, cpu_model);
7fb4fdcf 89 cpu_register_physical_memory(0, MAINSTONE_ROM,
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90 qemu_ram_alloc(NULL, "mainstone.rom",
91 MAINSTONE_ROM) | IO_MEM_ROM);
ef056e43 92
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93#ifdef TARGET_WORDS_BIGENDIAN
94 be = 1;
95#else
96 be = 0;
97#endif
e4bcb14c 98 /* There are two 32MiB flash devices on the board */
6d1f1778 99 for (i = 0; i < 2; i ++) {
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100 dinfo = drive_get(IF_PFLASH, 0, i);
101 if (!dinfo) {
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102 fprintf(stderr, "Two flash images must be given with the "
103 "'pflash' parameter\n");
104 exit(1);
105 }
106
107 if (!pflash_cfi01_register(mainstone_flash_base[i],
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108 qemu_ram_alloc(NULL, "mainstone.flash",
109 MAINSTONE_FLASH),
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110 dinfo->bdrv, sector_len,
111 MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0,
112 be)) {
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113 fprintf(stderr, "qemu: Error registering flash memory.\n");
114 exit(1);
115 }
e4bcb14c 116 }
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117
118 mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0);
f1de1334 119
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120 /* setup keypad */
121 printf("map addr %p\n", &map);
122 pxa27x_register_keypad(cpu->kp, map, 0xe0);
123
f1de1334 124 /* MMC/SD host */
8543243c 125 pxa2xx_mmci_handlers(cpu->mmc, NULL, mst_irq[MMC_IRQ]);
f1de1334 126
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127 smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]);
128
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129 mainstone_binfo.kernel_filename = kernel_filename;
130 mainstone_binfo.kernel_cmdline = kernel_cmdline;
131 mainstone_binfo.initrd_filename = initrd_filename;
132 mainstone_binfo.board_id = arm_id;
133 arm_load_kernel(cpu->env, &mainstone_binfo);
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134}
135
c227f099 136static void mainstone_init(ram_addr_t ram_size,
3023f332 137 const char *boot_device,
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138 const char *kernel_filename, const char *kernel_cmdline,
139 const char *initrd_filename, const char *cpu_model)
140{
fbe1b595 141 mainstone_common_init(ram_size, kernel_filename,
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142 kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
143}
144
f80f9ec9 145static QEMUMachine mainstone2_machine = {
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146 .name = "mainstone",
147 .desc = "Mainstone II (PXA27x)",
148 .init = mainstone_init,
ef056e43 149};
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150
151static void mainstone_machine_init(void)
152{
153 qemu_register_machine(&mainstone2_machine);
154}
155
156machine_init(mainstone_machine_init);