]>
Commit | Line | Data |
---|---|---|
80cabfad FB |
1 | /* |
2 | * QEMU MC146818 RTC emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "qemu-timer.h" | |
26 | #include "sysemu.h" | |
1d914fa0 | 27 | #include "mc146818rtc.h" |
80cabfad | 28 | |
d362e757 JK |
29 | #ifdef TARGET_I386 |
30 | #include "apic.h" | |
31 | #endif | |
32 | ||
80cabfad | 33 | //#define DEBUG_CMOS |
aa6f63ff | 34 | //#define DEBUG_COALESCED |
80cabfad | 35 | |
ec51e364 IY |
36 | #ifdef DEBUG_CMOS |
37 | # define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
38 | #else | |
39 | # define CMOS_DPRINTF(format, ...) do { } while (0) | |
40 | #endif | |
41 | ||
aa6f63ff BS |
42 | #ifdef DEBUG_COALESCED |
43 | # define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__) | |
44 | #else | |
45 | # define DPRINTF_C(format, ...) do { } while (0) | |
46 | #endif | |
47 | ||
56038ef6 | 48 | #define NSEC_PER_SEC 1000000000LL |
00cf5774 PB |
49 | #define SEC_PER_MIN 60 |
50 | #define MIN_PER_HOUR 60 | |
51 | #define SEC_PER_HOUR 3600 | |
52 | #define HOUR_PER_DAY 24 | |
53 | #define SEC_PER_DAY 86400 | |
56038ef6 | 54 | |
dd17765b | 55 | #define RTC_REINJECT_ON_ACK_COUNT 20 |
e46deaba | 56 | #define RTC_CLOCK_RATE 32768 |
56038ef6 | 57 | #define UIP_HOLD_LENGTH (8 * NSEC_PER_SEC / 32768) |
ba32edab | 58 | |
1d914fa0 | 59 | typedef struct RTCState { |
32e0c826 | 60 | ISADevice dev; |
b2c5009b | 61 | MemoryRegion io; |
dff38e7b FB |
62 | uint8_t cmos_data[128]; |
63 | uint8_t cmos_index; | |
43f493af | 64 | struct tm current_tm; |
32e0c826 | 65 | int32_t base_year; |
56038ef6 YZ |
66 | uint64_t base_rtc; |
67 | uint64_t last_update; | |
68 | int64_t offset; | |
d537cf6c | 69 | qemu_irq irq; |
100d9891 | 70 | qemu_irq sqw_irq; |
18c6e2ff | 71 | int it_shift; |
dff38e7b FB |
72 | /* periodic timer */ |
73 | QEMUTimer *periodic_timer; | |
74 | int64_t next_periodic_time; | |
56038ef6 YZ |
75 | /* update-ended timer */ |
76 | QEMUTimer *update_timer; | |
00cf5774 | 77 | uint64_t next_alarm_time; |
ba32edab | 78 | uint16_t irq_reinject_on_ack_count; |
73822ec8 AL |
79 | uint32_t irq_coalesced; |
80 | uint32_t period; | |
93b66569 | 81 | QEMUTimer *coalesced_timer; |
17604dac | 82 | Notifier clock_reset_notifier; |
433acf0d | 83 | LostTickPolicy lost_tick_policy; |
da98c8eb | 84 | Notifier suspend_notifier; |
1d914fa0 | 85 | } RTCState; |
dff38e7b FB |
86 | |
87 | static void rtc_set_time(RTCState *s); | |
56038ef6 | 88 | static void rtc_update_time(RTCState *s); |
e2826cf4 | 89 | static void rtc_set_cmos(RTCState *s, const struct tm *tm); |
56038ef6 | 90 | static inline int rtc_from_bcd(RTCState *s, int a); |
00cf5774 | 91 | static uint64_t get_next_alarm(RTCState *s); |
56038ef6 | 92 | |
41a9b8b2 YZ |
93 | static inline bool rtc_running(RTCState *s) |
94 | { | |
95 | return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) && | |
96 | (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20); | |
97 | } | |
98 | ||
56038ef6 YZ |
99 | static uint64_t get_guest_rtc_ns(RTCState *s) |
100 | { | |
101 | uint64_t guest_rtc; | |
102 | uint64_t guest_clock = qemu_get_clock_ns(rtc_clock); | |
103 | ||
104 | guest_rtc = s->base_rtc * NSEC_PER_SEC | |
105 | + guest_clock - s->last_update + s->offset; | |
106 | return guest_rtc; | |
107 | } | |
dff38e7b | 108 | |
93b66569 AL |
109 | #ifdef TARGET_I386 |
110 | static void rtc_coalesced_timer_update(RTCState *s) | |
111 | { | |
112 | if (s->irq_coalesced == 0) { | |
113 | qemu_del_timer(s->coalesced_timer); | |
114 | } else { | |
115 | /* divide each RTC interval to 2 - 8 smaller intervals */ | |
116 | int c = MIN(s->irq_coalesced, 7) + 1; | |
74475455 | 117 | int64_t next_clock = qemu_get_clock_ns(rtc_clock) + |
e46deaba | 118 | muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE); |
93b66569 AL |
119 | qemu_mod_timer(s->coalesced_timer, next_clock); |
120 | } | |
121 | } | |
122 | ||
123 | static void rtc_coalesced_timer(void *opaque) | |
124 | { | |
125 | RTCState *s = opaque; | |
126 | ||
127 | if (s->irq_coalesced != 0) { | |
128 | apic_reset_irq_delivered(); | |
129 | s->cmos_data[RTC_REG_C] |= 0xc0; | |
aa6f63ff | 130 | DPRINTF_C("cmos: injecting from timer\n"); |
7d932dfd | 131 | qemu_irq_raise(s->irq); |
93b66569 AL |
132 | if (apic_get_irq_delivered()) { |
133 | s->irq_coalesced--; | |
aa6f63ff BS |
134 | DPRINTF_C("cmos: coalesced irqs decreased to %d\n", |
135 | s->irq_coalesced); | |
93b66569 AL |
136 | } |
137 | } | |
138 | ||
139 | rtc_coalesced_timer_update(s); | |
140 | } | |
141 | #endif | |
142 | ||
56038ef6 | 143 | /* handle periodic timer */ |
c4c18e24 | 144 | static void periodic_timer_update(RTCState *s, int64_t current_time) |
dff38e7b FB |
145 | { |
146 | int period_code, period; | |
147 | int64_t cur_clock, next_irq_clock; | |
148 | ||
149 | period_code = s->cmos_data[RTC_REG_A] & 0x0f; | |
100d9891 | 150 | if (period_code != 0 |
7d932dfd | 151 | && ((s->cmos_data[RTC_REG_B] & REG_B_PIE) |
100d9891 | 152 | || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { |
dff38e7b FB |
153 | if (period_code <= 2) |
154 | period_code += 7; | |
155 | /* period in 32 Khz cycles */ | |
156 | period = 1 << (period_code - 1); | |
73822ec8 | 157 | #ifdef TARGET_I386 |
aa6f63ff | 158 | if (period != s->period) { |
73822ec8 | 159 | s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
aa6f63ff BS |
160 | DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced); |
161 | } | |
73822ec8 AL |
162 | s->period = period; |
163 | #endif | |
dff38e7b | 164 | /* compute 32 khz clock */ |
e46deaba | 165 | cur_clock = muldiv64(current_time, RTC_CLOCK_RATE, get_ticks_per_sec()); |
dff38e7b | 166 | next_irq_clock = (cur_clock & ~(period - 1)) + period; |
6875204c | 167 | s->next_periodic_time = |
e46deaba | 168 | muldiv64(next_irq_clock, get_ticks_per_sec(), RTC_CLOCK_RATE) + 1; |
dff38e7b FB |
169 | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
170 | } else { | |
73822ec8 AL |
171 | #ifdef TARGET_I386 |
172 | s->irq_coalesced = 0; | |
173 | #endif | |
dff38e7b FB |
174 | qemu_del_timer(s->periodic_timer); |
175 | } | |
176 | } | |
177 | ||
178 | static void rtc_periodic_timer(void *opaque) | |
179 | { | |
180 | RTCState *s = opaque; | |
181 | ||
c4c18e24 | 182 | periodic_timer_update(s, s->next_periodic_time); |
663447d4 | 183 | s->cmos_data[RTC_REG_C] |= REG_C_PF; |
100d9891 | 184 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) { |
663447d4 | 185 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
93b66569 | 186 | #ifdef TARGET_I386 |
433acf0d | 187 | if (s->lost_tick_policy == LOST_TICK_SLEW) { |
ba32edab GN |
188 | if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT) |
189 | s->irq_reinject_on_ack_count = 0; | |
93b66569 | 190 | apic_reset_irq_delivered(); |
7d932dfd | 191 | qemu_irq_raise(s->irq); |
93b66569 AL |
192 | if (!apic_get_irq_delivered()) { |
193 | s->irq_coalesced++; | |
194 | rtc_coalesced_timer_update(s); | |
aa6f63ff BS |
195 | DPRINTF_C("cmos: coalesced irqs increased to %d\n", |
196 | s->irq_coalesced); | |
93b66569 AL |
197 | } |
198 | } else | |
199 | #endif | |
7d932dfd | 200 | qemu_irq_raise(s->irq); |
100d9891 AJ |
201 | } |
202 | if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) { | |
203 | /* Not square wave at all but we don't want 2048Hz interrupts! | |
204 | Must be seen as a pulse. */ | |
205 | qemu_irq_raise(s->sqw_irq); | |
206 | } | |
dff38e7b | 207 | } |
80cabfad | 208 | |
56038ef6 YZ |
209 | /* handle update-ended timer */ |
210 | static void check_update_timer(RTCState *s) | |
211 | { | |
212 | uint64_t next_update_time; | |
213 | uint64_t guest_nsec; | |
00cf5774 | 214 | int next_alarm_sec; |
56038ef6 | 215 | |
41a9b8b2 YZ |
216 | /* From the data sheet: "Holding the dividers in reset prevents |
217 | * interrupts from operating, while setting the SET bit allows" | |
218 | * them to occur. However, it will prevent an alarm interrupt | |
219 | * from occurring, because the time of day is not updated. | |
56038ef6 | 220 | */ |
41a9b8b2 YZ |
221 | if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) { |
222 | qemu_del_timer(s->update_timer); | |
223 | return; | |
224 | } | |
56038ef6 YZ |
225 | if ((s->cmos_data[RTC_REG_C] & REG_C_UF) && |
226 | (s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
227 | qemu_del_timer(s->update_timer); | |
228 | return; | |
229 | } | |
230 | if ((s->cmos_data[RTC_REG_C] & REG_C_UF) && | |
231 | (s->cmos_data[RTC_REG_C] & REG_C_AF)) { | |
232 | qemu_del_timer(s->update_timer); | |
233 | return; | |
234 | } | |
235 | ||
236 | guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC; | |
00cf5774 | 237 | /* if UF is clear, reprogram to next second */ |
56038ef6 YZ |
238 | next_update_time = qemu_get_clock_ns(rtc_clock) |
239 | + NSEC_PER_SEC - guest_nsec; | |
00cf5774 PB |
240 | |
241 | /* Compute time of next alarm. One second is already accounted | |
242 | * for in next_update_time. | |
243 | */ | |
244 | next_alarm_sec = get_next_alarm(s); | |
245 | s->next_alarm_time = next_update_time + (next_alarm_sec - 1) * NSEC_PER_SEC; | |
246 | ||
247 | if (s->cmos_data[RTC_REG_C] & REG_C_UF) { | |
248 | /* UF is set, but AF is clear. Program the timer to target | |
249 | * the alarm time. */ | |
250 | next_update_time = s->next_alarm_time; | |
251 | } | |
56038ef6 YZ |
252 | if (next_update_time != qemu_timer_expire_time_ns(s->update_timer)) { |
253 | qemu_mod_timer(s->update_timer, next_update_time); | |
254 | } | |
255 | } | |
256 | ||
257 | static inline uint8_t convert_hour(RTCState *s, uint8_t hour) | |
258 | { | |
259 | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) { | |
260 | hour %= 12; | |
261 | if (s->cmos_data[RTC_HOURS] & 0x80) { | |
262 | hour += 12; | |
263 | } | |
264 | } | |
265 | return hour; | |
266 | } | |
267 | ||
00cf5774 | 268 | static uint64_t get_next_alarm(RTCState *s) |
56038ef6 | 269 | { |
00cf5774 PB |
270 | int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec; |
271 | int32_t hour, min, sec; | |
272 | ||
273 | rtc_update_time(s); | |
56038ef6 YZ |
274 | |
275 | alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]); | |
276 | alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]); | |
277 | alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]); | |
00cf5774 | 278 | alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour); |
56038ef6 YZ |
279 | |
280 | cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); | |
281 | cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
282 | cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]); | |
283 | cur_hour = convert_hour(s, cur_hour); | |
284 | ||
00cf5774 PB |
285 | if (alarm_hour == -1) { |
286 | alarm_hour = cur_hour; | |
287 | if (alarm_min == -1) { | |
288 | alarm_min = cur_min; | |
289 | if (alarm_sec == -1) { | |
290 | alarm_sec = cur_sec + 1; | |
291 | } else if (cur_sec > alarm_sec) { | |
292 | alarm_min++; | |
293 | } | |
294 | } else if (cur_min == alarm_min) { | |
295 | if (alarm_sec == -1) { | |
296 | alarm_sec = cur_sec + 1; | |
297 | } else { | |
298 | if (cur_sec > alarm_sec) { | |
299 | alarm_hour++; | |
300 | } | |
301 | } | |
302 | if (alarm_sec == SEC_PER_MIN) { | |
303 | /* wrap to next hour, minutes is not in don't care mode */ | |
304 | alarm_sec = 0; | |
305 | alarm_hour++; | |
306 | } | |
307 | } else if (cur_min > alarm_min) { | |
308 | alarm_hour++; | |
309 | } | |
310 | } else if (cur_hour == alarm_hour) { | |
311 | if (alarm_min == -1) { | |
312 | alarm_min = cur_min; | |
313 | if (alarm_sec == -1) { | |
314 | alarm_sec = cur_sec + 1; | |
315 | } else if (cur_sec > alarm_sec) { | |
316 | alarm_min++; | |
317 | } | |
318 | ||
319 | if (alarm_sec == SEC_PER_MIN) { | |
320 | alarm_sec = 0; | |
321 | alarm_min++; | |
322 | } | |
323 | /* wrap to next day, hour is not in don't care mode */ | |
324 | alarm_min %= MIN_PER_HOUR; | |
325 | } else if (cur_min == alarm_min) { | |
326 | if (alarm_sec == -1) { | |
327 | alarm_sec = cur_sec + 1; | |
328 | } | |
329 | /* wrap to next day, hours+minutes not in don't care mode */ | |
330 | alarm_sec %= SEC_PER_MIN; | |
331 | } | |
56038ef6 | 332 | } |
56038ef6 | 333 | |
00cf5774 PB |
334 | /* values that are still don't care fire at the next min/sec */ |
335 | if (alarm_min == -1) { | |
336 | alarm_min = 0; | |
337 | } | |
338 | if (alarm_sec == -1) { | |
339 | alarm_sec = 0; | |
340 | } | |
341 | ||
342 | /* keep values in range */ | |
343 | if (alarm_sec == SEC_PER_MIN) { | |
344 | alarm_sec = 0; | |
345 | alarm_min++; | |
346 | } | |
347 | if (alarm_min == MIN_PER_HOUR) { | |
348 | alarm_min = 0; | |
349 | alarm_hour++; | |
350 | } | |
351 | alarm_hour %= HOUR_PER_DAY; | |
352 | ||
353 | hour = alarm_hour - cur_hour; | |
354 | min = hour * MIN_PER_HOUR + alarm_min - cur_min; | |
355 | sec = min * SEC_PER_MIN + alarm_sec - cur_sec; | |
356 | return sec <= 0 ? sec + SEC_PER_DAY : sec; | |
56038ef6 YZ |
357 | } |
358 | ||
359 | static void rtc_update_timer(void *opaque) | |
360 | { | |
361 | RTCState *s = opaque; | |
362 | int32_t irqs = REG_C_UF; | |
363 | int32_t new_irqs; | |
364 | ||
41a9b8b2 YZ |
365 | assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60); |
366 | ||
56038ef6 YZ |
367 | /* UIP might have been latched, update time and clear it. */ |
368 | rtc_update_time(s); | |
369 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
370 | ||
00cf5774 | 371 | if (qemu_get_clock_ns(rtc_clock) >= s->next_alarm_time) { |
56038ef6 YZ |
372 | irqs |= REG_C_AF; |
373 | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) { | |
374 | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC); | |
375 | } | |
376 | } | |
00cf5774 | 377 | |
56038ef6 YZ |
378 | new_irqs = irqs & ~s->cmos_data[RTC_REG_C]; |
379 | s->cmos_data[RTC_REG_C] |= irqs; | |
380 | if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) { | |
381 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; | |
382 | qemu_irq_raise(s->irq); | |
383 | } | |
384 | check_update_timer(s); | |
385 | } | |
386 | ||
b41a2cd1 | 387 | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
80cabfad | 388 | { |
b41a2cd1 | 389 | RTCState *s = opaque; |
80cabfad FB |
390 | |
391 | if ((addr & 1) == 0) { | |
392 | s->cmos_index = data & 0x7f; | |
393 | } else { | |
ec51e364 IY |
394 | CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n", |
395 | s->cmos_index, data); | |
dff38e7b | 396 | switch(s->cmos_index) { |
80cabfad FB |
397 | case RTC_SECONDS_ALARM: |
398 | case RTC_MINUTES_ALARM: | |
399 | case RTC_HOURS_ALARM: | |
80cabfad | 400 | s->cmos_data[s->cmos_index] = data; |
56038ef6 | 401 | check_update_timer(s); |
80cabfad FB |
402 | break; |
403 | case RTC_SECONDS: | |
404 | case RTC_MINUTES: | |
405 | case RTC_HOURS: | |
406 | case RTC_DAY_OF_WEEK: | |
407 | case RTC_DAY_OF_MONTH: | |
408 | case RTC_MONTH: | |
409 | case RTC_YEAR: | |
410 | s->cmos_data[s->cmos_index] = data; | |
dff38e7b | 411 | /* if in set mode, do not update the time */ |
41a9b8b2 | 412 | if (rtc_running(s)) { |
dff38e7b | 413 | rtc_set_time(s); |
56038ef6 | 414 | check_update_timer(s); |
dff38e7b | 415 | } |
80cabfad FB |
416 | break; |
417 | case RTC_REG_A: | |
41a9b8b2 YZ |
418 | if ((data & 0x60) == 0x60) { |
419 | if (rtc_running(s)) { | |
420 | rtc_update_time(s); | |
421 | } | |
422 | /* What happens to UIP when divider reset is enabled is | |
423 | * unclear from the datasheet. Shouldn't matter much | |
424 | * though. | |
425 | */ | |
426 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
427 | } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) && | |
428 | (data & 0x70) <= 0x20) { | |
429 | /* when the divider reset is removed, the first update cycle | |
430 | * begins one-half second later*/ | |
431 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
432 | s->offset = 500000000; | |
433 | rtc_set_time(s); | |
434 | } | |
435 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
436 | } | |
dff38e7b FB |
437 | /* UIP bit is read only */ |
438 | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | | |
439 | (s->cmos_data[RTC_REG_A] & REG_A_UIP); | |
c4c18e24 | 440 | periodic_timer_update(s, qemu_get_clock_ns(rtc_clock)); |
56038ef6 | 441 | check_update_timer(s); |
dff38e7b | 442 | break; |
80cabfad | 443 | case RTC_REG_B: |
dff38e7b | 444 | if (data & REG_B_SET) { |
56038ef6 | 445 | /* update cmos to when the rtc was stopping */ |
41a9b8b2 | 446 | if (rtc_running(s)) { |
56038ef6 YZ |
447 | rtc_update_time(s); |
448 | } | |
dff38e7b FB |
449 | /* set mode: reset UIP mode */ |
450 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
451 | data &= ~REG_B_UIE; | |
452 | } else { | |
453 | /* if disabling set mode, update the time */ | |
41a9b8b2 YZ |
454 | if ((s->cmos_data[RTC_REG_B] & REG_B_SET) && |
455 | (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) { | |
56038ef6 | 456 | s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC; |
dff38e7b FB |
457 | rtc_set_time(s); |
458 | } | |
459 | } | |
9324cc50 YZ |
460 | /* if an interrupt flag is already set when the interrupt |
461 | * becomes enabled, raise an interrupt immediately. */ | |
462 | if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) { | |
463 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; | |
464 | qemu_irq_raise(s->irq); | |
465 | } else { | |
466 | s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF; | |
467 | qemu_irq_lower(s->irq); | |
468 | } | |
bedc572e | 469 | s->cmos_data[RTC_REG_B] = data; |
c4c18e24 | 470 | periodic_timer_update(s, qemu_get_clock_ns(rtc_clock)); |
56038ef6 | 471 | check_update_timer(s); |
80cabfad FB |
472 | break; |
473 | case RTC_REG_C: | |
474 | case RTC_REG_D: | |
475 | /* cannot write to them */ | |
476 | break; | |
477 | default: | |
478 | s->cmos_data[s->cmos_index] = data; | |
479 | break; | |
480 | } | |
481 | } | |
482 | } | |
483 | ||
abd0c6bd | 484 | static inline int rtc_to_bcd(RTCState *s, int a) |
80cabfad | 485 | { |
6f1bf24d | 486 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
487 | return a; |
488 | } else { | |
489 | return ((a / 10) << 4) | (a % 10); | |
490 | } | |
80cabfad FB |
491 | } |
492 | ||
abd0c6bd | 493 | static inline int rtc_from_bcd(RTCState *s, int a) |
80cabfad | 494 | { |
00cf5774 PB |
495 | if ((a & 0xc0) == 0xc0) { |
496 | return -1; | |
497 | } | |
6f1bf24d | 498 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
499 | return a; |
500 | } else { | |
501 | return ((a >> 4) * 10) + (a & 0x0f); | |
502 | } | |
503 | } | |
504 | ||
e2826cf4 | 505 | static void rtc_get_time(RTCState *s, struct tm *tm) |
dff38e7b | 506 | { |
abd0c6bd PB |
507 | tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
508 | tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
509 | tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f); | |
3b89eb43 PB |
510 | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) { |
511 | tm->tm_hour %= 12; | |
512 | if (s->cmos_data[RTC_HOURS] & 0x80) { | |
513 | tm->tm_hour += 12; | |
514 | } | |
43f493af | 515 | } |
abd0c6bd PB |
516 | tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1; |
517 | tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); | |
518 | tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1; | |
519 | tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900; | |
e2826cf4 PB |
520 | } |
521 | ||
522 | static void rtc_set_time(RTCState *s) | |
523 | { | |
524 | struct tm tm; | |
80cd3478 | 525 | |
e2826cf4 PB |
526 | rtc_get_time(s, &tm); |
527 | s->current_tm = tm; | |
528 | s->base_rtc = mktimegm(&tm); | |
56038ef6 YZ |
529 | s->last_update = qemu_get_clock_ns(rtc_clock); |
530 | ||
e2826cf4 | 531 | rtc_change_mon_event(&tm); |
43f493af FB |
532 | } |
533 | ||
e2826cf4 | 534 | static void rtc_set_cmos(RTCState *s, const struct tm *tm) |
43f493af | 535 | { |
42fc73a1 | 536 | int year; |
dff38e7b | 537 | |
abd0c6bd PB |
538 | s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
539 | s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); | |
c29cd656 | 540 | if (s->cmos_data[RTC_REG_B] & REG_B_24H) { |
43f493af | 541 | /* 24 hour format */ |
abd0c6bd | 542 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
43f493af FB |
543 | } else { |
544 | /* 12 hour format */ | |
3b89eb43 PB |
545 | int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12; |
546 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h); | |
43f493af FB |
547 | if (tm->tm_hour >= 12) |
548 | s->cmos_data[RTC_HOURS] |= 0x80; | |
549 | } | |
abd0c6bd PB |
550 | s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1); |
551 | s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); | |
552 | s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1); | |
42fc73a1 AJ |
553 | year = (tm->tm_year - s->base_year) % 100; |
554 | if (year < 0) | |
555 | year += 100; | |
abd0c6bd | 556 | s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year); |
43f493af FB |
557 | } |
558 | ||
56038ef6 | 559 | static void rtc_update_time(RTCState *s) |
43f493af | 560 | { |
56038ef6 YZ |
561 | struct tm ret; |
562 | time_t guest_sec; | |
563 | int64_t guest_nsec; | |
564 | ||
565 | guest_nsec = get_guest_rtc_ns(s); | |
566 | guest_sec = guest_nsec / NSEC_PER_SEC; | |
567 | gmtime_r(&guest_sec, &ret); | |
e2826cf4 | 568 | rtc_set_cmos(s, &ret); |
56038ef6 | 569 | s->current_tm = ret; |
43f493af FB |
570 | } |
571 | ||
56038ef6 | 572 | static int update_in_progress(RTCState *s) |
43f493af | 573 | { |
56038ef6 | 574 | int64_t guest_nsec; |
3b46e624 | 575 | |
41a9b8b2 | 576 | if (!rtc_running(s)) { |
56038ef6 | 577 | return 0; |
dff38e7b | 578 | } |
56038ef6 YZ |
579 | if (qemu_timer_pending(s->update_timer)) { |
580 | int64_t next_update_time = qemu_timer_expire_time_ns(s->update_timer); | |
581 | /* Latch UIP until the timer expires. */ | |
582 | if (qemu_get_clock_ns(rtc_clock) >= (next_update_time - UIP_HOLD_LENGTH)) { | |
583 | s->cmos_data[RTC_REG_A] |= REG_A_UIP; | |
584 | return 1; | |
dff38e7b FB |
585 | } |
586 | } | |
587 | ||
56038ef6 YZ |
588 | guest_nsec = get_guest_rtc_ns(s); |
589 | /* UIP bit will be set at last 244us of every second. */ | |
590 | if ((guest_nsec % NSEC_PER_SEC) >= (NSEC_PER_SEC - UIP_HOLD_LENGTH)) { | |
591 | return 1; | |
dff38e7b | 592 | } |
56038ef6 | 593 | return 0; |
80cabfad FB |
594 | } |
595 | ||
b41a2cd1 | 596 | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
80cabfad | 597 | { |
b41a2cd1 | 598 | RTCState *s = opaque; |
80cabfad FB |
599 | int ret; |
600 | if ((addr & 1) == 0) { | |
601 | return 0xff; | |
602 | } else { | |
603 | switch(s->cmos_index) { | |
604 | case RTC_SECONDS: | |
605 | case RTC_MINUTES: | |
606 | case RTC_HOURS: | |
607 | case RTC_DAY_OF_WEEK: | |
608 | case RTC_DAY_OF_MONTH: | |
609 | case RTC_MONTH: | |
610 | case RTC_YEAR: | |
56038ef6 YZ |
611 | /* if not in set mode, calibrate cmos before |
612 | * reading*/ | |
41a9b8b2 | 613 | if (rtc_running(s)) { |
56038ef6 YZ |
614 | rtc_update_time(s); |
615 | } | |
80cabfad FB |
616 | ret = s->cmos_data[s->cmos_index]; |
617 | break; | |
618 | case RTC_REG_A: | |
56038ef6 YZ |
619 | if (update_in_progress(s)) { |
620 | s->cmos_data[s->cmos_index] |= REG_A_UIP; | |
621 | } else { | |
622 | s->cmos_data[s->cmos_index] &= ~REG_A_UIP; | |
623 | } | |
80cabfad | 624 | ret = s->cmos_data[s->cmos_index]; |
80cabfad FB |
625 | break; |
626 | case RTC_REG_C: | |
627 | ret = s->cmos_data[s->cmos_index]; | |
d537cf6c | 628 | qemu_irq_lower(s->irq); |
fbc15e27 | 629 | s->cmos_data[RTC_REG_C] = 0x00; |
56038ef6 YZ |
630 | if (ret & (REG_C_UF | REG_C_AF)) { |
631 | check_update_timer(s); | |
632 | } | |
ba32edab GN |
633 | #ifdef TARGET_I386 |
634 | if(s->irq_coalesced && | |
fbc15e27 | 635 | (s->cmos_data[RTC_REG_B] & REG_B_PIE) && |
ba32edab GN |
636 | s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
637 | s->irq_reinject_on_ack_count++; | |
fbc15e27 | 638 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF; |
ba32edab | 639 | apic_reset_irq_delivered(); |
aa6f63ff | 640 | DPRINTF_C("cmos: injecting on ack\n"); |
ba32edab | 641 | qemu_irq_raise(s->irq); |
aa6f63ff | 642 | if (apic_get_irq_delivered()) { |
ba32edab | 643 | s->irq_coalesced--; |
aa6f63ff BS |
644 | DPRINTF_C("cmos: coalesced irqs decreased to %d\n", |
645 | s->irq_coalesced); | |
646 | } | |
ba32edab GN |
647 | } |
648 | #endif | |
80cabfad FB |
649 | break; |
650 | default: | |
651 | ret = s->cmos_data[s->cmos_index]; | |
652 | break; | |
653 | } | |
ec51e364 IY |
654 | CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n", |
655 | s->cmos_index, ret); | |
80cabfad FB |
656 | return ret; |
657 | } | |
658 | } | |
659 | ||
1d914fa0 | 660 | void rtc_set_memory(ISADevice *dev, int addr, int val) |
dff38e7b | 661 | { |
1d914fa0 | 662 | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
dff38e7b FB |
663 | if (addr >= 0 && addr <= 127) |
664 | s->cmos_data[addr] = val; | |
665 | } | |
666 | ||
ea55ffb3 TS |
667 | /* PC cmos mappings */ |
668 | #define REG_IBM_CENTURY_BYTE 0x32 | |
669 | #define REG_IBM_PS2_CENTURY_BYTE 0x37 | |
670 | ||
1d914fa0 | 671 | static void rtc_set_date_from_host(ISADevice *dev) |
ea55ffb3 | 672 | { |
1d914fa0 | 673 | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
f6503059 | 674 | struct tm tm; |
ea55ffb3 TS |
675 | int val; |
676 | ||
f6503059 | 677 | qemu_get_timedate(&tm, 0); |
56038ef6 YZ |
678 | |
679 | s->base_rtc = mktimegm(&tm); | |
680 | s->last_update = qemu_get_clock_ns(rtc_clock); | |
681 | s->offset = 0; | |
682 | ||
683 | /* set the CMOS date */ | |
e2826cf4 | 684 | rtc_set_cmos(s, &tm); |
56038ef6 | 685 | s->current_tm = tm; |
ea55ffb3 | 686 | |
abd0c6bd | 687 | val = rtc_to_bcd(s, (tm.tm_year / 100) + 19); |
1d914fa0 IY |
688 | rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val); |
689 | rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val); | |
ea55ffb3 TS |
690 | } |
691 | ||
6b075b8a | 692 | static int rtc_post_load(void *opaque, int version_id) |
80cabfad | 693 | { |
dff38e7b FB |
694 | RTCState *s = opaque; |
695 | ||
56038ef6 YZ |
696 | if (version_id <= 2) { |
697 | rtc_set_time(s); | |
698 | s->offset = 0; | |
699 | check_update_timer(s); | |
700 | } | |
701 | ||
702 | #ifdef TARGET_I386 | |
048c74c4 | 703 | if (version_id >= 2) { |
433acf0d | 704 | if (s->lost_tick_policy == LOST_TICK_SLEW) { |
048c74c4 JQ |
705 | rtc_coalesced_timer_update(s); |
706 | } | |
048c74c4 | 707 | } |
6b075b8a | 708 | #endif |
73822ec8 AL |
709 | return 0; |
710 | } | |
73822ec8 | 711 | |
6b075b8a JQ |
712 | static const VMStateDescription vmstate_rtc = { |
713 | .name = "mc146818rtc", | |
56038ef6 | 714 | .version_id = 3, |
6b075b8a JQ |
715 | .minimum_version_id = 1, |
716 | .minimum_version_id_old = 1, | |
717 | .post_load = rtc_post_load, | |
718 | .fields = (VMStateField []) { | |
719 | VMSTATE_BUFFER(cmos_data, RTCState), | |
720 | VMSTATE_UINT8(cmos_index, RTCState), | |
721 | VMSTATE_INT32(current_tm.tm_sec, RTCState), | |
722 | VMSTATE_INT32(current_tm.tm_min, RTCState), | |
723 | VMSTATE_INT32(current_tm.tm_hour, RTCState), | |
724 | VMSTATE_INT32(current_tm.tm_wday, RTCState), | |
725 | VMSTATE_INT32(current_tm.tm_mday, RTCState), | |
726 | VMSTATE_INT32(current_tm.tm_mon, RTCState), | |
727 | VMSTATE_INT32(current_tm.tm_year, RTCState), | |
728 | VMSTATE_TIMER(periodic_timer, RTCState), | |
729 | VMSTATE_INT64(next_periodic_time, RTCState), | |
56038ef6 | 730 | VMSTATE_UNUSED(3*8), |
6b075b8a JQ |
731 | VMSTATE_UINT32_V(irq_coalesced, RTCState, 2), |
732 | VMSTATE_UINT32_V(period, RTCState, 2), | |
56038ef6 YZ |
733 | VMSTATE_UINT64_V(base_rtc, RTCState, 3), |
734 | VMSTATE_UINT64_V(last_update, RTCState, 3), | |
735 | VMSTATE_INT64_V(offset, RTCState, 3), | |
736 | VMSTATE_TIMER_V(update_timer, RTCState, 3), | |
00cf5774 | 737 | VMSTATE_UINT64_V(next_alarm_time, RTCState, 3), |
6b075b8a JQ |
738 | VMSTATE_END_OF_LIST() |
739 | } | |
740 | }; | |
741 | ||
17604dac JK |
742 | static void rtc_notify_clock_reset(Notifier *notifier, void *data) |
743 | { | |
744 | RTCState *s = container_of(notifier, RTCState, clock_reset_notifier); | |
745 | int64_t now = *(int64_t *)data; | |
746 | ||
747 | rtc_set_date_from_host(&s->dev); | |
c4c18e24 | 748 | periodic_timer_update(s, now); |
56038ef6 | 749 | check_update_timer(s); |
17604dac | 750 | #ifdef TARGET_I386 |
433acf0d | 751 | if (s->lost_tick_policy == LOST_TICK_SLEW) { |
17604dac JK |
752 | rtc_coalesced_timer_update(s); |
753 | } | |
754 | #endif | |
755 | } | |
756 | ||
da98c8eb GH |
757 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
758 | BIOS will read it and start S3 resume at POST Entry */ | |
759 | static void rtc_notify_suspend(Notifier *notifier, void *data) | |
760 | { | |
761 | RTCState *s = container_of(notifier, RTCState, suspend_notifier); | |
762 | rtc_set_memory(&s->dev, 0xF, 0xFE); | |
763 | } | |
764 | ||
eeb7c03c GN |
765 | static void rtc_reset(void *opaque) |
766 | { | |
767 | RTCState *s = opaque; | |
768 | ||
72716184 AL |
769 | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
770 | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); | |
56038ef6 | 771 | check_update_timer(s); |
eeb7c03c | 772 | |
72716184 | 773 | qemu_irq_lower(s->irq); |
eeb7c03c GN |
774 | |
775 | #ifdef TARGET_I386 | |
433acf0d JK |
776 | if (s->lost_tick_policy == LOST_TICK_SLEW) { |
777 | s->irq_coalesced = 0; | |
778 | } | |
eeb7c03c GN |
779 | #endif |
780 | } | |
781 | ||
b2c5009b RH |
782 | static const MemoryRegionPortio cmos_portio[] = { |
783 | {0, 2, 1, .read = cmos_ioport_read, .write = cmos_ioport_write }, | |
784 | PORTIO_END_OF_LIST(), | |
785 | }; | |
786 | ||
787 | static const MemoryRegionOps cmos_ops = { | |
788 | .old_portio = cmos_portio | |
789 | }; | |
790 | ||
57c9fafe | 791 | static void rtc_get_date(Object *obj, Visitor *v, void *opaque, |
18297050 AL |
792 | const char *name, Error **errp) |
793 | { | |
57c9fafe | 794 | ISADevice *isa = ISA_DEVICE(obj); |
18297050 | 795 | RTCState *s = DO_UPCAST(RTCState, dev, isa); |
e2826cf4 | 796 | struct tm current_tm; |
18297050 | 797 | |
56038ef6 | 798 | rtc_update_time(s); |
e2826cf4 | 799 | rtc_get_time(s, ¤t_tm); |
18297050 | 800 | visit_start_struct(v, NULL, "struct tm", name, 0, errp); |
e2826cf4 PB |
801 | visit_type_int32(v, ¤t_tm.tm_year, "tm_year", errp); |
802 | visit_type_int32(v, ¤t_tm.tm_mon, "tm_mon", errp); | |
803 | visit_type_int32(v, ¤t_tm.tm_mday, "tm_mday", errp); | |
804 | visit_type_int32(v, ¤t_tm.tm_hour, "tm_hour", errp); | |
805 | visit_type_int32(v, ¤t_tm.tm_min, "tm_min", errp); | |
806 | visit_type_int32(v, ¤t_tm.tm_sec, "tm_sec", errp); | |
18297050 AL |
807 | visit_end_struct(v, errp); |
808 | } | |
809 | ||
32e0c826 | 810 | static int rtc_initfn(ISADevice *dev) |
dff38e7b | 811 | { |
32e0c826 GH |
812 | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
813 | int base = 0x70; | |
80cabfad | 814 | |
80cabfad FB |
815 | s->cmos_data[RTC_REG_A] = 0x26; |
816 | s->cmos_data[RTC_REG_B] = 0x02; | |
817 | s->cmos_data[RTC_REG_C] = 0x00; | |
818 | s->cmos_data[RTC_REG_D] = 0x80; | |
819 | ||
1d914fa0 | 820 | rtc_set_date_from_host(dev); |
ea55ffb3 | 821 | |
93b66569 | 822 | #ifdef TARGET_I386 |
433acf0d JK |
823 | switch (s->lost_tick_policy) { |
824 | case LOST_TICK_SLEW: | |
6875204c | 825 | s->coalesced_timer = |
74475455 | 826 | qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s); |
433acf0d JK |
827 | break; |
828 | case LOST_TICK_DISCARD: | |
829 | break; | |
830 | default: | |
831 | return -EINVAL; | |
832 | } | |
93b66569 | 833 | #endif |
433acf0d JK |
834 | |
835 | s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s); | |
56038ef6 YZ |
836 | s->update_timer = qemu_new_timer_ns(rtc_clock, rtc_update_timer, s); |
837 | check_update_timer(s); | |
dff38e7b | 838 | |
17604dac JK |
839 | s->clock_reset_notifier.notify = rtc_notify_clock_reset; |
840 | qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier); | |
841 | ||
da98c8eb GH |
842 | s->suspend_notifier.notify = rtc_notify_suspend; |
843 | qemu_register_suspend_notifier(&s->suspend_notifier); | |
844 | ||
b2c5009b RH |
845 | memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2); |
846 | isa_register_ioport(dev, &s->io, base); | |
dff38e7b | 847 | |
56038ef6 | 848 | qdev_set_legacy_instance_id(&dev->qdev, base, 3); |
a08d4367 | 849 | qemu_register_reset(rtc_reset, s); |
18297050 | 850 | |
57c9fafe AL |
851 | object_property_add(OBJECT(s), "date", "struct tm", |
852 | rtc_get_date, NULL, NULL, s, NULL); | |
18297050 | 853 | |
32e0c826 GH |
854 | return 0; |
855 | } | |
856 | ||
48a18b3c | 857 | ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq) |
32e0c826 GH |
858 | { |
859 | ISADevice *dev; | |
7d932dfd | 860 | RTCState *s; |
eeb7c03c | 861 | |
48a18b3c | 862 | dev = isa_create(bus, "mc146818rtc"); |
7d932dfd | 863 | s = DO_UPCAST(RTCState, dev, dev); |
32e0c826 | 864 | qdev_prop_set_int32(&dev->qdev, "base_year", base_year); |
e23a1b33 | 865 | qdev_init_nofail(&dev->qdev); |
7d932dfd JK |
866 | if (intercept_irq) { |
867 | s->irq = intercept_irq; | |
868 | } else { | |
869 | isa_init_irq(dev, &s->irq, RTC_ISA_IRQ); | |
870 | } | |
1d914fa0 | 871 | return dev; |
80cabfad FB |
872 | } |
873 | ||
39bffca2 AL |
874 | static Property mc146818rtc_properties[] = { |
875 | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), | |
876 | DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState, | |
877 | lost_tick_policy, LOST_TICK_DISCARD), | |
878 | DEFINE_PROP_END_OF_LIST(), | |
879 | }; | |
880 | ||
8f04ee08 AL |
881 | static void rtc_class_initfn(ObjectClass *klass, void *data) |
882 | { | |
39bffca2 | 883 | DeviceClass *dc = DEVICE_CLASS(klass); |
8f04ee08 AL |
884 | ISADeviceClass *ic = ISA_DEVICE_CLASS(klass); |
885 | ic->init = rtc_initfn; | |
39bffca2 AL |
886 | dc->no_user = 1; |
887 | dc->vmsd = &vmstate_rtc; | |
888 | dc->props = mc146818rtc_properties; | |
8f04ee08 AL |
889 | } |
890 | ||
39bffca2 AL |
891 | static TypeInfo mc146818rtc_info = { |
892 | .name = "mc146818rtc", | |
893 | .parent = TYPE_ISA_DEVICE, | |
894 | .instance_size = sizeof(RTCState), | |
895 | .class_init = rtc_class_initfn, | |
32e0c826 GH |
896 | }; |
897 | ||
83f7d43a | 898 | static void mc146818rtc_register_types(void) |
100d9891 | 899 | { |
39bffca2 | 900 | type_register_static(&mc146818rtc_info); |
100d9891 | 901 | } |
83f7d43a AF |
902 | |
903 | type_init(mc146818rtc_register_types) |