[qemu.git] / hw / mcf.h

#ifndef HW_MCF_H
#define HW_MCF_H
/* Motorola ColdFire device prototypes.  */

struct MemoryRegion;

/* mcf_uart.c */
uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
                       unsigned size);
void mcf_uart_write(void *opaque, target_phys_addr_t addr,
                    uint64_t val, unsigned size);
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
void mcf_uart_mm_init(struct MemoryRegion *sysmem,
                      target_phys_addr_t base,
                      qemu_irq irq, CharDriverState *chr);

/* mcf_intc.c */
qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);

/* mcf_fec.c */
void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);

/* mcf5206.c */
qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
                       uint32_t base, CPUState *env);

#endif
Commit	Line	Data
87ecb68b PB	1	#ifndef HW_MCF_H
	2	#define HW_MCF_H
	3	/* Motorola ColdFire device prototypes. */
	4
653fa85c BC	5	struct MemoryRegion;
653fa85c BC	6
87ecb68b	7	/* mcf_uart.c */
aa6e4986 BC	8	uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
	9	unsigned size);
	10	void mcf_uart_write(void *opaque, target_phys_addr_t addr,
	11	uint64_t val, unsigned size);
87ecb68b	12	void mcf_uart_init(qemu_irq irq, CharDriverState chr);
aa6e4986 BC	13	void mcf_uart_mm_init(struct MemoryRegion *sysmem,
	14	target_phys_addr_t base,
	15	qemu_irq irq, CharDriverState *chr);
87ecb68b PB	16
87ecb68b PB	17	/* mcf_intc.c */
c227f099	18	qemu_irq mcf_intc_init(target_phys_addr_t base, CPUState env);
87ecb68b PB	19
87ecb68b PB	20	/* mcf_fec.c */
c227f099	21	void mcf_fec_init(NICInfo nd, target_phys_addr_t base, qemu_irq irq);
87ecb68b PB	22
87ecb68b PB	23	/* mcf5206.c */
653fa85c BC	24	qemu_irq mcf5206_init(struct MemoryRegion sysmem,
653fa85c BC	25	uint32_t base, CPUState *env);
87ecb68b PB	26
87ecb68b PB	27	#endif