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96832424 MW |
1 | /* |
2 | * QEMU model of the Milkymist System Controller. | |
3 | * | |
4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | * | |
20 | * Specification available at: | |
21 | * http://www.milkymist.org/socdoc/sysctl.pdf | |
22 | */ | |
23 | ||
24 | #include "hw.h" | |
25 | #include "sysbus.h" | |
26 | #include "sysemu.h" | |
27 | #include "trace.h" | |
28 | #include "qemu-timer.h" | |
49d4d9b6 | 29 | #include "ptimer.h" |
96832424 MW |
30 | #include "qemu-error.h" |
31 | ||
32 | enum { | |
33 | CTRL_ENABLE = (1<<0), | |
34 | CTRL_AUTORESTART = (1<<1), | |
35 | }; | |
36 | ||
37 | enum { | |
38 | ICAP_READY = (1<<0), | |
39 | }; | |
40 | ||
41 | enum { | |
42 | R_GPIO_IN = 0, | |
43 | R_GPIO_OUT, | |
44 | R_GPIO_INTEN, | |
45 | R_RESERVED0, | |
46 | R_TIMER0_CONTROL, | |
47 | R_TIMER0_COMPARE, | |
48 | R_TIMER0_COUNTER, | |
49 | R_RESERVED1, | |
50 | R_TIMER1_CONTROL, | |
51 | R_TIMER1_COMPARE, | |
52 | R_TIMER1_COUNTER, | |
53 | R_RESERVED2, | |
54 | R_RESERVED3, | |
55 | R_ICAP, | |
56 | R_CAPABILITIES, | |
57 | R_SYSTEM_ID, | |
58 | R_MAX | |
59 | }; | |
60 | ||
61 | struct MilkymistSysctlState { | |
62 | SysBusDevice busdev; | |
dfa87ccf | 63 | MemoryRegion regs_region; |
96832424 MW |
64 | |
65 | QEMUBH *bh0; | |
66 | QEMUBH *bh1; | |
67 | ptimer_state *ptimer0; | |
68 | ptimer_state *ptimer1; | |
69 | ||
70 | uint32_t freq_hz; | |
71 | uint32_t capabilities; | |
72 | uint32_t systemid; | |
73 | uint32_t strappings; | |
74 | ||
75 | uint32_t regs[R_MAX]; | |
76 | ||
77 | qemu_irq gpio_irq; | |
78 | qemu_irq timer0_irq; | |
79 | qemu_irq timer1_irq; | |
80 | }; | |
81 | typedef struct MilkymistSysctlState MilkymistSysctlState; | |
82 | ||
83 | static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value) | |
84 | { | |
85 | trace_milkymist_sysctl_icap_write(value); | |
86 | switch (value & 0xffff) { | |
87 | case 0x000e: | |
88 | qemu_system_shutdown_request(); | |
89 | break; | |
90 | } | |
91 | } | |
92 | ||
dfa87ccf MW |
93 | static uint64_t sysctl_read(void *opaque, target_phys_addr_t addr, |
94 | unsigned size) | |
96832424 MW |
95 | { |
96 | MilkymistSysctlState *s = opaque; | |
97 | uint32_t r = 0; | |
98 | ||
99 | addr >>= 2; | |
100 | switch (addr) { | |
101 | case R_TIMER0_COUNTER: | |
102 | r = (uint32_t)ptimer_get_count(s->ptimer0); | |
103 | /* milkymist timer counts up */ | |
104 | r = s->regs[R_TIMER0_COMPARE] - r; | |
105 | break; | |
106 | case R_TIMER1_COUNTER: | |
107 | r = (uint32_t)ptimer_get_count(s->ptimer1); | |
108 | /* milkymist timer counts up */ | |
109 | r = s->regs[R_TIMER1_COMPARE] - r; | |
110 | break; | |
111 | case R_GPIO_IN: | |
112 | case R_GPIO_OUT: | |
113 | case R_GPIO_INTEN: | |
114 | case R_TIMER0_CONTROL: | |
115 | case R_TIMER0_COMPARE: | |
116 | case R_TIMER1_CONTROL: | |
117 | case R_TIMER1_COMPARE: | |
118 | case R_ICAP: | |
119 | case R_CAPABILITIES: | |
120 | case R_SYSTEM_ID: | |
121 | r = s->regs[addr]; | |
122 | break; | |
123 | ||
124 | default: | |
dd3d6775 | 125 | error_report("milkymist_sysctl: read access to unknown register 0x" |
96832424 MW |
126 | TARGET_FMT_plx, addr << 2); |
127 | break; | |
128 | } | |
129 | ||
130 | trace_milkymist_sysctl_memory_read(addr << 2, r); | |
131 | ||
132 | return r; | |
133 | } | |
134 | ||
dfa87ccf MW |
135 | static void sysctl_write(void *opaque, target_phys_addr_t addr, uint64_t value, |
136 | unsigned size) | |
96832424 MW |
137 | { |
138 | MilkymistSysctlState *s = opaque; | |
139 | ||
140 | trace_milkymist_sysctl_memory_write(addr, value); | |
141 | ||
142 | addr >>= 2; | |
143 | switch (addr) { | |
144 | case R_GPIO_OUT: | |
145 | case R_GPIO_INTEN: | |
146 | case R_TIMER0_COUNTER: | |
96832424 | 147 | case R_TIMER1_COUNTER: |
f3172a0e | 148 | s->regs[addr] = value; |
96832424 MW |
149 | break; |
150 | case R_TIMER0_COMPARE: | |
151 | ptimer_set_limit(s->ptimer0, value, 0); | |
152 | s->regs[addr] = value; | |
153 | break; | |
154 | case R_TIMER1_COMPARE: | |
155 | ptimer_set_limit(s->ptimer1, value, 0); | |
156 | s->regs[addr] = value; | |
157 | break; | |
158 | case R_TIMER0_CONTROL: | |
159 | s->regs[addr] = value; | |
160 | if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) { | |
f3172a0e MW |
161 | trace_milkymist_sysctl_start_timer0(); |
162 | ptimer_set_count(s->ptimer0, | |
163 | s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]); | |
96832424 MW |
164 | ptimer_run(s->ptimer0, 0); |
165 | } else { | |
f3172a0e | 166 | trace_milkymist_sysctl_stop_timer0(); |
96832424 MW |
167 | ptimer_stop(s->ptimer0); |
168 | } | |
169 | break; | |
170 | case R_TIMER1_CONTROL: | |
171 | s->regs[addr] = value; | |
172 | if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) { | |
173 | trace_milkymist_sysctl_start_timer1(); | |
f3172a0e MW |
174 | ptimer_set_count(s->ptimer1, |
175 | s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]); | |
96832424 MW |
176 | ptimer_run(s->ptimer1, 0); |
177 | } else { | |
178 | trace_milkymist_sysctl_stop_timer1(); | |
179 | ptimer_stop(s->ptimer1); | |
180 | } | |
181 | break; | |
182 | case R_ICAP: | |
183 | sysctl_icap_write(s, value); | |
184 | break; | |
185 | case R_SYSTEM_ID: | |
186 | qemu_system_reset_request(); | |
187 | break; | |
188 | ||
189 | case R_GPIO_IN: | |
190 | case R_CAPABILITIES: | |
191 | error_report("milkymist_sysctl: write to read-only register 0x" | |
192 | TARGET_FMT_plx, addr << 2); | |
193 | break; | |
194 | ||
195 | default: | |
dd3d6775 | 196 | error_report("milkymist_sysctl: write access to unknown register 0x" |
96832424 MW |
197 | TARGET_FMT_plx, addr << 2); |
198 | break; | |
199 | } | |
200 | } | |
201 | ||
dfa87ccf MW |
202 | static const MemoryRegionOps sysctl_mmio_ops = { |
203 | .read = sysctl_read, | |
204 | .write = sysctl_write, | |
205 | .valid = { | |
206 | .min_access_size = 4, | |
207 | .max_access_size = 4, | |
208 | }, | |
209 | .endianness = DEVICE_NATIVE_ENDIAN, | |
96832424 MW |
210 | }; |
211 | ||
212 | static void timer0_hit(void *opaque) | |
213 | { | |
214 | MilkymistSysctlState *s = opaque; | |
215 | ||
216 | if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) { | |
217 | s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE; | |
218 | trace_milkymist_sysctl_stop_timer0(); | |
219 | ptimer_stop(s->ptimer0); | |
220 | } | |
221 | ||
222 | trace_milkymist_sysctl_pulse_irq_timer0(); | |
223 | qemu_irq_pulse(s->timer0_irq); | |
224 | } | |
225 | ||
226 | static void timer1_hit(void *opaque) | |
227 | { | |
228 | MilkymistSysctlState *s = opaque; | |
229 | ||
230 | if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) { | |
231 | s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE; | |
232 | trace_milkymist_sysctl_stop_timer1(); | |
233 | ptimer_stop(s->ptimer1); | |
234 | } | |
235 | ||
236 | trace_milkymist_sysctl_pulse_irq_timer1(); | |
237 | qemu_irq_pulse(s->timer1_irq); | |
238 | } | |
239 | ||
240 | static void milkymist_sysctl_reset(DeviceState *d) | |
241 | { | |
242 | MilkymistSysctlState *s = | |
243 | container_of(d, MilkymistSysctlState, busdev.qdev); | |
244 | int i; | |
245 | ||
246 | for (i = 0; i < R_MAX; i++) { | |
247 | s->regs[i] = 0; | |
248 | } | |
249 | ||
250 | ptimer_stop(s->ptimer0); | |
251 | ptimer_stop(s->ptimer1); | |
252 | ||
253 | /* defaults */ | |
254 | s->regs[R_ICAP] = ICAP_READY; | |
255 | s->regs[R_SYSTEM_ID] = s->systemid; | |
256 | s->regs[R_CAPABILITIES] = s->capabilities; | |
257 | s->regs[R_GPIO_IN] = s->strappings; | |
258 | } | |
259 | ||
260 | static int milkymist_sysctl_init(SysBusDevice *dev) | |
261 | { | |
262 | MilkymistSysctlState *s = FROM_SYSBUS(typeof(*s), dev); | |
96832424 MW |
263 | |
264 | sysbus_init_irq(dev, &s->gpio_irq); | |
265 | sysbus_init_irq(dev, &s->timer0_irq); | |
266 | sysbus_init_irq(dev, &s->timer1_irq); | |
267 | ||
268 | s->bh0 = qemu_bh_new(timer0_hit, s); | |
269 | s->bh1 = qemu_bh_new(timer1_hit, s); | |
270 | s->ptimer0 = ptimer_init(s->bh0); | |
271 | s->ptimer1 = ptimer_init(s->bh1); | |
272 | ptimer_set_freq(s->ptimer0, s->freq_hz); | |
273 | ptimer_set_freq(s->ptimer1, s->freq_hz); | |
274 | ||
dfa87ccf MW |
275 | memory_region_init_io(&s->regs_region, &sysctl_mmio_ops, s, |
276 | "milkymist-sysctl", R_MAX * 4); | |
750ecd44 | 277 | sysbus_init_mmio(dev, &s->regs_region); |
96832424 MW |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
282 | static const VMStateDescription vmstate_milkymist_sysctl = { | |
283 | .name = "milkymist-sysctl", | |
284 | .version_id = 1, | |
285 | .minimum_version_id = 1, | |
286 | .minimum_version_id_old = 1, | |
287 | .fields = (VMStateField[]) { | |
288 | VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX), | |
289 | VMSTATE_PTIMER(ptimer0, MilkymistSysctlState), | |
290 | VMSTATE_PTIMER(ptimer1, MilkymistSysctlState), | |
291 | VMSTATE_END_OF_LIST() | |
292 | } | |
293 | }; | |
294 | ||
999e12bb AL |
295 | static Property milkymist_sysctl_properties[] = { |
296 | DEFINE_PROP_UINT32("frequency", MilkymistSysctlState, | |
297 | freq_hz, 80000000), | |
298 | DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState, | |
299 | capabilities, 0x00000000), | |
300 | DEFINE_PROP_UINT32("systemid", MilkymistSysctlState, | |
301 | systemid, 0x10014d31), | |
302 | DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState, | |
303 | strappings, 0x00000001), | |
304 | DEFINE_PROP_END_OF_LIST(), | |
305 | }; | |
306 | ||
307 | static void milkymist_sysctl_class_init(ObjectClass *klass, void *data) | |
308 | { | |
39bffca2 | 309 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
310 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
311 | ||
312 | k->init = milkymist_sysctl_init; | |
39bffca2 AL |
313 | dc->reset = milkymist_sysctl_reset; |
314 | dc->vmsd = &vmstate_milkymist_sysctl; | |
315 | dc->props = milkymist_sysctl_properties; | |
999e12bb AL |
316 | } |
317 | ||
39bffca2 AL |
318 | static TypeInfo milkymist_sysctl_info = { |
319 | .name = "milkymist-sysctl", | |
320 | .parent = TYPE_SYS_BUS_DEVICE, | |
321 | .instance_size = sizeof(MilkymistSysctlState), | |
322 | .class_init = milkymist_sysctl_class_init, | |
96832424 MW |
323 | }; |
324 | ||
83f7d43a | 325 | static void milkymist_sysctl_register_types(void) |
96832424 | 326 | { |
39bffca2 | 327 | type_register_static(&milkymist_sysctl_info); |
96832424 MW |
328 | } |
329 | ||
83f7d43a | 330 | type_init(milkymist_sysctl_register_types) |