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Commit | Line | Data |
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7b9cbadb AJ |
1 | /* |
2 | * QEMU MIPS interrupt support | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
5 | * of this software and associated documentation files (the "Software"), to deal | |
6 | * in the Software without restriction, including without limitation the rights | |
7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
8 | * copies of the Software, and to permit persons to whom the Software is | |
9 | * furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
20 | * THE SOFTWARE. | |
21 | */ | |
22 | ||
83c9f4ca | 23 | #include "hw/hw.h" |
0d09e41a | 24 | #include "hw/mips/cpudevs.h" |
4de9b249 TS |
25 | #include "cpu.h" |
26 | ||
d537cf6c | 27 | static void cpu_mips_irq_request(void *opaque, int irq, int level) |
4de9b249 | 28 | { |
d8ed887b AF |
29 | MIPSCPU *cpu = opaque; |
30 | CPUMIPSState *env = &cpu->env; | |
31 | CPUState *cs = CPU(cpu); | |
4de9b249 | 32 | |
39d51eb8 | 33 | if (irq < 0 || irq > 7) |
4de9b249 TS |
34 | return; |
35 | ||
4de9b249 | 36 | if (level) { |
39d51eb8 | 37 | env->CP0_Cause |= 1 << (irq + CP0Ca_IP); |
4de9b249 | 38 | } else { |
a4bc3afc | 39 | env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); |
4de9b249 | 40 | } |
36388314 EI |
41 | |
42 | if (env->CP0_Cause & CP0Ca_IP_mask) { | |
c3affe56 | 43 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
36388314 | 44 | } else { |
d8ed887b | 45 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
36388314 | 46 | } |
4de9b249 | 47 | } |
d537cf6c | 48 | |
61c56c8c | 49 | void cpu_mips_irq_init_cpu(CPUMIPSState *env) |
d537cf6c PB |
50 | { |
51 | qemu_irq *qi; | |
52 | int i; | |
53 | ||
d8ed887b | 54 | qi = qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env), 8); |
d537cf6c PB |
55 | for (i = 0; i < 8; i++) { |
56 | env->irq[i] = qi[i]; | |
57 | } | |
58 | } | |
5dc5d9f0 | 59 | |
61c56c8c | 60 | void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level) |
5dc5d9f0 AJ |
61 | { |
62 | if (irq < 0 || irq > 2) { | |
63 | return; | |
64 | } | |
65 | ||
66 | qemu_set_irq(env->irq[irq], level); | |
67 | } |