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1#ifndef HW_MIPS_H
2#define HW_MIPS_H
3/* Definitions for mips board emulation. */
4
5/* gt64xxx.c */
6PCIBus *pci_gt64120_init(qemu_irq *pic);
7
8/* ds1225y.c */
c227f099 9void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
02cb1585 10void ds1225y_set_protection(void *opaque, int protection);
87ecb68b 11
4ce7ff6e 12/* g364fb.c */
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13int g364fb_mm_init(target_phys_addr_t vram_base,
14 target_phys_addr_t ctrl_base, int it_shift,
0add30cf 15 qemu_irq irq);
4ce7ff6e 16
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17/* mipsnet.c */
18void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
19
20/* jazz_led.c */
c227f099 21extern void jazz_led_init(target_phys_addr_t base);
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22
23/* mips_int.c */
24extern void cpu_mips_irq_init_cpu(CPUState *env);
25
26/* mips_timer.c */
27extern void cpu_mips_clock_init(CPUState *);
87ecb68b 28
4ce7ff6e 29/* rc4030.c */
c6945b15 30typedef struct rc4030DMAState *rc4030_dma;
c227f099 31void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
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32void rc4030_dma_read(void *dma, uint8_t *buf, int len);
33void rc4030_dma_write(void *dma, uint8_t *buf, int len);
34
35void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
36 qemu_irq **irqs, rc4030_dma **dmas);
4ce7ff6e 37
a65f56ee 38/* dp8393x.c */
c227f099 39void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
a65f56ee 40 qemu_irq irq, void* mem_opaque,
c227f099 41 void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write));
a65f56ee 42
87ecb68b 43#endif