[qemu.git] / hw / mips_fulong2e.c

/*
 * QEMU fulong 2e mini pc support
 *
 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
 * This code is licensed under the GNU GPL v2.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */

/*
 * Fulong 2e mini pc is based on ICT/ST Loongson 2e CPU (MIPS III like, 800MHz)
 * http://www.linux-mips.org/wiki/Fulong
 *
 * Loongson 2e user manual:
 * http://www.loongsondeveloper.com/doc/Loongson2EUserGuide.pdf
 */

#include "hw.h"
#include "pc.h"
#include "serial.h"
#include "fdc.h"
#include "net.h"
#include "boards.h"
#include "smbus.h"
#include "block.h"
#include "flash.h"
#include "mips.h"
#include "mips_cpudevs.h"
#include "pci/pci.h"
#include "qemu-char.h"
#include "sysemu.h"
#include "audio/audio.h"
#include "qemu-log.h"
#include "loader.h"
#include "mips-bios.h"
#include "ide.h"
#include "elf.h"
#include "vt82c686.h"
#include "mc146818rtc.h"
#include "i8254.h"
#include "blockdev.h"
#include "exec-memory.h"

#define DEBUG_FULONG2E_INIT

#define ENVP_ADDR       0x80002000l
#define ENVP_NB_ENTRIES	 	16
#define ENVP_ENTRY_SIZE	 	256

#define MAX_IDE_BUS 2

/*
 * PMON is not part of qemu and released with BSD license, anyone
 * who want to build a pmon binary please first git-clone the source
 * from the git repository at:
 * http://www.loongson.cn/support/git/pmon
 * Then follow the "Compile Guide" available at:
 * http://dev.lemote.com/code/pmon
 *
 * Notes:
 * 1, don't use the source at http://dev.lemote.com/http_git/pmon.git
 * 2, use "Bonito2edev" to replace "dir_corresponding_to_your_target_hardware"
 * in the "Compile Guide".
 */
#define FULONG_BIOSNAME "pmon_fulong2e.bin"

/* PCI SLOT in fulong 2e */
#define FULONG2E_VIA_SLOT        5
#define FULONG2E_ATI_SLOT        6
#define FULONG2E_RTL8139_SLOT    7

static ISADevice *pit;

static struct _loaderparams {
    int ram_size;
    const char *kernel_filename;
    const char *kernel_cmdline;
    const char *initrd_filename;
} loaderparams;

static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
                                        const char *string, ...)
{
    va_list ap;
    int32_t table_addr;

    if (index >= ENVP_NB_ENTRIES)
        return;

    if (string == NULL) {
        prom_buf[index] = 0;
        return;
    }

    table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
    prom_buf[index] = tswap32(ENVP_ADDR + table_addr);

    va_start(ap, string);
    vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
    va_end(ap);
}

static int64_t load_kernel (CPUMIPSState *env)
{
    int64_t kernel_entry, kernel_low, kernel_high;
    int index = 0;
    long initrd_size;
    ram_addr_t initrd_offset;
    uint32_t *prom_buf;
    long prom_size;

    if (load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL,
                 (uint64_t *)&kernel_entry, (uint64_t *)&kernel_low,
                 (uint64_t *)&kernel_high, 0, ELF_MACHINE, 1) < 0) {
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
                loaderparams.kernel_filename);
        exit(1);
    }

    /* load initrd */
    initrd_size = 0;
    initrd_offset = 0;
    if (loaderparams.initrd_filename) {
        initrd_size = get_image_size (loaderparams.initrd_filename);
        if (initrd_size > 0) {
            initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
            if (initrd_offset + initrd_size > ram_size) {
                fprintf(stderr,
                        "qemu: memory too small for initial ram disk '%s'\n",
                        loaderparams.initrd_filename);
                exit(1);
            }
            initrd_size = load_image_targphys(loaderparams.initrd_filename,
                                     initrd_offset, ram_size - initrd_offset);
        }
        if (initrd_size == (target_ulong) -1) {
            fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
                    loaderparams.initrd_filename);
            exit(1);
        }
    }

    /* Setup prom parameters. */
    prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
    prom_buf = g_malloc(prom_size);

    prom_set(prom_buf, index++, "%s", loaderparams.kernel_filename);
    if (initrd_size > 0) {
        prom_set(prom_buf, index++, "rd_start=0x%" PRIx64 " rd_size=%li %s",
                 cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size,
                 loaderparams.kernel_cmdline);
    } else {
        prom_set(prom_buf, index++, "%s", loaderparams.kernel_cmdline);
    }

    /* Setup minimum environment variables */
    prom_set(prom_buf, index++, "busclock=33000000");
    prom_set(prom_buf, index++, "cpuclock=100000000");
    prom_set(prom_buf, index++, "memsize=%i", loaderparams.ram_size/1024/1024);
    prom_set(prom_buf, index++, "modetty0=38400n8r");
    prom_set(prom_buf, index++, NULL);

    rom_add_blob_fixed("prom", prom_buf, prom_size,
                       cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));

    return kernel_entry;
}

static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_addr)
{
    uint32_t *p;

    /* Small bootloader */
    p = (uint32_t *) base;

    stl_raw(p++, 0x0bf00010);                                      /* j 0x1fc00040 */
    stl_raw(p++, 0x00000000);                                      /* nop */

    /* Second part of the bootloader */
    p = (uint32_t *) (base + 0x040);

    stl_raw(p++, 0x3c040000);                                      /* lui a0, 0 */
    stl_raw(p++, 0x34840002);                                      /* ori a0, a0, 2 */
    stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));       /* lui a1, high(ENVP_ADDR) */
    stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));               /* ori a1, a0, low(ENVP_ADDR) */
    stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
    stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));         /* ori a2, a2, low(ENVP_ADDR + 8) */
    stl_raw(p++, 0x3c070000 | (loaderparams.ram_size >> 16));      /* lui a3, high(env->ram_size) */
    stl_raw(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff));   /* ori a3, a3, low(env->ram_size) */
    stl_raw(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff));     /* lui ra, high(kernel_addr) */;
    stl_raw(p++, 0x37ff0000 | (kernel_addr & 0xffff));             /* ori ra, ra, low(kernel_addr) */
    stl_raw(p++, 0x03e00008);                                      /* jr ra */
    stl_raw(p++, 0x00000000);                                      /* nop */
}


static void main_cpu_reset(void *opaque)
{
    MIPSCPU *cpu = opaque;
    CPUMIPSState *env = &cpu->env;

    cpu_reset(CPU(cpu));
    /* TODO: 2E reset stuff */
    if (loaderparams.kernel_filename) {
        env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
    }
}

uint8_t eeprom_spd[0x80] = {
    0x80,0x08,0x07,0x0d,0x09,0x02,0x40,0x00,0x04,0x70,
    0x70,0x00,0x82,0x10,0x00,0x01,0x0e,0x04,0x0c,0x01,
    0x02,0x20,0x80,0x75,0x70,0x00,0x00,0x50,0x3c,0x50,
    0x2d,0x20,0xb0,0xb0,0x50,0x50,0x00,0x00,0x00,0x00,
    0x00,0x41,0x48,0x3c,0x32,0x75,0x00,0x00,0x00,0x00,
    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
    0x00,0x00,0x00,0x9c,0x7b,0x07,0x00,0x00,0x00,0x00,
    0x00,0x00,0x00,0x00,0x48,0x42,0x35,0x34,0x41,0x32,
    0x35,0x36,0x38,0x4b,0x4e,0x2d,0x41,0x37,0x35,0x42,
    0x20,0x30,0x20
};

/* Audio support */
static void audio_init (PCIBus *pci_bus)
{
    vt82c686b_ac97_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 5));
    vt82c686b_mc97_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 6));
}

/* Network support */
static void network_init (void)
{
    int i;

    for(i = 0; i < nb_nics; i++) {
        NICInfo *nd = &nd_table[i];
        const char *default_devaddr = NULL;

        if (i == 0 && (!nd->model || strcmp(nd->model, "rtl8139") == 0)) {
            /* The fulong board has a RTL8139 card using PCI SLOT 7 */
            default_devaddr = "07";
        }

        pci_nic_init_nofail(nd, "rtl8139", default_devaddr);
    }
}

static void cpu_request_exit(void *opaque, int irq, int level)
{
    CPUMIPSState *env = cpu_single_env;

    if (env && level) {
        cpu_exit(env);
    }
}

static void mips_fulong2e_init(QEMUMachineInitArgs *args)
{
    ram_addr_t ram_size = args->ram_size;
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    const char *kernel_cmdline = args->kernel_cmdline;
    const char *initrd_filename = args->initrd_filename;
    char *filename;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *ram = g_new(MemoryRegion, 1);
    MemoryRegion *bios = g_new(MemoryRegion, 1);
    long bios_size;
    int64_t kernel_entry;
    qemu_irq *i8259;
    qemu_irq *cpu_exit_irq;
    PCIBus *pci_bus;
    ISABus *isa_bus;
    i2c_bus *smbus;
    int i;
    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
    MIPSCPU *cpu;
    CPUMIPSState *env;

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "Loongson-2E";
    }
    cpu = cpu_mips_init(cpu_model);
    if (cpu == NULL) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }
    env = &cpu->env;

    qemu_register_reset(main_cpu_reset, cpu);

    /* fulong 2e has 256M ram. */
    ram_size = 256 * 1024 * 1024;

    /* fulong 2e has a 1M flash.Winbond W39L040AP70Z */
    bios_size = 1024 * 1024;

    /* allocate RAM */
    memory_region_init_ram(ram, "fulong2e.ram", ram_size);
    vmstate_register_ram_global(ram);
    memory_region_init_ram(bios, "fulong2e.bios", bios_size);
    vmstate_register_ram_global(bios);
    memory_region_set_readonly(bios, true);

    memory_region_add_subregion(address_space_mem, 0, ram);
    memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);

    /* We do not support flash operation, just loading pmon.bin as raw BIOS.
     * Please use -L to set the BIOS path and -bios to set bios name. */

    if (kernel_filename) {
        loaderparams.ram_size = ram_size;
        loaderparams.kernel_filename = kernel_filename;
        loaderparams.kernel_cmdline = kernel_cmdline;
        loaderparams.initrd_filename = initrd_filename;
        kernel_entry = load_kernel (env);
        write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
    } else {
        if (bios_name == NULL) {
                bios_name = FULONG_BIOSNAME;
        }
        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
        if (filename) {
            bios_size = load_image_targphys(filename, 0x1fc00000LL,
                                            BIOS_SIZE);
            g_free(filename);
        } else {
            bios_size = -1;
        }

        if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {
            fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n", bios_name);
            exit(1);
        }
    }

    /* Init internal devices */
    cpu_mips_irq_init_cpu(env);
    cpu_mips_clock_init(env);

    /* North bridge, Bonito --> IP2 */
    pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));

    /* South bridge */
    ide_drive_get(hd, MAX_IDE_BUS);

    isa_bus = vt82c686b_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 0));
    if (!isa_bus) {
        fprintf(stderr, "vt82c686b_init error\n");
        exit(1);
    }

    /* Interrupt controller */
    /* The 8259 -> IP5  */
    i8259 = i8259_init(isa_bus, env->irq[5]);
    isa_bus_irqs(isa_bus, i8259);

    vt82c686b_ide_init(pci_bus, hd, PCI_DEVFN(FULONG2E_VIA_SLOT, 1));
    pci_create_simple(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 2),
                      "vt82c686b-usb-uhci");
    pci_create_simple(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 3),
                      "vt82c686b-usb-uhci");

    smbus = vt82c686b_pm_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 4),
                              0xeee1, NULL);
    /* TODO: Populate SPD eeprom data.  */
    smbus_eeprom_init(smbus, 1, eeprom_spd, sizeof(eeprom_spd));

    /* init other devices */
    pit = pit_init(isa_bus, 0x40, 0, NULL);
    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
    DMA_init(0, cpu_exit_irq);

    /* Super I/O */
    isa_create_simple(isa_bus, "i8042");

    rtc_init(isa_bus, 2000, NULL);

    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
        if (serial_hds[i]) {
            serial_isa_init(isa_bus, i, serial_hds[i]);
        }
    }

    if (parallel_hds[0]) {
        parallel_init(isa_bus, 0, parallel_hds[0]);
    }

    /* Sound card */
    audio_init(pci_bus);
    /* Network card */
    network_init();
}

static QEMUMachine mips_fulong2e_machine = {
    .name = "fulong2e",
    .desc = "Fulong 2e mini pc",
    .init = mips_fulong2e_init,
};

static void mips_fulong2e_machine_init(void)
{
    qemu_register_machine(&mips_fulong2e_machine);
}

machine_init(mips_fulong2e_machine_init);
Commit	Line	Data
051c190b HC	1	/*
	2	* QEMU fulong 2e mini pc support
	3	*
	4	* Copyright (c) 2008 yajin (yajin@vm-kernel.org)
	5	* Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
	6	* Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
	7	* This code is licensed under the GNU GPL v2.
6b620ca3 PB	8	*
	9	* Contributions after 2012-01-13 are licensed under the terms of the
	10	* GNU GPL, version 2 or (at your option) any later version.
051c190b HC	11	*/
	12
	13	/*
	14	* Fulong 2e mini pc is based on ICT/ST Loongson 2e CPU (MIPS III like, 800MHz)
	15	* http://www.linux-mips.org/wiki/Fulong
	16	*
	17	* Loongson 2e user manual:
	18	* http://www.loongsondeveloper.com/doc/Loongson2EUserGuide.pdf
	19	*/
	20
	21	#include "hw.h"
	22	#include "pc.h"
488cb996	23	#include "serial.h"
051c190b HC	24	#include "fdc.h"
	25	#include "net.h"
	26	#include "boards.h"
	27	#include "smbus.h"
	28	#include "block.h"
	29	#include "flash.h"
	30	#include "mips.h"
	31	#include "mips_cpudevs.h"
a2cb15b0	32	#include "pci/pci.h"
051c190b HC	33	#include "qemu-char.h"
	34	#include "sysemu.h"
	35	#include "audio/audio.h"
	36	#include "qemu-log.h"
	37	#include "loader.h"
	38	#include "mips-bios.h"
	39	#include "ide.h"
	40	#include "elf.h"
	41	#include "vt82c686.h"
	42	#include "mc146818rtc.h"
b1277b03	43	#include "i8254.h"
2446333c	44	#include "blockdev.h"
13faf2a7	45	#include "exec-memory.h"
051c190b HC	46
	47	#define DEBUG_FULONG2E_INIT
	48
	49	#define ENVP_ADDR 0x80002000l
	50	#define ENVP_NB_ENTRIES 16
	51	#define ENVP_ENTRY_SIZE 256
	52
	53	#define MAX_IDE_BUS 2
	54
	55	/*
	56	* PMON is not part of qemu and released with BSD license, anyone
	57	* who want to build a pmon binary please first git-clone the source
	58	* from the git repository at:
	59	* http://www.loongson.cn/support/git/pmon
	60	* Then follow the "Compile Guide" available at:
	61	* http://dev.lemote.com/code/pmon
	62	*
	63	* Notes:
	64	* 1, don't use the source at http://dev.lemote.com/http_git/pmon.git
	65	* 2, use "Bonito2edev" to replace "dir_corresponding_to_your_target_hardware"
	66	* in the "Compile Guide".
	67	*/
	68	#define FULONG_BIOSNAME "pmon_fulong2e.bin"
	69
	70	/* PCI SLOT in fulong 2e */
	71	#define FULONG2E_VIA_SLOT 5
	72	#define FULONG2E_ATI_SLOT 6
	73	#define FULONG2E_RTL8139_SLOT 7
	74
64d7e9a4	75	static ISADevice *pit;
051c190b HC	76
	77	static struct _loaderparams {
	78	int ram_size;
	79	const char *kernel_filename;
	80	const char *kernel_cmdline;
	81	const char *initrd_filename;
	82	} loaderparams;
	83
8b7968f7 SW	84	static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
8b7968f7 SW	85	const char *string, ...)
051c190b HC	86	{
	87	va_list ap;
	88	int32_t table_addr;
	89
	90	if (index >= ENVP_NB_ENTRIES)
	91	return;
	92
	93	if (string == NULL) {
	94	prom_buf[index] = 0;
	95	return;
	96	}
	97
	98	table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
	99	prom_buf[index] = tswap32(ENVP_ADDR + table_addr);
	100
	101	va_start(ap, string);
	102	vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
	103	va_end(ap);
	104	}
	105
61c56c8c	106	static int64_t load_kernel (CPUMIPSState *env)
051c190b HC	107	{
	108	int64_t kernel_entry, kernel_low, kernel_high;
	109	int index = 0;
	110	long initrd_size;
	111	ram_addr_t initrd_offset;
	112	uint32_t *prom_buf;
	113	long prom_size;
	114
	115	if (load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL,
	116	(uint64_t )&kernel_entry, (uint64_t )&kernel_low,
	117	(uint64_t *)&kernel_high, 0, ELF_MACHINE, 1) < 0) {
	118	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	119	loaderparams.kernel_filename);
	120	exit(1);
	121	}
	122
	123	/* load initrd */
	124	initrd_size = 0;
	125	initrd_offset = 0;
	126	if (loaderparams.initrd_filename) {
	127	initrd_size = get_image_size (loaderparams.initrd_filename);
	128	if (initrd_size > 0) {
	129	initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
	130	if (initrd_offset + initrd_size > ram_size) {
	131	fprintf(stderr,
	132	"qemu: memory too small for initial ram disk '%s'\n",
	133	loaderparams.initrd_filename);
	134	exit(1);
	135	}
	136	initrd_size = load_image_targphys(loaderparams.initrd_filename,
	137	initrd_offset, ram_size - initrd_offset);
	138	}
	139	if (initrd_size == (target_ulong) -1) {
	140	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
	141	loaderparams.initrd_filename);
	142	exit(1);
	143	}
	144	}
	145
	146	/* Setup prom parameters. */
	147	prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
7267c094	148	prom_buf = g_malloc(prom_size);
051c190b	149
1ed1139d	150	prom_set(prom_buf, index++, "%s", loaderparams.kernel_filename);
051c190b	151	if (initrd_size > 0) {
1ed1139d	152	prom_set(prom_buf, index++, "rd_start=0x%" PRIx64 " rd_size=%li %s",
051c190b HC	153	cpu_mips_phys_to_kseg0(NULL, initrd_offset), initrd_size,
	154	loaderparams.kernel_cmdline);
	155	} else {
1ed1139d	156	prom_set(prom_buf, index++, "%s", loaderparams.kernel_cmdline);
051c190b HC	157	}
	158
	159	/* Setup minimum environment variables */
	160	prom_set(prom_buf, index++, "busclock=33000000");
	161	prom_set(prom_buf, index++, "cpuclock=100000000");
	162	prom_set(prom_buf, index++, "memsize=%i", loaderparams.ram_size/1024/1024);
	163	prom_set(prom_buf, index++, "modetty0=38400n8r");
	164	prom_set(prom_buf, index++, NULL);
	165
	166	rom_add_blob_fixed("prom", prom_buf, prom_size,
	167	cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));
	168
	169	return kernel_entry;
	170	}
	171
61c56c8c	172	static void write_bootloader (CPUMIPSState env, uint8_t base, int64_t kernel_addr)
051c190b HC	173	{
	174	uint32_t *p;
	175
	176	/* Small bootloader */
	177	p = (uint32_t *) base;
	178
	179	stl_raw(p++, 0x0bf00010); /* j 0x1fc00040 */
	180	stl_raw(p++, 0x00000000); /* nop */
	181
	182	/* Second part of the bootloader */
	183	p = (uint32_t *) (base + 0x040);
	184
	185	stl_raw(p++, 0x3c040000); /* lui a0, 0 */
	186	stl_raw(p++, 0x34840002); /* ori a0, a0, 2 */
	187	stl_raw(p++, 0x3c050000 \| ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
	188	stl_raw(p++, 0x34a50000 \| (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */
	189	stl_raw(p++, 0x3c060000 \| (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
	190	stl_raw(p++, 0x34c60000 \| ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
	191	stl_raw(p++, 0x3c070000 \| (loaderparams.ram_size >> 16)); /* lui a3, high(env->ram_size) */
	192	stl_raw(p++, 0x34e70000 \| (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */
	193	stl_raw(p++, 0x3c1f0000 \| ((kernel_addr >> 16) & 0xffff)); /* lui ra, high(kernel_addr) */;
	194	stl_raw(p++, 0x37ff0000 \| (kernel_addr & 0xffff)); /* ori ra, ra, low(kernel_addr) */
	195	stl_raw(p++, 0x03e00008); /* jr ra */
	196	stl_raw(p++, 0x00000000); /* nop */
	197	}
	198
	199
	200	static void main_cpu_reset(void *opaque)
	201	{
800cf598 AF	202	MIPSCPU *cpu = opaque;
800cf598 AF	203	CPUMIPSState *env = &cpu->env;
051c190b	204
800cf598	205	cpu_reset(CPU(cpu));
051c190b HC	206	/* TODO: 2E reset stuff */
	207	if (loaderparams.kernel_filename) {
	208	env->CP0_Status &= ~((1 << CP0St_BEV) \| (1 << CP0St_ERL));
	209	}
	210	}
	211
	212	uint8_t eeprom_spd[0x80] = {
	213	0x80,0x08,0x07,0x0d,0x09,0x02,0x40,0x00,0x04,0x70,
	214	0x70,0x00,0x82,0x10,0x00,0x01,0x0e,0x04,0x0c,0x01,
	215	0x02,0x20,0x80,0x75,0x70,0x00,0x00,0x50,0x3c,0x50,
	216	0x2d,0x20,0xb0,0xb0,0x50,0x50,0x00,0x00,0x00,0x00,
	217	0x00,0x41,0x48,0x3c,0x32,0x75,0x00,0x00,0x00,0x00,
	218	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	219	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	220	0x00,0x00,0x00,0x9c,0x7b,0x07,0x00,0x00,0x00,0x00,
	221	0x00,0x00,0x00,0x00,0x48,0x42,0x35,0x34,0x41,0x32,
	222	0x35,0x36,0x38,0x4b,0x4e,0x2d,0x41,0x37,0x35,0x42,
	223	0x20,0x30,0x20
	224	};
	225
	226	/* Audio support */
051c190b HC	227	static void audio_init (PCIBus *pci_bus)
051c190b HC	228	{
7899f799 IY	229	vt82c686b_ac97_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 5));
7899f799 IY	230	vt82c686b_mc97_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 6));
051c190b	231	}
051c190b HC	232
	233	/* Network support */
	234	static void network_init (void)
	235	{
	236	int i;
	237
	238	for(i = 0; i < nb_nics; i++) {
	239	NICInfo *nd = &nd_table[i];
	240	const char *default_devaddr = NULL;
	241
	242	if (i == 0 && (!nd->model \|\| strcmp(nd->model, "rtl8139") == 0)) {
	243	/* The fulong board has a RTL8139 card using PCI SLOT 7 */
	244	default_devaddr = "07";
	245	}
	246
	247	pci_nic_init_nofail(nd, "rtl8139", default_devaddr);
	248	}
	249	}
	250
	251	static void cpu_request_exit(void *opaque, int irq, int level)
	252	{
61c56c8c	253	CPUMIPSState *env = cpu_single_env;
051c190b HC	254
	255	if (env && level) {
	256	cpu_exit(env);
	257	}
	258	}
	259
5f072e1f	260	static void mips_fulong2e_init(QEMUMachineInitArgs *args)
051c190b	261	{
5f072e1f EH	262	ram_addr_t ram_size = args->ram_size;
	263	const char *cpu_model = args->cpu_model;
	264	const char *kernel_filename = args->kernel_filename;
	265	const char *kernel_cmdline = args->kernel_cmdline;
	266	const char *initrd_filename = args->initrd_filename;
051c190b	267	char *filename;
13faf2a7 AK	268	MemoryRegion *address_space_mem = get_system_memory();
	269	MemoryRegion *ram = g_new(MemoryRegion, 1);
	270	MemoryRegion *bios = g_new(MemoryRegion, 1);
093209cd	271	long bios_size;
051c190b HC	272	int64_t kernel_entry;
	273	qemu_irq *i8259;
	274	qemu_irq *cpu_exit_irq;
051c190b	275	PCIBus *pci_bus;
48a18b3c	276	ISABus *isa_bus;
051c190b HC	277	i2c_bus *smbus;
	278	int i;
	279	DriveInfo hd[MAX_IDE_BUS MAX_IDE_DEVS];
f0f80366	280	MIPSCPU *cpu;
61c56c8c	281	CPUMIPSState *env;
051c190b HC	282
	283	/* init CPUs */
	284	if (cpu_model == NULL) {
	285	cpu_model = "Loongson-2E";
	286	}
f0f80366 AF	287	cpu = cpu_mips_init(cpu_model);
f0f80366 AF	288	if (cpu == NULL) {
051c190b HC	289	fprintf(stderr, "Unable to find CPU definition\n");
	290	exit(1);
	291	}
f0f80366	292	env = &cpu->env;
051c190b	293
800cf598	294	qemu_register_reset(main_cpu_reset, cpu);
051c190b HC	295
	296	/* fulong 2e has 256M ram. */
	297	ram_size = 256 * 1024 * 1024;
	298
	299	/* fulong 2e has a 1M flash.Winbond W39L040AP70Z */
	300	bios_size = 1024 * 1024;
	301
	302	/* allocate RAM */
c5705a77 AK	303	memory_region_init_ram(ram, "fulong2e.ram", ram_size);
	304	vmstate_register_ram_global(ram);
	305	memory_region_init_ram(bios, "fulong2e.bios", bios_size);
	306	vmstate_register_ram_global(bios);
13faf2a7	307	memory_region_set_readonly(bios, true);
051c190b	308
13faf2a7 AK	309	memory_region_add_subregion(address_space_mem, 0, ram);
13faf2a7 AK	310	memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
051c190b HC	311
	312	/* We do not support flash operation, just loading pmon.bin as raw BIOS.
	313	* Please use -L to set the BIOS path and -bios to set bios name. */
	314
	315	if (kernel_filename) {
	316	loaderparams.ram_size = ram_size;
	317	loaderparams.kernel_filename = kernel_filename;
	318	loaderparams.kernel_cmdline = kernel_cmdline;
	319	loaderparams.initrd_filename = initrd_filename;
	320	kernel_entry = load_kernel (env);
13faf2a7	321	write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
051c190b	322	} else {
33dd2983 AJ	323	if (bios_name == NULL) {
33dd2983 AJ	324	bios_name = FULONG_BIOSNAME;
051c190b HC	325	}
	326	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
	327	if (filename) {
	328	bios_size = load_image_targphys(filename, 0x1fc00000LL,
	329	BIOS_SIZE);
7267c094	330	g_free(filename);
051c190b HC	331	} else {
	332	bios_size = -1;
	333	}
	334
33dd2983 AJ	335	if ((bios_size < 0 \|\| bios_size > BIOS_SIZE) && !kernel_filename) {
33dd2983 AJ	336	fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n", bios_name);
051c190b	337	exit(1);
33dd2983	338	}
051c190b HC	339	}
	340
	341	/* Init internal devices */
	342	cpu_mips_irq_init_cpu(env);
	343	cpu_mips_clock_init(env);
	344
051c190b HC	345	/* North bridge, Bonito --> IP2 */
	346	pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));
	347
	348	/* South bridge */
75717903	349	ide_drive_get(hd, MAX_IDE_BUS);
051c190b	350
c9940edb HP	351	isa_bus = vt82c686b_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 0));
c9940edb HP	352	if (!isa_bus) {
b2bedb21	353	fprintf(stderr, "vt82c686b_init error\n");
051c190b HC	354	exit(1);
	355	}
	356
7e17a217 JK	357	/* Interrupt controller */
7e17a217 JK	358	/* The 8259 -> IP5 */
48a18b3c HP	359	i8259 = i8259_init(isa_bus, env->irq[5]);
48a18b3c HP	360	isa_bus_irqs(isa_bus, i8259);
7e17a217	361
7899f799	362	vt82c686b_ide_init(pci_bus, hd, PCI_DEVFN(FULONG2E_VIA_SLOT, 1));
afb9a60e GH	363	pci_create_simple(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 2),
	364	"vt82c686b-usb-uhci");
	365	pci_create_simple(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 3),
	366	"vt82c686b-usb-uhci");
051c190b	367
7899f799	368	smbus = vt82c686b_pm_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 4),
051c190b	369	0xeee1, NULL);
051c190b	370	/* TODO: Populate SPD eeprom data. */
a88df0b9	371	smbus_eeprom_init(smbus, 1, eeprom_spd, sizeof(eeprom_spd));
051c190b HC	372
051c190b HC	373	/* init other devices */
319ba9f5	374	pit = pit_init(isa_bus, 0x40, 0, NULL);
051c190b HC	375	cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
	376	DMA_init(0, cpu_exit_irq);
	377
	378	/* Super I/O */
48a18b3c	379	isa_create_simple(isa_bus, "i8042");
051c190b	380
48a18b3c	381	rtc_init(isa_bus, 2000, NULL);
051c190b HC	382
	383	for(i = 0; i < MAX_SERIAL_PORTS; i++) {
	384	if (serial_hds[i]) {
48a18b3c	385	serial_isa_init(isa_bus, i, serial_hds[i]);
051c190b HC	386	}
	387	}
	388
	389	if (parallel_hds[0]) {
48a18b3c	390	parallel_init(isa_bus, 0, parallel_hds[0]);
051c190b HC	391	}
	392
	393	/* Sound card */
051c190b	394	audio_init(pci_bus);
051c190b HC	395	/* Network card */
	396	network_init();
	397	}
	398
da665c99	399	static QEMUMachine mips_fulong2e_machine = {
051c190b HC	400	.name = "fulong2e",
	401	.desc = "Fulong 2e mini pc",
	402	.init = mips_fulong2e_init,
	403	};
	404
	405	static void mips_fulong2e_machine_init(void)
	406	{
	407	qemu_register_machine(&mips_fulong2e_machine);
	408	}
	409
	410	machine_init(mips_fulong2e_machine_init);