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4ce7ff6e AJ |
1 | /* |
2 | * QEMU MIPS Jazz support | |
3 | * | |
4 | * Copyright (c) 2007-2008 Hervé Poussineau | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "hw.h" | |
26 | #include "mips.h" | |
27 | #include "pc.h" | |
28 | #include "isa.h" | |
29 | #include "fdc.h" | |
30 | #include "sysemu.h" | |
31 | #include "audio/audio.h" | |
32 | #include "boards.h" | |
33 | #include "net.h" | |
34 | #include "scsi.h" | |
bba831e8 | 35 | #include "mips-bios.h" |
ca20cf32 | 36 | #include "loader.h" |
4ce7ff6e | 37 | |
4ce7ff6e AJ |
38 | enum jazz_model_e |
39 | { | |
40 | JAZZ_MAGNUM, | |
c171148c | 41 | JAZZ_PICA61, |
4ce7ff6e AJ |
42 | }; |
43 | ||
44 | static void main_cpu_reset(void *opaque) | |
45 | { | |
46 | CPUState *env = opaque; | |
47 | cpu_reset(env); | |
48 | } | |
49 | ||
c227f099 | 50 | static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr) |
4ce7ff6e | 51 | { |
afcea8cb | 52 | return cpu_inw(0x71); |
4ce7ff6e AJ |
53 | } |
54 | ||
c227f099 | 55 | static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
4ce7ff6e | 56 | { |
afcea8cb | 57 | cpu_outw(0x71, val & 0xff); |
4ce7ff6e AJ |
58 | } |
59 | ||
d60efc6b | 60 | static CPUReadMemoryFunc * const rtc_read[3] = { |
4ce7ff6e AJ |
61 | rtc_readb, |
62 | rtc_readb, | |
63 | rtc_readb, | |
64 | }; | |
65 | ||
d60efc6b | 66 | static CPUWriteMemoryFunc * const rtc_write[3] = { |
4ce7ff6e AJ |
67 | rtc_writeb, |
68 | rtc_writeb, | |
69 | rtc_writeb, | |
70 | }; | |
71 | ||
c227f099 | 72 | static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
c6945b15 AJ |
73 | { |
74 | /* Nothing to do. That is only to ensure that | |
75 | * the current DMA acknowledge cycle is completed. */ | |
76 | } | |
77 | ||
d60efc6b | 78 | static CPUReadMemoryFunc * const dma_dummy_read[3] = { |
c6945b15 AJ |
79 | NULL, |
80 | NULL, | |
81 | NULL, | |
82 | }; | |
83 | ||
d60efc6b | 84 | static CPUWriteMemoryFunc * const dma_dummy_write[3] = { |
c6945b15 AJ |
85 | dma_dummy_writeb, |
86 | dma_dummy_writeb, | |
87 | dma_dummy_writeb, | |
88 | }; | |
89 | ||
4ce7ff6e AJ |
90 | #ifdef HAS_AUDIO |
91 | static void audio_init(qemu_irq *pic) | |
92 | { | |
93 | struct soundhw *c; | |
94 | int audio_enabled = 0; | |
95 | ||
96 | for (c = soundhw; !audio_enabled && c->name; ++c) { | |
97 | audio_enabled = c->enabled; | |
98 | } | |
99 | ||
100 | if (audio_enabled) { | |
0d9acba8 PB |
101 | for (c = soundhw; c->name; ++c) { |
102 | if (c->enabled) { | |
103 | if (c->isa) { | |
22d83b14 | 104 | c->init.init_isa(pic); |
4ce7ff6e AJ |
105 | } |
106 | } | |
107 | } | |
108 | } | |
109 | } | |
110 | #endif | |
111 | ||
4ce7ff6e AJ |
112 | #define MAGNUM_BIOS_SIZE_MAX 0x7e000 |
113 | #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) | |
114 | ||
115 | static | |
c227f099 | 116 | void mips_jazz_init (ram_addr_t ram_size, |
3023f332 | 117 | const char *cpu_model, |
4ce7ff6e AJ |
118 | enum jazz_model_e jazz_model) |
119 | { | |
5cea8590 | 120 | char *filename; |
4ce7ff6e AJ |
121 | int bios_size, n; |
122 | CPUState *env; | |
123 | qemu_irq *rc4030, *i8259; | |
c6945b15 | 124 | rc4030_dma *dmas; |
68238a9e | 125 | void* rc4030_opaque; |
c6945b15 | 126 | int s_rtc, s_dma_dummy; |
a65f56ee | 127 | NICInfo *nd; |
4ce7ff6e | 128 | PITState *pit; |
fd8014e1 | 129 | DriveInfo *fds[MAX_FD]; |
4ce7ff6e | 130 | qemu_irq esp_reset; |
c227f099 AL |
131 | ram_addr_t ram_offset; |
132 | ram_addr_t bios_offset; | |
4ce7ff6e AJ |
133 | |
134 | /* init CPUs */ | |
135 | if (cpu_model == NULL) { | |
136 | #ifdef TARGET_MIPS64 | |
137 | cpu_model = "R4000"; | |
138 | #else | |
139 | /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */ | |
140 | cpu_model = "24Kf"; | |
141 | #endif | |
142 | } | |
143 | env = cpu_init(cpu_model); | |
144 | if (!env) { | |
145 | fprintf(stderr, "Unable to find CPU definition\n"); | |
146 | exit(1); | |
147 | } | |
a08d4367 | 148 | qemu_register_reset(main_cpu_reset, env); |
4ce7ff6e AJ |
149 | |
150 | /* allocate RAM */ | |
dcac9679 PB |
151 | ram_offset = qemu_ram_alloc(ram_size); |
152 | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); | |
153 | ||
dcac9679 PB |
154 | bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE); |
155 | cpu_register_physical_memory(0x1fc00000LL, | |
156 | MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); | |
157 | cpu_register_physical_memory(0xfff00000LL, | |
158 | MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); | |
4ce7ff6e AJ |
159 | |
160 | /* load the BIOS image. */ | |
c6945b15 AJ |
161 | if (bios_name == NULL) |
162 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
163 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
164 | if (filename) { | |
165 | bios_size = load_image_targphys(filename, 0xfff00000LL, | |
166 | MAGNUM_BIOS_SIZE); | |
167 | qemu_free(filename); | |
168 | } else { | |
169 | bios_size = -1; | |
170 | } | |
4ce7ff6e AJ |
171 | if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) { |
172 | fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n", | |
5cea8590 | 173 | bios_name); |
4ce7ff6e AJ |
174 | exit(1); |
175 | } | |
176 | ||
4ce7ff6e AJ |
177 | /* Init CPU internal devices */ |
178 | cpu_mips_irq_init_cpu(env); | |
179 | cpu_mips_clock_init(env); | |
180 | ||
181 | /* Chipset */ | |
68238a9e | 182 | rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas); |
1eed09cb | 183 | s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL); |
c6945b15 | 184 | cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy); |
4ce7ff6e AJ |
185 | |
186 | /* ISA devices */ | |
187 | i8259 = i8259_init(env->irq[4]); | |
c6945b15 | 188 | DMA_init(0); |
4ce7ff6e AJ |
189 | pit = pit_init(0x40, i8259[0]); |
190 | pcspk_init(pit); | |
191 | ||
192 | /* ISA IO space at 0x90000000 */ | |
193 | isa_mmio_init(0x90000000, 0x01000000); | |
194 | isa_mem_base = 0x11000000; | |
195 | ||
196 | /* Video card */ | |
197 | switch (jazz_model) { | |
198 | case JAZZ_MAGNUM: | |
fbe1b595 | 199 | g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]); |
4ce7ff6e | 200 | break; |
c171148c | 201 | case JAZZ_PICA61: |
fbe1b595 | 202 | isa_vga_mm_init(0x40000000, 0x60000000, 0); |
c171148c | 203 | break; |
4ce7ff6e AJ |
204 | default: |
205 | break; | |
206 | } | |
207 | ||
208 | /* Network controller */ | |
a65f56ee AJ |
209 | for (n = 0; n < nb_nics; n++) { |
210 | nd = &nd_table[n]; | |
211 | if (!nd->model) | |
212 | nd->model = "dp83932"; | |
213 | if (strcmp(nd->model, "dp83932") == 0) { | |
214 | dp83932_init(nd, 0x80001000, 2, rc4030[4], | |
215 | rc4030_opaque, rc4030_dma_memory_rw); | |
216 | break; | |
217 | } else if (strcmp(nd->model, "?") == 0) { | |
218 | fprintf(stderr, "qemu: Supported NICs: dp83932\n"); | |
219 | exit(1); | |
220 | } else { | |
221 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); | |
222 | exit(1); | |
223 | } | |
224 | } | |
4ce7ff6e AJ |
225 | |
226 | /* SCSI adapter */ | |
cfb9de9c PB |
227 | esp_init(0x80002000, 0, |
228 | rc4030_dma_read, rc4030_dma_write, dmas[0], | |
229 | rc4030[5], &esp_reset); | |
4ce7ff6e AJ |
230 | |
231 | /* Floppy */ | |
232 | if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) { | |
233 | fprintf(stderr, "qemu: too many floppy drives\n"); | |
234 | exit(1); | |
235 | } | |
236 | for (n = 0; n < MAX_FD; n++) { | |
fd8014e1 | 237 | fds[n] = drive_get(IF_FLOPPY, 0, n); |
4ce7ff6e | 238 | } |
2091ba23 | 239 | fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds); |
4ce7ff6e AJ |
240 | |
241 | /* Real time clock */ | |
32e0c826 | 242 | rtc_init(1980); |
afcea8cb | 243 | s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL); |
4ce7ff6e AJ |
244 | cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc); |
245 | ||
246 | /* Keyboard (i8042) */ | |
4efbe58f | 247 | i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1); |
4ce7ff6e AJ |
248 | |
249 | /* Serial ports */ | |
250 | if (serial_hds[0]) | |
b6cd0ea1 | 251 | serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1); |
4ce7ff6e | 252 | if (serial_hds[1]) |
b6cd0ea1 | 253 | serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1); |
4ce7ff6e AJ |
254 | |
255 | /* Parallel port */ | |
256 | if (parallel_hds[0]) | |
257 | parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]); | |
258 | ||
259 | /* Sound card */ | |
260 | /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ | |
261 | #ifdef HAS_AUDIO | |
262 | audio_init(i8259); | |
263 | #endif | |
264 | ||
265 | /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */ | |
266 | ds1225y_init(0x80009000, "nvram"); | |
267 | ||
268 | /* LED indicator */ | |
3023f332 | 269 | jazz_led_init(0x8000f000); |
4ce7ff6e AJ |
270 | } |
271 | ||
272 | static | |
c227f099 | 273 | void mips_magnum_init (ram_addr_t ram_size, |
3023f332 | 274 | const char *boot_device, |
4ce7ff6e AJ |
275 | const char *kernel_filename, const char *kernel_cmdline, |
276 | const char *initrd_filename, const char *cpu_model) | |
277 | { | |
fbe1b595 | 278 | mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM); |
4ce7ff6e AJ |
279 | } |
280 | ||
c171148c | 281 | static |
c227f099 | 282 | void mips_pica61_init (ram_addr_t ram_size, |
3023f332 | 283 | const char *boot_device, |
c171148c AJ |
284 | const char *kernel_filename, const char *kernel_cmdline, |
285 | const char *initrd_filename, const char *cpu_model) | |
286 | { | |
fbe1b595 | 287 | mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61); |
c171148c AJ |
288 | } |
289 | ||
f80f9ec9 | 290 | static QEMUMachine mips_magnum_machine = { |
eec2743e TS |
291 | .name = "magnum", |
292 | .desc = "MIPS Magnum", | |
293 | .init = mips_magnum_init, | |
c6945b15 | 294 | .use_scsi = 1, |
4ce7ff6e | 295 | }; |
c171148c | 296 | |
f80f9ec9 | 297 | static QEMUMachine mips_pica61_machine = { |
eec2743e TS |
298 | .name = "pica61", |
299 | .desc = "Acer Pica 61", | |
300 | .init = mips_pica61_init, | |
c6945b15 | 301 | .use_scsi = 1, |
c171148c | 302 | }; |
f80f9ec9 AL |
303 | |
304 | static void mips_jazz_machine_init(void) | |
305 | { | |
306 | qemu_register_machine(&mips_magnum_machine); | |
307 | qemu_register_machine(&mips_pica61_machine); | |
308 | } | |
309 | ||
310 | machine_init(mips_jazz_machine_init); |