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1/*
2 * QEMU MIPS Jazz support
3 *
4 * Copyright (c) 2007-2008 Hervé Poussineau
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#include "hw.h"
26#include "mips.h"
b970ea8f 27#include "mips_cpudevs.h"
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28#include "pc.h"
29#include "isa.h"
30#include "fdc.h"
31#include "sysemu.h"
0dfa5ef9 32#include "arch_init.h"
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33#include "boards.h"
34#include "net.h"
1cd3af54 35#include "esp.h"
bba831e8 36#include "mips-bios.h"
ca20cf32 37#include "loader.h"
1d914fa0 38#include "mc146818rtc.h"
b1277b03 39#include "i8254.h"
302fe51b 40#include "pcspk.h"
2446333c 41#include "blockdev.h"
cd3e2409 42#include "sysbus.h"
be20f9e9 43#include "exec-memory.h"
4ce7ff6e 44
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45enum jazz_model_e
46{
47 JAZZ_MAGNUM,
c171148c 48 JAZZ_PICA61,
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49};
50
51static void main_cpu_reset(void *opaque)
52{
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53 MIPSCPU *cpu = opaque;
54
55 cpu_reset(CPU(cpu));
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56}
57
60581b37 58static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
4ce7ff6e 59{
afcea8cb 60 return cpu_inw(0x71);
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61}
62
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63static void rtc_write(void *opaque, target_phys_addr_t addr,
64 uint64_t val, unsigned size)
4ce7ff6e 65{
afcea8cb 66 cpu_outw(0x71, val & 0xff);
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67}
68
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69static const MemoryRegionOps rtc_ops = {
70 .read = rtc_read,
71 .write = rtc_write,
72 .endianness = DEVICE_NATIVE_ENDIAN,
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73};
74
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75static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
76 unsigned size)
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77{
78 /* Nothing to do. That is only to ensure that
79 * the current DMA acknowledge cycle is completed. */
60581b37 80 return 0xff;
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81}
82
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83static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
84 uint64_t val, unsigned size)
85{
86 /* Nothing to do. That is only to ensure that
87 * the current DMA acknowledge cycle is completed. */
88}
c6945b15 89
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90static const MemoryRegionOps dma_dummy_ops = {
91 .read = dma_dummy_read,
92 .write = dma_dummy_write,
93 .endianness = DEVICE_NATIVE_ENDIAN,
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94};
95
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96#define MAGNUM_BIOS_SIZE_MAX 0x7e000
97#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
98
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99static void cpu_request_exit(void *opaque, int irq, int level)
100{
61c56c8c 101 CPUMIPSState *env = cpu_single_env;
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102
103 if (env && level) {
104 cpu_exit(env);
105 }
106}
107
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108static void mips_jazz_init(MemoryRegion *address_space,
109 MemoryRegion *address_space_io,
110 ram_addr_t ram_size,
111 const char *cpu_model,
112 enum jazz_model_e jazz_model)
4ce7ff6e 113{
5cea8590 114 char *filename;
4ce7ff6e 115 int bios_size, n;
6bd8da65 116 MIPSCPU *cpu;
61c56c8c 117 CPUMIPSState *env;
4ce7ff6e 118 qemu_irq *rc4030, *i8259;
c6945b15 119 rc4030_dma *dmas;
68238a9e 120 void* rc4030_opaque;
60581b37 121 MemoryRegion *rtc = g_new(MemoryRegion, 1);
dbff76ac 122 MemoryRegion *i8042 = g_new(MemoryRegion, 1);
60581b37 123 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
a65f56ee 124 NICInfo *nd;
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125 DeviceState *dev;
126 SysBusDevice *sysbus;
48a18b3c 127 ISABus *isa_bus;
64d7e9a4 128 ISADevice *pit;
fd8014e1 129 DriveInfo *fds[MAX_FD];
73d74342 130 qemu_irq esp_reset, dma_enable;
4556bd8b 131 qemu_irq *cpu_exit_irq;
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132 MemoryRegion *ram = g_new(MemoryRegion, 1);
133 MemoryRegion *bios = g_new(MemoryRegion, 1);
134 MemoryRegion *bios2 = g_new(MemoryRegion, 1);
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135
136 /* init CPUs */
137 if (cpu_model == NULL) {
138#ifdef TARGET_MIPS64
139 cpu_model = "R4000";
140#else
141 /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
142 cpu_model = "24Kf";
143#endif
144 }
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145 cpu = cpu_mips_init(cpu_model);
146 if (cpu == NULL) {
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147 fprintf(stderr, "Unable to find CPU definition\n");
148 exit(1);
149 }
6bd8da65 150 env = &cpu->env;
f37f435a 151 qemu_register_reset(main_cpu_reset, cpu);
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152
153 /* allocate RAM */
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154 memory_region_init_ram(ram, "mips_jazz.ram", ram_size);
155 vmstate_register_ram_global(ram);
60581b37 156 memory_region_add_subregion(address_space, 0, ram);
dcac9679 157
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158 memory_region_init_ram(bios, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
159 vmstate_register_ram_global(bios);
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160 memory_region_set_readonly(bios, true);
161 memory_region_init_alias(bios2, "mips_jazz.bios", bios,
162 0, MAGNUM_BIOS_SIZE);
163 memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
164 memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
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165
166 /* load the BIOS image. */
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167 if (bios_name == NULL)
168 bios_name = BIOS_FILENAME;
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169 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
170 if (filename) {
171 bios_size = load_image_targphys(filename, 0xfff00000LL,
172 MAGNUM_BIOS_SIZE);
7267c094 173 g_free(filename);
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174 } else {
175 bios_size = -1;
176 }
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177 if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
178 fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
5cea8590 179 bios_name);
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180 exit(1);
181 }
182
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183 /* Init CPU internal devices */
184 cpu_mips_irq_init_cpu(env);
185 cpu_mips_clock_init(env);
186
187 /* Chipset */
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188 rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas,
189 address_space);
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190 memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
191 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
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192
193 /* ISA devices */
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HP
194 isa_bus = isa_bus_new(NULL, address_space_io);
195 i8259 = i8259_init(isa_bus, env->irq[4]);
196 isa_bus_irqs(isa_bus, i8259);
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197 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
198 DMA_init(0, cpu_exit_irq);
319ba9f5 199 pit = pit_init(isa_bus, 0x40, 0, NULL);
302fe51b 200 pcspk_init(isa_bus, pit);
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201
202 /* ISA IO space at 0x90000000 */
968d683c 203 isa_mmio_init(0x90000000, 0x01000000);
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204 isa_mem_base = 0x11000000;
205
206 /* Video card */
207 switch (jazz_model) {
208 case JAZZ_MAGNUM:
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209 dev = qdev_create(NULL, "sysbus-g364");
210 qdev_init_nofail(dev);
211 sysbus = sysbus_from_qdev(dev);
212 sysbus_mmio_map(sysbus, 0, 0x60080000);
213 sysbus_mmio_map(sysbus, 1, 0x40000000);
214 sysbus_connect_irq(sysbus, 0, rc4030[3]);
215 {
216 /* Simple ROM, so user doesn't have to provide one */
60581b37 217 MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
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218 memory_region_init_ram(rom_mr, "g364fb.rom", 0x80000);
219 vmstate_register_ram_global(rom_mr);
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220 memory_region_set_readonly(rom_mr, true);
221 uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
222 memory_region_add_subregion(address_space, 0x60000000, rom_mr);
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223 rom[0] = 0x10; /* Mips G364 */
224 }
4ce7ff6e 225 break;
c171148c 226 case JAZZ_PICA61:
be20f9e9 227 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
c171148c 228 break;
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229 default:
230 break;
231 }
232
233 /* Network controller */
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234 for (n = 0; n < nb_nics; n++) {
235 nd = &nd_table[n];
236 if (!nd->model)
7267c094 237 nd->model = g_strdup("dp83932");
a65f56ee 238 if (strcmp(nd->model, "dp83932") == 0) {
024e5bb6 239 dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4],
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240 rc4030_opaque, rc4030_dma_memory_rw);
241 break;
c8057f95 242 } else if (is_help_option(nd->model)) {
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243 fprintf(stderr, "qemu: Supported NICs: dp83932\n");
244 exit(1);
245 } else {
246 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
247 exit(1);
248 }
249 }
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250
251 /* SCSI adapter */
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PB
252 esp_init(0x80002000, 0,
253 rc4030_dma_read, rc4030_dma_write, dmas[0],
73d74342 254 rc4030[5], &esp_reset, &dma_enable);
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255
256 /* Floppy */
257 if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
258 fprintf(stderr, "qemu: too many floppy drives\n");
259 exit(1);
260 }
261 for (n = 0; n < MAX_FD; n++) {
fd8014e1 262 fds[n] = drive_get(IF_FLOPPY, 0, n);
4ce7ff6e 263 }
2091ba23 264 fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
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265
266 /* Real time clock */
48a18b3c 267 rtc_init(isa_bus, 1980, NULL);
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268 memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
269 memory_region_add_subregion(address_space, 0x80004000, rtc);
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270
271 /* Keyboard (i8042) */
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272 i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
273 memory_region_add_subregion(address_space, 0x80005000, i8042);
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274
275 /* Serial ports */
2d48377a 276 if (serial_hds[0]) {
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RH
277 serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
278 serial_hds[0], DEVICE_NATIVE_ENDIAN);
2d48377a
BS
279 }
280 if (serial_hds[1]) {
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RH
281 serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
282 serial_hds[1], DEVICE_NATIVE_ENDIAN);
2d48377a 283 }
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284
285 /* Parallel port */
286 if (parallel_hds[0])
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287 parallel_mm_init(address_space, 0x80008000, 0, rc4030[0],
288 parallel_hds[0]);
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289
290 /* Sound card */
291 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
4a0f031d 292 audio_init(isa_bus, NULL);
4ce7ff6e 293
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HP
294 /* NVRAM */
295 dev = qdev_create(NULL, "ds1225y");
296 qdev_init_nofail(dev);
297 sysbus = sysbus_from_qdev(dev);
298 sysbus_mmio_map(sysbus, 0, 0x80009000);
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299
300 /* LED indicator */
b39506e4 301 sysbus_create_simple("jazz-led", 0x8000f000, NULL);
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302}
303
304static
5f072e1f 305void mips_magnum_init(QEMUMachineInitArgs *args)
4ce7ff6e 306{
5f072e1f
EH
307 ram_addr_t ram_size = args->ram_size;
308 const char *cpu_model = args->cpu_model;
c2d0d012
RH
309 mips_jazz_init(get_system_memory(), get_system_io(),
310 ram_size, cpu_model, JAZZ_MAGNUM);
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311}
312
c171148c 313static
5f072e1f 314void mips_pica61_init(QEMUMachineInitArgs *args)
c171148c 315{
5f072e1f
EH
316 ram_addr_t ram_size = args->ram_size;
317 const char *cpu_model = args->cpu_model;
c2d0d012
RH
318 mips_jazz_init(get_system_memory(), get_system_io(),
319 ram_size, cpu_model, JAZZ_PICA61);
c171148c
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320}
321
f80f9ec9 322static QEMUMachine mips_magnum_machine = {
eec2743e
TS
323 .name = "magnum",
324 .desc = "MIPS Magnum",
325 .init = mips_magnum_init,
c6945b15 326 .use_scsi = 1,
4ce7ff6e 327};
c171148c 328
f80f9ec9 329static QEMUMachine mips_pica61_machine = {
eec2743e
TS
330 .name = "pica61",
331 .desc = "Acer Pica 61",
332 .init = mips_pica61_init,
c6945b15 333 .use_scsi = 1,
c171148c 334};
f80f9ec9
AL
335
336static void mips_jazz_machine_init(void)
337{
338 qemu_register_machine(&mips_magnum_machine);
339 qemu_register_machine(&mips_pica61_machine);
340}
341
342machine_init(mips_jazz_machine_init);