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4ce7ff6e AJ |
1 | /* |
2 | * QEMU MIPS Jazz support | |
3 | * | |
4 | * Copyright (c) 2007-2008 Hervé Poussineau | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "hw.h" | |
26 | #include "mips.h" | |
b970ea8f | 27 | #include "mips_cpudevs.h" |
4ce7ff6e AJ |
28 | #include "pc.h" |
29 | #include "isa.h" | |
30 | #include "fdc.h" | |
31 | #include "sysemu.h" | |
32 | #include "audio/audio.h" | |
33 | #include "boards.h" | |
34 | #include "net.h" | |
1cd3af54 | 35 | #include "esp.h" |
bba831e8 | 36 | #include "mips-bios.h" |
ca20cf32 | 37 | #include "loader.h" |
1d914fa0 | 38 | #include "mc146818rtc.h" |
2446333c | 39 | #include "blockdev.h" |
4ce7ff6e | 40 | |
4ce7ff6e AJ |
41 | enum jazz_model_e |
42 | { | |
43 | JAZZ_MAGNUM, | |
c171148c | 44 | JAZZ_PICA61, |
4ce7ff6e AJ |
45 | }; |
46 | ||
47 | static void main_cpu_reset(void *opaque) | |
48 | { | |
49 | CPUState *env = opaque; | |
50 | cpu_reset(env); | |
51 | } | |
52 | ||
c227f099 | 53 | static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr) |
4ce7ff6e | 54 | { |
afcea8cb | 55 | return cpu_inw(0x71); |
4ce7ff6e AJ |
56 | } |
57 | ||
c227f099 | 58 | static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
4ce7ff6e | 59 | { |
afcea8cb | 60 | cpu_outw(0x71, val & 0xff); |
4ce7ff6e AJ |
61 | } |
62 | ||
d60efc6b | 63 | static CPUReadMemoryFunc * const rtc_read[3] = { |
4ce7ff6e AJ |
64 | rtc_readb, |
65 | rtc_readb, | |
66 | rtc_readb, | |
67 | }; | |
68 | ||
d60efc6b | 69 | static CPUWriteMemoryFunc * const rtc_write[3] = { |
4ce7ff6e AJ |
70 | rtc_writeb, |
71 | rtc_writeb, | |
72 | rtc_writeb, | |
73 | }; | |
74 | ||
c227f099 | 75 | static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
c6945b15 AJ |
76 | { |
77 | /* Nothing to do. That is only to ensure that | |
78 | * the current DMA acknowledge cycle is completed. */ | |
79 | } | |
80 | ||
d60efc6b | 81 | static CPUReadMemoryFunc * const dma_dummy_read[3] = { |
c6945b15 AJ |
82 | NULL, |
83 | NULL, | |
84 | NULL, | |
85 | }; | |
86 | ||
d60efc6b | 87 | static CPUWriteMemoryFunc * const dma_dummy_write[3] = { |
c6945b15 AJ |
88 | dma_dummy_writeb, |
89 | dma_dummy_writeb, | |
90 | dma_dummy_writeb, | |
91 | }; | |
92 | ||
4ce7ff6e AJ |
93 | static void audio_init(qemu_irq *pic) |
94 | { | |
95 | struct soundhw *c; | |
96 | int audio_enabled = 0; | |
97 | ||
98 | for (c = soundhw; !audio_enabled && c->name; ++c) { | |
99 | audio_enabled = c->enabled; | |
100 | } | |
101 | ||
102 | if (audio_enabled) { | |
0d9acba8 PB |
103 | for (c = soundhw; c->name; ++c) { |
104 | if (c->enabled) { | |
105 | if (c->isa) { | |
22d83b14 | 106 | c->init.init_isa(pic); |
4ce7ff6e AJ |
107 | } |
108 | } | |
109 | } | |
110 | } | |
111 | } | |
4ce7ff6e | 112 | |
4ce7ff6e AJ |
113 | #define MAGNUM_BIOS_SIZE_MAX 0x7e000 |
114 | #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) | |
115 | ||
4556bd8b BS |
116 | static void cpu_request_exit(void *opaque, int irq, int level) |
117 | { | |
118 | CPUState *env = cpu_single_env; | |
119 | ||
120 | if (env && level) { | |
121 | cpu_exit(env); | |
122 | } | |
123 | } | |
124 | ||
4ce7ff6e | 125 | static |
c227f099 | 126 | void mips_jazz_init (ram_addr_t ram_size, |
3023f332 | 127 | const char *cpu_model, |
4ce7ff6e AJ |
128 | enum jazz_model_e jazz_model) |
129 | { | |
5cea8590 | 130 | char *filename; |
4ce7ff6e AJ |
131 | int bios_size, n; |
132 | CPUState *env; | |
133 | qemu_irq *rc4030, *i8259; | |
c6945b15 | 134 | rc4030_dma *dmas; |
68238a9e | 135 | void* rc4030_opaque; |
c6945b15 | 136 | int s_rtc, s_dma_dummy; |
a65f56ee | 137 | NICInfo *nd; |
4ce7ff6e | 138 | PITState *pit; |
fd8014e1 | 139 | DriveInfo *fds[MAX_FD]; |
73d74342 | 140 | qemu_irq esp_reset, dma_enable; |
4556bd8b | 141 | qemu_irq *cpu_exit_irq; |
c227f099 AL |
142 | ram_addr_t ram_offset; |
143 | ram_addr_t bios_offset; | |
4ce7ff6e AJ |
144 | |
145 | /* init CPUs */ | |
146 | if (cpu_model == NULL) { | |
147 | #ifdef TARGET_MIPS64 | |
148 | cpu_model = "R4000"; | |
149 | #else | |
150 | /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */ | |
151 | cpu_model = "24Kf"; | |
152 | #endif | |
153 | } | |
154 | env = cpu_init(cpu_model); | |
155 | if (!env) { | |
156 | fprintf(stderr, "Unable to find CPU definition\n"); | |
157 | exit(1); | |
158 | } | |
a08d4367 | 159 | qemu_register_reset(main_cpu_reset, env); |
4ce7ff6e AJ |
160 | |
161 | /* allocate RAM */ | |
1724f049 | 162 | ram_offset = qemu_ram_alloc(NULL, "mips_jazz.ram", ram_size); |
dcac9679 PB |
163 | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); |
164 | ||
1724f049 | 165 | bios_offset = qemu_ram_alloc(NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE); |
dcac9679 PB |
166 | cpu_register_physical_memory(0x1fc00000LL, |
167 | MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); | |
168 | cpu_register_physical_memory(0xfff00000LL, | |
169 | MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); | |
4ce7ff6e AJ |
170 | |
171 | /* load the BIOS image. */ | |
c6945b15 AJ |
172 | if (bios_name == NULL) |
173 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
174 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
175 | if (filename) { | |
176 | bios_size = load_image_targphys(filename, 0xfff00000LL, | |
177 | MAGNUM_BIOS_SIZE); | |
178 | qemu_free(filename); | |
179 | } else { | |
180 | bios_size = -1; | |
181 | } | |
4ce7ff6e AJ |
182 | if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) { |
183 | fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n", | |
5cea8590 | 184 | bios_name); |
4ce7ff6e AJ |
185 | exit(1); |
186 | } | |
187 | ||
4ce7ff6e AJ |
188 | /* Init CPU internal devices */ |
189 | cpu_mips_irq_init_cpu(env); | |
190 | cpu_mips_clock_init(env); | |
191 | ||
192 | /* Chipset */ | |
68238a9e | 193 | rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas); |
2507c12a AG |
194 | s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL, |
195 | DEVICE_NATIVE_ENDIAN); | |
c6945b15 | 196 | cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy); |
4ce7ff6e AJ |
197 | |
198 | /* ISA devices */ | |
199 | i8259 = i8259_init(env->irq[4]); | |
5041fccd RT |
200 | isa_bus_new(NULL); |
201 | isa_bus_irqs(i8259); | |
4556bd8b BS |
202 | cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
203 | DMA_init(0, cpu_exit_irq); | |
4ce7ff6e AJ |
204 | pit = pit_init(0x40, i8259[0]); |
205 | pcspk_init(pit); | |
206 | ||
207 | /* ISA IO space at 0x90000000 */ | |
968d683c | 208 | isa_mmio_init(0x90000000, 0x01000000); |
4ce7ff6e AJ |
209 | isa_mem_base = 0x11000000; |
210 | ||
211 | /* Video card */ | |
212 | switch (jazz_model) { | |
213 | case JAZZ_MAGNUM: | |
fbe1b595 | 214 | g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]); |
4ce7ff6e | 215 | break; |
c171148c | 216 | case JAZZ_PICA61: |
fbe1b595 | 217 | isa_vga_mm_init(0x40000000, 0x60000000, 0); |
c171148c | 218 | break; |
4ce7ff6e AJ |
219 | default: |
220 | break; | |
221 | } | |
222 | ||
223 | /* Network controller */ | |
a65f56ee AJ |
224 | for (n = 0; n < nb_nics; n++) { |
225 | nd = &nd_table[n]; | |
226 | if (!nd->model) | |
9203f520 | 227 | nd->model = qemu_strdup("dp83932"); |
a65f56ee AJ |
228 | if (strcmp(nd->model, "dp83932") == 0) { |
229 | dp83932_init(nd, 0x80001000, 2, rc4030[4], | |
230 | rc4030_opaque, rc4030_dma_memory_rw); | |
231 | break; | |
232 | } else if (strcmp(nd->model, "?") == 0) { | |
233 | fprintf(stderr, "qemu: Supported NICs: dp83932\n"); | |
234 | exit(1); | |
235 | } else { | |
236 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model); | |
237 | exit(1); | |
238 | } | |
239 | } | |
4ce7ff6e AJ |
240 | |
241 | /* SCSI adapter */ | |
cfb9de9c PB |
242 | esp_init(0x80002000, 0, |
243 | rc4030_dma_read, rc4030_dma_write, dmas[0], | |
73d74342 | 244 | rc4030[5], &esp_reset, &dma_enable); |
4ce7ff6e AJ |
245 | |
246 | /* Floppy */ | |
247 | if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) { | |
248 | fprintf(stderr, "qemu: too many floppy drives\n"); | |
249 | exit(1); | |
250 | } | |
251 | for (n = 0; n < MAX_FD; n++) { | |
fd8014e1 | 252 | fds[n] = drive_get(IF_FLOPPY, 0, n); |
4ce7ff6e | 253 | } |
2091ba23 | 254 | fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds); |
4ce7ff6e AJ |
255 | |
256 | /* Real time clock */ | |
7d932dfd | 257 | rtc_init(1980, NULL); |
2507c12a AG |
258 | s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL, |
259 | DEVICE_NATIVE_ENDIAN); | |
4ce7ff6e AJ |
260 | cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc); |
261 | ||
262 | /* Keyboard (i8042) */ | |
4efbe58f | 263 | i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1); |
4ce7ff6e AJ |
264 | |
265 | /* Serial ports */ | |
2d48377a BS |
266 | if (serial_hds[0]) { |
267 | #ifdef TARGET_WORDS_BIGENDIAN | |
268 | serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1); | |
269 | #else | |
270 | serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0); | |
271 | #endif | |
272 | } | |
273 | if (serial_hds[1]) { | |
274 | #ifdef TARGET_WORDS_BIGENDIAN | |
275 | serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1); | |
276 | #else | |
277 | serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0); | |
278 | #endif | |
279 | } | |
4ce7ff6e AJ |
280 | |
281 | /* Parallel port */ | |
282 | if (parallel_hds[0]) | |
283 | parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]); | |
284 | ||
285 | /* Sound card */ | |
286 | /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */ | |
4ce7ff6e | 287 | audio_init(i8259); |
4ce7ff6e AJ |
288 | |
289 | /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */ | |
290 | ds1225y_init(0x80009000, "nvram"); | |
291 | ||
292 | /* LED indicator */ | |
3023f332 | 293 | jazz_led_init(0x8000f000); |
4ce7ff6e AJ |
294 | } |
295 | ||
296 | static | |
c227f099 | 297 | void mips_magnum_init (ram_addr_t ram_size, |
3023f332 | 298 | const char *boot_device, |
4ce7ff6e AJ |
299 | const char *kernel_filename, const char *kernel_cmdline, |
300 | const char *initrd_filename, const char *cpu_model) | |
301 | { | |
fbe1b595 | 302 | mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM); |
4ce7ff6e AJ |
303 | } |
304 | ||
c171148c | 305 | static |
c227f099 | 306 | void mips_pica61_init (ram_addr_t ram_size, |
3023f332 | 307 | const char *boot_device, |
c171148c AJ |
308 | const char *kernel_filename, const char *kernel_cmdline, |
309 | const char *initrd_filename, const char *cpu_model) | |
310 | { | |
fbe1b595 | 311 | mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61); |
c171148c AJ |
312 | } |
313 | ||
f80f9ec9 | 314 | static QEMUMachine mips_magnum_machine = { |
eec2743e TS |
315 | .name = "magnum", |
316 | .desc = "MIPS Magnum", | |
317 | .init = mips_magnum_init, | |
c6945b15 | 318 | .use_scsi = 1, |
4ce7ff6e | 319 | }; |
c171148c | 320 | |
f80f9ec9 | 321 | static QEMUMachine mips_pica61_machine = { |
eec2743e TS |
322 | .name = "pica61", |
323 | .desc = "Acer Pica 61", | |
324 | .init = mips_pica61_init, | |
c6945b15 | 325 | .use_scsi = 1, |
c171148c | 326 | }; |
f80f9ec9 AL |
327 | |
328 | static void mips_jazz_machine_init(void) | |
329 | { | |
330 | qemu_register_machine(&mips_magnum_machine); | |
331 | qemu_register_machine(&mips_pica61_machine); | |
332 | } | |
333 | ||
334 | machine_init(mips_jazz_machine_init); |