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f0fc6f8f TS |
1 | /* |
2 | * QEMU/mipssim emulation | |
3 | * | |
4 | * Emulates a very simple machine model similiar to the one use by the | |
5 | * proprietary MIPS emulator. | |
a79ee211 TS |
6 | * |
7 | * Copyright (c) 2007 Thiemo Seufer | |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
10 | * of this software and associated documentation files (the "Software"), to deal | |
11 | * in the Software without restriction, including without limitation the rights | |
12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
13 | * copies of the Software, and to permit persons to whom the Software is | |
14 | * furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice shall be included in | |
17 | * all copies or substantial portions of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
25 | * THE SOFTWARE. | |
f0fc6f8f TS |
26 | */ |
27 | #include "vl.h" | |
28 | ||
29 | #ifdef TARGET_WORDS_BIGENDIAN | |
30 | #define BIOS_FILENAME "mips_bios.bin" | |
31 | #else | |
32 | #define BIOS_FILENAME "mipsel_bios.bin" | |
33 | #endif | |
34 | ||
35 | #ifdef TARGET_MIPS64 | |
36 | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL) | |
37 | #else | |
38 | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU) | |
39 | #endif | |
40 | ||
41 | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) | |
42 | ||
43 | static void load_kernel (CPUState *env) | |
44 | { | |
45 | int64_t entry, kernel_low, kernel_high; | |
46 | long kernel_size; | |
47 | long initrd_size; | |
48 | ram_addr_t initrd_offset; | |
49 | ||
50 | kernel_size = load_elf(env->kernel_filename, VIRT_TO_PHYS_ADDEND, | |
51 | &entry, &kernel_low, &kernel_high); | |
52 | if (kernel_size >= 0) { | |
53 | if ((entry & ~0x7fffffffULL) == 0x80000000) | |
54 | entry = (int32_t)entry; | |
55 | env->PC[env->current_tc] = entry; | |
56 | } else { | |
57 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
58 | env->kernel_filename); | |
59 | exit(1); | |
60 | } | |
61 | ||
62 | /* load initrd */ | |
63 | initrd_size = 0; | |
64 | initrd_offset = 0; | |
65 | if (env->initrd_filename) { | |
66 | initrd_size = get_image_size (env->initrd_filename); | |
67 | if (initrd_size > 0) { | |
68 | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; | |
69 | if (initrd_offset + initrd_size > env->ram_size) { | |
70 | fprintf(stderr, | |
71 | "qemu: memory too small for initial ram disk '%s'\n", | |
72 | env->initrd_filename); | |
73 | exit(1); | |
74 | } | |
75 | initrd_size = load_image(env->initrd_filename, | |
76 | phys_ram_base + initrd_offset); | |
77 | } | |
78 | if (initrd_size == (target_ulong) -1) { | |
79 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
80 | env->initrd_filename); | |
81 | exit(1); | |
82 | } | |
83 | } | |
84 | } | |
85 | ||
86 | static void main_cpu_reset(void *opaque) | |
87 | { | |
88 | CPUState *env = opaque; | |
89 | cpu_reset(env); | |
90 | cpu_mips_register(env, NULL); | |
91 | ||
92 | if (env->kernel_filename) | |
93 | load_kernel (env); | |
94 | } | |
95 | ||
96 | static void | |
6ac0e82d | 97 | mips_mipssim_init (int ram_size, int vga_ram_size, const char *boot_device, |
f0fc6f8f TS |
98 | DisplayState *ds, const char **fd_filename, int snapshot, |
99 | const char *kernel_filename, const char *kernel_cmdline, | |
100 | const char *initrd_filename, const char *cpu_model) | |
101 | { | |
102 | char buf[1024]; | |
103 | unsigned long bios_offset; | |
104 | CPUState *env; | |
b5334159 | 105 | int bios_size; |
f0fc6f8f TS |
106 | mips_def_t *def; |
107 | ||
108 | /* Init CPUs. */ | |
109 | if (cpu_model == NULL) { | |
110 | #ifdef TARGET_MIPS64 | |
111 | cpu_model = "5Kf"; | |
112 | #else | |
113 | cpu_model = "24Kf"; | |
114 | #endif | |
115 | } | |
116 | if (mips_find_by_name(cpu_model, &def) != 0) | |
117 | def = NULL; | |
118 | env = cpu_init(); | |
119 | cpu_mips_register(env, def); | |
120 | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | |
121 | qemu_register_reset(main_cpu_reset, env); | |
122 | ||
123 | /* Allocate RAM. */ | |
124 | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); | |
125 | ||
f0fc6f8f | 126 | /* Load a BIOS / boot exception handler image. */ |
b5334159 | 127 | bios_offset = ram_size + vga_ram_size; |
f0fc6f8f TS |
128 | if (bios_name == NULL) |
129 | bios_name = BIOS_FILENAME; | |
130 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
b5334159 TS |
131 | bios_size = load_image(buf, phys_ram_base + bios_offset); |
132 | if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) { | |
f0fc6f8f TS |
133 | /* Bail out if we have neither a kernel image nor boot vector code. */ |
134 | fprintf(stderr, | |
135 | "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n", | |
136 | buf); | |
137 | exit(1); | |
138 | } else { | |
b5334159 | 139 | /* Map the BIOS / boot exception handler. */ |
f0fc6f8f | 140 | cpu_register_physical_memory(0x1fc00000LL, |
b5334159 TS |
141 | bios_size, bios_offset | IO_MEM_ROM); |
142 | /* We have a boot vector start address. */ | |
143 | env->PC[env->current_tc] = (target_long)(int32_t)0xbfc00000; | |
f0fc6f8f TS |
144 | } |
145 | ||
146 | if (kernel_filename) { | |
147 | env->ram_size = ram_size; | |
148 | env->kernel_filename = kernel_filename; | |
149 | env->kernel_cmdline = kernel_cmdline; | |
150 | env->initrd_filename = initrd_filename; | |
151 | load_kernel(env); | |
152 | } | |
153 | ||
154 | /* Init CPU internal devices. */ | |
155 | cpu_mips_irq_init_cpu(env); | |
156 | cpu_mips_clock_init(env); | |
157 | cpu_mips_irqctrl_init(); | |
158 | ||
159 | /* Register 64 KB of ISA IO space at 0x1fd00000. */ | |
160 | isa_mmio_init(0x1fd00000, 0x00010000); | |
161 | ||
162 | /* A single 16450 sits at offset 0x3f8. It is attached to | |
163 | MIPS CPU INT2, which is interrupt 4. */ | |
164 | if (serial_hds[0]) | |
165 | serial_init(0x3f8, env->irq[4], serial_hds[0]); | |
166 | ||
167 | if (nd_table[0].vlan) { | |
168 | if (nd_table[0].model == NULL | |
169 | || strcmp(nd_table[0].model, "mipsnet") == 0) { | |
170 | /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */ | |
171 | mipsnet_init(0x4200, env->irq[2], &nd_table[0]); | |
172 | } else if (strcmp(nd_table[0].model, "?") == 0) { | |
173 | fprintf(stderr, "qemu: Supported NICs: mipsnet\n"); | |
174 | exit (1); | |
175 | } else { | |
176 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | |
177 | exit (1); | |
178 | } | |
179 | } | |
180 | } | |
181 | ||
182 | QEMUMachine mips_mipssim_machine = { | |
183 | "mipssim", | |
184 | "MIPS MIPSsim platform", | |
185 | mips_mipssim_init, | |
186 | }; |