]>
Commit | Line | Data |
---|---|---|
e16fe40c TS |
1 | /* |
2 | * QEMU/MIPS pseudo-board | |
3 | * | |
4 | * emulates a simple machine with ISA-like bus. | |
5 | * ISA IO space mapped to the 0x14000000 (PHYS) and | |
6 | * ISA memory at the 0x10000000 (PHYS, 16Mb in size). | |
7 | * All peripherial devices are attached to this "bus" with | |
8 | * the standard PC ISA addresses. | |
9 | */ | |
6af0bf9c FB |
10 | #include "vl.h" |
11 | ||
2909b29a | 12 | #ifdef TARGET_WORDS_BIGENDIAN |
6af0bf9c | 13 | #define BIOS_FILENAME "mips_bios.bin" |
f7bcd4e3 TS |
14 | #else |
15 | #define BIOS_FILENAME "mipsel_bios.bin" | |
16 | #endif | |
44cbbf18 | 17 | |
c6ee607c | 18 | #define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fffffff) |
6af0bf9c | 19 | |
5dc4b744 | 20 | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
66a93e0f | 21 | |
58126404 PB |
22 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
23 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
24 | static const int ide_irq[2] = { 14, 15 }; | |
25 | ||
eddbd288 TS |
26 | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
27 | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
28 | ||
6af0bf9c FB |
29 | extern FILE *logfile; |
30 | ||
e16fe40c | 31 | static PITState *pit; /* PIT i8254 */ |
697584ab | 32 | |
e16fe40c | 33 | /*i8254 PIT is attached to the IRQ0 at PIC i8259 */ |
6af0bf9c | 34 | |
7df526e3 TS |
35 | static struct _loaderparams { |
36 | int ram_size; | |
37 | const char *kernel_filename; | |
38 | const char *kernel_cmdline; | |
39 | const char *initrd_filename; | |
40 | } loaderparams; | |
41 | ||
6ae81775 TS |
42 | static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, |
43 | uint32_t val) | |
44 | { | |
45 | if ((addr & 0xffff) == 0 && val == 42) | |
46 | qemu_system_reset_request (); | |
47 | else if ((addr & 0xffff) == 4 && val == 42) | |
48 | qemu_system_shutdown_request (); | |
49 | } | |
50 | ||
51 | static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) | |
52 | { | |
53 | return 0; | |
54 | } | |
55 | ||
56 | static CPUWriteMemoryFunc *mips_qemu_write[] = { | |
57 | &mips_qemu_writel, | |
58 | &mips_qemu_writel, | |
59 | &mips_qemu_writel, | |
60 | }; | |
61 | ||
62 | static CPUReadMemoryFunc *mips_qemu_read[] = { | |
63 | &mips_qemu_readl, | |
64 | &mips_qemu_readl, | |
65 | &mips_qemu_readl, | |
66 | }; | |
67 | ||
68 | static int mips_qemu_iomemtype = 0; | |
69 | ||
7df526e3 | 70 | static void load_kernel (CPUState *env) |
6ae81775 | 71 | { |
74287114 | 72 | int64_t entry, kernel_low, kernel_high; |
6ae81775 | 73 | long kernel_size, initrd_size; |
74287114 | 74 | ram_addr_t initrd_offset; |
6ae81775 | 75 | |
7df526e3 | 76 | kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, |
74287114 | 77 | &entry, &kernel_low, &kernel_high); |
c570fd16 TS |
78 | if (kernel_size >= 0) { |
79 | if ((entry & ~0x7fffffffULL) == 0x80000000) | |
5dc4b744 | 80 | entry = (int32_t)entry; |
ead9360e | 81 | env->PC[env->current_tc] = entry; |
c570fd16 | 82 | } else { |
9042c0e2 | 83 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
7df526e3 | 84 | loaderparams.kernel_filename); |
9042c0e2 | 85 | exit(1); |
6ae81775 TS |
86 | } |
87 | ||
88 | /* load initrd */ | |
89 | initrd_size = 0; | |
74287114 | 90 | initrd_offset = 0; |
7df526e3 TS |
91 | if (loaderparams.initrd_filename) { |
92 | initrd_size = get_image_size (loaderparams.initrd_filename); | |
74287114 TS |
93 | if (initrd_size > 0) { |
94 | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; | |
95 | if (initrd_offset + initrd_size > ram_size) { | |
96 | fprintf(stderr, | |
97 | "qemu: memory too small for initial ram disk '%s'\n", | |
7df526e3 | 98 | loaderparams.initrd_filename); |
74287114 TS |
99 | exit(1); |
100 | } | |
7df526e3 | 101 | initrd_size = load_image(loaderparams.initrd_filename, |
74287114 TS |
102 | phys_ram_base + initrd_offset); |
103 | } | |
6ae81775 TS |
104 | if (initrd_size == (target_ulong) -1) { |
105 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
7df526e3 | 106 | loaderparams.initrd_filename); |
6ae81775 TS |
107 | exit(1); |
108 | } | |
109 | } | |
110 | ||
111 | /* Store command line. */ | |
112 | if (initrd_size > 0) { | |
113 | int ret; | |
114 | ret = sprintf(phys_ram_base + (16 << 20) - 256, | |
3594c774 | 115 | "rd_start=0x" TARGET_FMT_lx " rd_size=%li ", |
74287114 | 116 | PHYS_TO_VIRT((uint32_t)initrd_offset), |
6ae81775 | 117 | initrd_size); |
7df526e3 TS |
118 | strcpy (phys_ram_base + (16 << 20) - 256 + ret, |
119 | loaderparams.kernel_cmdline); | |
6ae81775 TS |
120 | } |
121 | else { | |
7df526e3 TS |
122 | strcpy (phys_ram_base + (16 << 20) - 256, |
123 | loaderparams.kernel_cmdline); | |
6ae81775 TS |
124 | } |
125 | ||
44cbbf18 TS |
126 | *(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); |
127 | *(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); | |
6ae81775 TS |
128 | } |
129 | ||
130 | static void main_cpu_reset(void *opaque) | |
131 | { | |
132 | CPUState *env = opaque; | |
133 | cpu_reset(env); | |
134 | ||
7df526e3 TS |
135 | if (loaderparams.kernel_filename) |
136 | load_kernel (env); | |
6ae81775 | 137 | } |
66a93e0f | 138 | |
70705261 | 139 | static |
6ac0e82d | 140 | void mips_r4k_init (int ram_size, int vga_ram_size, const char *boot_device, |
6af0bf9c FB |
141 | DisplayState *ds, const char **fd_filename, int snapshot, |
142 | const char *kernel_filename, const char *kernel_cmdline, | |
94fc95cd | 143 | const char *initrd_filename, const char *cpu_model) |
6af0bf9c FB |
144 | { |
145 | char buf[1024]; | |
6af0bf9c | 146 | unsigned long bios_offset; |
f7bcd4e3 | 147 | int bios_size; |
c68ea704 | 148 | CPUState *env; |
153a08db | 149 | RTCState *rtc_state; |
58126404 | 150 | int i; |
d537cf6c | 151 | qemu_irq *i8259; |
c68ea704 | 152 | |
33d68b5f TS |
153 | /* init CPUs */ |
154 | if (cpu_model == NULL) { | |
60aa19ab | 155 | #ifdef TARGET_MIPS64 |
33d68b5f TS |
156 | cpu_model = "R4000"; |
157 | #else | |
1c32f43e | 158 | cpu_model = "24Kf"; |
33d68b5f TS |
159 | #endif |
160 | } | |
aaed909a FB |
161 | env = cpu_init(cpu_model); |
162 | if (!env) { | |
163 | fprintf(stderr, "Unable to find CPU definition\n"); | |
164 | exit(1); | |
165 | } | |
c68ea704 | 166 | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
6ae81775 | 167 | qemu_register_reset(main_cpu_reset, env); |
c68ea704 | 168 | |
6af0bf9c FB |
169 | /* allocate RAM */ |
170 | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); | |
66a93e0f | 171 | |
6ae81775 TS |
172 | if (!mips_qemu_iomemtype) { |
173 | mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read, | |
33d68b5f | 174 | mips_qemu_write, NULL); |
6ae81775 TS |
175 | } |
176 | cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); | |
177 | ||
66a93e0f FB |
178 | /* Try to load a BIOS image. If this fails, we continue regardless, |
179 | but initialize the hardware ourselves. When a kernel gets | |
180 | preloaded we also initialize the hardware, since the BIOS wasn't | |
181 | run. */ | |
6af0bf9c | 182 | bios_offset = ram_size + vga_ram_size; |
1192dad8 JM |
183 | if (bios_name == NULL) |
184 | bios_name = BIOS_FILENAME; | |
185 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
f7bcd4e3 | 186 | bios_size = load_image(buf, phys_ram_base + bios_offset); |
2909b29a | 187 | if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { |
44cbbf18 | 188 | cpu_register_physical_memory(0x1fc00000, |
66a93e0f | 189 | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
66a93e0f FB |
190 | } else { |
191 | /* not fatal */ | |
192 | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", | |
193 | buf); | |
6af0bf9c | 194 | } |
66a93e0f | 195 | |
66a93e0f | 196 | if (kernel_filename) { |
7df526e3 TS |
197 | loaderparams.ram_size = ram_size; |
198 | loaderparams.kernel_filename = kernel_filename; | |
199 | loaderparams.kernel_cmdline = kernel_cmdline; | |
200 | loaderparams.initrd_filename = initrd_filename; | |
201 | load_kernel (env); | |
6af0bf9c | 202 | } |
6af0bf9c | 203 | |
e16fe40c | 204 | /* Init CPU internal devices */ |
d537cf6c | 205 | cpu_mips_irq_init_cpu(env); |
c68ea704 | 206 | cpu_mips_clock_init(env); |
6af0bf9c FB |
207 | cpu_mips_irqctrl_init(); |
208 | ||
d537cf6c PB |
209 | /* The PIC is attached to the MIPS CPU INT0 pin */ |
210 | i8259 = i8259_init(env->irq[2]); | |
211 | ||
212 | rtc_state = rtc_init(0x70, i8259[8]); | |
afdfa781 | 213 | |
0699b548 | 214 | /* Register 64 KB of ISA IO space at 0x14000000 */ |
aef445bd | 215 | isa_mmio_init(0x14000000, 0x00010000); |
0699b548 FB |
216 | isa_mem_base = 0x10000000; |
217 | ||
d537cf6c | 218 | pit = pit_init(0x40, i8259[0]); |
afdfa781 | 219 | |
eddbd288 TS |
220 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
221 | if (serial_hds[i]) { | |
d537cf6c | 222 | serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]); |
eddbd288 TS |
223 | } |
224 | } | |
225 | ||
5fafdf24 | 226 | isa_vga_init(ds, phys_ram_base + ram_size, ram_size, |
89b6b508 | 227 | vga_ram_size); |
9827e95c | 228 | |
a41b2ff2 PB |
229 | if (nd_table[0].vlan) { |
230 | if (nd_table[0].model == NULL | |
231 | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { | |
d537cf6c | 232 | isa_ne2000_init(0x300, i8259[9], &nd_table[0]); |
c4a7060c BS |
233 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
234 | fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n"); | |
235 | exit (1); | |
a41b2ff2 PB |
236 | } else { |
237 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | |
238 | exit (1); | |
239 | } | |
240 | } | |
58126404 PB |
241 | |
242 | for(i = 0; i < 2; i++) | |
d537cf6c | 243 | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
58126404 | 244 | bs_table[2 * i], bs_table[2 * i + 1]); |
70705261 | 245 | |
d537cf6c | 246 | i8042_init(i8259[1], i8259[12], 0x60); |
9542611a | 247 | ds1225y_init(0x9000, "nvram"); |
6af0bf9c FB |
248 | } |
249 | ||
250 | QEMUMachine mips_machine = { | |
251 | "mips", | |
252 | "mips r4k platform", | |
253 | mips_r4k_init, | |
254 | }; |