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Commit | Line | Data |
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6af0bf9c FB |
1 | #include "vl.h" |
2 | ||
6af0bf9c FB |
3 | #define BIOS_FILENAME "mips_bios.bin" |
4 | //#define BIOS_FILENAME "system.bin" | |
5 | #define KERNEL_LOAD_ADDR 0x80010000 | |
6 | #define INITRD_LOAD_ADDR 0x80800000 | |
7 | ||
6af0bf9c FB |
8 | extern FILE *logfile; |
9 | ||
697584ab FB |
10 | static PITState *pit; |
11 | ||
73133662 | 12 | static void pic_irq_request(void *opaque, int level) |
6af0bf9c | 13 | { |
c68ea704 | 14 | CPUState *env = first_cpu; |
73133662 | 15 | if (level) { |
c68ea704 FB |
16 | env->CP0_Cause |= 0x00000400; |
17 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
6af0bf9c | 18 | } else { |
c68ea704 FB |
19 | env->CP0_Cause &= ~0x00000400; |
20 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
6af0bf9c | 21 | } |
6af0bf9c FB |
22 | } |
23 | ||
24 | void cpu_mips_irqctrl_init (void) | |
25 | { | |
26 | } | |
27 | ||
6af0bf9c FB |
28 | uint32_t cpu_mips_get_random (CPUState *env) |
29 | { | |
899abcf5 | 30 | uint32_t now = qemu_get_clock(vm_clock); |
6af0bf9c | 31 | |
899abcf5 | 32 | return now % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired; |
6af0bf9c FB |
33 | } |
34 | ||
899abcf5 | 35 | /* MIPS R4K timer */ |
6af0bf9c FB |
36 | uint32_t cpu_mips_get_count (CPUState *env) |
37 | { | |
38 | return env->CP0_Count + | |
39 | (uint32_t)muldiv64(qemu_get_clock(vm_clock), | |
40 | 100 * 1000 * 1000, ticks_per_sec); | |
41 | } | |
42 | ||
43 | static void cpu_mips_update_count (CPUState *env, uint32_t count, | |
44 | uint32_t compare) | |
45 | { | |
46 | uint64_t now, next; | |
47 | uint32_t tmp; | |
48 | ||
49 | tmp = count; | |
50 | if (count == compare) | |
51 | tmp++; | |
52 | now = qemu_get_clock(vm_clock); | |
53 | next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); | |
54 | if (next == now) | |
55 | next++; | |
56 | #if 1 | |
57 | if (logfile) { | |
58 | fprintf(logfile, "%s: 0x%08llx %08x %08x => 0x%08llx\n", | |
59 | __func__, now, count, compare, next - now); | |
60 | } | |
61 | #endif | |
62 | /* Store new count and compare registers */ | |
63 | env->CP0_Compare = compare; | |
64 | env->CP0_Count = | |
65 | count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); | |
66 | /* Adjust timer */ | |
67 | qemu_mod_timer(env->timer, next); | |
68 | } | |
69 | ||
70 | void cpu_mips_store_count (CPUState *env, uint32_t value) | |
71 | { | |
72 | cpu_mips_update_count(env, value, env->CP0_Compare); | |
73 | } | |
74 | ||
75 | void cpu_mips_store_compare (CPUState *env, uint32_t value) | |
76 | { | |
77 | cpu_mips_update_count(env, cpu_mips_get_count(env), value); | |
c68ea704 FB |
78 | env->CP0_Cause &= ~0x00008000; |
79 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
6af0bf9c FB |
80 | } |
81 | ||
82 | static void mips_timer_cb (void *opaque) | |
83 | { | |
84 | CPUState *env; | |
85 | ||
86 | env = opaque; | |
87 | #if 1 | |
88 | if (logfile) { | |
89 | fprintf(logfile, "%s\n", __func__); | |
90 | } | |
91 | #endif | |
92 | cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); | |
c68ea704 FB |
93 | env->CP0_Cause |= 0x00008000; |
94 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
6af0bf9c FB |
95 | } |
96 | ||
97 | void cpu_mips_clock_init (CPUState *env) | |
98 | { | |
99 | env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); | |
100 | env->CP0_Compare = 0; | |
101 | cpu_mips_update_count(env, 1, 0); | |
102 | } | |
103 | ||
104 | static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) | |
105 | { | |
106 | if (logfile) | |
107 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); | |
108 | cpu_outb(NULL, addr & 0xffff, value); | |
109 | } | |
110 | ||
111 | static uint32_t io_readb (void *opaque, target_phys_addr_t addr) | |
112 | { | |
113 | uint32_t ret = cpu_inb(NULL, addr & 0xffff); | |
114 | if (logfile) | |
115 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); | |
116 | return ret; | |
117 | } | |
118 | ||
119 | static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value) | |
120 | { | |
121 | if (logfile) | |
122 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); | |
123 | #ifdef TARGET_WORDS_BIGENDIAN | |
124 | value = bswap16(value); | |
125 | #endif | |
126 | cpu_outw(NULL, addr & 0xffff, value); | |
127 | } | |
128 | ||
129 | static uint32_t io_readw (void *opaque, target_phys_addr_t addr) | |
130 | { | |
131 | uint32_t ret = cpu_inw(NULL, addr & 0xffff); | |
132 | #ifdef TARGET_WORDS_BIGENDIAN | |
133 | ret = bswap16(ret); | |
134 | #endif | |
135 | if (logfile) | |
136 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); | |
137 | return ret; | |
138 | } | |
139 | ||
140 | static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value) | |
141 | { | |
142 | if (logfile) | |
143 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); | |
144 | #ifdef TARGET_WORDS_BIGENDIAN | |
145 | value = bswap32(value); | |
146 | #endif | |
147 | cpu_outl(NULL, addr & 0xffff, value); | |
148 | } | |
149 | ||
150 | static uint32_t io_readl (void *opaque, target_phys_addr_t addr) | |
151 | { | |
152 | uint32_t ret = cpu_inl(NULL, addr & 0xffff); | |
153 | ||
154 | #ifdef TARGET_WORDS_BIGENDIAN | |
155 | ret = bswap32(ret); | |
156 | #endif | |
157 | if (logfile) | |
158 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); | |
159 | return ret; | |
160 | } | |
161 | ||
162 | CPUWriteMemoryFunc *io_write[] = { | |
163 | &io_writeb, | |
164 | &io_writew, | |
165 | &io_writel, | |
166 | }; | |
167 | ||
168 | CPUReadMemoryFunc *io_read[] = { | |
169 | &io_readb, | |
170 | &io_readw, | |
171 | &io_readl, | |
172 | }; | |
173 | ||
174 | void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, | |
175 | DisplayState *ds, const char **fd_filename, int snapshot, | |
176 | const char *kernel_filename, const char *kernel_cmdline, | |
177 | const char *initrd_filename) | |
178 | { | |
179 | char buf[1024]; | |
180 | target_ulong kernel_base, kernel_size, initrd_base, initrd_size; | |
181 | unsigned long bios_offset; | |
182 | int io_memory; | |
183 | int linux_boot; | |
184 | int ret; | |
c68ea704 | 185 | CPUState *env; |
6af0bf9c FB |
186 | |
187 | printf("%s: start\n", __func__); | |
188 | linux_boot = (kernel_filename != NULL); | |
c68ea704 FB |
189 | |
190 | env = cpu_init(); | |
191 | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | |
192 | ||
6af0bf9c FB |
193 | /* allocate RAM */ |
194 | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); | |
195 | bios_offset = ram_size + vga_ram_size; | |
196 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); | |
197 | printf("%s: load BIOS '%s' size %d\n", __func__, buf, BIOS_SIZE); | |
198 | ret = load_image(buf, phys_ram_base + bios_offset); | |
199 | if (ret != BIOS_SIZE) { | |
200 | fprintf(stderr, "qemu: could not load MIPS bios '%s'\n", buf); | |
201 | exit(1); | |
202 | } | |
203 | cpu_register_physical_memory((uint32_t)(0x1fc00000), | |
204 | BIOS_SIZE, bios_offset | IO_MEM_ROM); | |
205 | #if 0 | |
206 | memcpy(phys_ram_base + 0x10000, phys_ram_base + bios_offset, BIOS_SIZE); | |
c68ea704 | 207 | env->PC = 0x80010004; |
6af0bf9c | 208 | #else |
c68ea704 | 209 | env->PC = 0xBFC00004; |
6af0bf9c FB |
210 | #endif |
211 | if (linux_boot) { | |
212 | kernel_base = KERNEL_LOAD_ADDR; | |
213 | /* now we can load the kernel */ | |
de12d636 FB |
214 | kernel_size = load_image(kernel_filename, |
215 | phys_ram_base + (kernel_base - 0x80000000)); | |
216 | if (kernel_size == (target_ulong) -1) { | |
6af0bf9c FB |
217 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
218 | kernel_filename); | |
219 | exit(1); | |
220 | } | |
221 | /* load initrd */ | |
222 | if (initrd_filename) { | |
223 | initrd_base = INITRD_LOAD_ADDR; | |
224 | initrd_size = load_image(initrd_filename, | |
225 | phys_ram_base + initrd_base); | |
de12d636 | 226 | if (initrd_size == (target_ulong) -1) { |
6af0bf9c FB |
227 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
228 | initrd_filename); | |
229 | exit(1); | |
230 | } | |
231 | } else { | |
232 | initrd_base = 0; | |
233 | initrd_size = 0; | |
234 | } | |
c68ea704 | 235 | env->PC = KERNEL_LOAD_ADDR; |
6af0bf9c FB |
236 | } else { |
237 | kernel_base = 0; | |
238 | kernel_size = 0; | |
239 | initrd_base = 0; | |
240 | initrd_size = 0; | |
241 | } | |
6af0bf9c FB |
242 | |
243 | /* Init internal devices */ | |
c68ea704 | 244 | cpu_mips_clock_init(env); |
6af0bf9c FB |
245 | cpu_mips_irqctrl_init(); |
246 | ||
0699b548 | 247 | /* Register 64 KB of ISA IO space at 0x14000000 */ |
6af0bf9c | 248 | io_memory = cpu_register_io_memory(0, io_read, io_write, NULL); |
0699b548 FB |
249 | cpu_register_physical_memory(0x14000000, 0x00010000, io_memory); |
250 | isa_mem_base = 0x10000000; | |
251 | ||
c68ea704 | 252 | isa_pic = pic_init(pic_irq_request, env); |
697584ab | 253 | pit = pit_init(0x40, 0); |
e5d13e2f | 254 | serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); |
0699b548 | 255 | vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size, |
d5295253 | 256 | vga_ram_size, 0, 0); |
9827e95c FB |
257 | |
258 | isa_ne2000_init(0x300, 9, &nd_table[0]); | |
6af0bf9c FB |
259 | } |
260 | ||
261 | QEMUMachine mips_machine = { | |
262 | "mips", | |
263 | "mips r4k platform", | |
264 | mips_r4k_init, | |
265 | }; |