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Commit | Line | Data |
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e16fe40c TS |
1 | /* |
2 | * QEMU/MIPS pseudo-board | |
3 | * | |
4 | * emulates a simple machine with ISA-like bus. | |
5 | * ISA IO space mapped to the 0x14000000 (PHYS) and | |
6 | * ISA memory at the 0x10000000 (PHYS, 16Mb in size). | |
7 | * All peripherial devices are attached to this "bus" with | |
8 | * the standard PC ISA addresses. | |
9 | */ | |
87ecb68b PB |
10 | #include "hw.h" |
11 | #include "mips.h" | |
12 | #include "pc.h" | |
13 | #include "isa.h" | |
14 | #include "net.h" | |
15 | #include "sysemu.h" | |
16 | #include "boards.h" | |
b305b5ba | 17 | #include "flash.h" |
3b3fb322 | 18 | #include "qemu-log.h" |
bba831e8 | 19 | #include "mips-bios.h" |
ec82026c | 20 | #include "ide.h" |
ca20cf32 BS |
21 | #include "loader.h" |
22 | #include "elf.h" | |
44cbbf18 | 23 | |
e4bcb14c TS |
24 | #define MAX_IDE_BUS 2 |
25 | ||
58126404 PB |
26 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
27 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
28 | static const int ide_irq[2] = { 14, 15 }; | |
29 | ||
e16fe40c | 30 | static PITState *pit; /* PIT i8254 */ |
697584ab | 31 | |
1b66074b | 32 | /* i8254 PIT is attached to the IRQ0 at PIC i8259 */ |
6af0bf9c | 33 | |
7df526e3 TS |
34 | static struct _loaderparams { |
35 | int ram_size; | |
36 | const char *kernel_filename; | |
37 | const char *kernel_cmdline; | |
38 | const char *initrd_filename; | |
39 | } loaderparams; | |
40 | ||
c227f099 | 41 | static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, |
6ae81775 TS |
42 | uint32_t val) |
43 | { | |
44 | if ((addr & 0xffff) == 0 && val == 42) | |
45 | qemu_system_reset_request (); | |
46 | else if ((addr & 0xffff) == 4 && val == 42) | |
47 | qemu_system_shutdown_request (); | |
48 | } | |
49 | ||
c227f099 | 50 | static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) |
6ae81775 TS |
51 | { |
52 | return 0; | |
53 | } | |
54 | ||
d60efc6b | 55 | static CPUWriteMemoryFunc * const mips_qemu_write[] = { |
6ae81775 TS |
56 | &mips_qemu_writel, |
57 | &mips_qemu_writel, | |
58 | &mips_qemu_writel, | |
59 | }; | |
60 | ||
d60efc6b | 61 | static CPUReadMemoryFunc * const mips_qemu_read[] = { |
6ae81775 TS |
62 | &mips_qemu_readl, |
63 | &mips_qemu_readl, | |
64 | &mips_qemu_readl, | |
65 | }; | |
66 | ||
67 | static int mips_qemu_iomemtype = 0; | |
68 | ||
e16ad5b0 AJ |
69 | typedef struct ResetData { |
70 | CPUState *env; | |
71 | uint64_t vector; | |
72 | } ResetData; | |
73 | ||
74 | static int64_t load_kernel(void) | |
6ae81775 | 75 | { |
409dbce5 | 76 | int64_t entry, kernel_high; |
e90e795e | 77 | long kernel_size, initrd_size, params_size; |
c227f099 | 78 | ram_addr_t initrd_offset; |
e90e795e | 79 | uint32_t *params_buf; |
ca20cf32 | 80 | int big_endian; |
6ae81775 | 81 | |
ca20cf32 BS |
82 | #ifdef TARGET_WORDS_BIGENDIAN |
83 | big_endian = 1; | |
84 | #else | |
85 | big_endian = 0; | |
86 | #endif | |
409dbce5 AJ |
87 | kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, |
88 | NULL, (uint64_t *)&entry, NULL, | |
89 | (uint64_t *)&kernel_high, big_endian, | |
90 | ELF_MACHINE, 1); | |
c570fd16 TS |
91 | if (kernel_size >= 0) { |
92 | if ((entry & ~0x7fffffffULL) == 0x80000000) | |
5dc4b744 | 93 | entry = (int32_t)entry; |
c570fd16 | 94 | } else { |
9042c0e2 | 95 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
7df526e3 | 96 | loaderparams.kernel_filename); |
9042c0e2 | 97 | exit(1); |
6ae81775 TS |
98 | } |
99 | ||
100 | /* load initrd */ | |
101 | initrd_size = 0; | |
74287114 | 102 | initrd_offset = 0; |
7df526e3 TS |
103 | if (loaderparams.initrd_filename) { |
104 | initrd_size = get_image_size (loaderparams.initrd_filename); | |
74287114 TS |
105 | if (initrd_size > 0) { |
106 | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; | |
107 | if (initrd_offset + initrd_size > ram_size) { | |
108 | fprintf(stderr, | |
109 | "qemu: memory too small for initial ram disk '%s'\n", | |
7df526e3 | 110 | loaderparams.initrd_filename); |
74287114 TS |
111 | exit(1); |
112 | } | |
dcac9679 PB |
113 | initrd_size = load_image_targphys(loaderparams.initrd_filename, |
114 | initrd_offset, | |
115 | ram_size - initrd_offset); | |
74287114 | 116 | } |
6ae81775 TS |
117 | if (initrd_size == (target_ulong) -1) { |
118 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
7df526e3 | 119 | loaderparams.initrd_filename); |
6ae81775 TS |
120 | exit(1); |
121 | } | |
122 | } | |
123 | ||
124 | /* Store command line. */ | |
e90e795e AJ |
125 | params_size = 264; |
126 | params_buf = qemu_malloc(params_size); | |
127 | ||
128 | params_buf[0] = tswap32(ram_size); | |
129 | params_buf[1] = tswap32(0x12345678); | |
130 | ||
6ae81775 | 131 | if (initrd_size > 0) { |
409dbce5 AJ |
132 | snprintf((char *)params_buf + 8, 256, "rd_start=0x%" PRIx64 " rd_size=%li %s", |
133 | cpu_mips_phys_to_kseg0(NULL, initrd_offset), | |
e90e795e | 134 | initrd_size, loaderparams.kernel_cmdline); |
d7585251 | 135 | } else { |
e90e795e | 136 | snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline); |
6ae81775 TS |
137 | } |
138 | ||
e90e795e AJ |
139 | rom_add_blob_fixed("params", params_buf, params_size, |
140 | (16 << 20) - 264); | |
141 | ||
e16ad5b0 | 142 | return entry; |
6ae81775 TS |
143 | } |
144 | ||
145 | static void main_cpu_reset(void *opaque) | |
146 | { | |
e16ad5b0 AJ |
147 | ResetData *s = (ResetData *)opaque; |
148 | CPUState *env = s->env; | |
6ae81775 | 149 | |
e16ad5b0 AJ |
150 | cpu_reset(env); |
151 | env->active_tc.PC = s->vector; | |
6ae81775 | 152 | } |
66a93e0f | 153 | |
b305b5ba | 154 | static const int sector_len = 32 * 1024; |
70705261 | 155 | static |
c227f099 | 156 | void mips_r4k_init (ram_addr_t ram_size, |
3023f332 | 157 | const char *boot_device, |
6af0bf9c | 158 | const char *kernel_filename, const char *kernel_cmdline, |
94fc95cd | 159 | const char *initrd_filename, const char *cpu_model) |
6af0bf9c | 160 | { |
5cea8590 | 161 | char *filename; |
c227f099 AL |
162 | ram_addr_t ram_offset; |
163 | ram_addr_t bios_offset; | |
f7bcd4e3 | 164 | int bios_size; |
c68ea704 | 165 | CPUState *env; |
e16ad5b0 | 166 | ResetData *reset_info; |
153a08db | 167 | RTCState *rtc_state; |
58126404 | 168 | int i; |
d537cf6c | 169 | qemu_irq *i8259; |
f455e98c | 170 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
751c6a17 | 171 | DriveInfo *dinfo; |
c68ea704 | 172 | |
33d68b5f TS |
173 | /* init CPUs */ |
174 | if (cpu_model == NULL) { | |
60aa19ab | 175 | #ifdef TARGET_MIPS64 |
33d68b5f TS |
176 | cpu_model = "R4000"; |
177 | #else | |
1c32f43e | 178 | cpu_model = "24Kf"; |
33d68b5f TS |
179 | #endif |
180 | } | |
aaed909a FB |
181 | env = cpu_init(cpu_model); |
182 | if (!env) { | |
183 | fprintf(stderr, "Unable to find CPU definition\n"); | |
184 | exit(1); | |
185 | } | |
e16ad5b0 AJ |
186 | reset_info = qemu_mallocz(sizeof(ResetData)); |
187 | reset_info->env = env; | |
188 | reset_info->vector = env->active_tc.PC; | |
189 | qemu_register_reset(main_cpu_reset, reset_info); | |
c68ea704 | 190 | |
6af0bf9c | 191 | /* allocate RAM */ |
0ccff151 AJ |
192 | if (ram_size > (256 << 20)) { |
193 | fprintf(stderr, | |
194 | "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n", | |
195 | ((unsigned int)ram_size / (1 << 20))); | |
196 | exit(1); | |
197 | } | |
dcac9679 | 198 | ram_offset = qemu_ram_alloc(ram_size); |
dcac9679 PB |
199 | |
200 | cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); | |
66a93e0f | 201 | |
6ae81775 | 202 | if (!mips_qemu_iomemtype) { |
1eed09cb | 203 | mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read, |
33d68b5f | 204 | mips_qemu_write, NULL); |
6ae81775 TS |
205 | } |
206 | cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); | |
207 | ||
66a93e0f FB |
208 | /* Try to load a BIOS image. If this fails, we continue regardless, |
209 | but initialize the hardware ourselves. When a kernel gets | |
210 | preloaded we also initialize the hardware, since the BIOS wasn't | |
211 | run. */ | |
1192dad8 JM |
212 | if (bios_name == NULL) |
213 | bios_name = BIOS_FILENAME; | |
5cea8590 PB |
214 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
215 | if (filename) { | |
216 | bios_size = get_image_size(filename); | |
217 | } else { | |
218 | bios_size = -1; | |
219 | } | |
2909b29a | 220 | if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { |
dcac9679 PB |
221 | bios_offset = qemu_ram_alloc(BIOS_SIZE); |
222 | cpu_register_physical_memory(0x1fc00000, BIOS_SIZE, | |
223 | bios_offset | IO_MEM_ROM); | |
224 | ||
5cea8590 | 225 | load_image_targphys(filename, 0x1fc00000, BIOS_SIZE); |
751c6a17 | 226 | } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) { |
b305b5ba | 227 | uint32_t mips_rom = 0x00400000; |
dcac9679 PB |
228 | bios_offset = qemu_ram_alloc(mips_rom); |
229 | if (!pflash_cfi01_register(0x1fc00000, bios_offset, | |
751c6a17 | 230 | dinfo->bdrv, sector_len, mips_rom / sector_len, |
b305b5ba TS |
231 | 4, 0, 0, 0, 0)) { |
232 | fprintf(stderr, "qemu: Error registering flash memory.\n"); | |
233 | } | |
234 | } | |
235 | else { | |
66a93e0f FB |
236 | /* not fatal */ |
237 | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", | |
5cea8590 PB |
238 | bios_name); |
239 | } | |
240 | if (filename) { | |
241 | qemu_free(filename); | |
6af0bf9c | 242 | } |
66a93e0f | 243 | |
66a93e0f | 244 | if (kernel_filename) { |
7df526e3 TS |
245 | loaderparams.ram_size = ram_size; |
246 | loaderparams.kernel_filename = kernel_filename; | |
247 | loaderparams.kernel_cmdline = kernel_cmdline; | |
248 | loaderparams.initrd_filename = initrd_filename; | |
e16ad5b0 | 249 | reset_info->vector = load_kernel(); |
6af0bf9c | 250 | } |
6af0bf9c | 251 | |
e16fe40c | 252 | /* Init CPU internal devices */ |
d537cf6c | 253 | cpu_mips_irq_init_cpu(env); |
c68ea704 | 254 | cpu_mips_clock_init(env); |
6af0bf9c | 255 | |
d537cf6c PB |
256 | /* The PIC is attached to the MIPS CPU INT0 pin */ |
257 | i8259 = i8259_init(env->irq[2]); | |
11d23c35 GH |
258 | isa_bus_new(NULL); |
259 | isa_bus_irqs(i8259); | |
d537cf6c | 260 | |
32e0c826 | 261 | rtc_state = rtc_init(2000); |
afdfa781 | 262 | |
0699b548 | 263 | /* Register 64 KB of ISA IO space at 0x14000000 */ |
84108e12 BS |
264 | #ifdef TARGET_WORDS_BIGENDIAN |
265 | isa_mmio_init(0x14000000, 0x00010000, 1); | |
266 | #else | |
267 | isa_mmio_init(0x14000000, 0x00010000, 0); | |
268 | #endif | |
0699b548 FB |
269 | isa_mem_base = 0x10000000; |
270 | ||
d537cf6c | 271 | pit = pit_init(0x40, i8259[0]); |
afdfa781 | 272 | |
eddbd288 TS |
273 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
274 | if (serial_hds[i]) { | |
ac0be998 | 275 | serial_isa_init(i, serial_hds[i]); |
eddbd288 TS |
276 | } |
277 | } | |
278 | ||
fbe1b595 | 279 | isa_vga_init(); |
9827e95c | 280 | |
0ae18cee | 281 | if (nd_table[0].vlan) |
9453c5bc | 282 | isa_ne2000_init(0x300, 9, &nd_table[0]); |
58126404 | 283 | |
e4bcb14c TS |
284 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
285 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
286 | exit(1); | |
287 | } | |
288 | ||
289 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
f455e98c | 290 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
e4bcb14c TS |
291 | } |
292 | ||
293 | for(i = 0; i < MAX_IDE_BUS; i++) | |
dea21e97 | 294 | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], |
e4bcb14c TS |
295 | hd[MAX_IDE_DEVS * i], |
296 | hd[MAX_IDE_DEVS * i + 1]); | |
70705261 | 297 | |
11d23c35 | 298 | isa_create_simple("i8042"); |
6af0bf9c FB |
299 | } |
300 | ||
f80f9ec9 | 301 | static QEMUMachine mips_machine = { |
eec2743e TS |
302 | .name = "mips", |
303 | .desc = "mips r4k platform", | |
304 | .init = mips_r4k_init, | |
6af0bf9c | 305 | }; |
f80f9ec9 AL |
306 | |
307 | static void mips_machine_init(void) | |
308 | { | |
309 | qemu_register_machine(&mips_machine); | |
310 | } | |
311 | ||
312 | machine_init(mips_machine_init); |