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Commit | Line | Data |
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6af0bf9c FB |
1 | #include "vl.h" |
2 | ||
6af0bf9c FB |
3 | #define BIOS_FILENAME "mips_bios.bin" |
4 | //#define BIOS_FILENAME "system.bin" | |
5 | #define KERNEL_LOAD_ADDR 0x80010000 | |
6 | #define INITRD_LOAD_ADDR 0x80800000 | |
7 | ||
6af0bf9c FB |
8 | extern FILE *logfile; |
9 | ||
73133662 | 10 | static void pic_irq_request(void *opaque, int level) |
6af0bf9c | 11 | { |
73133662 FB |
12 | if (level) { |
13 | cpu_single_env->CP0_Cause |= 0x00000400; | |
14 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); | |
6af0bf9c | 15 | } else { |
73133662 FB |
16 | cpu_single_env->CP0_Cause &= ~0x00000400; |
17 | cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); | |
6af0bf9c | 18 | } |
6af0bf9c FB |
19 | } |
20 | ||
21 | void cpu_mips_irqctrl_init (void) | |
22 | { | |
23 | } | |
24 | ||
6af0bf9c FB |
25 | uint32_t cpu_mips_get_random (CPUState *env) |
26 | { | |
899abcf5 | 27 | uint32_t now = qemu_get_clock(vm_clock); |
6af0bf9c | 28 | |
899abcf5 | 29 | return now % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired; |
6af0bf9c FB |
30 | } |
31 | ||
899abcf5 | 32 | /* MIPS R4K timer */ |
6af0bf9c FB |
33 | uint32_t cpu_mips_get_count (CPUState *env) |
34 | { | |
35 | return env->CP0_Count + | |
36 | (uint32_t)muldiv64(qemu_get_clock(vm_clock), | |
37 | 100 * 1000 * 1000, ticks_per_sec); | |
38 | } | |
39 | ||
40 | static void cpu_mips_update_count (CPUState *env, uint32_t count, | |
41 | uint32_t compare) | |
42 | { | |
43 | uint64_t now, next; | |
44 | uint32_t tmp; | |
45 | ||
46 | tmp = count; | |
47 | if (count == compare) | |
48 | tmp++; | |
49 | now = qemu_get_clock(vm_clock); | |
50 | next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); | |
51 | if (next == now) | |
52 | next++; | |
53 | #if 1 | |
54 | if (logfile) { | |
55 | fprintf(logfile, "%s: 0x%08llx %08x %08x => 0x%08llx\n", | |
56 | __func__, now, count, compare, next - now); | |
57 | } | |
58 | #endif | |
59 | /* Store new count and compare registers */ | |
60 | env->CP0_Compare = compare; | |
61 | env->CP0_Count = | |
62 | count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); | |
63 | /* Adjust timer */ | |
64 | qemu_mod_timer(env->timer, next); | |
65 | } | |
66 | ||
67 | void cpu_mips_store_count (CPUState *env, uint32_t value) | |
68 | { | |
69 | cpu_mips_update_count(env, value, env->CP0_Compare); | |
70 | } | |
71 | ||
72 | void cpu_mips_store_compare (CPUState *env, uint32_t value) | |
73 | { | |
74 | cpu_mips_update_count(env, cpu_mips_get_count(env), value); | |
c96a29cd FB |
75 | cpu_single_env->CP0_Cause &= ~0x00008000; |
76 | cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); | |
6af0bf9c FB |
77 | } |
78 | ||
79 | static void mips_timer_cb (void *opaque) | |
80 | { | |
81 | CPUState *env; | |
82 | ||
83 | env = opaque; | |
84 | #if 1 | |
85 | if (logfile) { | |
86 | fprintf(logfile, "%s\n", __func__); | |
87 | } | |
88 | #endif | |
89 | cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); | |
c96a29cd FB |
90 | cpu_single_env->CP0_Cause |= 0x00008000; |
91 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); | |
6af0bf9c FB |
92 | } |
93 | ||
94 | void cpu_mips_clock_init (CPUState *env) | |
95 | { | |
96 | env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); | |
97 | env->CP0_Compare = 0; | |
98 | cpu_mips_update_count(env, 1, 0); | |
99 | } | |
100 | ||
101 | static void io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) | |
102 | { | |
103 | if (logfile) | |
104 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); | |
105 | cpu_outb(NULL, addr & 0xffff, value); | |
106 | } | |
107 | ||
108 | static uint32_t io_readb (void *opaque, target_phys_addr_t addr) | |
109 | { | |
110 | uint32_t ret = cpu_inb(NULL, addr & 0xffff); | |
111 | if (logfile) | |
112 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); | |
113 | return ret; | |
114 | } | |
115 | ||
116 | static void io_writew (void *opaque, target_phys_addr_t addr, uint32_t value) | |
117 | { | |
118 | if (logfile) | |
119 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); | |
120 | #ifdef TARGET_WORDS_BIGENDIAN | |
121 | value = bswap16(value); | |
122 | #endif | |
123 | cpu_outw(NULL, addr & 0xffff, value); | |
124 | } | |
125 | ||
126 | static uint32_t io_readw (void *opaque, target_phys_addr_t addr) | |
127 | { | |
128 | uint32_t ret = cpu_inw(NULL, addr & 0xffff); | |
129 | #ifdef TARGET_WORDS_BIGENDIAN | |
130 | ret = bswap16(ret); | |
131 | #endif | |
132 | if (logfile) | |
133 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); | |
134 | return ret; | |
135 | } | |
136 | ||
137 | static void io_writel (void *opaque, target_phys_addr_t addr, uint32_t value) | |
138 | { | |
139 | if (logfile) | |
140 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, value); | |
141 | #ifdef TARGET_WORDS_BIGENDIAN | |
142 | value = bswap32(value); | |
143 | #endif | |
144 | cpu_outl(NULL, addr & 0xffff, value); | |
145 | } | |
146 | ||
147 | static uint32_t io_readl (void *opaque, target_phys_addr_t addr) | |
148 | { | |
149 | uint32_t ret = cpu_inl(NULL, addr & 0xffff); | |
150 | ||
151 | #ifdef TARGET_WORDS_BIGENDIAN | |
152 | ret = bswap32(ret); | |
153 | #endif | |
154 | if (logfile) | |
155 | fprintf(logfile, "%s: addr %08x val %08x\n", __func__, addr, ret); | |
156 | return ret; | |
157 | } | |
158 | ||
159 | CPUWriteMemoryFunc *io_write[] = { | |
160 | &io_writeb, | |
161 | &io_writew, | |
162 | &io_writel, | |
163 | }; | |
164 | ||
165 | CPUReadMemoryFunc *io_read[] = { | |
166 | &io_readb, | |
167 | &io_readw, | |
168 | &io_readl, | |
169 | }; | |
170 | ||
171 | void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, | |
172 | DisplayState *ds, const char **fd_filename, int snapshot, | |
173 | const char *kernel_filename, const char *kernel_cmdline, | |
174 | const char *initrd_filename) | |
175 | { | |
176 | char buf[1024]; | |
177 | target_ulong kernel_base, kernel_size, initrd_base, initrd_size; | |
178 | unsigned long bios_offset; | |
179 | int io_memory; | |
180 | int linux_boot; | |
181 | int ret; | |
182 | ||
183 | printf("%s: start\n", __func__); | |
184 | linux_boot = (kernel_filename != NULL); | |
185 | /* allocate RAM */ | |
186 | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); | |
187 | bios_offset = ram_size + vga_ram_size; | |
188 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); | |
189 | printf("%s: load BIOS '%s' size %d\n", __func__, buf, BIOS_SIZE); | |
190 | ret = load_image(buf, phys_ram_base + bios_offset); | |
191 | if (ret != BIOS_SIZE) { | |
192 | fprintf(stderr, "qemu: could not load MIPS bios '%s'\n", buf); | |
193 | exit(1); | |
194 | } | |
195 | cpu_register_physical_memory((uint32_t)(0x1fc00000), | |
196 | BIOS_SIZE, bios_offset | IO_MEM_ROM); | |
197 | #if 0 | |
198 | memcpy(phys_ram_base + 0x10000, phys_ram_base + bios_offset, BIOS_SIZE); | |
199 | cpu_single_env->PC = 0x80010004; | |
200 | #else | |
201 | cpu_single_env->PC = 0xBFC00004; | |
202 | #endif | |
203 | if (linux_boot) { | |
204 | kernel_base = KERNEL_LOAD_ADDR; | |
205 | /* now we can load the kernel */ | |
de12d636 FB |
206 | kernel_size = load_image(kernel_filename, |
207 | phys_ram_base + (kernel_base - 0x80000000)); | |
208 | if (kernel_size == (target_ulong) -1) { | |
6af0bf9c FB |
209 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
210 | kernel_filename); | |
211 | exit(1); | |
212 | } | |
213 | /* load initrd */ | |
214 | if (initrd_filename) { | |
215 | initrd_base = INITRD_LOAD_ADDR; | |
216 | initrd_size = load_image(initrd_filename, | |
217 | phys_ram_base + initrd_base); | |
de12d636 | 218 | if (initrd_size == (target_ulong) -1) { |
6af0bf9c FB |
219 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
220 | initrd_filename); | |
221 | exit(1); | |
222 | } | |
223 | } else { | |
224 | initrd_base = 0; | |
225 | initrd_size = 0; | |
226 | } | |
227 | cpu_single_env->PC = KERNEL_LOAD_ADDR; | |
228 | } else { | |
229 | kernel_base = 0; | |
230 | kernel_size = 0; | |
231 | initrd_base = 0; | |
232 | initrd_size = 0; | |
233 | } | |
6af0bf9c FB |
234 | |
235 | /* Init internal devices */ | |
236 | cpu_mips_clock_init(cpu_single_env); | |
237 | cpu_mips_irqctrl_init(); | |
238 | ||
0699b548 | 239 | /* Register 64 KB of ISA IO space at 0x14000000 */ |
6af0bf9c | 240 | io_memory = cpu_register_io_memory(0, io_read, io_write, NULL); |
0699b548 FB |
241 | cpu_register_physical_memory(0x14000000, 0x00010000, io_memory); |
242 | isa_mem_base = 0x10000000; | |
243 | ||
73133662 | 244 | isa_pic = pic_init(pic_irq_request, cpu_single_env); |
6af0bf9c | 245 | serial_init(0x3f8, 4, serial_hds[0]); |
0699b548 | 246 | vga_initialize(NULL, ds, phys_ram_base + ram_size, ram_size, |
d5295253 | 247 | vga_ram_size, 0, 0); |
9827e95c FB |
248 | |
249 | isa_ne2000_init(0x300, 9, &nd_table[0]); | |
6af0bf9c FB |
250 | } |
251 | ||
252 | QEMUMachine mips_machine = { | |
253 | "mips", | |
254 | "mips r4k platform", | |
255 | mips_r4k_init, | |
256 | }; |