[qemu.git] / hw / mips_r4k.c

/*
 * QEMU/MIPS pseudo-board
 *
 * emulates a simple machine with ISA-like bus.
 * ISA IO space mapped to the 0x14000000 (PHYS) and
 * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
 * All peripherial devices are attached to this "bus" with
 * the standard PC ISA addresses.
*/
#include "vl.h"

#define BIOS_FILENAME "mips_bios.bin"
//#define BIOS_FILENAME "system.bin"
#define KERNEL_LOAD_ADDR 0x80010000
#define INITRD_LOAD_ADDR 0x80800000

#define VIRT_TO_PHYS_ADDEND (-0x80000000LL)

static const int ide_iobase[2] = { 0x1f0, 0x170 };
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
static const int ide_irq[2] = { 14, 15 };

extern FILE *logfile;

static PITState *pit; /* PIT i8254 */

/*i8254 PIT is attached to the IRQ0 at PIC i8259 */
/*The PIC is attached to the MIPS CPU INT0 pin */
static void pic_irq_request(void *opaque, int level)
{
    CPUState *env = first_cpu;
    if (level) {
        env->CP0_Cause |= 0x00000400;
        cpu_interrupt(env, CPU_INTERRUPT_HARD);
    } else {
	env->CP0_Cause &= ~0x00000400;
        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
    }
}

static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
			      uint32_t val)
{
    if ((addr & 0xffff) == 0 && val == 42)
        qemu_system_reset_request ();
    else if ((addr & 0xffff) == 4 && val == 42)
        qemu_system_shutdown_request ();
}

static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static CPUWriteMemoryFunc *mips_qemu_write[] = {
    &mips_qemu_writel,
    &mips_qemu_writel,
    &mips_qemu_writel,
};

static CPUReadMemoryFunc *mips_qemu_read[] = {
    &mips_qemu_readl,
    &mips_qemu_readl,
    &mips_qemu_readl,
};

static int mips_qemu_iomemtype = 0;

void load_kernel (CPUState *env, int ram_size, const char *kernel_filename,
		  const char *kernel_cmdline,
		  const char *initrd_filename)
{
    int64_t entry = 0;
    long kernel_size, initrd_size;

    kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
    if (kernel_size >= 0)
        env->PC = entry;
    else {
        kernel_size = load_image(kernel_filename,
                                 phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
        env->PC = KERNEL_LOAD_ADDR;
    }

    /* load initrd */
    initrd_size = 0;
    if (initrd_filename) {
        initrd_size = load_image(initrd_filename,
                                 phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
        if (initrd_size == (target_ulong) -1) {
            fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
                    initrd_filename);
            exit(1);
        }
    }

    /* Store command line.  */
    if (initrd_size > 0) {
        int ret;
        ret = sprintf(phys_ram_base + (16 << 20) - 256,
                      "rd_start=0x%08x rd_size=%li ",
                      INITRD_LOAD_ADDR,
                      initrd_size);
        strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline);
    }
    else {
        strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
    }

    *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
    *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
}

static void main_cpu_reset(void *opaque)
{
    CPUState *env = opaque;
    cpu_reset(env);

    if (env->kernel_filename)
        load_kernel (env, env->ram_size, env->kernel_filename,
                     env->kernel_cmdline, env->initrd_filename);
}

void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
                    DisplayState *ds, const char **fd_filename, int snapshot,
                    const char *kernel_filename, const char *kernel_cmdline,
                    const char *initrd_filename)
{
    char buf[1024];
    unsigned long bios_offset;
    int ret;
    CPUState *env;
    int i;

    env = cpu_init();
    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
    qemu_register_reset(main_cpu_reset, env);

    /* allocate RAM */
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);

    if (!mips_qemu_iomemtype) {
        mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
						     mips_qemu_write, NULL);
    }
    cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);

    /* Try to load a BIOS image. If this fails, we continue regardless,
       but initialize the hardware ourselves. When a kernel gets
       preloaded we also initialize the hardware, since the BIOS wasn't
       run. */
    bios_offset = ram_size + vga_ram_size;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
    ret = load_image(buf, phys_ram_base + bios_offset);
    if (ret == BIOS_SIZE) {
	cpu_register_physical_memory((uint32_t)(0x1fc00000),
				     BIOS_SIZE, bios_offset | IO_MEM_ROM);
    } else {
	/* not fatal */
        fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
		buf);
    }

    if (kernel_filename) {
        load_kernel (env, ram_size, kernel_filename, kernel_cmdline,
		     initrd_filename);
	env->ram_size = ram_size;
	env->kernel_filename = kernel_filename;
	env->kernel_cmdline = kernel_cmdline;
	env->initrd_filename = initrd_filename;
    }

    /* Init CPU internal devices */
    cpu_mips_clock_init(env);
    cpu_mips_irqctrl_init();

    /* Register 64 KB of ISA IO space at 0x14000000 */
    isa_mmio_init(0x14000000, 0x00010000);
    isa_mem_base = 0x10000000;

    isa_pic = pic_init(pic_irq_request, env);
    pit = pit_init(0x40, 0);
    serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
    isa_vga_init(ds, phys_ram_base + ram_size, ram_size, 
                 vga_ram_size);

    if (nd_table[0].vlan) {
        if (nd_table[0].model == NULL
            || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
            isa_ne2000_init(0x300, 9, &nd_table[0]);
        } else {
            fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
            exit (1);
        }
    }

    for(i = 0; i < 2; i++)
        isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
                     bs_table[2 * i], bs_table[2 * i + 1]);
}

QEMUMachine mips_machine = {
    "mips",
    "mips r4k platform",
    mips_r4k_init,
};
Commit	Line	Data
e16fe40c TS	1	/*
	2	* QEMU/MIPS pseudo-board
	3	*
	4	* emulates a simple machine with ISA-like bus.
	5	* ISA IO space mapped to the 0x14000000 (PHYS) and
	6	* ISA memory at the 0x10000000 (PHYS, 16Mb in size).
	7	* All peripherial devices are attached to this "bus" with
	8	* the standard PC ISA addresses.
	9	*/
6af0bf9c FB	10	#include "vl.h"
6af0bf9c FB	11
6af0bf9c FB	12	#define BIOS_FILENAME "mips_bios.bin"
	13	//#define BIOS_FILENAME "system.bin"
	14	#define KERNEL_LOAD_ADDR 0x80010000
	15	#define INITRD_LOAD_ADDR 0x80800000
	16
66a93e0f FB	17	#define VIRT_TO_PHYS_ADDEND (-0x80000000LL)
66a93e0f FB	18
58126404 PB	19	static const int ide_iobase[2] = { 0x1f0, 0x170 };
	20	static const int ide_iobase2[2] = { 0x3f6, 0x376 };
	21	static const int ide_irq[2] = { 14, 15 };
	22
6af0bf9c FB	23	extern FILE *logfile;
6af0bf9c FB	24
e16fe40c	25	static PITState pit; / PIT i8254 */
697584ab	26
e16fe40c TS	27	/i8254 PIT is attached to the IRQ0 at PIC i8259 /
e16fe40c TS	28	/The PIC is attached to the MIPS CPU INT0 pin /
73133662	29	static void pic_irq_request(void *opaque, int level)
6af0bf9c	30	{
c68ea704	31	CPUState *env = first_cpu;
73133662	32	if (level) {
c68ea704 FB	33	env->CP0_Cause \|= 0x00000400;
c68ea704 FB	34	cpu_interrupt(env, CPU_INTERRUPT_HARD);
6af0bf9c	35	} else {
c68ea704 FB	36	env->CP0_Cause &= ~0x00000400;
c68ea704 FB	37	cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
6af0bf9c	38	}
6af0bf9c FB	39	}
6af0bf9c FB	40
6ae81775 TS	41	static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
	42	uint32_t val)
	43	{
	44	if ((addr & 0xffff) == 0 && val == 42)
	45	qemu_system_reset_request ();
	46	else if ((addr & 0xffff) == 4 && val == 42)
	47	qemu_system_shutdown_request ();
	48	}
	49
	50	static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
	51	{
	52	return 0;
	53	}
	54
	55	static CPUWriteMemoryFunc *mips_qemu_write[] = {
	56	&mips_qemu_writel,
	57	&mips_qemu_writel,
	58	&mips_qemu_writel,
	59	};
	60
	61	static CPUReadMemoryFunc *mips_qemu_read[] = {
	62	&mips_qemu_readl,
	63	&mips_qemu_readl,
	64	&mips_qemu_readl,
	65	};
	66
	67	static int mips_qemu_iomemtype = 0;
	68
	69	void load_kernel (CPUState env, int ram_size, const char kernel_filename,
	70	const char *kernel_cmdline,
	71	const char *initrd_filename)
	72	{
	73	int64_t entry = 0;
	74	long kernel_size, initrd_size;
	75
	76	kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
	77	if (kernel_size >= 0)
	78	env->PC = entry;
	79	else {
	80	kernel_size = load_image(kernel_filename,
	81	phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
	82	if (kernel_size < 0) {
	83	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	84	kernel_filename);
	85	exit(1);
	86	}
	87	env->PC = KERNEL_LOAD_ADDR;
	88	}
	89
	90	/* load initrd */
	91	initrd_size = 0;
	92	if (initrd_filename) {
	93	initrd_size = load_image(initrd_filename,
	94	phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
	95	if (initrd_size == (target_ulong) -1) {
	96	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
	97	initrd_filename);
	98	exit(1);
	99	}
	100	}
	101
	102	/* Store command line. */
	103	if (initrd_size > 0) {
	104	int ret;
105	ret = sprintf(phys_ram_base + (16 << 20) - 256,
106	"rd_start=0x%08x rd_size=%li ",
107	INITRD_LOAD_ADDR,
108	initrd_size);
109	strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline);
110	}
111	else {
112	strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
113	}
114
115	(int )(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
116	(int )(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
117	}
118
119	static void main_cpu_reset(void *opaque)
120	{
121	CPUState *env = opaque;
122	cpu_reset(env);
123
124	if (env->kernel_filename)
125	load_kernel (env, env->ram_size, env->kernel_filename,
126	env->kernel_cmdline, env->initrd_filename);
127	}
66a93e0f	128
6af0bf9c FB	129	void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
	130	DisplayState ds, const char *fd_filename, int snapshot,
	131	const char kernel_filename, const char kernel_cmdline,
	132	const char *initrd_filename)
	133	{
	134	char buf[1024];
6af0bf9c	135	unsigned long bios_offset;
6af0bf9c	136	int ret;
c68ea704	137	CPUState *env;
58126404	138	int i;
c68ea704 FB	139
	140	env = cpu_init();
	141	register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
6ae81775	142	qemu_register_reset(main_cpu_reset, env);
c68ea704	143
6af0bf9c FB	144	/* allocate RAM */
6af0bf9c FB	145	cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
66a93e0f	146
6ae81775 TS	147	if (!mips_qemu_iomemtype) {
	148	mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
	149	mips_qemu_write, NULL);
	150	}
	151	cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
	152
66a93e0f FB	153	/* Try to load a BIOS image. If this fails, we continue regardless,
	154	but initialize the hardware ourselves. When a kernel gets
	155	preloaded we also initialize the hardware, since the BIOS wasn't
	156	run. */
6af0bf9c FB	157	bios_offset = ram_size + vga_ram_size;
6af0bf9c FB	158	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
6af0bf9c	159	ret = load_image(buf, phys_ram_base + bios_offset);
66a93e0f FB	160	if (ret == BIOS_SIZE) {
	161	cpu_register_physical_memory((uint32_t)(0x1fc00000),
	162	BIOS_SIZE, bios_offset \| IO_MEM_ROM);
66a93e0f FB	163	} else {
	164	/* not fatal */
	165	fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
	166	buf);
6af0bf9c	167	}
66a93e0f	168
66a93e0f	169	if (kernel_filename) {
6ae81775 TS	170	load_kernel (env, ram_size, kernel_filename, kernel_cmdline,
	171	initrd_filename);
	172	env->ram_size = ram_size;
	173	env->kernel_filename = kernel_filename;
	174	env->kernel_cmdline = kernel_cmdline;
	175	env->initrd_filename = initrd_filename;
6af0bf9c	176	}
6af0bf9c	177
e16fe40c	178	/* Init CPU internal devices */
c68ea704	179	cpu_mips_clock_init(env);
6af0bf9c FB	180	cpu_mips_irqctrl_init();
6af0bf9c FB	181
0699b548	182	/* Register 64 KB of ISA IO space at 0x14000000 */
aef445bd	183	isa_mmio_init(0x14000000, 0x00010000);
0699b548 FB	184	isa_mem_base = 0x10000000;
0699b548 FB	185
c68ea704	186	isa_pic = pic_init(pic_irq_request, env);
697584ab	187	pit = pit_init(0x40, 0);
e5d13e2f	188	serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
89b6b508 FB	189	isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
89b6b508 FB	190	vga_ram_size);
9827e95c	191
a41b2ff2 PB	192	if (nd_table[0].vlan) {
	193	if (nd_table[0].model == NULL
	194	\|\| strcmp(nd_table[0].model, "ne2k_isa") == 0) {
	195	isa_ne2000_init(0x300, 9, &nd_table[0]);
	196	} else {
	197	fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
	198	exit (1);
	199	}
	200	}
58126404 PB	201
	202	for(i = 0; i < 2; i++)
	203	isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
	204	bs_table[2 * i], bs_table[2 * i + 1]);
6af0bf9c FB	205	}
	206
	207	QEMUMachine mips_machine = {
	208	"mips",
	209	"mips r4k platform",
	210	mips_r4k_init,
	211	};