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Commit | Line | Data |
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e16fe40c TS |
1 | /* |
2 | * QEMU/MIPS pseudo-board | |
3 | * | |
4 | * emulates a simple machine with ISA-like bus. | |
5 | * ISA IO space mapped to the 0x14000000 (PHYS) and | |
6 | * ISA memory at the 0x10000000 (PHYS, 16Mb in size). | |
7 | * All peripherial devices are attached to this "bus" with | |
8 | * the standard PC ISA addresses. | |
9 | */ | |
6af0bf9c FB |
10 | #include "vl.h" |
11 | ||
2909b29a | 12 | #ifdef TARGET_WORDS_BIGENDIAN |
6af0bf9c | 13 | #define BIOS_FILENAME "mips_bios.bin" |
f7bcd4e3 TS |
14 | #else |
15 | #define BIOS_FILENAME "mipsel_bios.bin" | |
16 | #endif | |
44cbbf18 | 17 | |
5dc4b744 | 18 | #ifdef MIPS_HAS_MIPS64 |
f8c6ff6c | 19 | #define INITRD_LOAD_ADDR (int64_t)(int32_t)0x80800000 |
5dc4b744 TS |
20 | #else |
21 | #define INITRD_LOAD_ADDR (int32_t)0x80800000 | |
22 | #endif | |
6af0bf9c | 23 | |
5dc4b744 | 24 | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
66a93e0f | 25 | |
58126404 PB |
26 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
27 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
28 | static const int ide_irq[2] = { 14, 15 }; | |
29 | ||
eddbd288 TS |
30 | static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
31 | static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
32 | ||
6af0bf9c FB |
33 | extern FILE *logfile; |
34 | ||
e16fe40c | 35 | static PITState *pit; /* PIT i8254 */ |
697584ab | 36 | |
e16fe40c TS |
37 | /*i8254 PIT is attached to the IRQ0 at PIC i8259 */ |
38 | /*The PIC is attached to the MIPS CPU INT0 pin */ | |
73133662 | 39 | static void pic_irq_request(void *opaque, int level) |
6af0bf9c | 40 | { |
4de9b249 | 41 | cpu_mips_irq_request(opaque, 2, level); |
6af0bf9c FB |
42 | } |
43 | ||
6ae81775 TS |
44 | static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, |
45 | uint32_t val) | |
46 | { | |
47 | if ((addr & 0xffff) == 0 && val == 42) | |
48 | qemu_system_reset_request (); | |
49 | else if ((addr & 0xffff) == 4 && val == 42) | |
50 | qemu_system_shutdown_request (); | |
51 | } | |
52 | ||
53 | static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) | |
54 | { | |
55 | return 0; | |
56 | } | |
57 | ||
58 | static CPUWriteMemoryFunc *mips_qemu_write[] = { | |
59 | &mips_qemu_writel, | |
60 | &mips_qemu_writel, | |
61 | &mips_qemu_writel, | |
62 | }; | |
63 | ||
64 | static CPUReadMemoryFunc *mips_qemu_read[] = { | |
65 | &mips_qemu_readl, | |
66 | &mips_qemu_readl, | |
67 | &mips_qemu_readl, | |
68 | }; | |
69 | ||
70 | static int mips_qemu_iomemtype = 0; | |
71 | ||
72 | void load_kernel (CPUState *env, int ram_size, const char *kernel_filename, | |
73 | const char *kernel_cmdline, | |
74 | const char *initrd_filename) | |
75 | { | |
76 | int64_t entry = 0; | |
77 | long kernel_size, initrd_size; | |
78 | ||
79 | kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry); | |
c570fd16 TS |
80 | if (kernel_size >= 0) { |
81 | if ((entry & ~0x7fffffffULL) == 0x80000000) | |
5dc4b744 | 82 | entry = (int32_t)entry; |
6ae81775 | 83 | env->PC = entry; |
c570fd16 | 84 | } else { |
9042c0e2 TS |
85 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
86 | kernel_filename); | |
87 | exit(1); | |
6ae81775 TS |
88 | } |
89 | ||
90 | /* load initrd */ | |
91 | initrd_size = 0; | |
92 | if (initrd_filename) { | |
93 | initrd_size = load_image(initrd_filename, | |
94 | phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND); | |
95 | if (initrd_size == (target_ulong) -1) { | |
96 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
97 | initrd_filename); | |
98 | exit(1); | |
99 | } | |
100 | } | |
101 | ||
102 | /* Store command line. */ | |
103 | if (initrd_size > 0) { | |
104 | int ret; | |
105 | ret = sprintf(phys_ram_base + (16 << 20) - 256, | |
3594c774 | 106 | "rd_start=0x" TARGET_FMT_lx " rd_size=%li ", |
6ae81775 TS |
107 | INITRD_LOAD_ADDR, |
108 | initrd_size); | |
109 | strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline); | |
110 | } | |
111 | else { | |
112 | strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline); | |
113 | } | |
114 | ||
44cbbf18 TS |
115 | *(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678); |
116 | *(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size); | |
6ae81775 TS |
117 | } |
118 | ||
119 | static void main_cpu_reset(void *opaque) | |
120 | { | |
121 | CPUState *env = opaque; | |
122 | cpu_reset(env); | |
123 | ||
124 | if (env->kernel_filename) | |
125 | load_kernel (env, env->ram_size, env->kernel_filename, | |
126 | env->kernel_cmdline, env->initrd_filename); | |
127 | } | |
66a93e0f | 128 | |
70705261 | 129 | static |
6af0bf9c FB |
130 | void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device, |
131 | DisplayState *ds, const char **fd_filename, int snapshot, | |
132 | const char *kernel_filename, const char *kernel_cmdline, | |
94fc95cd | 133 | const char *initrd_filename, const char *cpu_model) |
6af0bf9c FB |
134 | { |
135 | char buf[1024]; | |
6af0bf9c | 136 | unsigned long bios_offset; |
f7bcd4e3 | 137 | int bios_size; |
c68ea704 | 138 | CPUState *env; |
153a08db | 139 | RTCState *rtc_state; |
58126404 | 140 | int i; |
33d68b5f | 141 | mips_def_t *def; |
c68ea704 | 142 | |
33d68b5f TS |
143 | /* init CPUs */ |
144 | if (cpu_model == NULL) { | |
145 | #ifdef MIPS_HAS_MIPS64 | |
146 | cpu_model = "R4000"; | |
147 | #else | |
148 | cpu_model = "4KEc"; | |
149 | #endif | |
150 | } | |
151 | if (mips_find_by_name(cpu_model, &def) != 0) | |
152 | def = NULL; | |
c68ea704 | 153 | env = cpu_init(); |
33d68b5f | 154 | cpu_mips_register(env, def); |
c68ea704 | 155 | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
6ae81775 | 156 | qemu_register_reset(main_cpu_reset, env); |
c68ea704 | 157 | |
6af0bf9c FB |
158 | /* allocate RAM */ |
159 | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); | |
66a93e0f | 160 | |
6ae81775 TS |
161 | if (!mips_qemu_iomemtype) { |
162 | mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read, | |
33d68b5f | 163 | mips_qemu_write, NULL); |
6ae81775 TS |
164 | } |
165 | cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype); | |
166 | ||
66a93e0f FB |
167 | /* Try to load a BIOS image. If this fails, we continue regardless, |
168 | but initialize the hardware ourselves. When a kernel gets | |
169 | preloaded we also initialize the hardware, since the BIOS wasn't | |
170 | run. */ | |
6af0bf9c FB |
171 | bios_offset = ram_size + vga_ram_size; |
172 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); | |
f7bcd4e3 | 173 | bios_size = load_image(buf, phys_ram_base + bios_offset); |
2909b29a | 174 | if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { |
44cbbf18 | 175 | cpu_register_physical_memory(0x1fc00000, |
66a93e0f | 176 | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
66a93e0f FB |
177 | } else { |
178 | /* not fatal */ | |
179 | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n", | |
180 | buf); | |
6af0bf9c | 181 | } |
66a93e0f | 182 | |
66a93e0f | 183 | if (kernel_filename) { |
6ae81775 TS |
184 | load_kernel (env, ram_size, kernel_filename, kernel_cmdline, |
185 | initrd_filename); | |
186 | env->ram_size = ram_size; | |
187 | env->kernel_filename = kernel_filename; | |
188 | env->kernel_cmdline = kernel_cmdline; | |
189 | env->initrd_filename = initrd_filename; | |
6af0bf9c | 190 | } |
6af0bf9c | 191 | |
e16fe40c | 192 | /* Init CPU internal devices */ |
c68ea704 | 193 | cpu_mips_clock_init(env); |
6af0bf9c FB |
194 | cpu_mips_irqctrl_init(); |
195 | ||
afdfa781 TS |
196 | rtc_state = rtc_init(0x70, 8); |
197 | ||
0699b548 | 198 | /* Register 64 KB of ISA IO space at 0x14000000 */ |
aef445bd | 199 | isa_mmio_init(0x14000000, 0x00010000); |
0699b548 FB |
200 | isa_mem_base = 0x10000000; |
201 | ||
c68ea704 | 202 | isa_pic = pic_init(pic_irq_request, env); |
697584ab | 203 | pit = pit_init(0x40, 0); |
afdfa781 | 204 | |
eddbd288 TS |
205 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
206 | if (serial_hds[i]) { | |
207 | serial_init(&pic_set_irq_new, isa_pic, | |
208 | serial_io[i], serial_irq[i], serial_hds[i]); | |
209 | } | |
210 | } | |
211 | ||
89b6b508 FB |
212 | isa_vga_init(ds, phys_ram_base + ram_size, ram_size, |
213 | vga_ram_size); | |
9827e95c | 214 | |
a41b2ff2 PB |
215 | if (nd_table[0].vlan) { |
216 | if (nd_table[0].model == NULL | |
217 | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { | |
218 | isa_ne2000_init(0x300, 9, &nd_table[0]); | |
219 | } else { | |
220 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | |
221 | exit (1); | |
222 | } | |
223 | } | |
58126404 PB |
224 | |
225 | for(i = 0; i < 2; i++) | |
226 | isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i], | |
227 | bs_table[2 * i], bs_table[2 * i + 1]); | |
70705261 TS |
228 | |
229 | kbd_init(); | |
9542611a | 230 | ds1225y_init(0x9000, "nvram"); |
6af0bf9c FB |
231 | } |
232 | ||
233 | QEMUMachine mips_machine = { | |
234 | "mips", | |
235 | "mips r4k platform", | |
236 | mips_r4k_init, | |
237 | }; |