[qemu.git] / hw / mipsnet.c

#include "hw.h"
#include "mips.h"
#include "net.h"
#include "isa.h"

//#define DEBUG_MIPSNET_SEND
//#define DEBUG_MIPSNET_RECEIVE
//#define DEBUG_MIPSNET_DATA
//#define DEBUG_MIPSNET_IRQ

/* MIPSnet register offsets */

#define MIPSNET_DEV_ID		0x00
#define MIPSNET_BUSY		0x08
#define MIPSNET_RX_DATA_COUNT	0x0c
#define MIPSNET_TX_DATA_COUNT	0x10
#define MIPSNET_INT_CTL		0x14
# define MIPSNET_INTCTL_TXDONE		0x00000001
# define MIPSNET_INTCTL_RXDONE		0x00000002
# define MIPSNET_INTCTL_TESTBIT		0x80000000
#define MIPSNET_INTERRUPT_INFO	0x18
#define MIPSNET_RX_DATA_BUFFER	0x1c
#define MIPSNET_TX_DATA_BUFFER	0x20

#define MAX_ETH_FRAME_SIZE	1514

typedef struct MIPSnetState {
    uint32_t busy;
    uint32_t rx_count;
    uint32_t rx_read;
    uint32_t tx_count;
    uint32_t tx_written;
    uint32_t intctl;
    uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
    uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
    qemu_irq irq;
    VLANClientState *vc;
} MIPSnetState;

static void mipsnet_reset(MIPSnetState *s)
{
    s->busy = 1;
    s->rx_count = 0;
    s->rx_read = 0;
    s->tx_count = 0;
    s->tx_written = 0;
    s->intctl = 0;
    memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
    memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
}

static void mipsnet_update_irq(MIPSnetState *s)
{
    int isr = !!s->intctl;
#ifdef DEBUG_MIPSNET_IRQ
    printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
#endif
    qemu_set_irq(s->irq, isr);
}

static int mipsnet_buffer_full(MIPSnetState *s)
{
    if (s->rx_count >= MAX_ETH_FRAME_SIZE)
        return 1;
    return 0;
}

static int mipsnet_can_receive(void *opaque)
{
    MIPSnetState *s = opaque;

    if (s->busy)
        return 0;
    return !mipsnet_buffer_full(s);
}

static void mipsnet_receive(void *opaque, const uint8_t *buf, int size)
{
    MIPSnetState *s = opaque;

#ifdef DEBUG_MIPSNET_RECEIVE
    printf("mipsnet: receiving len=%d\n", size);
#endif
    if (!mipsnet_can_receive(opaque))
        return;

    s->busy = 1;

    /* Just accept everything. */

    /* Write packet data. */
    memcpy(s->rx_buffer, buf, size);

    s->rx_count = size;
    s->rx_read = 0;

    /* Now we can signal we have received something. */
    s->intctl |= MIPSNET_INTCTL_RXDONE;
    mipsnet_update_irq(s);
}

static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr)
{
    MIPSnetState *s = opaque;
    int ret = 0;

    addr &= 0x3f;
    switch (addr) {
    case MIPSNET_DEV_ID:
	ret = be32_to_cpu(0x4d495053);		/* MIPS */
        break;
    case MIPSNET_DEV_ID + 4:
	ret = be32_to_cpu(0x4e455430);		/* NET0 */
        break;
    case MIPSNET_BUSY:
	ret = s->busy;
        break;
    case MIPSNET_RX_DATA_COUNT:
	ret = s->rx_count;
        break;
    case MIPSNET_TX_DATA_COUNT:
	ret = s->tx_count;
        break;
    case MIPSNET_INT_CTL:
	ret = s->intctl;
        s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
        break;
    case MIPSNET_INTERRUPT_INFO:
        /* XXX: This seems to be a per-VPE interrupt number. */
	ret = 0;
        break;
    case MIPSNET_RX_DATA_BUFFER:
        if (s->rx_count) {
            s->rx_count--;
            ret = s->rx_buffer[s->rx_read++];
        }
        break;
    /* Reads as zero. */
    case MIPSNET_TX_DATA_BUFFER:
    default:
        break;
    }
#ifdef DEBUG_MIPSNET_DATA
    printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
#endif
    return ret;
}

static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    MIPSnetState *s = opaque;

    addr &= 0x3f;
#ifdef DEBUG_MIPSNET_DATA
    printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
    switch (addr) {
    case MIPSNET_TX_DATA_COUNT:
	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
        s->tx_written = 0;
        break;
    case MIPSNET_INT_CTL:
        if (val & MIPSNET_INTCTL_TXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_TXDONE;
        } else if (val & MIPSNET_INTCTL_RXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_RXDONE;
        } else if (val & MIPSNET_INTCTL_TESTBIT) {
            mipsnet_reset(s);
            s->intctl |= MIPSNET_INTCTL_TESTBIT;
        } else if (!val) {
            /* ACK testbit interrupt, flag was cleared on read. */
        }
        s->busy = !!s->intctl;
        mipsnet_update_irq(s);
        break;
    case MIPSNET_TX_DATA_BUFFER:
        s->tx_buffer[s->tx_written++] = val;
        if (s->tx_written == s->tx_count) {
            /* Send buffer. */
#ifdef DEBUG_MIPSNET_SEND
            printf("mipsnet: sending len=%d\n", s->tx_count);
#endif
            qemu_send_packet(s->vc, s->tx_buffer, s->tx_count);
            s->tx_count = s->tx_written = 0;
            s->intctl |= MIPSNET_INTCTL_TXDONE;
            s->busy = 1;
            mipsnet_update_irq(s);
        }
        break;
    /* Read-only registers */
    case MIPSNET_DEV_ID:
    case MIPSNET_BUSY:
    case MIPSNET_RX_DATA_COUNT:
    case MIPSNET_INTERRUPT_INFO:
    case MIPSNET_RX_DATA_BUFFER:
    default:
        break;
    }
}

static void mipsnet_save(QEMUFile *f, void *opaque)
{
    MIPSnetState *s = opaque;

    qemu_put_be32s(f, &s->busy);
    qemu_put_be32s(f, &s->rx_count);
    qemu_put_be32s(f, &s->rx_read);
    qemu_put_be32s(f, &s->tx_count);
    qemu_put_be32s(f, &s->tx_written);
    qemu_put_be32s(f, &s->intctl);
    qemu_put_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
    qemu_put_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
}

static int mipsnet_load(QEMUFile *f, void *opaque, int version_id)
{
    MIPSnetState *s = opaque;

    if (version_id > 0)
        return -EINVAL;

    qemu_get_be32s(f, &s->busy);
    qemu_get_be32s(f, &s->rx_count);
    qemu_get_be32s(f, &s->rx_read);
    qemu_get_be32s(f, &s->tx_count);
    qemu_get_be32s(f, &s->tx_written);
    qemu_get_be32s(f, &s->intctl);
    qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
    qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);

    return 0;
}

void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
{
    MIPSnetState *s;

    qemu_check_nic_model(nd, "mipsnet");

    s = qemu_mallocz(sizeof(MIPSnetState));

    register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
    register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
    register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
    register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
    register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
    register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);

    s->irq = irq;
    if (nd && nd->vlan) {
        s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
                                     mipsnet_receive, mipsnet_can_receive, s);
    } else {
        s->vc = NULL;
    }

    qemu_format_nic_info_str(s->vc, nd->macaddr);

    mipsnet_reset(s);
    register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
}
Commit	Line	Data
87ecb68b PB	1	#include "hw.h"
	2	#include "mips.h"
	3	#include "net.h"
	4	#include "isa.h"
f0fc6f8f	5
57ba97de TS	6	//#define DEBUG_MIPSNET_SEND
57ba97de TS	7	//#define DEBUG_MIPSNET_RECEIVE
f0fc6f8f	8	//#define DEBUG_MIPSNET_DATA
57ba97de	9	//#define DEBUG_MIPSNET_IRQ
f0fc6f8f TS	10
	11	/* MIPSnet register offsets */
	12
	13	#define MIPSNET_DEV_ID 0x00
f0fc6f8f TS	14	#define MIPSNET_BUSY 0x08
	15	#define MIPSNET_RX_DATA_COUNT 0x0c
	16	#define MIPSNET_TX_DATA_COUNT 0x10
	17	#define MIPSNET_INT_CTL 0x14
	18	# define MIPSNET_INTCTL_TXDONE 0x00000001
	19	# define MIPSNET_INTCTL_RXDONE 0x00000002
	20	# define MIPSNET_INTCTL_TESTBIT 0x80000000
	21	#define MIPSNET_INTERRUPT_INFO 0x18
	22	#define MIPSNET_RX_DATA_BUFFER 0x1c
	23	#define MIPSNET_TX_DATA_BUFFER 0x20
	24
	25	#define MAX_ETH_FRAME_SIZE 1514
	26
	27	typedef struct MIPSnetState {
	28	uint32_t busy;
	29	uint32_t rx_count;
	30	uint32_t rx_read;
	31	uint32_t tx_count;
	32	uint32_t tx_written;
	33	uint32_t intctl;
	34	uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
	35	uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
	36	qemu_irq irq;
	37	VLANClientState *vc;
f0fc6f8f TS	38	} MIPSnetState;
	39
	40	static void mipsnet_reset(MIPSnetState *s)
	41	{
	42	s->busy = 1;
	43	s->rx_count = 0;
	44	s->rx_read = 0;
	45	s->tx_count = 0;
	46	s->tx_written = 0;
	47	s->intctl = 0;
	48	memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
	49	memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
	50	}
	51
	52	static void mipsnet_update_irq(MIPSnetState *s)
	53	{
	54	int isr = !!s->intctl;
	55	#ifdef DEBUG_MIPSNET_IRQ
	56	printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
	57	#endif
	58	qemu_set_irq(s->irq, isr);
	59	}
	60
	61	static int mipsnet_buffer_full(MIPSnetState *s)
	62	{
	63	if (s->rx_count >= MAX_ETH_FRAME_SIZE)
	64	return 1;
	65	return 0;
	66	}
	67
	68	static int mipsnet_can_receive(void *opaque)
	69	{
	70	MIPSnetState *s = opaque;
	71
	72	if (s->busy)
	73	return 0;
	74	return !mipsnet_buffer_full(s);
	75	}
	76
	77	static void mipsnet_receive(void opaque, const uint8_t buf, int size)
	78	{
	79	MIPSnetState *s = opaque;
	80
	81	#ifdef DEBUG_MIPSNET_RECEIVE
	82	printf("mipsnet: receiving len=%d\n", size);
	83	#endif
	84	if (!mipsnet_can_receive(opaque))
	85	return;
	86
	87	s->busy = 1;
	88
	89	/* Just accept everything. */
	90
	91	/* Write packet data. */
	92	memcpy(s->rx_buffer, buf, size);
	93
	94	s->rx_count = size;
	95	s->rx_read = 0;
	96
	97	/* Now we can signal we have received something. */
	98	s->intctl \|= MIPSNET_INTCTL_RXDONE;
	99	mipsnet_update_irq(s);
	100	}
	101
102	static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr)
103	{
104	MIPSnetState *s = opaque;
105	int ret = 0;
f0fc6f8f TS	106
	107	addr &= 0x3f;
	108	switch (addr) {
	109	case MIPSNET_DEV_ID:
9b595395	110	ret = be32_to_cpu(0x4d495053); /* MIPS */
f0fc6f8f TS	111	break;
f0fc6f8f TS	112	case MIPSNET_DEV_ID + 4:
9b595395	113	ret = be32_to_cpu(0x4e455430); /* NET0 */
f0fc6f8f TS	114	break;
	115	case MIPSNET_BUSY:
	116	ret = s->busy;
	117	break;
	118	case MIPSNET_RX_DATA_COUNT:
	119	ret = s->rx_count;
	120	break;
	121	case MIPSNET_TX_DATA_COUNT:
	122	ret = s->tx_count;
	123	break;
	124	case MIPSNET_INT_CTL:
	125	ret = s->intctl;
	126	s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
	127	break;
	128	case MIPSNET_INTERRUPT_INFO:
	129	/* XXX: This seems to be a per-VPE interrupt number. */
	130	ret = 0;
	131	break;
	132	case MIPSNET_RX_DATA_BUFFER:
	133	if (s->rx_count) {
	134	s->rx_count--;
	135	ret = s->rx_buffer[s->rx_read++];
	136	}
	137	break;
	138	/* Reads as zero. */
	139	case MIPSNET_TX_DATA_BUFFER:
	140	default:
	141	break;
	142	}
	143	#ifdef DEBUG_MIPSNET_DATA
	144	printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
	145	#endif
	146	return ret;
	147	}
	148
	149	static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val)
	150	{
	151	MIPSnetState *s = opaque;
	152
	153	addr &= 0x3f;
	154	#ifdef DEBUG_MIPSNET_DATA
	155	printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
	156	#endif
	157	switch (addr) {
	158	case MIPSNET_TX_DATA_COUNT:
	159	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
	160	s->tx_written = 0;
	161	break;
	162	case MIPSNET_INT_CTL:
	163	if (val & MIPSNET_INTCTL_TXDONE) {
	164	s->intctl &= ~MIPSNET_INTCTL_TXDONE;
	165	} else if (val & MIPSNET_INTCTL_RXDONE) {
	166	s->intctl &= ~MIPSNET_INTCTL_RXDONE;
	167	} else if (val & MIPSNET_INTCTL_TESTBIT) {
	168	mipsnet_reset(s);
	169	s->intctl \|= MIPSNET_INTCTL_TESTBIT;
	170	} else if (!val) {
	171	/* ACK testbit interrupt, flag was cleared on read. */
	172	}
	173	s->busy = !!s->intctl;
	174	mipsnet_update_irq(s);
	175	break;
	176	case MIPSNET_TX_DATA_BUFFER:
	177	s->tx_buffer[s->tx_written++] = val;
178	if (s->tx_written == s->tx_count) {
179	/* Send buffer. */
180	#ifdef DEBUG_MIPSNET_SEND
181	printf("mipsnet: sending len=%d\n", s->tx_count);
182	#endif
183	qemu_send_packet(s->vc, s->tx_buffer, s->tx_count);
184	s->tx_count = s->tx_written = 0;
185	s->intctl \|= MIPSNET_INTCTL_TXDONE;
186	s->busy = 1;
187	mipsnet_update_irq(s);
188	}
189	break;
190	/* Read-only registers */
191	case MIPSNET_DEV_ID:
192	case MIPSNET_BUSY:
193	case MIPSNET_RX_DATA_COUNT:
194	case MIPSNET_INTERRUPT_INFO:
195	case MIPSNET_RX_DATA_BUFFER:
196	default:
197	break;
198	}
199	}
200
201	static void mipsnet_save(QEMUFile f, void opaque)
202	{
203	MIPSnetState *s = opaque;
204
205	qemu_put_be32s(f, &s->busy);
206	qemu_put_be32s(f, &s->rx_count);
207	qemu_put_be32s(f, &s->rx_read);
208	qemu_put_be32s(f, &s->tx_count);
209	qemu_put_be32s(f, &s->tx_written);
210	qemu_put_be32s(f, &s->intctl);
211	qemu_put_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
212	qemu_put_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
213	}
214
215	static int mipsnet_load(QEMUFile f, void opaque, int version_id)
216	{
217	MIPSnetState *s = opaque;
218
219	if (version_id > 0)
220	return -EINVAL;
221
222	qemu_get_be32s(f, &s->busy);
223	qemu_get_be32s(f, &s->rx_count);
224	qemu_get_be32s(f, &s->rx_read);
225	qemu_get_be32s(f, &s->tx_count);
226	qemu_get_be32s(f, &s->tx_written);
227	qemu_get_be32s(f, &s->intctl);
228	qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
229	qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
230
231	return 0;
232	}
233
234	void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
235	{
236	MIPSnetState *s;
237
0ae18cee AL	238	qemu_check_nic_model(nd, "mipsnet");
0ae18cee AL	239
f0fc6f8f	240	s = qemu_mallocz(sizeof(MIPSnetState));
f0fc6f8f TS	241
	242	register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
	243	register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
	244	register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
	245	register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
	246	register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
	247	register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
	248
	249	s->irq = irq;
f0fc6f8f	250	if (nd && nd->vlan) {
7a9f6e4a	251	s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
bf38c1a0	252	mipsnet_receive, mipsnet_can_receive, s);
f0fc6f8f TS	253	} else {
	254	s->vc = NULL;
	255	}
	256
ad067148	257	qemu_format_nic_info_str(s->vc, nd->macaddr);
f0fc6f8f TS	258
	259	mipsnet_reset(s);
	260	register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
	261	}