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f19410ca MW |
1 | /* |
2 | * QEMU model of the LatticeMico32 system control block. | |
3 | * | |
4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | /* | |
21 | * This model is mainly intended for testing purposes and doesn't fit to any | |
22 | * real hardware. On the one hand it provides a control register (R_CTRL) on | |
23 | * the other hand it supports the lm32 tests. | |
24 | * | |
25 | * A write to the control register causes a system shutdown. | |
26 | * Tests first write the pointer to a test name to the test name register | |
27 | * (R_TESTNAME) and then write a zero to the pass/fail register (R_PASSFAIL) if | |
28 | * the test is passed or any non-zero value to it if the test is failed. | |
29 | */ | |
30 | ||
83c9f4ca PB |
31 | #include "hw/hw.h" |
32 | #include "hw/sysbus.h" | |
f19410ca | 33 | #include "trace.h" |
1de7afc9 PB |
34 | #include "qemu/log.h" |
35 | #include "qemu/error-report.h" | |
9c17d615 | 36 | #include "sysemu/sysemu.h" |
f19410ca MW |
37 | |
38 | enum { | |
39 | R_CTRL = 0, | |
40 | R_PASSFAIL, | |
41 | R_TESTNAME, | |
42 | R_MAX | |
43 | }; | |
44 | ||
45 | #define MAX_TESTNAME_LEN 16 | |
46 | ||
816d323b AF |
47 | #define TYPE_LM32_SYS "lm32-sys" |
48 | #define LM32_SYS(obj) OBJECT_CHECK(LM32SysState, (obj), TYPE_LM32_SYS) | |
49 | ||
f19410ca | 50 | struct LM32SysState { |
816d323b AF |
51 | SysBusDevice parent_obj; |
52 | ||
0aa27efa | 53 | MemoryRegion iomem; |
f19410ca MW |
54 | uint32_t base; |
55 | uint32_t regs[R_MAX]; | |
56 | uint8_t testname[MAX_TESTNAME_LEN]; | |
57 | }; | |
58 | typedef struct LM32SysState LM32SysState; | |
59 | ||
60 | static void copy_testname(LM32SysState *s) | |
61 | { | |
62 | cpu_physical_memory_read(s->regs[R_TESTNAME], s->testname, | |
63 | MAX_TESTNAME_LEN); | |
64 | s->testname[MAX_TESTNAME_LEN - 1] = '\0'; | |
65 | } | |
66 | ||
a8170e5e | 67 | static void sys_write(void *opaque, hwaddr addr, |
0aa27efa | 68 | uint64_t value, unsigned size) |
f19410ca MW |
69 | { |
70 | LM32SysState *s = opaque; | |
71 | char *testname; | |
72 | ||
73 | trace_lm32_sys_memory_write(addr, value); | |
74 | ||
75 | addr >>= 2; | |
76 | switch (addr) { | |
77 | case R_CTRL: | |
78 | qemu_system_shutdown_request(); | |
79 | break; | |
80 | case R_PASSFAIL: | |
81 | s->regs[addr] = value; | |
82 | testname = (char *)s->testname; | |
83 | qemu_log("TC %-16s %s\n", testname, (value) ? "FAILED" : "OK"); | |
84 | break; | |
85 | case R_TESTNAME: | |
86 | s->regs[addr] = value; | |
87 | copy_testname(s); | |
88 | break; | |
89 | ||
90 | default: | |
dd3d6775 | 91 | error_report("lm32_sys: write access to unknown register 0x" |
f19410ca MW |
92 | TARGET_FMT_plx, addr << 2); |
93 | break; | |
94 | } | |
95 | } | |
96 | ||
a8170e5e | 97 | static bool sys_ops_accepts(void *opaque, hwaddr addr, |
0aa27efa BC |
98 | unsigned size, bool is_write) |
99 | { | |
100 | return is_write && size == 4; | |
101 | } | |
f19410ca | 102 | |
0aa27efa BC |
103 | static const MemoryRegionOps sys_ops = { |
104 | .write = sys_write, | |
105 | .valid.accepts = sys_ops_accepts, | |
106 | .endianness = DEVICE_NATIVE_ENDIAN, | |
f19410ca MW |
107 | }; |
108 | ||
109 | static void sys_reset(DeviceState *d) | |
110 | { | |
816d323b | 111 | LM32SysState *s = LM32_SYS(d); |
f19410ca MW |
112 | int i; |
113 | ||
114 | for (i = 0; i < R_MAX; i++) { | |
115 | s->regs[i] = 0; | |
116 | } | |
117 | memset(s->testname, 0, MAX_TESTNAME_LEN); | |
118 | } | |
119 | ||
120 | static int lm32_sys_init(SysBusDevice *dev) | |
121 | { | |
816d323b | 122 | LM32SysState *s = LM32_SYS(dev); |
f19410ca | 123 | |
3c161542 PB |
124 | memory_region_init_io(&s->iomem, OBJECT(dev), &sys_ops , s, |
125 | "sys", R_MAX * 4); | |
750ecd44 | 126 | sysbus_init_mmio(dev, &s->iomem); |
f19410ca MW |
127 | |
128 | /* Note: This device is not created in the board initialization, | |
129 | * instead it has to be added with the -device parameter. Therefore, | |
130 | * the device maps itself. */ | |
131 | sysbus_mmio_map(dev, 0, s->base); | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | static const VMStateDescription vmstate_lm32_sys = { | |
137 | .name = "lm32-sys", | |
138 | .version_id = 1, | |
139 | .minimum_version_id = 1, | |
140 | .minimum_version_id_old = 1, | |
141 | .fields = (VMStateField[]) { | |
142 | VMSTATE_UINT32_ARRAY(regs, LM32SysState, R_MAX), | |
143 | VMSTATE_BUFFER(testname, LM32SysState), | |
144 | VMSTATE_END_OF_LIST() | |
145 | } | |
146 | }; | |
147 | ||
999e12bb AL |
148 | static Property lm32_sys_properties[] = { |
149 | DEFINE_PROP_UINT32("base", LM32SysState, base, 0xffff0000), | |
150 | DEFINE_PROP_END_OF_LIST(), | |
151 | }; | |
152 | ||
153 | static void lm32_sys_class_init(ObjectClass *klass, void *data) | |
154 | { | |
39bffca2 | 155 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
156 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
157 | ||
158 | k->init = lm32_sys_init; | |
39bffca2 AL |
159 | dc->reset = sys_reset; |
160 | dc->vmsd = &vmstate_lm32_sys; | |
161 | dc->props = lm32_sys_properties; | |
999e12bb AL |
162 | } |
163 | ||
8c43a6f0 | 164 | static const TypeInfo lm32_sys_info = { |
816d323b | 165 | .name = TYPE_LM32_SYS, |
39bffca2 AL |
166 | .parent = TYPE_SYS_BUS_DEVICE, |
167 | .instance_size = sizeof(LM32SysState), | |
168 | .class_init = lm32_sys_class_init, | |
f19410ca MW |
169 | }; |
170 | ||
83f7d43a | 171 | static void lm32_sys_register_types(void) |
f19410ca | 172 | { |
39bffca2 | 173 | type_register_static(&lm32_sys_info); |
f19410ca MW |
174 | } |
175 | ||
83f7d43a | 176 | type_init(lm32_sys_register_types) |