[qemu.git] / hw / msix.c

/*
 * MSI-X device support
 *
 * This module includes support for MSI-X in pci devices.
 *
 * Author: Michael S. Tsirkin <mst@redhat.com>
 *
 *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */

#include "hw.h"
#include "msi.h"
#include "msix.h"
#include "pci.h"
#include "range.h"

#define MSIX_CAP_LENGTH 12

/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)

/* How much space does an MSIX table need. */
/* The spec requires giving the table structure
 * a 4K aligned region all by itself. */
#define MSIX_PAGE_SIZE 0x1000
/* Reserve second half of the page for pending bits */
#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
#define MSIX_MAX_ENTRIES 32

static MSIMessage msix_get_message(PCIDevice *dev, unsigned vector)
{
    uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
    MSIMessage msg;

    msg.address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
    msg.data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
    return msg;
}

/* Add MSI-X capability to the config space for the device. */
/* Given a bar and its size, add MSI-X table on top of it
 * and fill MSI-X capability in the config space.
 * Original bar size must be a power of 2 or 0.
 * New bar size is returned. */
static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
                           unsigned bar_nr, unsigned bar_size)
{
    int config_offset;
    uint8_t *config;
    uint32_t new_size;

    if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
        return -EINVAL;
    if (bar_size > 0x80000000)
        return -ENOSPC;

    /* Add space for MSI-X structures */
    if (!bar_size) {
        new_size = MSIX_PAGE_SIZE;
    } else if (bar_size < MSIX_PAGE_SIZE) {
        bar_size = MSIX_PAGE_SIZE;
        new_size = MSIX_PAGE_SIZE * 2;
    } else {
        new_size = bar_size * 2;
    }

    pdev->msix_bar_size = new_size;
    config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
                                       0, MSIX_CAP_LENGTH);
    if (config_offset < 0)
        return config_offset;
    config = pdev->config + config_offset;

    pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
    /* Table on top of BAR */
    pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr);
    /* Pending bits on top of that */
    pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) |
                 bar_nr);
    pdev->msix_cap = config_offset;
    /* Make flags bit writable. */
    pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
	    MSIX_MASKALL_MASK;
    pdev->msix_function_masked = true;
    return 0;
}

static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
                               unsigned size)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    void *page = dev->msix_table_page;

    return pci_get_long(page + offset);
}

static uint8_t msix_pending_mask(int vector)
{
    return 1 << (vector % 8);
}

static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
{
    return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
}

static int msix_is_pending(PCIDevice *dev, int vector)
{
    return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
}

static void msix_set_pending(PCIDevice *dev, int vector)
{
    *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
}

static void msix_clr_pending(PCIDevice *dev, int vector)
{
    *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
}

static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
{
    unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
    return fmask || dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
}

static bool msix_is_masked(PCIDevice *dev, int vector)
{
    return msix_vector_masked(dev, vector, dev->msix_function_masked);
}

static void msix_fire_vector_notifier(PCIDevice *dev,
                                      unsigned int vector, bool is_masked)
{
    MSIMessage msg;
    int ret;

    if (!dev->msix_vector_use_notifier) {
        return;
    }
    if (is_masked) {
        dev->msix_vector_release_notifier(dev, vector);
    } else {
        msg = msix_get_message(dev, vector);
        ret = dev->msix_vector_use_notifier(dev, vector, msg);
        assert(ret >= 0);
    }
}

static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
{
    bool is_masked = msix_is_masked(dev, vector);

    if (is_masked == was_masked) {
        return;
    }

    msix_fire_vector_notifier(dev, vector, is_masked);

    if (!is_masked && msix_is_pending(dev, vector)) {
        msix_clr_pending(dev, vector);
        msix_notify(dev, vector);
    }
}

static void msix_update_function_masked(PCIDevice *dev)
{
    dev->msix_function_masked = !msix_enabled(dev) ||
        (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
}

/* Handle MSI-X capability config write. */
void msix_write_config(PCIDevice *dev, uint32_t addr,
                       uint32_t val, int len)
{
    unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
    int vector;
    bool was_masked;

    if (!range_covers_byte(addr, len, enable_pos)) {
        return;
    }

    was_masked = dev->msix_function_masked;
    msix_update_function_masked(dev);

    if (!msix_enabled(dev)) {
        return;
    }

    pci_device_deassert_intx(dev);

    if (dev->msix_function_masked == was_masked) {
        return;
    }

    for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
        msix_handle_mask_update(dev, vector,
                                msix_vector_masked(dev, vector, was_masked));
    }
}

static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
                            uint64_t val, unsigned size)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    int vector = offset / PCI_MSIX_ENTRY_SIZE;
    bool was_masked;

    /* MSI-X page includes a read-only PBA and a writeable Vector Control. */
    if (vector >= dev->msix_entries_nr) {
        return;
    }

    was_masked = msix_is_masked(dev, vector);
    pci_set_long(dev->msix_table_page + offset, val);
    msix_handle_mask_update(dev, vector, was_masked);
}

static const MemoryRegionOps msix_mmio_ops = {
    .read = msix_mmio_read,
    .write = msix_mmio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
{
    uint8_t *config = d->config + d->msix_cap;
    uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
    uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
    /* TODO: for assigned devices, we'll want to make it possible to map
     * pending bits separately in case they are in a separate bar. */

    memory_region_add_subregion(bar, offset, &d->msix_mmio);
}

static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
{
    int vector;

    for (vector = 0; vector < nentries; ++vector) {
        unsigned offset =
            vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
        bool was_masked = msix_is_masked(dev, vector);

        dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
        msix_handle_mask_update(dev, vector, was_masked);
    }
}

/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 * modified, it should be retrieved with msix_bar_size. */
int msix_init(struct PCIDevice *dev, unsigned short nentries,
              MemoryRegion *bar,
              unsigned bar_nr, unsigned bar_size)
{
    int ret;

    /* Nothing to do if MSI is not supported by interrupt controller */
    if (!msi_supported) {
        return -ENOTSUP;
    }
    if (nentries > MSIX_MAX_ENTRIES)
        return -EINVAL;

    dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
                                        sizeof *dev->msix_entry_used);

    dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
    msix_mask_all(dev, nentries);

    memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
                          "msix", MSIX_PAGE_SIZE);

    dev->msix_entries_nr = nentries;
    ret = msix_add_config(dev, nentries, bar_nr, bar_size);
    if (ret)
        goto err_config;

    dev->cap_present |= QEMU_PCI_CAP_MSIX;
    msix_mmio_setup(dev, bar);
    return 0;

err_config:
    dev->msix_entries_nr = 0;
    memory_region_destroy(&dev->msix_mmio);
    g_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    g_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    return ret;
}

static void msix_free_irq_entries(PCIDevice *dev)
{
    int vector;

    for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
        dev->msix_entry_used[vector] = 0;
        msix_clr_pending(dev, vector);
    }
}

/* Clean up resources for the device. */
int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return 0;
    pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
    dev->msix_cap = 0;
    msix_free_irq_entries(dev);
    dev->msix_entries_nr = 0;
    memory_region_del_subregion(bar, &dev->msix_mmio);
    memory_region_destroy(&dev->msix_mmio);
    g_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    g_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
    return 0;
}

void msix_save(PCIDevice *dev, QEMUFile *f)
{
    unsigned n = dev->msix_entries_nr;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
        return;
    }

    qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
    qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
}

/* Should be called after restoring the config space. */
void msix_load(PCIDevice *dev, QEMUFile *f)
{
    unsigned n = dev->msix_entries_nr;
    unsigned int vector;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
        return;
    }

    msix_free_irq_entries(dev);
    qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
    qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
    msix_update_function_masked(dev);

    for (vector = 0; vector < n; vector++) {
        msix_handle_mask_update(dev, vector, true);
    }
}

/* Does device support MSI-X? */
int msix_present(PCIDevice *dev)
{
    return dev->cap_present & QEMU_PCI_CAP_MSIX;
}

/* Is MSI-X enabled? */
int msix_enabled(PCIDevice *dev)
{
    return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
        (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
         MSIX_ENABLE_MASK);
}

/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
uint32_t msix_bar_size(PCIDevice *dev)
{
    return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
        dev->msix_bar_size : 0;
}

/* Send an MSI-X message */
void msix_notify(PCIDevice *dev, unsigned vector)
{
    MSIMessage msg;

    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
        return;
    if (msix_is_masked(dev, vector)) {
        msix_set_pending(dev, vector);
        return;
    }

    msg = msix_get_message(dev, vector);

    stl_le_phys(msg.address, msg.data);
}

void msix_reset(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return;
    msix_free_irq_entries(dev);
    dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
	    ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
    memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
    msix_mask_all(dev, dev->msix_entries_nr);
}

/* PCI spec suggests that devices make it possible for software to configure
 * less vectors than supported by the device, but does not specify a standard
 * mechanism for devices to do so.
 *
 * We support this by asking devices to declare vectors software is going to
 * actually use, and checking this on the notification path. Devices that
 * don't want to follow the spec suggestion can declare all vectors as used. */

/* Mark vector as used. */
int msix_vector_use(PCIDevice *dev, unsigned vector)
{
    if (vector >= dev->msix_entries_nr)
        return -EINVAL;
    dev->msix_entry_used[vector]++;
    return 0;
}

/* Mark vector as unused. */
void msix_vector_unuse(PCIDevice *dev, unsigned vector)
{
    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
        return;
    }
    if (--dev->msix_entry_used[vector]) {
        return;
    }
    msix_clr_pending(dev, vector);
}

void msix_unuse_all_vectors(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return;
    msix_free_irq_entries(dev);
}

static int msix_set_notifier_for_vector(PCIDevice *dev, unsigned int vector)
{
    MSIMessage msg;

    if (msix_is_masked(dev, vector)) {
        return 0;
    }
    msg = msix_get_message(dev, vector);
    return dev->msix_vector_use_notifier(dev, vector, msg);
}

static void msix_unset_notifier_for_vector(PCIDevice *dev, unsigned int vector)
{
    if (msix_is_masked(dev, vector)) {
        return;
    }
    dev->msix_vector_release_notifier(dev, vector);
}

int msix_set_vector_notifiers(PCIDevice *dev,
                              MSIVectorUseNotifier use_notifier,
                              MSIVectorReleaseNotifier release_notifier)
{
    int vector, ret;

    assert(use_notifier && release_notifier);

    dev->msix_vector_use_notifier = use_notifier;
    dev->msix_vector_release_notifier = release_notifier;

    if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
        (MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) {
        for (vector = 0; vector < dev->msix_entries_nr; vector++) {
            ret = msix_set_notifier_for_vector(dev, vector);
            if (ret < 0) {
                goto undo;
            }
        }
    }
    return 0;

undo:
    while (--vector >= 0) {
        msix_unset_notifier_for_vector(dev, vector);
    }
    dev->msix_vector_use_notifier = NULL;
    dev->msix_vector_release_notifier = NULL;
    return ret;
}

void msix_unset_vector_notifiers(PCIDevice *dev)
{
    int vector;

    assert(dev->msix_vector_use_notifier &&
           dev->msix_vector_release_notifier);

    if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
        (MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) {
        for (vector = 0; vector < dev->msix_entries_nr; vector++) {
            msix_unset_notifier_for_vector(dev, vector);
        }
    }
    dev->msix_vector_use_notifier = NULL;
    dev->msix_vector_release_notifier = NULL;
}
Commit	Line	Data
02eb84d0 MT	1	/*
	2	* MSI-X device support
	3	*
	4	* This module includes support for MSI-X in pci devices.
	5	*
	6	* Author: Michael S. Tsirkin <mst@redhat.com>
	7	*
	8	* Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
	9	*
	10	* This work is licensed under the terms of the GNU GPL, version 2. See
	11	* the COPYING file in the top-level directory.
6b620ca3 PB	12	*
	13	* Contributions after 2012-01-13 are licensed under the terms of the
	14	* GNU GPL, version 2 or (at your option) any later version.
02eb84d0 MT	15	*/
	16
	17	#include "hw.h"
60ba3cc2	18	#include "msi.h"
02eb84d0 MT	19	#include "msix.h"
02eb84d0 MT	20	#include "pci.h"
bf1b0071	21	#include "range.h"
02eb84d0	22
02eb84d0 MT	23	#define MSIX_CAP_LENGTH 12
02eb84d0 MT	24
2760952b MT	25	/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
2760952b MT	26	#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
02eb84d0	27	#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
5b5cb086	28	#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
02eb84d0	29
5a1fc5e8 MT	30	/* How much space does an MSIX table need. */
	31	/* The spec requires giving the table structure
	32	* a 4K aligned region all by itself. */
	33	#define MSIX_PAGE_SIZE 0x1000
	34	/* Reserve second half of the page for pending bits */
	35	#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
02eb84d0 MT	36	#define MSIX_MAX_ENTRIES 32
02eb84d0 MT	37
bc4caf49 JK	38	static MSIMessage msix_get_message(PCIDevice *dev, unsigned vector)
	39	{
	40	uint8_t table_entry = dev->msix_table_page + vector PCI_MSIX_ENTRY_SIZE;
	41	MSIMessage msg;
	42
	43	msg.address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
	44	msg.data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
	45	return msg;
	46	}
02eb84d0	47
02eb84d0 MT	48	/* Add MSI-X capability to the config space for the device. */
	49	/* Given a bar and its size, add MSI-X table on top of it
	50	* and fill MSI-X capability in the config space.
	51	* Original bar size must be a power of 2 or 0.
	52	* New bar size is returned. */
	53	static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
	54	unsigned bar_nr, unsigned bar_size)
	55	{
	56	int config_offset;
	57	uint8_t *config;
	58	uint32_t new_size;
	59
	60	if (nentries < 1 \|\| nentries > PCI_MSIX_FLAGS_QSIZE + 1)
	61	return -EINVAL;
	62	if (bar_size > 0x80000000)
	63	return -ENOSPC;
	64
	65	/* Add space for MSI-X structures */
5e520a7d	66	if (!bar_size) {
5a1fc5e8 MT	67	new_size = MSIX_PAGE_SIZE;
	68	} else if (bar_size < MSIX_PAGE_SIZE) {
	69	bar_size = MSIX_PAGE_SIZE;
	70	new_size = MSIX_PAGE_SIZE * 2;
	71	} else {
02eb84d0	72	new_size = bar_size * 2;
5a1fc5e8	73	}
02eb84d0 MT	74
02eb84d0 MT	75	pdev->msix_bar_size = new_size;
ca77089d IY	76	config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
ca77089d IY	77	0, MSIX_CAP_LENGTH);
02eb84d0 MT	78	if (config_offset < 0)
	79	return config_offset;
	80	config = pdev->config + config_offset;
	81
	82	pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
	83	/* Table on top of BAR */
01731cfb	84	pci_set_long(config + PCI_MSIX_TABLE, bar_size \| bar_nr);
02eb84d0	85	/* Pending bits on top of that */
01731cfb	86	pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) \|
5a1fc5e8	87	bar_nr);
02eb84d0	88	pdev->msix_cap = config_offset;
ebabb67a	89	/* Make flags bit writable. */
5b5cb086 MT	90	pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] \|= MSIX_ENABLE_MASK \|
5b5cb086 MT	91	MSIX_MASKALL_MASK;
50322249	92	pdev->msix_function_masked = true;
02eb84d0 MT	93	return 0;
	94	}
	95
95524ae8 AK	96	static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
95524ae8 AK	97	unsigned size)
02eb84d0 MT	98	{
02eb84d0 MT	99	PCIDevice *dev = opaque;
76f5159d	100	unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
02eb84d0	101	void *page = dev->msix_table_page;
02eb84d0	102
76f5159d	103	return pci_get_long(page + offset);
02eb84d0 MT	104	}
02eb84d0 MT	105
02eb84d0 MT	106	static uint8_t msix_pending_mask(int vector)
	107	{
	108	return 1 << (vector % 8);
	109	}
	110
	111	static uint8_t msix_pending_byte(PCIDevice dev, int vector)
	112	{
5a1fc5e8	113	return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
02eb84d0 MT	114	}
	115
	116	static int msix_is_pending(PCIDevice *dev, int vector)
	117	{
	118	return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
	119	}
	120
	121	static void msix_set_pending(PCIDevice *dev, int vector)
	122	{
	123	*msix_pending_byte(dev, vector) \|= msix_pending_mask(vector);
	124	}
	125
	126	static void msix_clr_pending(PCIDevice *dev, int vector)
	127	{
	128	*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
	129	}
	130
ae392c41	131	static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
02eb84d0	132	{
ae392c41 MT	133	unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
ae392c41 MT	134	return fmask \|\| dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
5b5cb086 MT	135	}
5b5cb086 MT	136
ae392c41	137	static bool msix_is_masked(PCIDevice *dev, int vector)
5b5cb086	138	{
ae392c41 MT	139	return msix_vector_masked(dev, vector, dev->msix_function_masked);
	140	}
	141
2cdfe53c JK	142	static void msix_fire_vector_notifier(PCIDevice *dev,
	143	unsigned int vector, bool is_masked)
	144	{
	145	MSIMessage msg;
	146	int ret;
	147
	148	if (!dev->msix_vector_use_notifier) {
	149	return;
	150	}
	151	if (is_masked) {
	152	dev->msix_vector_release_notifier(dev, vector);
	153	} else {
	154	msg = msix_get_message(dev, vector);
	155	ret = dev->msix_vector_use_notifier(dev, vector, msg);
	156	assert(ret >= 0);
	157	}
	158	}
	159
ae392c41 MT	160	static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
	161	{
	162	bool is_masked = msix_is_masked(dev, vector);
2cdfe53c	163
ae392c41 MT	164	if (is_masked == was_masked) {
	165	return;
	166	}
	167
2cdfe53c JK	168	msix_fire_vector_notifier(dev, vector, is_masked);
2cdfe53c JK	169
ae392c41	170	if (!is_masked && msix_is_pending(dev, vector)) {
5b5cb086 MT	171	msix_clr_pending(dev, vector);
	172	msix_notify(dev, vector);
	173	}
	174	}
	175
50322249 MT	176	static void msix_update_function_masked(PCIDevice *dev)
	177	{
	178	dev->msix_function_masked = !msix_enabled(dev) \|\|
	179	(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
	180	}
	181
5b5cb086 MT	182	/* Handle MSI-X capability config write. */
	183	void msix_write_config(PCIDevice *dev, uint32_t addr,
	184	uint32_t val, int len)
	185	{
	186	unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
	187	int vector;
50322249	188	bool was_masked;
5b5cb086	189
98a3cb02	190	if (!range_covers_byte(addr, len, enable_pos)) {
5b5cb086 MT	191	return;
	192	}
	193
50322249 MT	194	was_masked = dev->msix_function_masked;
	195	msix_update_function_masked(dev);
	196
5b5cb086 MT	197	if (!msix_enabled(dev)) {
	198	return;
	199	}
	200
e407bf13	201	pci_device_deassert_intx(dev);
5b5cb086	202
50322249	203	if (dev->msix_function_masked == was_masked) {
5b5cb086 MT	204	return;
	205	}
	206
	207	for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
ae392c41 MT	208	msix_handle_mask_update(dev, vector,
ae392c41 MT	209	msix_vector_masked(dev, vector, was_masked));
5b5cb086	210	}
02eb84d0 MT	211	}
02eb84d0 MT	212
95524ae8 AK	213	static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
95524ae8 AK	214	uint64_t val, unsigned size)
02eb84d0 MT	215	{
02eb84d0 MT	216	PCIDevice *dev = opaque;
76f5159d	217	unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
01731cfb	218	int vector = offset / PCI_MSIX_ENTRY_SIZE;
ae392c41	219	bool was_masked;
9a93b617 MT	220
	221	/* MSI-X page includes a read-only PBA and a writeable Vector Control. */
	222	if (vector >= dev->msix_entries_nr) {
	223	return;
	224	}
	225
ae392c41	226	was_masked = msix_is_masked(dev, vector);
76f5159d	227	pci_set_long(dev->msix_table_page + offset, val);
ae392c41	228	msix_handle_mask_update(dev, vector, was_masked);
02eb84d0 MT	229	}
02eb84d0 MT	230
95524ae8 AK	231	static const MemoryRegionOps msix_mmio_ops = {
	232	.read = msix_mmio_read,
	233	.write = msix_mmio_write,
	234	.endianness = DEVICE_NATIVE_ENDIAN,
	235	.valid = {
	236	.min_access_size = 4,
	237	.max_access_size = 4,
	238	},
02eb84d0 MT	239	};
02eb84d0 MT	240
95524ae8	241	static void msix_mmio_setup(PCIDevice d, MemoryRegion bar)
02eb84d0 MT	242	{
02eb84d0 MT	243	uint8_t *config = d->config + d->msix_cap;
01731cfb	244	uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
5a1fc5e8	245	uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
02eb84d0 MT	246	/* TODO: for assigned devices, we'll want to make it possible to map
02eb84d0 MT	247	* pending bits separately in case they are in a separate bar. */
02eb84d0	248
95524ae8	249	memory_region_add_subregion(bar, offset, &d->msix_mmio);
02eb84d0 MT	250	}
02eb84d0 MT	251
ae1be0bb MT	252	static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
	253	{
	254	int vector;
5b5f1330	255
ae1be0bb	256	for (vector = 0; vector < nentries; ++vector) {
01731cfb JK	257	unsigned offset =
01731cfb JK	258	vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
5b5f1330 JK	259	bool was_masked = msix_is_masked(dev, vector);
5b5f1330 JK	260
01731cfb	261	dev->msix_table_page[offset] \|= PCI_MSIX_ENTRY_CTRL_MASKBIT;
5b5f1330	262	msix_handle_mask_update(dev, vector, was_masked);
ae1be0bb MT	263	}
	264	}
	265
02eb84d0 MT	266	/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
	267	* modified, it should be retrieved with msix_bar_size. */
	268	int msix_init(struct PCIDevice *dev, unsigned short nentries,
95524ae8	269	MemoryRegion *bar,
5a1fc5e8	270	unsigned bar_nr, unsigned bar_size)
02eb84d0 MT	271	{
02eb84d0 MT	272	int ret;
60ba3cc2	273
02eb84d0	274	/* Nothing to do if MSI is not supported by interrupt controller */
60ba3cc2	275	if (!msi_supported) {
02eb84d0	276	return -ENOTSUP;
60ba3cc2	277	}
02eb84d0 MT	278	if (nentries > MSIX_MAX_ENTRIES)
	279	return -EINVAL;
	280
7267c094	281	dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
02eb84d0 MT	282	sizeof *dev->msix_entry_used);
02eb84d0 MT	283
7267c094	284	dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
ae1be0bb	285	msix_mask_all(dev, nentries);
02eb84d0	286
95524ae8 AK	287	memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
95524ae8 AK	288	"msix", MSIX_PAGE_SIZE);
02eb84d0 MT	289
	290	dev->msix_entries_nr = nentries;
	291	ret = msix_add_config(dev, nentries, bar_nr, bar_size);
	292	if (ret)
	293	goto err_config;
	294
	295	dev->cap_present \|= QEMU_PCI_CAP_MSIX;
95524ae8	296	msix_mmio_setup(dev, bar);
02eb84d0 MT	297	return 0;
	298
	299	err_config:
3174ecd1	300	dev->msix_entries_nr = 0;
95524ae8	301	memory_region_destroy(&dev->msix_mmio);
7267c094	302	g_free(dev->msix_table_page);
02eb84d0	303	dev->msix_table_page = NULL;
7267c094	304	g_free(dev->msix_entry_used);
02eb84d0 MT	305	dev->msix_entry_used = NULL;
	306	return ret;
	307	}
	308
98304c84 MT	309	static void msix_free_irq_entries(PCIDevice *dev)
	310	{
	311	int vector;
	312
	313	for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
	314	dev->msix_entry_used[vector] = 0;
	315	msix_clr_pending(dev, vector);
	316	}
	317	}
	318
02eb84d0	319	/* Clean up resources for the device. */
95524ae8	320	int msix_uninit(PCIDevice dev, MemoryRegion bar)
02eb84d0 MT	321	{
	322	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	323	return 0;
	324	pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
	325	dev->msix_cap = 0;
	326	msix_free_irq_entries(dev);
	327	dev->msix_entries_nr = 0;
95524ae8 AK	328	memory_region_del_subregion(bar, &dev->msix_mmio);
95524ae8 AK	329	memory_region_destroy(&dev->msix_mmio);
7267c094	330	g_free(dev->msix_table_page);
02eb84d0	331	dev->msix_table_page = NULL;
7267c094	332	g_free(dev->msix_entry_used);
02eb84d0 MT	333	dev->msix_entry_used = NULL;
	334	dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
	335	return 0;
	336	}
	337
	338	void msix_save(PCIDevice dev, QEMUFile f)
	339	{
9a3e12c8 MT	340	unsigned n = dev->msix_entries_nr;
9a3e12c8 MT	341
72755a70	342	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
9a3e12c8	343	return;
72755a70	344	}
9a3e12c8	345
01731cfb	346	qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
5a1fc5e8	347	qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
02eb84d0 MT	348	}
	349
	350	/* Should be called after restoring the config space. */
	351	void msix_load(PCIDevice dev, QEMUFile f)
	352	{
	353	unsigned n = dev->msix_entries_nr;
2cdfe53c	354	unsigned int vector;
02eb84d0	355
98846d73	356	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
02eb84d0	357	return;
98846d73	358	}
02eb84d0	359
4bfd1712	360	msix_free_irq_entries(dev);
01731cfb	361	qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
5a1fc5e8	362	qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
50322249	363	msix_update_function_masked(dev);
2cdfe53c JK	364
	365	for (vector = 0; vector < n; vector++) {
	366	msix_handle_mask_update(dev, vector, true);
	367	}
02eb84d0 MT	368	}
	369
	370	/* Does device support MSI-X? */
	371	int msix_present(PCIDevice *dev)
	372	{
	373	return dev->cap_present & QEMU_PCI_CAP_MSIX;
	374	}
	375
	376	/* Is MSI-X enabled? */
	377	int msix_enabled(PCIDevice *dev)
	378	{
	379	return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
2760952b	380	(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
02eb84d0 MT	381	MSIX_ENABLE_MASK);
	382	}
	383
	384	/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
	385	uint32_t msix_bar_size(PCIDevice *dev)
	386	{
	387	return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
	388	dev->msix_bar_size : 0;
	389	}
	390
	391	/* Send an MSI-X message */
	392	void msix_notify(PCIDevice *dev, unsigned vector)
	393	{
bc4caf49	394	MSIMessage msg;
02eb84d0 MT	395
	396	if (vector >= dev->msix_entries_nr \|\| !dev->msix_entry_used[vector])
	397	return;
	398	if (msix_is_masked(dev, vector)) {
	399	msix_set_pending(dev, vector);
	400	return;
	401	}
	402
bc4caf49 JK	403	msg = msix_get_message(dev, vector);
	404
	405	stl_le_phys(msg.address, msg.data);
02eb84d0 MT	406	}
	407
	408	void msix_reset(PCIDevice *dev)
	409	{
	410	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	411	return;
	412	msix_free_irq_entries(dev);
2760952b MT	413	dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
2760952b MT	414	~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
5a1fc5e8	415	memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
ae1be0bb	416	msix_mask_all(dev, dev->msix_entries_nr);
02eb84d0 MT	417	}
	418
	419	/* PCI spec suggests that devices make it possible for software to configure
	420	* less vectors than supported by the device, but does not specify a standard
	421	* mechanism for devices to do so.
	422	*
	423	* We support this by asking devices to declare vectors software is going to
	424	* actually use, and checking this on the notification path. Devices that
	425	* don't want to follow the spec suggestion can declare all vectors as used. */
	426
	427	/* Mark vector as used. */
	428	int msix_vector_use(PCIDevice *dev, unsigned vector)
	429	{
	430	if (vector >= dev->msix_entries_nr)
	431	return -EINVAL;
	432	dev->msix_entry_used[vector]++;
	433	return 0;
	434	}
	435
	436	/* Mark vector as unused. */
	437	void msix_vector_unuse(PCIDevice *dev, unsigned vector)
	438	{
98304c84 MT	439	if (vector >= dev->msix_entries_nr \|\| !dev->msix_entry_used[vector]) {
	440	return;
	441	}
	442	if (--dev->msix_entry_used[vector]) {
	443	return;
	444	}
	445	msix_clr_pending(dev, vector);
02eb84d0	446	}
b5f28bca MT	447
	448	void msix_unuse_all_vectors(PCIDevice *dev)
	449	{
	450	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	451	return;
	452	msix_free_irq_entries(dev);
	453	}
2cdfe53c JK	454
	455	static int msix_set_notifier_for_vector(PCIDevice *dev, unsigned int vector)
	456	{
	457	MSIMessage msg;
	458
	459	if (msix_is_masked(dev, vector)) {
	460	return 0;
	461	}
	462	msg = msix_get_message(dev, vector);
	463	return dev->msix_vector_use_notifier(dev, vector, msg);
	464	}
	465
	466	static void msix_unset_notifier_for_vector(PCIDevice *dev, unsigned int vector)
	467	{
	468	if (msix_is_masked(dev, vector)) {
	469	return;
	470	}
	471	dev->msix_vector_release_notifier(dev, vector);
	472	}
	473
	474	int msix_set_vector_notifiers(PCIDevice *dev,
	475	MSIVectorUseNotifier use_notifier,
	476	MSIVectorReleaseNotifier release_notifier)
	477	{
	478	int vector, ret;
	479
	480	assert(use_notifier && release_notifier);
	481
	482	dev->msix_vector_use_notifier = use_notifier;
	483	dev->msix_vector_release_notifier = release_notifier;
	484
	485	if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
	486	(MSIX_ENABLE_MASK \| MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) {
	487	for (vector = 0; vector < dev->msix_entries_nr; vector++) {
	488	ret = msix_set_notifier_for_vector(dev, vector);
	489	if (ret < 0) {
	490	goto undo;
	491	}
	492	}
	493	}
	494	return 0;
	495
	496	undo:
	497	while (--vector >= 0) {
	498	msix_unset_notifier_for_vector(dev, vector);
	499	}
	500	dev->msix_vector_use_notifier = NULL;
	501	dev->msix_vector_release_notifier = NULL;
	502	return ret;
	503	}
	504
	505	void msix_unset_vector_notifiers(PCIDevice *dev)
	506	{
	507	int vector;
	508
	509	assert(dev->msix_vector_use_notifier &&
	510	dev->msix_vector_release_notifier);
	511
	512	if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
	513	(MSIX_ENABLE_MASK \| MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) {
	514	for (vector = 0; vector < dev->msix_entries_nr; vector++) {
	515	msix_unset_notifier_for_vector(dev, vector);
	516	}
	517	}
518	dev->msix_vector_use_notifier = NULL;
519	dev->msix_vector_release_notifier = NULL;
520	}