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gdbstub: Drop redundant memset after qemu_mallocz (Jan Kiszka)
[qemu.git] / hw / musicpal.c
CommitLineData
24859b68
AZ		 1/*
2 * Marvell MV88W8618 / Freecom MusicPal emulation.
3 *
4 * Copyright (c) 2008 Jan Kiszka
5 *
6 * This code is licenced under the GNU GPL v2.
7 */
8
9#include "hw.h"
10#include "arm-misc.h"
11#include "devices.h"
12#include "net.h"
13#include "sysemu.h"
14#include "boards.h"
15#include "pc.h"
16#include "qemu-timer.h"
17#include "block.h"
18#include "flash.h"
19#include "console.h"
20#include "audio/audio.h"
21#include "i2c.h"
22
718ec0be 23#define MP_MISC_BASE 0x80002000
24#define MP_MISC_SIZE 0x00001000
25
24859b68
AZ		 26#define MP_ETH_BASE 0x80008000
27#define MP_ETH_SIZE 0x00001000
28
718ec0be 29#define MP_WLAN_BASE 0x8000C000
30#define MP_WLAN_SIZE 0x00000800
31
24859b68
AZ		 32#define MP_UART1_BASE 0x8000C840
33#define MP_UART2_BASE 0x8000C940
34
718ec0be 35#define MP_GPIO_BASE 0x8000D000
36#define MP_GPIO_SIZE 0x00001000
37
24859b68
AZ		 38#define MP_FLASHCFG_BASE 0x90006000
39#define MP_FLASHCFG_SIZE 0x00001000
40
41#define MP_AUDIO_BASE 0x90007000
42#define MP_AUDIO_SIZE 0x00001000
43
44#define MP_PIC_BASE 0x90008000
45#define MP_PIC_SIZE 0x00001000
46
47#define MP_PIT_BASE 0x90009000
48#define MP_PIT_SIZE 0x00001000
49
50#define MP_LCD_BASE 0x9000c000
51#define MP_LCD_SIZE 0x00001000
52
53#define MP_SRAM_BASE 0xC0000000
54#define MP_SRAM_SIZE 0x00020000
55
56#define MP_RAM_DEFAULT_SIZE 32*1024*1024
57#define MP_FLASH_SIZE_MAX 32*1024*1024
58
59#define MP_TIMER1_IRQ 4
60/* ... */
61#define MP_TIMER4_IRQ 7
62#define MP_EHCI_IRQ 8
63#define MP_ETH_IRQ 9
64#define MP_UART1_IRQ 11
65#define MP_UART2_IRQ 11
66#define MP_GPIO_IRQ 12
67#define MP_RTC_IRQ 28
68#define MP_AUDIO_IRQ 30
69
70static uint32_t gpio_in_state = 0xffffffff;
7c6ce4ba 71static uint32_t gpio_isr;
24859b68
AZ		 72static uint32_t gpio_out_state;
73static ram_addr_t sram_off;
74
75/* Address conversion helpers */
76static void *target2host_addr(uint32_t addr)
77{
78 if (addr < MP_SRAM_BASE) {
79 if (addr >= MP_RAM_DEFAULT_SIZE)
80 return NULL;
81 return (void *)(phys_ram_base + addr);
82 } else {
83 if (addr >= MP_SRAM_BASE + MP_SRAM_SIZE)
84 return NULL;
85 return (void *)(phys_ram_base + sram_off + addr - MP_SRAM_BASE);
86 }
87}
88
89static uint32_t host2target_addr(void *addr)
90{
91 if (addr < ((void *)phys_ram_base) + sram_off)
92 return (unsigned long)addr - (unsigned long)phys_ram_base;
93 else
94 return (unsigned long)addr - (unsigned long)phys_ram_base -
95 sram_off + MP_SRAM_BASE;
96}
97
98
99typedef enum i2c_state {
100 STOPPED = 0,
101 INITIALIZING,
102 SENDING_BIT7,
103 SENDING_BIT6,
104 SENDING_BIT5,
105 SENDING_BIT4,
106 SENDING_BIT3,
107 SENDING_BIT2,
108 SENDING_BIT1,
109 SENDING_BIT0,
110 WAITING_FOR_ACK,
111 RECEIVING_BIT7,
112 RECEIVING_BIT6,
113 RECEIVING_BIT5,
114 RECEIVING_BIT4,
115 RECEIVING_BIT3,
116 RECEIVING_BIT2,
117 RECEIVING_BIT1,
118 RECEIVING_BIT0,
119 SENDING_ACK
120} i2c_state;
121
122typedef struct i2c_interface {
123 i2c_bus *bus;
124 i2c_state state;
125 int last_data;
126 int last_clock;
127 uint8_t buffer;
128 int current_addr;
129} i2c_interface;
130
131static void i2c_enter_stop(i2c_interface *i2c)
132{
133 if (i2c->current_addr >= 0)
134 i2c_end_transfer(i2c->bus);
135 i2c->current_addr = -1;
136 i2c->state = STOPPED;
137}
138
139static void i2c_state_update(i2c_interface *i2c, int data, int clock)
140{
141 if (!i2c)
142 return;
143
144 switch (i2c->state) {
145 case STOPPED:
146 if (data == 0 && i2c->last_data == 1 && clock == 1)
147 i2c->state = INITIALIZING;
148 break;
149
150 case INITIALIZING:
151 if (clock == 0 && i2c->last_clock == 1 && data == 0)
152 i2c->state = SENDING_BIT7;
153 else
154 i2c_enter_stop(i2c);
155 break;
156
157 case SENDING_BIT7 ... SENDING_BIT0:
158 if (clock == 0 && i2c->last_clock == 1) {
159 i2c->buffer = (i2c->buffer << 1) | data;
160 i2c->state++; /* will end up in WAITING_FOR_ACK */
161 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
162 i2c_enter_stop(i2c);
163 break;
164
165 case WAITING_FOR_ACK:
166 if (clock == 0 && i2c->last_clock == 1) {
167 if (i2c->current_addr < 0) {
168 i2c->current_addr = i2c->buffer;
169 i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
170 i2c->buffer & 1);
171 } else
172 i2c_send(i2c->bus, i2c->buffer);
173 if (i2c->current_addr & 1) {
174 i2c->state = RECEIVING_BIT7;
175 i2c->buffer = i2c_recv(i2c->bus);
176 } else
177 i2c->state = SENDING_BIT7;
178 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
179 i2c_enter_stop(i2c);
180 break;
181
182 case RECEIVING_BIT7 ... RECEIVING_BIT0:
183 if (clock == 0 && i2c->last_clock == 1) {
184 i2c->state++; /* will end up in SENDING_ACK */
185 i2c->buffer <<= 1;
186 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
187 i2c_enter_stop(i2c);
188 break;
189
190 case SENDING_ACK:
191 if (clock == 0 && i2c->last_clock == 1) {
192 i2c->state = RECEIVING_BIT7;
193 if (data == 0)
194 i2c->buffer = i2c_recv(i2c->bus);
195 else
196 i2c_nack(i2c->bus);
197 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
198 i2c_enter_stop(i2c);
199 break;
200 }
201
202 i2c->last_data = data;
203 i2c->last_clock = clock;
204}
205
206static int i2c_get_data(i2c_interface *i2c)
207{
208 if (!i2c)
209 return 0;
210
211 switch (i2c->state) {
212 case RECEIVING_BIT7 ... RECEIVING_BIT0:
213 return (i2c->buffer >> 7);
214
215 case WAITING_FOR_ACK:
216 default:
217 return 0;
218 }
219}
220
221static i2c_interface *mixer_i2c;
222
223#ifdef HAS_AUDIO
224
225/* Audio register offsets */
226#define MP_AUDIO_PLAYBACK_MODE 0x00
227#define MP_AUDIO_CLOCK_DIV 0x18
228#define MP_AUDIO_IRQ_STATUS 0x20
229#define MP_AUDIO_IRQ_ENABLE 0x24
230#define MP_AUDIO_TX_START_LO 0x28
231#define MP_AUDIO_TX_THRESHOLD 0x2C
232#define MP_AUDIO_TX_STATUS 0x38
233#define MP_AUDIO_TX_START_HI 0x40
234
235/* Status register and IRQ enable bits */
236#define MP_AUDIO_TX_HALF (1 << 6)
237#define MP_AUDIO_TX_FULL (1 << 7)
238
239/* Playback mode bits */
240#define MP_AUDIO_16BIT_SAMPLE (1 << 0)
241#define MP_AUDIO_PLAYBACK_EN (1 << 7)
242#define MP_AUDIO_CLOCK_24MHZ (1 << 9)
4001a81e 243#define MP_AUDIO_MONO (1 << 14)
24859b68
AZ		 244
245/* Wolfson 8750 I2C address */
246#define MP_WM_ADDR 0x34
247
b1d8e52e 248static const char audio_name[] = "mv88w8618";
24859b68
AZ		 249
250typedef struct musicpal_audio_state {
24859b68
AZ		 251 qemu_irq irq;
252 uint32_t playback_mode;
253 uint32_t status;
254 uint32_t irq_enable;
255 unsigned long phys_buf;
a350e694 256 int8_t *target_buffer;
24859b68
AZ		 257 unsigned int threshold;
258 unsigned int play_pos;
259 unsigned int last_free;
260 uint32_t clock_div;
261 i2c_slave *wm;
262} musicpal_audio_state;
263
264static void audio_callback(void *opaque, int free_out, int free_in)
265{
266 musicpal_audio_state *s = opaque;
4f3cb3be 267 int16_t *codec_buffer;
a350e694 268 int8_t *mem_buffer;
24859b68
AZ		 269 int pos, block_size;
270
271 if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
272 return;
273
274 if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
4001a81e
AZ		 275 free_out <<= 1;
276
277 if (!(s->playback_mode & MP_AUDIO_MONO))
24859b68
AZ		 278 free_out <<= 1;
279
280 block_size = s->threshold/2;
281 if (free_out - s->last_free < block_size)
282 return;
283
4001a81e
AZ		 284 mem_buffer = s->target_buffer + s->play_pos;
285 if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
286 if (s->playback_mode & MP_AUDIO_MONO) {
287 codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
288 for (pos = 0; pos < block_size; pos += 2) {
a350e694
AZ		 289 *codec_buffer++ = *(int16_t *)mem_buffer;
290 *codec_buffer++ = *(int16_t *)mem_buffer;
4f3cb3be 291 mem_buffer += 2;
4001a81e
AZ		 292 }
293 } else
294 memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
295 (uint32_t *)mem_buffer, block_size);
296 } else {
297 if (s->playback_mode & MP_AUDIO_MONO) {
298 codec_buffer = wm8750_dac_buffer(s->wm, block_size);
299 for (pos = 0; pos < block_size; pos++) {
a350e694
AZ		 300 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer);
301 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
4001a81e
AZ		 302 }
303 } else {
304 codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
305 for (pos = 0; pos < block_size; pos += 2) {
a350e694
AZ		 306 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
307 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
4001a81e 308 }
24859b68 309 }
662caa6f
AZ		 310 }
311 wm8750_dac_commit(s->wm);
24859b68
AZ		 312
313 s->last_free = free_out - block_size;
314
315 if (s->play_pos == 0) {
316 s->status |= MP_AUDIO_TX_HALF;
317 s->play_pos = block_size;
318 } else {
319 s->status |= MP_AUDIO_TX_FULL;
320 s->play_pos = 0;
321 }
322
323 if (s->status & s->irq_enable)
324 qemu_irq_raise(s->irq);
325}
326
af83e09e
AZ		 327static void musicpal_audio_clock_update(musicpal_audio_state *s)
328{
329 int rate;
330
331 if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
332 rate = 24576000 / 64; /* 24.576MHz */
333 else
334 rate = 11289600 / 64; /* 11.2896MHz */
335
336 rate /= ((s->clock_div >> 8) & 0xff) + 1;
337
91834991 338 wm8750_set_bclk_in(s->wm, rate);
af83e09e
AZ		 339}
340
24859b68
AZ		 341static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset)
342{
343 musicpal_audio_state *s = opaque;
344
24859b68
AZ		 345 switch (offset) {
346 case MP_AUDIO_PLAYBACK_MODE:
347 return s->playback_mode;
348
349 case MP_AUDIO_CLOCK_DIV:
350 return s->clock_div;
351
352 case MP_AUDIO_IRQ_STATUS:
353 return s->status;
354
355 case MP_AUDIO_IRQ_ENABLE:
356 return s->irq_enable;
357
358 case MP_AUDIO_TX_STATUS:
359 return s->play_pos >> 2;
360
361 default:
362 return 0;
363 }
364}
365
366static void musicpal_audio_write(void *opaque, target_phys_addr_t offset,
367 uint32_t value)
368{
369 musicpal_audio_state *s = opaque;
370
24859b68
AZ		 371 switch (offset) {
372 case MP_AUDIO_PLAYBACK_MODE:
373 if (value & MP_AUDIO_PLAYBACK_EN &&
374 !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
375 s->status = 0;
376 s->last_free = 0;
377 s->play_pos = 0;
378 }
379 s->playback_mode = value;
af83e09e 380 musicpal_audio_clock_update(s);
24859b68
AZ		 381 break;
382
383 case MP_AUDIO_CLOCK_DIV:
384 s->clock_div = value;
385 s->last_free = 0;
386 s->play_pos = 0;
af83e09e 387 musicpal_audio_clock_update(s);
24859b68
AZ		 388 break;
389
390 case MP_AUDIO_IRQ_STATUS:
391 s->status &= ~value;
392 break;
393
394 case MP_AUDIO_IRQ_ENABLE:
395 s->irq_enable = value;
396 if (s->status & s->irq_enable)
397 qemu_irq_raise(s->irq);
398 break;
399
400 case MP_AUDIO_TX_START_LO:
401 s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
402 s->target_buffer = target2host_addr(s->phys_buf);
403 s->play_pos = 0;
404 s->last_free = 0;
405 break;
406
407 case MP_AUDIO_TX_THRESHOLD:
408 s->threshold = (value + 1) * 4;
409 break;
410
411 case MP_AUDIO_TX_START_HI:
412 s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
413 s->target_buffer = target2host_addr(s->phys_buf);
414 s->play_pos = 0;
415 s->last_free = 0;
416 break;
417 }
418}
419
420static void musicpal_audio_reset(void *opaque)
421{
422 musicpal_audio_state *s = opaque;
423
424 s->playback_mode = 0;
425 s->status = 0;
426 s->irq_enable = 0;
427}
428
429static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
430 musicpal_audio_read,
431 musicpal_audio_read,
432 musicpal_audio_read
433};
434
435static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
436 musicpal_audio_write,
437 musicpal_audio_write,
438 musicpal_audio_write
439};
440
718ec0be 441static i2c_interface *musicpal_audio_init(qemu_irq irq)
24859b68
AZ		 442{
443 AudioState *audio;
444 musicpal_audio_state *s;
445 i2c_interface *i2c;
446 int iomemtype;
447
448 audio = AUD_init();
449 if (!audio) {
450 AUD_log(audio_name, "No audio state\n");
451 return NULL;
452 }
453
454 s = qemu_mallocz(sizeof(musicpal_audio_state));
24859b68
AZ		 455 s->irq = irq;
456
457 i2c = qemu_mallocz(sizeof(i2c_interface));
24859b68
AZ		 458 i2c->bus = i2c_init_bus();
459 i2c->current_addr = -1;
460
461 s->wm = wm8750_init(i2c->bus, audio);
462 if (!s->wm)
463 return NULL;
464 i2c_set_slave_address(s->wm, MP_WM_ADDR);
465 wm8750_data_req_set(s->wm, audio_callback, s);
466
467 iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
468 musicpal_audio_writefn, s);
718ec0be 469 cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);
24859b68
AZ		 470
471 qemu_register_reset(musicpal_audio_reset, s);
472
473 return i2c;
474}
475#else /* !HAS_AUDIO */
718ec0be 476static i2c_interface *musicpal_audio_init(qemu_irq irq)
24859b68
AZ		 477{
478 return NULL;
479}
480#endif /* !HAS_AUDIO */
481
482/* Ethernet register offsets */
483#define MP_ETH_SMIR 0x010
484#define MP_ETH_PCXR 0x408
485#define MP_ETH_SDCMR 0x448
486#define MP_ETH_ICR 0x450
487#define MP_ETH_IMR 0x458
488#define MP_ETH_FRDP0 0x480
489#define MP_ETH_FRDP1 0x484
490#define MP_ETH_FRDP2 0x488
491#define MP_ETH_FRDP3 0x48C
492#define MP_ETH_CRDP0 0x4A0
493#define MP_ETH_CRDP1 0x4A4
494#define MP_ETH_CRDP2 0x4A8
495#define MP_ETH_CRDP3 0x4AC
496#define MP_ETH_CTDP0 0x4E0
497#define MP_ETH_CTDP1 0x4E4
498#define MP_ETH_CTDP2 0x4E8
499#define MP_ETH_CTDP3 0x4EC
500
501/* MII PHY access */
502#define MP_ETH_SMIR_DATA 0x0000FFFF
503#define MP_ETH_SMIR_ADDR 0x03FF0000
504#define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */
505#define MP_ETH_SMIR_RDVALID (1 << 27)
506
507/* PHY registers */
508#define MP_ETH_PHY1_BMSR 0x00210000
509#define MP_ETH_PHY1_PHYSID1 0x00410000
510#define MP_ETH_PHY1_PHYSID2 0x00610000
511
512#define MP_PHY_BMSR_LINK 0x0004
513#define MP_PHY_BMSR_AUTONEG 0x0008
514
515#define MP_PHY_88E3015 0x01410E20
516
517/* TX descriptor status */
518#define MP_ETH_TX_OWN (1 << 31)
519
520/* RX descriptor status */
521#define MP_ETH_RX_OWN (1 << 31)
522
523/* Interrupt cause/mask bits */
524#define MP_ETH_IRQ_RX_BIT 0
525#define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT)
526#define MP_ETH_IRQ_TXHI_BIT 2
527#define MP_ETH_IRQ_TXLO_BIT 3
528
529/* Port config bits */
530#define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */
531
532/* SDMA command bits */
533#define MP_ETH_CMD_TXHI (1 << 23)
534#define MP_ETH_CMD_TXLO (1 << 22)
535
536typedef struct mv88w8618_tx_desc {
537 uint32_t cmdstat;
538 uint16_t res;
539 uint16_t bytes;
540 uint32_t buffer;
541 uint32_t next;
542} mv88w8618_tx_desc;
543
544typedef struct mv88w8618_rx_desc {
545 uint32_t cmdstat;
546 uint16_t bytes;
547 uint16_t buffer_size;
548 uint32_t buffer;
549 uint32_t next;
550} mv88w8618_rx_desc;
551
552typedef struct mv88w8618_eth_state {
24859b68
AZ		 553 qemu_irq irq;
554 uint32_t smir;
555 uint32_t icr;
556 uint32_t imr;
557 int vlan_header;
558 mv88w8618_tx_desc *tx_queue[2];
559 mv88w8618_rx_desc *rx_queue[4];
560 mv88w8618_rx_desc *frx_queue[4];
561 mv88w8618_rx_desc *cur_rx[4];
562 VLANClientState *vc;
563} mv88w8618_eth_state;
564
565static int eth_can_receive(void *opaque)
566{
567 return 1;
568}
569
570static void eth_receive(void *opaque, const uint8_t *buf, int size)
571{
572 mv88w8618_eth_state *s = opaque;
573 mv88w8618_rx_desc *desc;
574 int i;
575
576 for (i = 0; i < 4; i++) {
577 desc = s->cur_rx[i];
578 if (!desc)
579 continue;
580 do {
581 if (le32_to_cpu(desc->cmdstat) & MP_ETH_RX_OWN &&
582 le16_to_cpu(desc->buffer_size) >= size) {
583 memcpy(target2host_addr(le32_to_cpu(desc->buffer) +
584 s->vlan_header),
585 buf, size);
586 desc->bytes = cpu_to_le16(size + s->vlan_header);
587 desc->cmdstat &= cpu_to_le32(~MP_ETH_RX_OWN);
588 s->cur_rx[i] = target2host_addr(le32_to_cpu(desc->next));
589
590 s->icr |= MP_ETH_IRQ_RX;
591 if (s->icr & s->imr)
592 qemu_irq_raise(s->irq);
593 return;
594 }
595 desc = target2host_addr(le32_to_cpu(desc->next));
596 } while (desc != s->rx_queue[i]);
597 }
598}
599
600static void eth_send(mv88w8618_eth_state *s, int queue_index)
601{
602 mv88w8618_tx_desc *desc = s->tx_queue[queue_index];
603
604 do {
605 if (le32_to_cpu(desc->cmdstat) & MP_ETH_TX_OWN) {
606 qemu_send_packet(s->vc,
607 target2host_addr(le32_to_cpu(desc->buffer)),
608 le16_to_cpu(desc->bytes));
609 desc->cmdstat &= cpu_to_le32(~MP_ETH_TX_OWN);
610 s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
611 }
612 desc = target2host_addr(le32_to_cpu(desc->next));
613 } while (desc != s->tx_queue[queue_index]);
614}
615
616static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
617{
618 mv88w8618_eth_state *s = opaque;
619
24859b68
AZ		 620 switch (offset) {
621 case MP_ETH_SMIR:
622 if (s->smir & MP_ETH_SMIR_OPCODE) {
623 switch (s->smir & MP_ETH_SMIR_ADDR) {
624 case MP_ETH_PHY1_BMSR:
625 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
626 MP_ETH_SMIR_RDVALID;
627 case MP_ETH_PHY1_PHYSID1:
628 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
629 case MP_ETH_PHY1_PHYSID2:
630 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
631 default:
632 return MP_ETH_SMIR_RDVALID;
633 }
634 }
635 return 0;
636
637 case MP_ETH_ICR:
638 return s->icr;
639
640 case MP_ETH_IMR:
641 return s->imr;
642
643 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
644 return host2target_addr(s->frx_queue[(offset - MP_ETH_FRDP0)/4]);
645
646 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
647 return host2target_addr(s->rx_queue[(offset - MP_ETH_CRDP0)/4]);
648
649 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
650 return host2target_addr(s->tx_queue[(offset - MP_ETH_CTDP0)/4]);
651
652 default:
653 return 0;
654 }
655}
656
657static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
658 uint32_t value)
659{
660 mv88w8618_eth_state *s = opaque;
661
24859b68
AZ		 662 switch (offset) {
663 case MP_ETH_SMIR:
664 s->smir = value;
665 break;
666
667 case MP_ETH_PCXR:
668 s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
669 break;
670
671 case MP_ETH_SDCMR:
672 if (value & MP_ETH_CMD_TXHI)
673 eth_send(s, 1);
674 if (value & MP_ETH_CMD_TXLO)
675 eth_send(s, 0);
676 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
677 qemu_irq_raise(s->irq);
678 break;
679
680 case MP_ETH_ICR:
681 s->icr &= value;
682 break;
683
684 case MP_ETH_IMR:
685 s->imr = value;
686 if (s->icr & s->imr)
687 qemu_irq_raise(s->irq);
688 break;
689
690 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
691 s->frx_queue[(offset - MP_ETH_FRDP0)/4] = target2host_addr(value);
692 break;
693
694 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
695 s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
696 s->cur_rx[(offset - MP_ETH_CRDP0)/4] = target2host_addr(value);
697 break;
698
699 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
700 s->tx_queue[(offset - MP_ETH_CTDP0)/4] = target2host_addr(value);
701 break;
702 }
703}
704
705static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
706 mv88w8618_eth_read,
707 mv88w8618_eth_read,
708 mv88w8618_eth_read
709};
710
711static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
712 mv88w8618_eth_write,
713 mv88w8618_eth_write,
714 mv88w8618_eth_write
715};
716
717static void mv88w8618_eth_init(NICInfo *nd, uint32_t base, qemu_irq irq)
718{
719 mv88w8618_eth_state *s;
720 int iomemtype;
721
0ae18cee
AL		 722 qemu_check_nic_model(nd, "mv88w8618");
723
24859b68 724 s = qemu_mallocz(sizeof(mv88w8618_eth_state));
24859b68 725 s->irq = irq;
7a9f6e4a 726 s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
bf38c1a0 727 eth_receive, eth_can_receive, s);
24859b68
AZ		 728 iomemtype = cpu_register_io_memory(0, mv88w8618_eth_readfn,
729 mv88w8618_eth_writefn, s);
730 cpu_register_physical_memory(base, MP_ETH_SIZE, iomemtype);
731}
732
733/* LCD register offsets */
734#define MP_LCD_IRQCTRL 0x180
735#define MP_LCD_IRQSTAT 0x184
736#define MP_LCD_SPICTRL 0x1ac
737#define MP_LCD_INST 0x1bc
738#define MP_LCD_DATA 0x1c0
739
740/* Mode magics */
741#define MP_LCD_SPI_DATA 0x00100011
742#define MP_LCD_SPI_CMD 0x00104011
743#define MP_LCD_SPI_INVALID 0x00000000
744
745/* Commmands */
746#define MP_LCD_INST_SETPAGE0 0xB0
747/* ... */
748#define MP_LCD_INST_SETPAGE7 0xB7
749
750#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
751
752typedef struct musicpal_lcd_state {
24859b68
AZ		 753 uint32_t mode;
754 uint32_t irqctrl;
755 int page;
756 int page_off;
757 DisplayState *ds;
758 uint8_t video_ram[128*64/8];
759} musicpal_lcd_state;
760
761static uint32_t lcd_brightness;
762
763static uint8_t scale_lcd_color(uint8_t col)
764{
765 int tmp = col;
766
767 switch (lcd_brightness) {
768 case 0x00000007: /* 0 */
769 return 0;
770
771 case 0x00020000: /* 1 */
772 return (tmp * 1) / 7;
773
774 case 0x00020001: /* 2 */
775 return (tmp * 2) / 7;
776
777 case 0x00040000: /* 3 */
778 return (tmp * 3) / 7;
779
780 case 0x00010006: /* 4 */
781 return (tmp * 4) / 7;
782
783 case 0x00020005: /* 5 */
784 return (tmp * 5) / 7;
785
786 case 0x00040003: /* 6 */
787 return (tmp * 6) / 7;
788
789 case 0x00030004: /* 7 */
790 default:
791 return col;
792 }
793}
794
0266f2c7
AZ		 795#define SET_LCD_PIXEL(depth, type) \
796static inline void glue(set_lcd_pixel, depth) \
797 (musicpal_lcd_state *s, int x, int y, type col) \
798{ \
799 int dx, dy; \
0e1f5a0c 800 type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
0266f2c7
AZ		 801\
802 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
803 for (dx = 0; dx < 3; dx++, pixel++) \
804 *pixel = col; \
24859b68 805}
0266f2c7
AZ		 806SET_LCD_PIXEL(8, uint8_t)
807SET_LCD_PIXEL(16, uint16_t)
808SET_LCD_PIXEL(32, uint32_t)
809
810#include "pixel_ops.h"
24859b68
AZ		 811
812static void lcd_refresh(void *opaque)
813{
814 musicpal_lcd_state *s = opaque;
0266f2c7 815 int x, y, col;
24859b68 816
0e1f5a0c 817 switch (ds_get_bits_per_pixel(s->ds)) {
0266f2c7
AZ		 818 case 0:
819 return;
820#define LCD_REFRESH(depth, func) \
821 case depth: \
822 col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \
823 scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \
824 scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
825 for (x = 0; x < 128; x++) \
826 for (y = 0; y < 64; y++) \
827 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
828 glue(set_lcd_pixel, depth)(s, x, y, col); \
829 else \
830 glue(set_lcd_pixel, depth)(s, x, y, 0); \
831 break;
832 LCD_REFRESH(8, rgb_to_pixel8)
833 LCD_REFRESH(16, rgb_to_pixel16)
7b5d76da 834 LCD_REFRESH(32, (is_surface_bgr(s->ds) ? rgb_to_pixel32bgr : rgb_to_pixel32))
0266f2c7
AZ		 835 default:
836 cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
0e1f5a0c 837 ds_get_bits_per_pixel(s->ds));
0266f2c7 838 }
24859b68
AZ		 839
840 dpy_update(s->ds, 0, 0, 128*3, 64*3);
841}
842
167bc3d2
AZ		 843static void lcd_invalidate(void *opaque)
844{
167bc3d2
AZ		 845}
846
24859b68
AZ		 847static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
848{
849 musicpal_lcd_state *s = opaque;
850
24859b68
AZ		 851 switch (offset) {
852 case MP_LCD_IRQCTRL:
853 return s->irqctrl;
854
855 default:
856 return 0;
857 }
858}
859
860static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
861 uint32_t value)
862{
863 musicpal_lcd_state *s = opaque;
864
24859b68
AZ		 865 switch (offset) {
866 case MP_LCD_IRQCTRL:
867 s->irqctrl = value;
868 break;
869
870 case MP_LCD_SPICTRL:
871 if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
872 s->mode = value;
873 else
874 s->mode = MP_LCD_SPI_INVALID;
875 break;
876
877 case MP_LCD_INST:
878 if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
879 s->page = value - MP_LCD_INST_SETPAGE0;
880 s->page_off = 0;
881 }
882 break;
883
884 case MP_LCD_DATA:
885 if (s->mode == MP_LCD_SPI_CMD) {
886 if (value >= MP_LCD_INST_SETPAGE0 &&
887 value <= MP_LCD_INST_SETPAGE7) {
888 s->page = value - MP_LCD_INST_SETPAGE0;
889 s->page_off = 0;
890 }
891 } else if (s->mode == MP_LCD_SPI_DATA) {
892 s->video_ram[s->page*128 + s->page_off] = value;
893 s->page_off = (s->page_off + 1) & 127;
894 }
895 break;
896 }
897}
898
899static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
900 musicpal_lcd_read,
901 musicpal_lcd_read,
902 musicpal_lcd_read
903};
904
905static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
906 musicpal_lcd_write,
907 musicpal_lcd_write,
908 musicpal_lcd_write
909};
910
718ec0be 911static void musicpal_lcd_init(void)
24859b68
AZ		 912{
913 musicpal_lcd_state *s;
914 int iomemtype;
915
916 s = qemu_mallocz(sizeof(musicpal_lcd_state));
24859b68
AZ		 917 iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
918 musicpal_lcd_writefn, s);
718ec0be 919 cpu_register_physical_memory(MP_LCD_BASE, MP_LCD_SIZE, iomemtype);
24859b68 920
3023f332
AL		 921 s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
922 NULL, NULL, s);
923 qemu_console_resize(s->ds, 128*3, 64*3);
24859b68
AZ		 924}
925
926/* PIC register offsets */
927#define MP_PIC_STATUS 0x00
928#define MP_PIC_ENABLE_SET 0x08
929#define MP_PIC_ENABLE_CLR 0x0C
930
931typedef struct mv88w8618_pic_state
932{
24859b68
AZ		 933 uint32_t level;
934 uint32_t enabled;
935 qemu_irq parent_irq;
936} mv88w8618_pic_state;
937
938static void mv88w8618_pic_update(mv88w8618_pic_state *s)
939{
940 qemu_set_irq(s->parent_irq, (s->level & s->enabled));
941}
942
943static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
944{
945 mv88w8618_pic_state *s = opaque;
946
947 if (level)
948 s->level |= 1 << irq;
949 else
950 s->level &= ~(1 << irq);
951 mv88w8618_pic_update(s);
952}
953
954static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
955{
956 mv88w8618_pic_state *s = opaque;
957
24859b68
AZ		 958 switch (offset) {
959 case MP_PIC_STATUS:
960 return s->level & s->enabled;
961
962 default:
963 return 0;
964 }
965}
966
967static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
968 uint32_t value)
969{
970 mv88w8618_pic_state *s = opaque;
971
24859b68
AZ		 972 switch (offset) {
973 case MP_PIC_ENABLE_SET:
974 s->enabled |= value;
975 break;
976
977 case MP_PIC_ENABLE_CLR:
978 s->enabled &= ~value;
979 s->level &= ~value;
980 break;
981 }
982 mv88w8618_pic_update(s);
983}
984
985static void mv88w8618_pic_reset(void *opaque)
986{
987 mv88w8618_pic_state *s = opaque;
988
989 s->level = 0;
990 s->enabled = 0;
991}
992
993static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
994 mv88w8618_pic_read,
995 mv88w8618_pic_read,
996 mv88w8618_pic_read
997};
998
999static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
1000 mv88w8618_pic_write,
1001 mv88w8618_pic_write,
1002 mv88w8618_pic_write
1003};
1004
1005static qemu_irq *mv88w8618_pic_init(uint32_t base, qemu_irq parent_irq)
1006{
1007 mv88w8618_pic_state *s;
1008 int iomemtype;
1009 qemu_irq *qi;
1010
1011 s = qemu_mallocz(sizeof(mv88w8618_pic_state));
24859b68 1012 qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
24859b68
AZ		 1013 s->parent_irq = parent_irq;
1014 iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
1015 mv88w8618_pic_writefn, s);
1016 cpu_register_physical_memory(base, MP_PIC_SIZE, iomemtype);
1017
1018 qemu_register_reset(mv88w8618_pic_reset, s);
1019
1020 return qi;
1021}
1022
1023/* PIT register offsets */
1024#define MP_PIT_TIMER1_LENGTH 0x00
1025/* ... */
1026#define MP_PIT_TIMER4_LENGTH 0x0C
1027#define MP_PIT_CONTROL 0x10
1028#define MP_PIT_TIMER1_VALUE 0x14
1029/* ... */
1030#define MP_PIT_TIMER4_VALUE 0x20
1031#define MP_BOARD_RESET 0x34
1032
1033/* Magic board reset value (probably some watchdog behind it) */
1034#define MP_BOARD_RESET_MAGIC 0x10000
1035
1036typedef struct mv88w8618_timer_state {
1037 ptimer_state *timer;
1038 uint32_t limit;
1039 int freq;
1040 qemu_irq irq;
1041} mv88w8618_timer_state;
1042
1043typedef struct mv88w8618_pit_state {
1044 void *timer[4];
1045 uint32_t control;
24859b68
AZ		 1046} mv88w8618_pit_state;
1047
1048static void mv88w8618_timer_tick(void *opaque)
1049{
1050 mv88w8618_timer_state *s = opaque;
1051
1052 qemu_irq_raise(s->irq);
1053}
1054
1055static void *mv88w8618_timer_init(uint32_t freq, qemu_irq irq)
1056{
1057 mv88w8618_timer_state *s;
1058 QEMUBH *bh;
1059
1060 s = qemu_mallocz(sizeof(mv88w8618_timer_state));
1061 s->irq = irq;
1062 s->freq = freq;
1063
1064 bh = qemu_bh_new(mv88w8618_timer_tick, s);
1065 s->timer = ptimer_init(bh);
1066
1067 return s;
1068}
1069
1070static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
1071{
1072 mv88w8618_pit_state *s = opaque;
1073 mv88w8618_timer_state *t;
1074
24859b68
AZ		 1075 switch (offset) {
1076 case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
1077 t = s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
1078 return ptimer_get_count(t->timer);
1079
1080 default:
1081 return 0;
1082 }
1083}
1084
1085static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
1086 uint32_t value)
1087{
1088 mv88w8618_pit_state *s = opaque;
1089 mv88w8618_timer_state *t;
1090 int i;
1091
24859b68
AZ		 1092 switch (offset) {
1093 case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
1094 t = s->timer[offset >> 2];
1095 t->limit = value;
1096 ptimer_set_limit(t->timer, t->limit, 1);
1097 break;
1098
1099 case MP_PIT_CONTROL:
1100 for (i = 0; i < 4; i++) {
1101 if (value & 0xf) {
1102 t = s->timer[i];
1103 ptimer_set_limit(t->timer, t->limit, 0);
1104 ptimer_set_freq(t->timer, t->freq);
1105 ptimer_run(t->timer, 0);
1106 }
1107 value >>= 4;
1108 }
1109 break;
1110
1111 case MP_BOARD_RESET:
1112 if (value == MP_BOARD_RESET_MAGIC)
1113 qemu_system_reset_request();
1114 break;
1115 }
1116}
1117
1118static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
1119 mv88w8618_pit_read,
1120 mv88w8618_pit_read,
1121 mv88w8618_pit_read
1122};
1123
1124static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
1125 mv88w8618_pit_write,
1126 mv88w8618_pit_write,
1127 mv88w8618_pit_write
1128};
1129
1130static void mv88w8618_pit_init(uint32_t base, qemu_irq *pic, int irq)
1131{
1132 int iomemtype;
1133 mv88w8618_pit_state *s;
1134
1135 s = qemu_mallocz(sizeof(mv88w8618_pit_state));
24859b68 1136
24859b68
AZ		 1137 /* Letting them all run at 1 MHz is likely just a pragmatic
1138 * simplification. */
1139 s->timer[0] = mv88w8618_timer_init(1000000, pic[irq]);
1140 s->timer[1] = mv88w8618_timer_init(1000000, pic[irq + 1]);
1141 s->timer[2] = mv88w8618_timer_init(1000000, pic[irq + 2]);
1142 s->timer[3] = mv88w8618_timer_init(1000000, pic[irq + 3]);
1143
1144 iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
1145 mv88w8618_pit_writefn, s);
1146 cpu_register_physical_memory(base, MP_PIT_SIZE, iomemtype);
1147}
1148
1149/* Flash config register offsets */
1150#define MP_FLASHCFG_CFGR0 0x04
1151
1152typedef struct mv88w8618_flashcfg_state {
24859b68
AZ		 1153 uint32_t cfgr0;
1154} mv88w8618_flashcfg_state;
1155
1156static uint32_t mv88w8618_flashcfg_read(void *opaque,
1157 target_phys_addr_t offset)
1158{
1159 mv88w8618_flashcfg_state *s = opaque;
1160
24859b68
AZ		 1161 switch (offset) {
1162 case MP_FLASHCFG_CFGR0:
1163 return s->cfgr0;
1164
1165 default:
1166 return 0;
1167 }
1168}
1169
1170static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
1171 uint32_t value)
1172{
1173 mv88w8618_flashcfg_state *s = opaque;
1174
24859b68
AZ		 1175 switch (offset) {
1176 case MP_FLASHCFG_CFGR0:
1177 s->cfgr0 = value;
1178 break;
1179 }
1180}
1181
1182static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
1183 mv88w8618_flashcfg_read,
1184 mv88w8618_flashcfg_read,
1185 mv88w8618_flashcfg_read
1186};
1187
1188static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
1189 mv88w8618_flashcfg_write,
1190 mv88w8618_flashcfg_write,
1191 mv88w8618_flashcfg_write
1192};
1193
1194static void mv88w8618_flashcfg_init(uint32_t base)
1195{
1196 int iomemtype;
1197 mv88w8618_flashcfg_state *s;
1198
1199 s = qemu_mallocz(sizeof(mv88w8618_flashcfg_state));
24859b68 1200
24859b68
AZ		 1201 s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1202 iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
1203 mv88w8618_flashcfg_writefn, s);
1204 cpu_register_physical_memory(base, MP_FLASHCFG_SIZE, iomemtype);
1205}
1206
718ec0be 1207/* Misc register offsets */
1208#define MP_MISC_BOARD_REVISION 0x18
1209
1210#define MP_BOARD_REVISION 0x31
1211
1212static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
1213{
1214 switch (offset) {
1215 case MP_MISC_BOARD_REVISION:
1216 return MP_BOARD_REVISION;
1217
1218 default:
1219 return 0;
1220 }
1221}
1222
1223static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
1224 uint32_t value)
1225{
1226}
1227
1228static CPUReadMemoryFunc *musicpal_misc_readfn[] = {
1229 musicpal_misc_read,
1230 musicpal_misc_read,
1231 musicpal_misc_read,
1232};
1233
1234static CPUWriteMemoryFunc *musicpal_misc_writefn[] = {
1235 musicpal_misc_write,
1236 musicpal_misc_write,
1237 musicpal_misc_write,
1238};
1239
1240static void musicpal_misc_init(void)
1241{
1242 int iomemtype;
1243
1244 iomemtype = cpu_register_io_memory(0, musicpal_misc_readfn,
1245 musicpal_misc_writefn, NULL);
1246 cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
1247}
1248
1249/* WLAN register offsets */
1250#define MP_WLAN_MAGIC1 0x11c
1251#define MP_WLAN_MAGIC2 0x124
1252
1253static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
1254{
1255 switch (offset) {
1256 /* Workaround to allow loading the binary-only wlandrv.ko crap
1257 * from the original Freecom firmware. */
1258 case MP_WLAN_MAGIC1:
1259 return ~3;
1260 case MP_WLAN_MAGIC2:
1261 return -1;
1262
1263 default:
1264 return 0;
1265 }
1266}
1267
1268static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
1269 uint32_t value)
1270{
1271}
1272
1273static CPUReadMemoryFunc *mv88w8618_wlan_readfn[] = {
1274 mv88w8618_wlan_read,
1275 mv88w8618_wlan_read,
1276 mv88w8618_wlan_read,
1277};
1278
1279static CPUWriteMemoryFunc *mv88w8618_wlan_writefn[] = {
1280 mv88w8618_wlan_write,
1281 mv88w8618_wlan_write,
1282 mv88w8618_wlan_write,
1283};
1284
1285static void mv88w8618_wlan_init(uint32_t base)
1286{
1287 int iomemtype;
24859b68 1288
718ec0be 1289 iomemtype = cpu_register_io_memory(0, mv88w8618_wlan_readfn,
1290 mv88w8618_wlan_writefn, NULL);
1291 cpu_register_physical_memory(base, MP_WLAN_SIZE, iomemtype);
1292}
24859b68 1293
718ec0be 1294/* GPIO register offsets */
1295#define MP_GPIO_OE_LO 0x008
1296#define MP_GPIO_OUT_LO 0x00c
1297#define MP_GPIO_IN_LO 0x010
1298#define MP_GPIO_ISR_LO 0x020
1299#define MP_GPIO_OE_HI 0x508
1300#define MP_GPIO_OUT_HI 0x50c
1301#define MP_GPIO_IN_HI 0x510
1302#define MP_GPIO_ISR_HI 0x520
24859b68
AZ		 1303
1304/* GPIO bits & masks */
1305#define MP_GPIO_WHEEL_VOL (1 << 8)
1306#define MP_GPIO_WHEEL_VOL_INV (1 << 9)
1307#define MP_GPIO_WHEEL_NAV (1 << 10)
1308#define MP_GPIO_WHEEL_NAV_INV (1 << 11)
1309#define MP_GPIO_LCD_BRIGHTNESS 0x00070000
1310#define MP_GPIO_BTN_FAVORITS (1 << 19)
1311#define MP_GPIO_BTN_MENU (1 << 20)
1312#define MP_GPIO_BTN_VOLUME (1 << 21)
1313#define MP_GPIO_BTN_NAVIGATION (1 << 22)
1314#define MP_GPIO_I2C_DATA_BIT 29
1315#define MP_GPIO_I2C_DATA (1 << MP_GPIO_I2C_DATA_BIT)
1316#define MP_GPIO_I2C_CLOCK_BIT 30
1317
1318/* LCD brightness bits in GPIO_OE_HI */
1319#define MP_OE_LCD_BRIGHTNESS 0x0007
1320
718ec0be 1321static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
24859b68 1322{
24859b68 1323 switch (offset) {
24859b68
AZ		 1324 case MP_GPIO_OE_HI: /* used for LCD brightness control */
1325 return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1326
1327 case MP_GPIO_OUT_LO:
1328 return gpio_out_state & 0xFFFF;
1329 case MP_GPIO_OUT_HI:
1330 return gpio_out_state >> 16;
1331
1332 case MP_GPIO_IN_LO:
1333 return gpio_in_state & 0xFFFF;
1334 case MP_GPIO_IN_HI:
1335 /* Update received I2C data */
1336 gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) |
1337 (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT);
1338 return gpio_in_state >> 16;
1339
24859b68 1340 case MP_GPIO_ISR_LO:
7c6ce4ba 1341 return gpio_isr & 0xFFFF;
24859b68 1342 case MP_GPIO_ISR_HI:
7c6ce4ba 1343 return gpio_isr >> 16;
24859b68 1344
24859b68
AZ		 1345 default:
1346 return 0;
1347 }
1348}
1349
718ec0be 1350static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1351 uint32_t value)
24859b68 1352{
24859b68
AZ		 1353 switch (offset) {
1354 case MP_GPIO_OE_HI: /* used for LCD brightness control */
1355 lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1356 (value & MP_OE_LCD_BRIGHTNESS);
1357 break;
1358
1359 case MP_GPIO_OUT_LO:
1360 gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF);
1361 break;
1362 case MP_GPIO_OUT_HI:
1363 gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16);
1364 lcd_brightness = (lcd_brightness & 0xFFFF) |
1365 (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS);
1366 i2c_state_update(mixer_i2c,
1367 (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
1368 (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1369 break;
1370
1371 }
1372}
1373
718ec0be 1374static CPUReadMemoryFunc *musicpal_gpio_readfn[] = {
1375 musicpal_gpio_read,
1376 musicpal_gpio_read,
1377 musicpal_gpio_read,
1378};
1379
1380static CPUWriteMemoryFunc *musicpal_gpio_writefn[] = {
1381 musicpal_gpio_write,
1382 musicpal_gpio_write,
1383 musicpal_gpio_write,
1384};
1385
1386static void musicpal_gpio_init(void)
1387{
1388 int iomemtype;
1389
1390 iomemtype = cpu_register_io_memory(0, musicpal_gpio_readfn,
1391 musicpal_gpio_writefn, NULL);
1392 cpu_register_physical_memory(MP_GPIO_BASE, MP_GPIO_SIZE, iomemtype);
1393}
1394
24859b68 1395/* Keyboard codes & masks */
7c6ce4ba 1396#define KEY_RELEASED 0x80
24859b68
AZ		 1397#define KEY_CODE 0x7f
1398
1399#define KEYCODE_TAB 0x0f
1400#define KEYCODE_ENTER 0x1c
1401#define KEYCODE_F 0x21
1402#define KEYCODE_M 0x32
1403
1404#define KEYCODE_EXTENDED 0xe0
1405#define KEYCODE_UP 0x48
1406#define KEYCODE_DOWN 0x50
1407#define KEYCODE_LEFT 0x4b
1408#define KEYCODE_RIGHT 0x4d
1409
1410static void musicpal_key_event(void *opaque, int keycode)
1411{
1412 qemu_irq irq = opaque;
1413 uint32_t event = 0;
1414 static int kbd_extended;
1415
1416 if (keycode == KEYCODE_EXTENDED) {
1417 kbd_extended = 1;
1418 return;
1419 }
1420
1421 if (kbd_extended)
1422 switch (keycode & KEY_CODE) {
1423 case KEYCODE_UP:
1424 event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV;
1425 break;
1426
1427 case KEYCODE_DOWN:
1428 event = MP_GPIO_WHEEL_NAV;
1429 break;
1430
1431 case KEYCODE_LEFT:
1432 event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV;
1433 break;
1434
1435 case KEYCODE_RIGHT:
1436 event = MP_GPIO_WHEEL_VOL;
1437 break;
1438 }
7c6ce4ba 1439 else {
24859b68
AZ		 1440 switch (keycode & KEY_CODE) {
1441 case KEYCODE_F:
1442 event = MP_GPIO_BTN_FAVORITS;
1443 break;
1444
1445 case KEYCODE_TAB:
1446 event = MP_GPIO_BTN_VOLUME;
1447 break;
1448
1449 case KEYCODE_ENTER:
1450 event = MP_GPIO_BTN_NAVIGATION;
1451 break;
1452
1453 case KEYCODE_M:
1454 event = MP_GPIO_BTN_MENU;
1455 break;
1456 }
7c6ce4ba
AZ		 1457 /* Do not repeat already pressed buttons */
1458 if (!(keycode & KEY_RELEASED) && !(gpio_in_state & event))
1459 event = 0;
1460 }
24859b68 1461
7c6ce4ba
AZ		 1462 if (event) {
1463 if (keycode & KEY_RELEASED) {
1464 gpio_in_state |= event;
1465 } else {
1466 gpio_in_state &= ~event;
1467 gpio_isr = event;
1468 qemu_irq_raise(irq);
1469 }
24859b68
AZ		 1470 }
1471
1472 kbd_extended = 0;
1473}
1474
24859b68
AZ		 1475static struct arm_boot_info musicpal_binfo = {
1476 .loader_start = 0x0,
1477 .board_id = 0x20e,
1478};
1479
b0f6edb1 1480static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
3023f332 1481 const char *boot_device,
24859b68
AZ		 1482 const char *kernel_filename, const char *kernel_cmdline,
1483 const char *initrd_filename, const char *cpu_model)
1484{
1485 CPUState *env;
1486 qemu_irq *pic;
1487 int index;
24859b68
AZ		 1488 unsigned long flash_size;
1489
1490 if (!cpu_model)
1491 cpu_model = "arm926";
1492
1493 env = cpu_init(cpu_model);
1494 if (!env) {
1495 fprintf(stderr, "Unable to find CPU definition\n");
1496 exit(1);
1497 }
1498 pic = arm_pic_init_cpu(env);
1499
1500 /* For now we use a fixed - the original - RAM size */
1501 cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1502 qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1503
1504 sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1505 cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1506
24859b68
AZ		 1507 pic = mv88w8618_pic_init(MP_PIC_BASE, pic[ARM_PIC_CPU_IRQ]);
1508 mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);
1509
1510 if (serial_hds[0])
b6cd0ea1 1511 serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
24859b68
AZ		 1512 serial_hds[0], 1);
1513 if (serial_hds[1])
b6cd0ea1 1514 serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
24859b68
AZ		 1515 serial_hds[1], 1);
1516
1517 /* Register flash */
1518 index = drive_get_index(IF_PFLASH, 0, 0);
1519 if (index != -1) {
1520 flash_size = bdrv_getlength(drives_table[index].bdrv);
1521 if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1522 flash_size != 32*1024*1024) {
1523 fprintf(stderr, "Invalid flash image size\n");
1524 exit(1);
1525 }
1526
1527 /*
1528 * The original U-Boot accesses the flash at 0xFE000000 instead of
1529 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1530 * image is smaller than 32 MB.
1531 */
1532 pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1533 drives_table[index].bdrv, 0x10000,
1534 (flash_size + 0xffff) >> 16,
1535 MP_FLASH_SIZE_MAX / flash_size,
1536 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1537 0x5555, 0x2AAA);
1538 }
1539 mv88w8618_flashcfg_init(MP_FLASHCFG_BASE);
1540
718ec0be 1541 musicpal_lcd_init();
24859b68
AZ		 1542
1543 qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
1544
24859b68
AZ		 1545 mv88w8618_eth_init(&nd_table[0], MP_ETH_BASE, pic[MP_ETH_IRQ]);
1546
718ec0be 1547 mixer_i2c = musicpal_audio_init(pic[MP_AUDIO_IRQ]);
1548
1549 mv88w8618_wlan_init(MP_WLAN_BASE);
1550
1551 musicpal_misc_init();
1552 musicpal_gpio_init();
24859b68
AZ		 1553
1554 musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1555 musicpal_binfo.kernel_filename = kernel_filename;
1556 musicpal_binfo.kernel_cmdline = kernel_cmdline;
1557 musicpal_binfo.initrd_filename = initrd_filename;
b0f6edb1 1558 arm_load_kernel(env, &musicpal_binfo);
24859b68
AZ		 1559}
1560
1561QEMUMachine musicpal_machine = {
4b32e168
AL		 1562 .name = "musicpal",
1563 .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1564 .init = musicpal_init,
3d878caa
AZ		 1565 .ram_require = MP_RAM_DEFAULT_SIZE + MP_SRAM_SIZE +
1566 MP_FLASH_SIZE_MAX + RAMSIZE_FIXED,
24859b68 1567};
Qemu copy for testing