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24859b68
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1/*
2 * Marvell MV88W8618 / Freecom MusicPal emulation.
3 *
4 * Copyright (c) 2008 Jan Kiszka
5 *
6 * This code is licenced under the GNU GPL v2.
7 */
8
b47b50fa 9#include "sysbus.h"
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10#include "arm-misc.h"
11#include "devices.h"
12#include "net.h"
13#include "sysemu.h"
14#include "boards.h"
15#include "pc.h"
16#include "qemu-timer.h"
17#include "block.h"
18#include "flash.h"
19#include "console.h"
24859b68 20#include "i2c.h"
2446333c 21#include "blockdev.h"
24859b68 22
718ec0be 23#define MP_MISC_BASE 0x80002000
24#define MP_MISC_SIZE 0x00001000
25
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26#define MP_ETH_BASE 0x80008000
27#define MP_ETH_SIZE 0x00001000
28
718ec0be 29#define MP_WLAN_BASE 0x8000C000
30#define MP_WLAN_SIZE 0x00000800
31
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32#define MP_UART1_BASE 0x8000C840
33#define MP_UART2_BASE 0x8000C940
34
718ec0be 35#define MP_GPIO_BASE 0x8000D000
36#define MP_GPIO_SIZE 0x00001000
37
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38#define MP_FLASHCFG_BASE 0x90006000
39#define MP_FLASHCFG_SIZE 0x00001000
40
41#define MP_AUDIO_BASE 0x90007000
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42
43#define MP_PIC_BASE 0x90008000
44#define MP_PIC_SIZE 0x00001000
45
46#define MP_PIT_BASE 0x90009000
47#define MP_PIT_SIZE 0x00001000
48
49#define MP_LCD_BASE 0x9000c000
50#define MP_LCD_SIZE 0x00001000
51
52#define MP_SRAM_BASE 0xC0000000
53#define MP_SRAM_SIZE 0x00020000
54
55#define MP_RAM_DEFAULT_SIZE 32*1024*1024
56#define MP_FLASH_SIZE_MAX 32*1024*1024
57
58#define MP_TIMER1_IRQ 4
b47b50fa
PB
59#define MP_TIMER2_IRQ 5
60#define MP_TIMER3_IRQ 6
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61#define MP_TIMER4_IRQ 7
62#define MP_EHCI_IRQ 8
63#define MP_ETH_IRQ 9
64#define MP_UART1_IRQ 11
65#define MP_UART2_IRQ 11
66#define MP_GPIO_IRQ 12
67#define MP_RTC_IRQ 28
68#define MP_AUDIO_IRQ 30
69
24859b68 70/* Wolfson 8750 I2C address */
64258229 71#define MP_WM_ADDR 0x1A
24859b68 72
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73/* Ethernet register offsets */
74#define MP_ETH_SMIR 0x010
75#define MP_ETH_PCXR 0x408
76#define MP_ETH_SDCMR 0x448
77#define MP_ETH_ICR 0x450
78#define MP_ETH_IMR 0x458
79#define MP_ETH_FRDP0 0x480
80#define MP_ETH_FRDP1 0x484
81#define MP_ETH_FRDP2 0x488
82#define MP_ETH_FRDP3 0x48C
83#define MP_ETH_CRDP0 0x4A0
84#define MP_ETH_CRDP1 0x4A4
85#define MP_ETH_CRDP2 0x4A8
86#define MP_ETH_CRDP3 0x4AC
87#define MP_ETH_CTDP0 0x4E0
88#define MP_ETH_CTDP1 0x4E4
89#define MP_ETH_CTDP2 0x4E8
90#define MP_ETH_CTDP3 0x4EC
91
92/* MII PHY access */
93#define MP_ETH_SMIR_DATA 0x0000FFFF
94#define MP_ETH_SMIR_ADDR 0x03FF0000
95#define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */
96#define MP_ETH_SMIR_RDVALID (1 << 27)
97
98/* PHY registers */
99#define MP_ETH_PHY1_BMSR 0x00210000
100#define MP_ETH_PHY1_PHYSID1 0x00410000
101#define MP_ETH_PHY1_PHYSID2 0x00610000
102
103#define MP_PHY_BMSR_LINK 0x0004
104#define MP_PHY_BMSR_AUTONEG 0x0008
105
106#define MP_PHY_88E3015 0x01410E20
107
108/* TX descriptor status */
109#define MP_ETH_TX_OWN (1 << 31)
110
111/* RX descriptor status */
112#define MP_ETH_RX_OWN (1 << 31)
113
114/* Interrupt cause/mask bits */
115#define MP_ETH_IRQ_RX_BIT 0
116#define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT)
117#define MP_ETH_IRQ_TXHI_BIT 2
118#define MP_ETH_IRQ_TXLO_BIT 3
119
120/* Port config bits */
121#define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */
122
123/* SDMA command bits */
124#define MP_ETH_CMD_TXHI (1 << 23)
125#define MP_ETH_CMD_TXLO (1 << 22)
126
127typedef struct mv88w8618_tx_desc {
128 uint32_t cmdstat;
129 uint16_t res;
130 uint16_t bytes;
131 uint32_t buffer;
132 uint32_t next;
133} mv88w8618_tx_desc;
134
135typedef struct mv88w8618_rx_desc {
136 uint32_t cmdstat;
137 uint16_t bytes;
138 uint16_t buffer_size;
139 uint32_t buffer;
140 uint32_t next;
141} mv88w8618_rx_desc;
142
143typedef struct mv88w8618_eth_state {
b47b50fa 144 SysBusDevice busdev;
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145 qemu_irq irq;
146 uint32_t smir;
147 uint32_t icr;
148 uint32_t imr;
b946a153 149 int mmio_index;
d5b61ddd 150 uint32_t vlan_header;
930c8682
PB
151 uint32_t tx_queue[2];
152 uint32_t rx_queue[4];
153 uint32_t frx_queue[4];
154 uint32_t cur_rx[4];
3a94dd18 155 NICState *nic;
4c91cd28 156 NICConf conf;
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157} mv88w8618_eth_state;
158
930c8682
PB
159static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
160{
161 cpu_to_le32s(&desc->cmdstat);
162 cpu_to_le16s(&desc->bytes);
163 cpu_to_le16s(&desc->buffer_size);
164 cpu_to_le32s(&desc->buffer);
165 cpu_to_le32s(&desc->next);
166 cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
167}
168
169static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
170{
171 cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
172 le32_to_cpus(&desc->cmdstat);
173 le16_to_cpus(&desc->bytes);
174 le16_to_cpus(&desc->buffer_size);
175 le32_to_cpus(&desc->buffer);
176 le32_to_cpus(&desc->next);
177}
178
3a94dd18 179static int eth_can_receive(VLANClientState *nc)
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AZ
180{
181 return 1;
182}
183
3a94dd18 184static ssize_t eth_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
24859b68 185{
3a94dd18 186 mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
930c8682
PB
187 uint32_t desc_addr;
188 mv88w8618_rx_desc desc;
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189 int i;
190
191 for (i = 0; i < 4; i++) {
930c8682 192 desc_addr = s->cur_rx[i];
49fedd0d 193 if (!desc_addr) {
24859b68 194 continue;
49fedd0d 195 }
24859b68 196 do {
930c8682
PB
197 eth_rx_desc_get(desc_addr, &desc);
198 if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
199 cpu_physical_memory_write(desc.buffer + s->vlan_header,
200 buf, size);
201 desc.bytes = size + s->vlan_header;
202 desc.cmdstat &= ~MP_ETH_RX_OWN;
203 s->cur_rx[i] = desc.next;
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204
205 s->icr |= MP_ETH_IRQ_RX;
49fedd0d 206 if (s->icr & s->imr) {
24859b68 207 qemu_irq_raise(s->irq);
49fedd0d 208 }
930c8682 209 eth_rx_desc_put(desc_addr, &desc);
4f1c942b 210 return size;
24859b68 211 }
930c8682
PB
212 desc_addr = desc.next;
213 } while (desc_addr != s->rx_queue[i]);
24859b68 214 }
4f1c942b 215 return size;
24859b68
AZ
216}
217
930c8682
PB
218static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
219{
220 cpu_to_le32s(&desc->cmdstat);
221 cpu_to_le16s(&desc->res);
222 cpu_to_le16s(&desc->bytes);
223 cpu_to_le32s(&desc->buffer);
224 cpu_to_le32s(&desc->next);
225 cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
226}
227
228static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
229{
230 cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
231 le32_to_cpus(&desc->cmdstat);
232 le16_to_cpus(&desc->res);
233 le16_to_cpus(&desc->bytes);
234 le32_to_cpus(&desc->buffer);
235 le32_to_cpus(&desc->next);
236}
237
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238static void eth_send(mv88w8618_eth_state *s, int queue_index)
239{
930c8682
PB
240 uint32_t desc_addr = s->tx_queue[queue_index];
241 mv88w8618_tx_desc desc;
07b064e9 242 uint32_t next_desc;
930c8682
PB
243 uint8_t buf[2048];
244 int len;
245
24859b68 246 do {
930c8682 247 eth_tx_desc_get(desc_addr, &desc);
07b064e9 248 next_desc = desc.next;
930c8682
PB
249 if (desc.cmdstat & MP_ETH_TX_OWN) {
250 len = desc.bytes;
251 if (len < 2048) {
252 cpu_physical_memory_read(desc.buffer, buf, len);
3a94dd18 253 qemu_send_packet(&s->nic->nc, buf, len);
930c8682
PB
254 }
255 desc.cmdstat &= ~MP_ETH_TX_OWN;
24859b68 256 s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
930c8682 257 eth_tx_desc_put(desc_addr, &desc);
24859b68 258 }
07b064e9 259 desc_addr = next_desc;
930c8682 260 } while (desc_addr != s->tx_queue[queue_index]);
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261}
262
c227f099 263static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
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264{
265 mv88w8618_eth_state *s = opaque;
266
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267 switch (offset) {
268 case MP_ETH_SMIR:
269 if (s->smir & MP_ETH_SMIR_OPCODE) {
270 switch (s->smir & MP_ETH_SMIR_ADDR) {
271 case MP_ETH_PHY1_BMSR:
272 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
273 MP_ETH_SMIR_RDVALID;
274 case MP_ETH_PHY1_PHYSID1:
275 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
276 case MP_ETH_PHY1_PHYSID2:
277 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
278 default:
279 return MP_ETH_SMIR_RDVALID;
280 }
281 }
282 return 0;
283
284 case MP_ETH_ICR:
285 return s->icr;
286
287 case MP_ETH_IMR:
288 return s->imr;
289
290 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
930c8682 291 return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
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292
293 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
930c8682 294 return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
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295
296 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
930c8682 297 return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
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298
299 default:
300 return 0;
301 }
302}
303
c227f099 304static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
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305 uint32_t value)
306{
307 mv88w8618_eth_state *s = opaque;
308
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309 switch (offset) {
310 case MP_ETH_SMIR:
311 s->smir = value;
312 break;
313
314 case MP_ETH_PCXR:
315 s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
316 break;
317
318 case MP_ETH_SDCMR:
49fedd0d 319 if (value & MP_ETH_CMD_TXHI) {
24859b68 320 eth_send(s, 1);
49fedd0d
JK
321 }
322 if (value & MP_ETH_CMD_TXLO) {
24859b68 323 eth_send(s, 0);
49fedd0d
JK
324 }
325 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
24859b68 326 qemu_irq_raise(s->irq);
49fedd0d 327 }
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328 break;
329
330 case MP_ETH_ICR:
331 s->icr &= value;
332 break;
333
334 case MP_ETH_IMR:
335 s->imr = value;
49fedd0d 336 if (s->icr & s->imr) {
24859b68 337 qemu_irq_raise(s->irq);
49fedd0d 338 }
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339 break;
340
341 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
930c8682 342 s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
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343 break;
344
345 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
346 s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
930c8682 347 s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
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348 break;
349
350 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
930c8682 351 s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
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352 break;
353 }
354}
355
d60efc6b 356static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = {
24859b68
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357 mv88w8618_eth_read,
358 mv88w8618_eth_read,
359 mv88w8618_eth_read
360};
361
d60efc6b 362static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = {
24859b68
AZ
363 mv88w8618_eth_write,
364 mv88w8618_eth_write,
365 mv88w8618_eth_write
366};
367
3a94dd18 368static void eth_cleanup(VLANClientState *nc)
b946a153 369{
3a94dd18 370 mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 371
3a94dd18 372 s->nic = NULL;
b946a153
AL
373}
374
3a94dd18
MM
375static NetClientInfo net_mv88w8618_info = {
376 .type = NET_CLIENT_TYPE_NIC,
377 .size = sizeof(NICState),
378 .can_receive = eth_can_receive,
379 .receive = eth_receive,
380 .cleanup = eth_cleanup,
381};
382
81a322d4 383static int mv88w8618_eth_init(SysBusDevice *dev)
24859b68 384{
b47b50fa 385 mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
0ae18cee 386
b47b50fa 387 sysbus_init_irq(dev, &s->irq);
3a94dd18
MM
388 s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
389 dev->qdev.info->name, dev->qdev.id, s);
1eed09cb 390 s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn,
b946a153 391 mv88w8618_eth_writefn, s);
b47b50fa 392 sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index);
81a322d4 393 return 0;
24859b68
AZ
394}
395
d5b61ddd
JK
396static const VMStateDescription mv88w8618_eth_vmsd = {
397 .name = "mv88w8618_eth",
398 .version_id = 1,
399 .minimum_version_id = 1,
400 .minimum_version_id_old = 1,
401 .fields = (VMStateField[]) {
402 VMSTATE_UINT32(smir, mv88w8618_eth_state),
403 VMSTATE_UINT32(icr, mv88w8618_eth_state),
404 VMSTATE_UINT32(imr, mv88w8618_eth_state),
405 VMSTATE_UINT32(vlan_header, mv88w8618_eth_state),
406 VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
407 VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
408 VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
409 VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
410 VMSTATE_END_OF_LIST()
411 }
412};
413
414static SysBusDeviceInfo mv88w8618_eth_info = {
415 .init = mv88w8618_eth_init,
416 .qdev.name = "mv88w8618_eth",
417 .qdev.size = sizeof(mv88w8618_eth_state),
418 .qdev.vmsd = &mv88w8618_eth_vmsd,
4c91cd28
GH
419 .qdev.props = (Property[]) {
420 DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
421 DEFINE_PROP_END_OF_LIST(),
422 },
d5b61ddd
JK
423};
424
24859b68
AZ
425/* LCD register offsets */
426#define MP_LCD_IRQCTRL 0x180
427#define MP_LCD_IRQSTAT 0x184
428#define MP_LCD_SPICTRL 0x1ac
429#define MP_LCD_INST 0x1bc
430#define MP_LCD_DATA 0x1c0
431
432/* Mode magics */
433#define MP_LCD_SPI_DATA 0x00100011
434#define MP_LCD_SPI_CMD 0x00104011
435#define MP_LCD_SPI_INVALID 0x00000000
436
437/* Commmands */
438#define MP_LCD_INST_SETPAGE0 0xB0
439/* ... */
440#define MP_LCD_INST_SETPAGE7 0xB7
441
442#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
443
444typedef struct musicpal_lcd_state {
b47b50fa 445 SysBusDevice busdev;
343ec8e4 446 uint32_t brightness;
24859b68
AZ
447 uint32_t mode;
448 uint32_t irqctrl;
d5b61ddd
JK
449 uint32_t page;
450 uint32_t page_off;
24859b68
AZ
451 DisplayState *ds;
452 uint8_t video_ram[128*64/8];
453} musicpal_lcd_state;
454
343ec8e4 455static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
24859b68 456{
343ec8e4
BC
457 switch (s->brightness) {
458 case 7:
459 return col;
460 case 0:
24859b68 461 return 0;
24859b68 462 default:
343ec8e4 463 return (col * s->brightness) / 7;
24859b68
AZ
464 }
465}
466
0266f2c7
AZ
467#define SET_LCD_PIXEL(depth, type) \
468static inline void glue(set_lcd_pixel, depth) \
469 (musicpal_lcd_state *s, int x, int y, type col) \
470{ \
471 int dx, dy; \
0e1f5a0c 472 type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
0266f2c7
AZ
473\
474 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
475 for (dx = 0; dx < 3; dx++, pixel++) \
476 *pixel = col; \
24859b68 477}
0266f2c7
AZ
478SET_LCD_PIXEL(8, uint8_t)
479SET_LCD_PIXEL(16, uint16_t)
480SET_LCD_PIXEL(32, uint32_t)
481
482#include "pixel_ops.h"
24859b68
AZ
483
484static void lcd_refresh(void *opaque)
485{
486 musicpal_lcd_state *s = opaque;
0266f2c7 487 int x, y, col;
24859b68 488
0e1f5a0c 489 switch (ds_get_bits_per_pixel(s->ds)) {
0266f2c7
AZ
490 case 0:
491 return;
492#define LCD_REFRESH(depth, func) \
493 case depth: \
343ec8e4
BC
494 col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
495 scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
496 scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
49fedd0d
JK
497 for (x = 0; x < 128; x++) { \
498 for (y = 0; y < 64; y++) { \
499 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
0266f2c7 500 glue(set_lcd_pixel, depth)(s, x, y, col); \
49fedd0d 501 } else { \
0266f2c7 502 glue(set_lcd_pixel, depth)(s, x, y, 0); \
49fedd0d
JK
503 } \
504 } \
505 } \
0266f2c7
AZ
506 break;
507 LCD_REFRESH(8, rgb_to_pixel8)
508 LCD_REFRESH(16, rgb_to_pixel16)
bf9b48af
AL
509 LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
510 rgb_to_pixel32bgr : rgb_to_pixel32))
0266f2c7 511 default:
2ac71179 512 hw_error("unsupported colour depth %i\n",
0e1f5a0c 513 ds_get_bits_per_pixel(s->ds));
0266f2c7 514 }
24859b68
AZ
515
516 dpy_update(s->ds, 0, 0, 128*3, 64*3);
517}
518
167bc3d2
AZ
519static void lcd_invalidate(void *opaque)
520{
167bc3d2
AZ
521}
522
343ec8e4
BC
523static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
524{
243cd13c 525 musicpal_lcd_state *s = opaque;
343ec8e4
BC
526 s->brightness &= ~(1 << irq);
527 s->brightness |= level << irq;
528}
529
c227f099 530static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
24859b68
AZ
531{
532 musicpal_lcd_state *s = opaque;
533
24859b68
AZ
534 switch (offset) {
535 case MP_LCD_IRQCTRL:
536 return s->irqctrl;
537
538 default:
539 return 0;
540 }
541}
542
c227f099 543static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
24859b68
AZ
544 uint32_t value)
545{
546 musicpal_lcd_state *s = opaque;
547
24859b68
AZ
548 switch (offset) {
549 case MP_LCD_IRQCTRL:
550 s->irqctrl = value;
551 break;
552
553 case MP_LCD_SPICTRL:
49fedd0d 554 if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
24859b68 555 s->mode = value;
49fedd0d 556 } else {
24859b68 557 s->mode = MP_LCD_SPI_INVALID;
49fedd0d 558 }
24859b68
AZ
559 break;
560
561 case MP_LCD_INST:
562 if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
563 s->page = value - MP_LCD_INST_SETPAGE0;
564 s->page_off = 0;
565 }
566 break;
567
568 case MP_LCD_DATA:
569 if (s->mode == MP_LCD_SPI_CMD) {
570 if (value >= MP_LCD_INST_SETPAGE0 &&
571 value <= MP_LCD_INST_SETPAGE7) {
572 s->page = value - MP_LCD_INST_SETPAGE0;
573 s->page_off = 0;
574 }
575 } else if (s->mode == MP_LCD_SPI_DATA) {
576 s->video_ram[s->page*128 + s->page_off] = value;
577 s->page_off = (s->page_off + 1) & 127;
578 }
579 break;
580 }
581}
582
d60efc6b 583static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = {
24859b68
AZ
584 musicpal_lcd_read,
585 musicpal_lcd_read,
586 musicpal_lcd_read
587};
588
d60efc6b 589static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = {
24859b68
AZ
590 musicpal_lcd_write,
591 musicpal_lcd_write,
592 musicpal_lcd_write
593};
594
81a322d4 595static int musicpal_lcd_init(SysBusDevice *dev)
24859b68 596{
b47b50fa 597 musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
24859b68
AZ
598 int iomemtype;
599
343ec8e4
BC
600 s->brightness = 7;
601
1eed09cb 602 iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
24859b68 603 musicpal_lcd_writefn, s);
b47b50fa 604 sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
24859b68 605
3023f332
AL
606 s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
607 NULL, NULL, s);
608 qemu_console_resize(s->ds, 128*3, 64*3);
343ec8e4
BC
609
610 qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
81a322d4
GH
611
612 return 0;
24859b68
AZ
613}
614
d5b61ddd
JK
615static const VMStateDescription musicpal_lcd_vmsd = {
616 .name = "musicpal_lcd",
617 .version_id = 1,
618 .minimum_version_id = 1,
619 .minimum_version_id_old = 1,
620 .fields = (VMStateField[]) {
621 VMSTATE_UINT32(brightness, musicpal_lcd_state),
622 VMSTATE_UINT32(mode, musicpal_lcd_state),
623 VMSTATE_UINT32(irqctrl, musicpal_lcd_state),
624 VMSTATE_UINT32(page, musicpal_lcd_state),
625 VMSTATE_UINT32(page_off, musicpal_lcd_state),
626 VMSTATE_BUFFER(video_ram, musicpal_lcd_state),
627 VMSTATE_END_OF_LIST()
628 }
629};
630
631static SysBusDeviceInfo musicpal_lcd_info = {
632 .init = musicpal_lcd_init,
633 .qdev.name = "musicpal_lcd",
634 .qdev.size = sizeof(musicpal_lcd_state),
635 .qdev.vmsd = &musicpal_lcd_vmsd,
636};
637
24859b68
AZ
638/* PIC register offsets */
639#define MP_PIC_STATUS 0x00
640#define MP_PIC_ENABLE_SET 0x08
641#define MP_PIC_ENABLE_CLR 0x0C
642
643typedef struct mv88w8618_pic_state
644{
b47b50fa 645 SysBusDevice busdev;
24859b68
AZ
646 uint32_t level;
647 uint32_t enabled;
648 qemu_irq parent_irq;
649} mv88w8618_pic_state;
650
651static void mv88w8618_pic_update(mv88w8618_pic_state *s)
652{
653 qemu_set_irq(s->parent_irq, (s->level & s->enabled));
654}
655
656static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
657{
658 mv88w8618_pic_state *s = opaque;
659
49fedd0d 660 if (level) {
24859b68 661 s->level |= 1 << irq;
49fedd0d 662 } else {
24859b68 663 s->level &= ~(1 << irq);
49fedd0d 664 }
24859b68
AZ
665 mv88w8618_pic_update(s);
666}
667
c227f099 668static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
24859b68
AZ
669{
670 mv88w8618_pic_state *s = opaque;
671
24859b68
AZ
672 switch (offset) {
673 case MP_PIC_STATUS:
674 return s->level & s->enabled;
675
676 default:
677 return 0;
678 }
679}
680
c227f099 681static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
24859b68
AZ
682 uint32_t value)
683{
684 mv88w8618_pic_state *s = opaque;
685
24859b68
AZ
686 switch (offset) {
687 case MP_PIC_ENABLE_SET:
688 s->enabled |= value;
689 break;
690
691 case MP_PIC_ENABLE_CLR:
692 s->enabled &= ~value;
693 s->level &= ~value;
694 break;
695 }
696 mv88w8618_pic_update(s);
697}
698
d5b61ddd 699static void mv88w8618_pic_reset(DeviceState *d)
24859b68 700{
d5b61ddd
JK
701 mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state,
702 sysbus_from_qdev(d));
24859b68
AZ
703
704 s->level = 0;
705 s->enabled = 0;
706}
707
d60efc6b 708static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = {
24859b68
AZ
709 mv88w8618_pic_read,
710 mv88w8618_pic_read,
711 mv88w8618_pic_read
712};
713
d60efc6b 714static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = {
24859b68
AZ
715 mv88w8618_pic_write,
716 mv88w8618_pic_write,
717 mv88w8618_pic_write
718};
719
81a322d4 720static int mv88w8618_pic_init(SysBusDevice *dev)
24859b68 721{
b47b50fa 722 mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
24859b68 723 int iomemtype;
24859b68 724
067a3ddc 725 qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
b47b50fa 726 sysbus_init_irq(dev, &s->parent_irq);
1eed09cb 727 iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn,
24859b68 728 mv88w8618_pic_writefn, s);
b47b50fa 729 sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);
81a322d4 730 return 0;
24859b68
AZ
731}
732
d5b61ddd
JK
733static const VMStateDescription mv88w8618_pic_vmsd = {
734 .name = "mv88w8618_pic",
735 .version_id = 1,
736 .minimum_version_id = 1,
737 .minimum_version_id_old = 1,
738 .fields = (VMStateField[]) {
739 VMSTATE_UINT32(level, mv88w8618_pic_state),
740 VMSTATE_UINT32(enabled, mv88w8618_pic_state),
741 VMSTATE_END_OF_LIST()
742 }
743};
744
745static SysBusDeviceInfo mv88w8618_pic_info = {
746 .init = mv88w8618_pic_init,
747 .qdev.name = "mv88w8618_pic",
748 .qdev.size = sizeof(mv88w8618_pic_state),
749 .qdev.reset = mv88w8618_pic_reset,
750 .qdev.vmsd = &mv88w8618_pic_vmsd,
751};
752
24859b68
AZ
753/* PIT register offsets */
754#define MP_PIT_TIMER1_LENGTH 0x00
755/* ... */
756#define MP_PIT_TIMER4_LENGTH 0x0C
757#define MP_PIT_CONTROL 0x10
758#define MP_PIT_TIMER1_VALUE 0x14
759/* ... */
760#define MP_PIT_TIMER4_VALUE 0x20
761#define MP_BOARD_RESET 0x34
762
763/* Magic board reset value (probably some watchdog behind it) */
764#define MP_BOARD_RESET_MAGIC 0x10000
765
766typedef struct mv88w8618_timer_state {
b47b50fa 767 ptimer_state *ptimer;
24859b68
AZ
768 uint32_t limit;
769 int freq;
770 qemu_irq irq;
771} mv88w8618_timer_state;
772
773typedef struct mv88w8618_pit_state {
b47b50fa
PB
774 SysBusDevice busdev;
775 mv88w8618_timer_state timer[4];
24859b68
AZ
776} mv88w8618_pit_state;
777
778static void mv88w8618_timer_tick(void *opaque)
779{
780 mv88w8618_timer_state *s = opaque;
781
782 qemu_irq_raise(s->irq);
783}
784
b47b50fa
PB
785static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
786 uint32_t freq)
24859b68 787{
24859b68
AZ
788 QEMUBH *bh;
789
b47b50fa 790 sysbus_init_irq(dev, &s->irq);
24859b68
AZ
791 s->freq = freq;
792
793 bh = qemu_bh_new(mv88w8618_timer_tick, s);
b47b50fa 794 s->ptimer = ptimer_init(bh);
24859b68
AZ
795}
796
c227f099 797static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
24859b68
AZ
798{
799 mv88w8618_pit_state *s = opaque;
800 mv88w8618_timer_state *t;
801
24859b68
AZ
802 switch (offset) {
803 case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
b47b50fa
PB
804 t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
805 return ptimer_get_count(t->ptimer);
24859b68
AZ
806
807 default:
808 return 0;
809 }
810}
811
c227f099 812static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
24859b68
AZ
813 uint32_t value)
814{
815 mv88w8618_pit_state *s = opaque;
816 mv88w8618_timer_state *t;
817 int i;
818
24859b68
AZ
819 switch (offset) {
820 case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
b47b50fa 821 t = &s->timer[offset >> 2];
24859b68 822 t->limit = value;
c88d6bde
JK
823 if (t->limit > 0) {
824 ptimer_set_limit(t->ptimer, t->limit, 1);
825 } else {
826 ptimer_stop(t->ptimer);
827 }
24859b68
AZ
828 break;
829
830 case MP_PIT_CONTROL:
831 for (i = 0; i < 4; i++) {
c88d6bde
JK
832 t = &s->timer[i];
833 if (value & 0xf && t->limit > 0) {
b47b50fa
PB
834 ptimer_set_limit(t->ptimer, t->limit, 0);
835 ptimer_set_freq(t->ptimer, t->freq);
836 ptimer_run(t->ptimer, 0);
c88d6bde
JK
837 } else {
838 ptimer_stop(t->ptimer);
24859b68
AZ
839 }
840 value >>= 4;
841 }
842 break;
843
844 case MP_BOARD_RESET:
49fedd0d 845 if (value == MP_BOARD_RESET_MAGIC) {
24859b68 846 qemu_system_reset_request();
49fedd0d 847 }
24859b68
AZ
848 break;
849 }
850}
851
d5b61ddd 852static void mv88w8618_pit_reset(DeviceState *d)
c88d6bde 853{
d5b61ddd
JK
854 mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state,
855 sysbus_from_qdev(d));
c88d6bde
JK
856 int i;
857
858 for (i = 0; i < 4; i++) {
859 ptimer_stop(s->timer[i].ptimer);
860 s->timer[i].limit = 0;
861 }
862}
863
d60efc6b 864static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = {
24859b68
AZ
865 mv88w8618_pit_read,
866 mv88w8618_pit_read,
867 mv88w8618_pit_read
868};
869
d60efc6b 870static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = {
24859b68
AZ
871 mv88w8618_pit_write,
872 mv88w8618_pit_write,
873 mv88w8618_pit_write
874};
875
81a322d4 876static int mv88w8618_pit_init(SysBusDevice *dev)
24859b68
AZ
877{
878 int iomemtype;
b47b50fa
PB
879 mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
880 int i;
24859b68 881
24859b68
AZ
882 /* Letting them all run at 1 MHz is likely just a pragmatic
883 * simplification. */
b47b50fa
PB
884 for (i = 0; i < 4; i++) {
885 mv88w8618_timer_init(dev, &s->timer[i], 1000000);
886 }
24859b68 887
1eed09cb 888 iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn,
24859b68 889 mv88w8618_pit_writefn, s);
b47b50fa 890 sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype);
81a322d4 891 return 0;
24859b68
AZ
892}
893
d5b61ddd
JK
894static const VMStateDescription mv88w8618_timer_vmsd = {
895 .name = "timer",
896 .version_id = 1,
897 .minimum_version_id = 1,
898 .minimum_version_id_old = 1,
899 .fields = (VMStateField[]) {
900 VMSTATE_PTIMER(ptimer, mv88w8618_timer_state),
901 VMSTATE_UINT32(limit, mv88w8618_timer_state),
902 VMSTATE_END_OF_LIST()
903 }
904};
905
906static const VMStateDescription mv88w8618_pit_vmsd = {
907 .name = "mv88w8618_pit",
908 .version_id = 1,
909 .minimum_version_id = 1,
910 .minimum_version_id_old = 1,
911 .fields = (VMStateField[]) {
912 VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1,
913 mv88w8618_timer_vmsd, mv88w8618_timer_state),
914 VMSTATE_END_OF_LIST()
915 }
916};
917
c88d6bde
JK
918static SysBusDeviceInfo mv88w8618_pit_info = {
919 .init = mv88w8618_pit_init,
920 .qdev.name = "mv88w8618_pit",
921 .qdev.size = sizeof(mv88w8618_pit_state),
922 .qdev.reset = mv88w8618_pit_reset,
d5b61ddd 923 .qdev.vmsd = &mv88w8618_pit_vmsd,
c88d6bde
JK
924};
925
24859b68
AZ
926/* Flash config register offsets */
927#define MP_FLASHCFG_CFGR0 0x04
928
929typedef struct mv88w8618_flashcfg_state {
b47b50fa 930 SysBusDevice busdev;
24859b68
AZ
931 uint32_t cfgr0;
932} mv88w8618_flashcfg_state;
933
934static uint32_t mv88w8618_flashcfg_read(void *opaque,
c227f099 935 target_phys_addr_t offset)
24859b68
AZ
936{
937 mv88w8618_flashcfg_state *s = opaque;
938
24859b68
AZ
939 switch (offset) {
940 case MP_FLASHCFG_CFGR0:
941 return s->cfgr0;
942
943 default:
944 return 0;
945 }
946}
947
c227f099 948static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
24859b68
AZ
949 uint32_t value)
950{
951 mv88w8618_flashcfg_state *s = opaque;
952
24859b68
AZ
953 switch (offset) {
954 case MP_FLASHCFG_CFGR0:
955 s->cfgr0 = value;
956 break;
957 }
958}
959
d60efc6b 960static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = {
24859b68
AZ
961 mv88w8618_flashcfg_read,
962 mv88w8618_flashcfg_read,
963 mv88w8618_flashcfg_read
964};
965
d60efc6b 966static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = {
24859b68
AZ
967 mv88w8618_flashcfg_write,
968 mv88w8618_flashcfg_write,
969 mv88w8618_flashcfg_write
970};
971
81a322d4 972static int mv88w8618_flashcfg_init(SysBusDevice *dev)
24859b68
AZ
973{
974 int iomemtype;
b47b50fa 975 mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
24859b68 976
24859b68 977 s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1eed09cb 978 iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn,
49fedd0d 979 mv88w8618_flashcfg_writefn, s);
b47b50fa 980 sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype);
81a322d4 981 return 0;
24859b68
AZ
982}
983
d5b61ddd
JK
984static const VMStateDescription mv88w8618_flashcfg_vmsd = {
985 .name = "mv88w8618_flashcfg",
986 .version_id = 1,
987 .minimum_version_id = 1,
988 .minimum_version_id_old = 1,
989 .fields = (VMStateField[]) {
990 VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state),
991 VMSTATE_END_OF_LIST()
992 }
993};
994
995static SysBusDeviceInfo mv88w8618_flashcfg_info = {
996 .init = mv88w8618_flashcfg_init,
997 .qdev.name = "mv88w8618_flashcfg",
998 .qdev.size = sizeof(mv88w8618_flashcfg_state),
999 .qdev.vmsd = &mv88w8618_flashcfg_vmsd,
1000};
1001
718ec0be 1002/* Misc register offsets */
1003#define MP_MISC_BOARD_REVISION 0x18
1004
1005#define MP_BOARD_REVISION 0x31
1006
c227f099 1007static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset)
718ec0be 1008{
1009 switch (offset) {
1010 case MP_MISC_BOARD_REVISION:
1011 return MP_BOARD_REVISION;
1012
1013 default:
1014 return 0;
1015 }
1016}
1017
c227f099 1018static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
718ec0be 1019 uint32_t value)
1020{
1021}
1022
d60efc6b 1023static CPUReadMemoryFunc * const musicpal_misc_readfn[] = {
718ec0be 1024 musicpal_misc_read,
1025 musicpal_misc_read,
1026 musicpal_misc_read,
1027};
1028
d60efc6b 1029static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = {
718ec0be 1030 musicpal_misc_write,
1031 musicpal_misc_write,
1032 musicpal_misc_write,
1033};
1034
1035static void musicpal_misc_init(void)
1036{
1037 int iomemtype;
1038
1eed09cb 1039 iomemtype = cpu_register_io_memory(musicpal_misc_readfn,
718ec0be 1040 musicpal_misc_writefn, NULL);
1041 cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype);
1042}
1043
1044/* WLAN register offsets */
1045#define MP_WLAN_MAGIC1 0x11c
1046#define MP_WLAN_MAGIC2 0x124
1047
c227f099 1048static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset)
718ec0be 1049{
1050 switch (offset) {
1051 /* Workaround to allow loading the binary-only wlandrv.ko crap
1052 * from the original Freecom firmware. */
1053 case MP_WLAN_MAGIC1:
1054 return ~3;
1055 case MP_WLAN_MAGIC2:
1056 return -1;
1057
1058 default:
1059 return 0;
1060 }
1061}
1062
c227f099 1063static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
718ec0be 1064 uint32_t value)
1065{
1066}
1067
d60efc6b 1068static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = {
718ec0be 1069 mv88w8618_wlan_read,
1070 mv88w8618_wlan_read,
1071 mv88w8618_wlan_read,
1072};
1073
d60efc6b 1074static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = {
718ec0be 1075 mv88w8618_wlan_write,
1076 mv88w8618_wlan_write,
1077 mv88w8618_wlan_write,
1078};
1079
81a322d4 1080static int mv88w8618_wlan_init(SysBusDevice *dev)
718ec0be 1081{
1082 int iomemtype;
24859b68 1083
1eed09cb 1084 iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn,
718ec0be 1085 mv88w8618_wlan_writefn, NULL);
b47b50fa 1086 sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype);
81a322d4 1087 return 0;
718ec0be 1088}
24859b68 1089
718ec0be 1090/* GPIO register offsets */
1091#define MP_GPIO_OE_LO 0x008
1092#define MP_GPIO_OUT_LO 0x00c
1093#define MP_GPIO_IN_LO 0x010
708afdf3
JK
1094#define MP_GPIO_IER_LO 0x014
1095#define MP_GPIO_IMR_LO 0x018
718ec0be 1096#define MP_GPIO_ISR_LO 0x020
1097#define MP_GPIO_OE_HI 0x508
1098#define MP_GPIO_OUT_HI 0x50c
1099#define MP_GPIO_IN_HI 0x510
708afdf3
JK
1100#define MP_GPIO_IER_HI 0x514
1101#define MP_GPIO_IMR_HI 0x518
718ec0be 1102#define MP_GPIO_ISR_HI 0x520
24859b68
AZ
1103
1104/* GPIO bits & masks */
24859b68 1105#define MP_GPIO_LCD_BRIGHTNESS 0x00070000
24859b68 1106#define MP_GPIO_I2C_DATA_BIT 29
24859b68
AZ
1107#define MP_GPIO_I2C_CLOCK_BIT 30
1108
1109/* LCD brightness bits in GPIO_OE_HI */
1110#define MP_OE_LCD_BRIGHTNESS 0x0007
1111
343ec8e4
BC
1112typedef struct musicpal_gpio_state {
1113 SysBusDevice busdev;
1114 uint32_t lcd_brightness;
1115 uint32_t out_state;
1116 uint32_t in_state;
708afdf3
JK
1117 uint32_t ier;
1118 uint32_t imr;
343ec8e4 1119 uint32_t isr;
343ec8e4 1120 qemu_irq irq;
708afdf3 1121 qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
343ec8e4
BC
1122} musicpal_gpio_state;
1123
1124static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
1125 int i;
1126 uint32_t brightness;
1127
1128 /* compute brightness ratio */
1129 switch (s->lcd_brightness) {
1130 case 0x00000007:
1131 brightness = 0;
1132 break;
1133
1134 case 0x00020000:
1135 brightness = 1;
1136 break;
1137
1138 case 0x00020001:
1139 brightness = 2;
1140 break;
1141
1142 case 0x00040000:
1143 brightness = 3;
1144 break;
1145
1146 case 0x00010006:
1147 brightness = 4;
1148 break;
1149
1150 case 0x00020005:
1151 brightness = 5;
1152 break;
1153
1154 case 0x00040003:
1155 brightness = 6;
1156 break;
1157
1158 case 0x00030004:
1159 default:
1160 brightness = 7;
1161 }
1162
1163 /* set lcd brightness GPIOs */
49fedd0d 1164 for (i = 0; i <= 2; i++) {
343ec8e4 1165 qemu_set_irq(s->out[i], (brightness >> i) & 1);
49fedd0d 1166 }
343ec8e4
BC
1167}
1168
708afdf3 1169static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
343ec8e4 1170{
243cd13c 1171 musicpal_gpio_state *s = opaque;
708afdf3
JK
1172 uint32_t mask = 1 << pin;
1173 uint32_t delta = level << pin;
1174 uint32_t old = s->in_state & mask;
343ec8e4 1175
708afdf3
JK
1176 s->in_state &= ~mask;
1177 s->in_state |= delta;
343ec8e4 1178
708afdf3
JK
1179 if ((old ^ delta) &&
1180 ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) {
1181 s->isr = mask;
1182 qemu_irq_raise(s->irq);
343ec8e4 1183 }
343ec8e4
BC
1184}
1185
c227f099 1186static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
24859b68 1187{
243cd13c 1188 musicpal_gpio_state *s = opaque;
343ec8e4 1189
24859b68 1190 switch (offset) {
24859b68 1191 case MP_GPIO_OE_HI: /* used for LCD brightness control */
343ec8e4 1192 return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
24859b68
AZ
1193
1194 case MP_GPIO_OUT_LO:
343ec8e4 1195 return s->out_state & 0xFFFF;
24859b68 1196 case MP_GPIO_OUT_HI:
343ec8e4 1197 return s->out_state >> 16;
24859b68
AZ
1198
1199 case MP_GPIO_IN_LO:
343ec8e4 1200 return s->in_state & 0xFFFF;
24859b68 1201 case MP_GPIO_IN_HI:
343ec8e4 1202 return s->in_state >> 16;
24859b68 1203
708afdf3
JK
1204 case MP_GPIO_IER_LO:
1205 return s->ier & 0xFFFF;
1206 case MP_GPIO_IER_HI:
1207 return s->ier >> 16;
1208
1209 case MP_GPIO_IMR_LO:
1210 return s->imr & 0xFFFF;
1211 case MP_GPIO_IMR_HI:
1212 return s->imr >> 16;
1213
24859b68 1214 case MP_GPIO_ISR_LO:
343ec8e4 1215 return s->isr & 0xFFFF;
24859b68 1216 case MP_GPIO_ISR_HI:
343ec8e4 1217 return s->isr >> 16;
24859b68 1218
24859b68
AZ
1219 default:
1220 return 0;
1221 }
1222}
1223
c227f099 1224static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
718ec0be 1225 uint32_t value)
24859b68 1226{
243cd13c 1227 musicpal_gpio_state *s = opaque;
24859b68
AZ
1228 switch (offset) {
1229 case MP_GPIO_OE_HI: /* used for LCD brightness control */
343ec8e4 1230 s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
24859b68 1231 (value & MP_OE_LCD_BRIGHTNESS);
343ec8e4 1232 musicpal_gpio_brightness_update(s);
24859b68
AZ
1233 break;
1234
1235 case MP_GPIO_OUT_LO:
343ec8e4 1236 s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
24859b68
AZ
1237 break;
1238 case MP_GPIO_OUT_HI:
343ec8e4
BC
1239 s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1240 s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1241 (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1242 musicpal_gpio_brightness_update(s);
d074769c
AZ
1243 qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1244 qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
24859b68
AZ
1245 break;
1246
708afdf3
JK
1247 case MP_GPIO_IER_LO:
1248 s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF);
1249 break;
1250 case MP_GPIO_IER_HI:
1251 s->ier = (s->ier & 0xFFFF) | (value << 16);
1252 break;
1253
1254 case MP_GPIO_IMR_LO:
1255 s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF);
1256 break;
1257 case MP_GPIO_IMR_HI:
1258 s->imr = (s->imr & 0xFFFF) | (value << 16);
1259 break;
24859b68
AZ
1260 }
1261}
1262
d60efc6b 1263static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = {
718ec0be 1264 musicpal_gpio_read,
1265 musicpal_gpio_read,
1266 musicpal_gpio_read,
1267};
1268
d60efc6b 1269static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = {
718ec0be 1270 musicpal_gpio_write,
1271 musicpal_gpio_write,
1272 musicpal_gpio_write,
1273};
1274
d5b61ddd 1275static void musicpal_gpio_reset(DeviceState *d)
718ec0be 1276{
d5b61ddd
JK
1277 musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state,
1278 sysbus_from_qdev(d));
30624c92
JK
1279
1280 s->lcd_brightness = 0;
1281 s->out_state = 0;
343ec8e4 1282 s->in_state = 0xffffffff;
708afdf3
JK
1283 s->ier = 0;
1284 s->imr = 0;
343ec8e4
BC
1285 s->isr = 0;
1286}
1287
81a322d4 1288static int musicpal_gpio_init(SysBusDevice *dev)
343ec8e4
BC
1289{
1290 musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
718ec0be 1291 int iomemtype;
1292
343ec8e4
BC
1293 sysbus_init_irq(dev, &s->irq);
1294
1eed09cb 1295 iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
343ec8e4
BC
1296 musicpal_gpio_writefn, s);
1297 sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
1298
708afdf3
JK
1299 qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1300
1301 qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
81a322d4
GH
1302
1303 return 0;
718ec0be 1304}
1305
d5b61ddd
JK
1306static const VMStateDescription musicpal_gpio_vmsd = {
1307 .name = "musicpal_gpio",
1308 .version_id = 1,
1309 .minimum_version_id = 1,
1310 .minimum_version_id_old = 1,
1311 .fields = (VMStateField[]) {
1312 VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state),
1313 VMSTATE_UINT32(out_state, musicpal_gpio_state),
1314 VMSTATE_UINT32(in_state, musicpal_gpio_state),
1315 VMSTATE_UINT32(ier, musicpal_gpio_state),
1316 VMSTATE_UINT32(imr, musicpal_gpio_state),
1317 VMSTATE_UINT32(isr, musicpal_gpio_state),
1318 VMSTATE_END_OF_LIST()
1319 }
1320};
1321
30624c92
JK
1322static SysBusDeviceInfo musicpal_gpio_info = {
1323 .init = musicpal_gpio_init,
1324 .qdev.name = "musicpal_gpio",
1325 .qdev.size = sizeof(musicpal_gpio_state),
1326 .qdev.reset = musicpal_gpio_reset,
d5b61ddd 1327 .qdev.vmsd = &musicpal_gpio_vmsd,
30624c92
JK
1328};
1329
24859b68 1330/* Keyboard codes & masks */
7c6ce4ba 1331#define KEY_RELEASED 0x80
24859b68
AZ
1332#define KEY_CODE 0x7f
1333
1334#define KEYCODE_TAB 0x0f
1335#define KEYCODE_ENTER 0x1c
1336#define KEYCODE_F 0x21
1337#define KEYCODE_M 0x32
1338
1339#define KEYCODE_EXTENDED 0xe0
1340#define KEYCODE_UP 0x48
1341#define KEYCODE_DOWN 0x50
1342#define KEYCODE_LEFT 0x4b
1343#define KEYCODE_RIGHT 0x4d
1344
708afdf3 1345#define MP_KEY_WHEEL_VOL (1 << 0)
343ec8e4
BC
1346#define MP_KEY_WHEEL_VOL_INV (1 << 1)
1347#define MP_KEY_WHEEL_NAV (1 << 2)
1348#define MP_KEY_WHEEL_NAV_INV (1 << 3)
1349#define MP_KEY_BTN_FAVORITS (1 << 4)
1350#define MP_KEY_BTN_MENU (1 << 5)
1351#define MP_KEY_BTN_VOLUME (1 << 6)
1352#define MP_KEY_BTN_NAVIGATION (1 << 7)
1353
1354typedef struct musicpal_key_state {
1355 SysBusDevice busdev;
1356 uint32_t kbd_extended;
708afdf3
JK
1357 uint32_t pressed_keys;
1358 qemu_irq out[8];
343ec8e4
BC
1359} musicpal_key_state;
1360
24859b68
AZ
1361static void musicpal_key_event(void *opaque, int keycode)
1362{
243cd13c 1363 musicpal_key_state *s = opaque;
24859b68 1364 uint32_t event = 0;
343ec8e4 1365 int i;
24859b68
AZ
1366
1367 if (keycode == KEYCODE_EXTENDED) {
343ec8e4 1368 s->kbd_extended = 1;
24859b68
AZ
1369 return;
1370 }
1371
49fedd0d 1372 if (s->kbd_extended) {
24859b68
AZ
1373 switch (keycode & KEY_CODE) {
1374 case KEYCODE_UP:
343ec8e4 1375 event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
24859b68
AZ
1376 break;
1377
1378 case KEYCODE_DOWN:
343ec8e4 1379 event = MP_KEY_WHEEL_NAV;
24859b68
AZ
1380 break;
1381
1382 case KEYCODE_LEFT:
343ec8e4 1383 event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
24859b68
AZ
1384 break;
1385
1386 case KEYCODE_RIGHT:
343ec8e4 1387 event = MP_KEY_WHEEL_VOL;
24859b68
AZ
1388 break;
1389 }
49fedd0d 1390 } else {
24859b68
AZ
1391 switch (keycode & KEY_CODE) {
1392 case KEYCODE_F:
343ec8e4 1393 event = MP_KEY_BTN_FAVORITS;
24859b68
AZ
1394 break;
1395
1396 case KEYCODE_TAB:
343ec8e4 1397 event = MP_KEY_BTN_VOLUME;
24859b68
AZ
1398 break;
1399
1400 case KEYCODE_ENTER:
343ec8e4 1401 event = MP_KEY_BTN_NAVIGATION;
24859b68
AZ
1402 break;
1403
1404 case KEYCODE_M:
343ec8e4 1405 event = MP_KEY_BTN_MENU;
24859b68
AZ
1406 break;
1407 }
7c6ce4ba 1408 /* Do not repeat already pressed buttons */
708afdf3 1409 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
7c6ce4ba 1410 event = 0;
708afdf3 1411 }
7c6ce4ba 1412 }
24859b68 1413
7c6ce4ba 1414 if (event) {
708afdf3
JK
1415 /* Raise GPIO pin first if repeating a key */
1416 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1417 for (i = 0; i <= 7; i++) {
1418 if (event & (1 << i)) {
1419 qemu_set_irq(s->out[i], 1);
1420 }
1421 }
1422 }
1423 for (i = 0; i <= 7; i++) {
1424 if (event & (1 << i)) {
1425 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
1426 }
1427 }
7c6ce4ba 1428 if (keycode & KEY_RELEASED) {
708afdf3 1429 s->pressed_keys &= ~event;
7c6ce4ba 1430 } else {
708afdf3 1431 s->pressed_keys |= event;
7c6ce4ba 1432 }
24859b68
AZ
1433 }
1434
343ec8e4
BC
1435 s->kbd_extended = 0;
1436}
1437
81a322d4 1438static int musicpal_key_init(SysBusDevice *dev)
343ec8e4
BC
1439{
1440 musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1441
1442 sysbus_init_mmio(dev, 0x0, 0);
1443
1444 s->kbd_extended = 0;
708afdf3 1445 s->pressed_keys = 0;
343ec8e4 1446
708afdf3 1447 qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
343ec8e4
BC
1448
1449 qemu_add_kbd_event_handler(musicpal_key_event, s);
81a322d4
GH
1450
1451 return 0;
24859b68
AZ
1452}
1453
d5b61ddd
JK
1454static const VMStateDescription musicpal_key_vmsd = {
1455 .name = "musicpal_key",
1456 .version_id = 1,
1457 .minimum_version_id = 1,
1458 .minimum_version_id_old = 1,
1459 .fields = (VMStateField[]) {
1460 VMSTATE_UINT32(kbd_extended, musicpal_key_state),
1461 VMSTATE_UINT32(pressed_keys, musicpal_key_state),
1462 VMSTATE_END_OF_LIST()
1463 }
1464};
1465
1466static SysBusDeviceInfo musicpal_key_info = {
1467 .init = musicpal_key_init,
1468 .qdev.name = "musicpal_key",
1469 .qdev.size = sizeof(musicpal_key_state),
1470 .qdev.vmsd = &musicpal_key_vmsd,
1471};
1472
24859b68
AZ
1473static struct arm_boot_info musicpal_binfo = {
1474 .loader_start = 0x0,
1475 .board_id = 0x20e,
1476};
1477
c227f099 1478static void musicpal_init(ram_addr_t ram_size,
3023f332 1479 const char *boot_device,
24859b68
AZ
1480 const char *kernel_filename, const char *kernel_cmdline,
1481 const char *initrd_filename, const char *cpu_model)
1482{
1483 CPUState *env;
b47b50fa
PB
1484 qemu_irq *cpu_pic;
1485 qemu_irq pic[32];
1486 DeviceState *dev;
d074769c 1487 DeviceState *i2c_dev;
343ec8e4
BC
1488 DeviceState *lcd_dev;
1489 DeviceState *key_dev;
d074769c
AZ
1490 DeviceState *wm8750_dev;
1491 SysBusDevice *s;
d074769c 1492 i2c_bus *i2c;
b47b50fa 1493 int i;
24859b68 1494 unsigned long flash_size;
751c6a17 1495 DriveInfo *dinfo;
c227f099 1496 ram_addr_t sram_off;
24859b68 1497
49fedd0d 1498 if (!cpu_model) {
24859b68 1499 cpu_model = "arm926";
49fedd0d 1500 }
24859b68
AZ
1501 env = cpu_init(cpu_model);
1502 if (!env) {
1503 fprintf(stderr, "Unable to find CPU definition\n");
1504 exit(1);
1505 }
b47b50fa 1506 cpu_pic = arm_pic_init_cpu(env);
24859b68
AZ
1507
1508 /* For now we use a fixed - the original - RAM size */
1509 cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1724f049
AW
1510 qemu_ram_alloc(NULL, "musicpal.ram",
1511 MP_RAM_DEFAULT_SIZE));
24859b68 1512
1724f049 1513 sram_off = qemu_ram_alloc(NULL, "musicpal.sram", MP_SRAM_SIZE);
24859b68
AZ
1514 cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1515
b47b50fa
PB
1516 dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1517 cpu_pic[ARM_PIC_CPU_IRQ]);
1518 for (i = 0; i < 32; i++) {
067a3ddc 1519 pic[i] = qdev_get_gpio_in(dev, i);
b47b50fa
PB
1520 }
1521 sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1522 pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1523 pic[MP_TIMER4_IRQ], NULL);
24859b68 1524
49fedd0d 1525 if (serial_hds[0]) {
2d48377a 1526#ifdef TARGET_WORDS_BIGENDIAN
b6cd0ea1 1527 serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
2d48377a
BS
1528 serial_hds[0], 1, 1);
1529#else
1530 serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1531 serial_hds[0], 1, 0);
1532#endif
49fedd0d
JK
1533 }
1534 if (serial_hds[1]) {
2d48377a 1535#ifdef TARGET_WORDS_BIGENDIAN
b6cd0ea1 1536 serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
2d48377a
BS
1537 serial_hds[1], 1, 1);
1538#else
1539 serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1540 serial_hds[1], 1, 0);
1541#endif
49fedd0d 1542 }
24859b68
AZ
1543
1544 /* Register flash */
751c6a17
GH
1545 dinfo = drive_get(IF_PFLASH, 0, 0);
1546 if (dinfo) {
1547 flash_size = bdrv_getlength(dinfo->bdrv);
24859b68
AZ
1548 if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1549 flash_size != 32*1024*1024) {
1550 fprintf(stderr, "Invalid flash image size\n");
1551 exit(1);
1552 }
1553
1554 /*
1555 * The original U-Boot accesses the flash at 0xFE000000 instead of
1556 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1557 * image is smaller than 32 MB.
1558 */
5f9fc5ad 1559#ifdef TARGET_WORDS_BIGENDIAN
1724f049
AW
1560 pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
1561 "musicpal.flash", flash_size),
751c6a17 1562 dinfo->bdrv, 0x10000,
24859b68
AZ
1563 (flash_size + 0xffff) >> 16,
1564 MP_FLASH_SIZE_MAX / flash_size,
1565 2, 0x00BF, 0x236D, 0x0000, 0x0000,
5f9fc5ad
BS
1566 0x5555, 0x2AAA, 1);
1567#else
1724f049
AW
1568 pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
1569 "musicpal.flash", flash_size),
5f9fc5ad
BS
1570 dinfo->bdrv, 0x10000,
1571 (flash_size + 0xffff) >> 16,
1572 MP_FLASH_SIZE_MAX / flash_size,
1573 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1574 0x5555, 0x2AAA, 0);
1575#endif
1576
24859b68 1577 }
b47b50fa 1578 sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
24859b68 1579
b47b50fa
PB
1580 qemu_check_nic_model(&nd_table[0], "mv88w8618");
1581 dev = qdev_create(NULL, "mv88w8618_eth");
4c91cd28 1582 qdev_set_nic_properties(dev, &nd_table[0]);
e23a1b33 1583 qdev_init_nofail(dev);
b47b50fa
PB
1584 sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1585 sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
24859b68 1586
b47b50fa 1587 sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
718ec0be 1588
1589 musicpal_misc_init();
343ec8e4
BC
1590
1591 dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
3cd035d8 1592 i2c_dev = sysbus_create_simple("gpio_i2c", 0, NULL);
d074769c
AZ
1593 i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1594
343ec8e4
BC
1595 lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1596 key_dev = sysbus_create_simple("musicpal_key", 0, NULL);
1597
d074769c 1598 /* I2C read data */
708afdf3
JK
1599 qdev_connect_gpio_out(i2c_dev, 0,
1600 qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT));
d074769c
AZ
1601 /* I2C data */
1602 qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1603 /* I2C clock */
1604 qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1605
49fedd0d 1606 for (i = 0; i < 3; i++) {
343ec8e4 1607 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
49fedd0d 1608 }
708afdf3
JK
1609 for (i = 0; i < 4; i++) {
1610 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
1611 }
1612 for (i = 4; i < 8; i++) {
1613 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
1614 }
24859b68 1615
d074769c
AZ
1616 wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1617 dev = qdev_create(NULL, "mv88w8618_audio");
1618 s = sysbus_from_qdev(dev);
1619 qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
e23a1b33 1620 qdev_init_nofail(dev);
d074769c
AZ
1621 sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1622 sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
d074769c 1623
24859b68
AZ
1624 musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1625 musicpal_binfo.kernel_filename = kernel_filename;
1626 musicpal_binfo.kernel_cmdline = kernel_cmdline;
1627 musicpal_binfo.initrd_filename = initrd_filename;
b0f6edb1 1628 arm_load_kernel(env, &musicpal_binfo);
24859b68
AZ
1629}
1630
f80f9ec9 1631static QEMUMachine musicpal_machine = {
4b32e168
AL
1632 .name = "musicpal",
1633 .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1634 .init = musicpal_init,
24859b68 1635};
b47b50fa 1636
f80f9ec9
AL
1637static void musicpal_machine_init(void)
1638{
1639 qemu_register_machine(&musicpal_machine);
1640}
1641
1642machine_init(musicpal_machine_init);
1643
b47b50fa
PB
1644static void musicpal_register_devices(void)
1645{
d5b61ddd 1646 sysbus_register_withprop(&mv88w8618_pic_info);
c88d6bde 1647 sysbus_register_withprop(&mv88w8618_pit_info);
d5b61ddd
JK
1648 sysbus_register_withprop(&mv88w8618_flashcfg_info);
1649 sysbus_register_withprop(&mv88w8618_eth_info);
b47b50fa
PB
1650 sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice),
1651 mv88w8618_wlan_init);
d5b61ddd 1652 sysbus_register_withprop(&musicpal_lcd_info);
30624c92 1653 sysbus_register_withprop(&musicpal_gpio_info);
d5b61ddd 1654 sysbus_register_withprop(&musicpal_key_info);
b47b50fa
PB
1655}
1656
1657device_init(musicpal_register_devices)