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Commit | Line | Data |
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24859b68 AZ |
1 | /* |
2 | * Marvell MV88W8618 / Freecom MusicPal emulation. | |
3 | * | |
4 | * Copyright (c) 2008 Jan Kiszka | |
5 | * | |
6 | * This code is licenced under the GNU GPL v2. | |
7 | */ | |
8 | ||
b47b50fa | 9 | #include "sysbus.h" |
24859b68 AZ |
10 | #include "arm-misc.h" |
11 | #include "devices.h" | |
12 | #include "net.h" | |
13 | #include "sysemu.h" | |
14 | #include "boards.h" | |
15 | #include "pc.h" | |
16 | #include "qemu-timer.h" | |
17 | #include "block.h" | |
18 | #include "flash.h" | |
19 | #include "console.h" | |
20 | #include "audio/audio.h" | |
21 | #include "i2c.h" | |
22 | ||
718ec0be | 23 | #define MP_MISC_BASE 0x80002000 |
24 | #define MP_MISC_SIZE 0x00001000 | |
25 | ||
24859b68 AZ |
26 | #define MP_ETH_BASE 0x80008000 |
27 | #define MP_ETH_SIZE 0x00001000 | |
28 | ||
718ec0be | 29 | #define MP_WLAN_BASE 0x8000C000 |
30 | #define MP_WLAN_SIZE 0x00000800 | |
31 | ||
24859b68 AZ |
32 | #define MP_UART1_BASE 0x8000C840 |
33 | #define MP_UART2_BASE 0x8000C940 | |
34 | ||
718ec0be | 35 | #define MP_GPIO_BASE 0x8000D000 |
36 | #define MP_GPIO_SIZE 0x00001000 | |
37 | ||
24859b68 AZ |
38 | #define MP_FLASHCFG_BASE 0x90006000 |
39 | #define MP_FLASHCFG_SIZE 0x00001000 | |
40 | ||
41 | #define MP_AUDIO_BASE 0x90007000 | |
42 | #define MP_AUDIO_SIZE 0x00001000 | |
43 | ||
44 | #define MP_PIC_BASE 0x90008000 | |
45 | #define MP_PIC_SIZE 0x00001000 | |
46 | ||
47 | #define MP_PIT_BASE 0x90009000 | |
48 | #define MP_PIT_SIZE 0x00001000 | |
49 | ||
50 | #define MP_LCD_BASE 0x9000c000 | |
51 | #define MP_LCD_SIZE 0x00001000 | |
52 | ||
53 | #define MP_SRAM_BASE 0xC0000000 | |
54 | #define MP_SRAM_SIZE 0x00020000 | |
55 | ||
56 | #define MP_RAM_DEFAULT_SIZE 32*1024*1024 | |
57 | #define MP_FLASH_SIZE_MAX 32*1024*1024 | |
58 | ||
59 | #define MP_TIMER1_IRQ 4 | |
b47b50fa PB |
60 | #define MP_TIMER2_IRQ 5 |
61 | #define MP_TIMER3_IRQ 6 | |
24859b68 AZ |
62 | #define MP_TIMER4_IRQ 7 |
63 | #define MP_EHCI_IRQ 8 | |
64 | #define MP_ETH_IRQ 9 | |
65 | #define MP_UART1_IRQ 11 | |
66 | #define MP_UART2_IRQ 11 | |
67 | #define MP_GPIO_IRQ 12 | |
68 | #define MP_RTC_IRQ 28 | |
69 | #define MP_AUDIO_IRQ 30 | |
70 | ||
24859b68 AZ |
71 | static ram_addr_t sram_off; |
72 | ||
24859b68 AZ |
73 | typedef enum i2c_state { |
74 | STOPPED = 0, | |
75 | INITIALIZING, | |
76 | SENDING_BIT7, | |
77 | SENDING_BIT6, | |
78 | SENDING_BIT5, | |
79 | SENDING_BIT4, | |
80 | SENDING_BIT3, | |
81 | SENDING_BIT2, | |
82 | SENDING_BIT1, | |
83 | SENDING_BIT0, | |
84 | WAITING_FOR_ACK, | |
85 | RECEIVING_BIT7, | |
86 | RECEIVING_BIT6, | |
87 | RECEIVING_BIT5, | |
88 | RECEIVING_BIT4, | |
89 | RECEIVING_BIT3, | |
90 | RECEIVING_BIT2, | |
91 | RECEIVING_BIT1, | |
92 | RECEIVING_BIT0, | |
93 | SENDING_ACK | |
94 | } i2c_state; | |
95 | ||
96 | typedef struct i2c_interface { | |
97 | i2c_bus *bus; | |
98 | i2c_state state; | |
99 | int last_data; | |
100 | int last_clock; | |
101 | uint8_t buffer; | |
102 | int current_addr; | |
103 | } i2c_interface; | |
104 | ||
105 | static void i2c_enter_stop(i2c_interface *i2c) | |
106 | { | |
107 | if (i2c->current_addr >= 0) | |
108 | i2c_end_transfer(i2c->bus); | |
109 | i2c->current_addr = -1; | |
110 | i2c->state = STOPPED; | |
111 | } | |
112 | ||
113 | static void i2c_state_update(i2c_interface *i2c, int data, int clock) | |
114 | { | |
115 | if (!i2c) | |
116 | return; | |
117 | ||
118 | switch (i2c->state) { | |
119 | case STOPPED: | |
120 | if (data == 0 && i2c->last_data == 1 && clock == 1) | |
121 | i2c->state = INITIALIZING; | |
122 | break; | |
123 | ||
124 | case INITIALIZING: | |
125 | if (clock == 0 && i2c->last_clock == 1 && data == 0) | |
126 | i2c->state = SENDING_BIT7; | |
127 | else | |
128 | i2c_enter_stop(i2c); | |
129 | break; | |
130 | ||
131 | case SENDING_BIT7 ... SENDING_BIT0: | |
132 | if (clock == 0 && i2c->last_clock == 1) { | |
133 | i2c->buffer = (i2c->buffer << 1) | data; | |
134 | i2c->state++; /* will end up in WAITING_FOR_ACK */ | |
135 | } else if (data == 1 && i2c->last_data == 0 && clock == 1) | |
136 | i2c_enter_stop(i2c); | |
137 | break; | |
138 | ||
139 | case WAITING_FOR_ACK: | |
140 | if (clock == 0 && i2c->last_clock == 1) { | |
141 | if (i2c->current_addr < 0) { | |
142 | i2c->current_addr = i2c->buffer; | |
143 | i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe, | |
144 | i2c->buffer & 1); | |
145 | } else | |
146 | i2c_send(i2c->bus, i2c->buffer); | |
147 | if (i2c->current_addr & 1) { | |
148 | i2c->state = RECEIVING_BIT7; | |
149 | i2c->buffer = i2c_recv(i2c->bus); | |
150 | } else | |
151 | i2c->state = SENDING_BIT7; | |
152 | } else if (data == 1 && i2c->last_data == 0 && clock == 1) | |
153 | i2c_enter_stop(i2c); | |
154 | break; | |
155 | ||
156 | case RECEIVING_BIT7 ... RECEIVING_BIT0: | |
157 | if (clock == 0 && i2c->last_clock == 1) { | |
158 | i2c->state++; /* will end up in SENDING_ACK */ | |
159 | i2c->buffer <<= 1; | |
160 | } else if (data == 1 && i2c->last_data == 0 && clock == 1) | |
161 | i2c_enter_stop(i2c); | |
162 | break; | |
163 | ||
164 | case SENDING_ACK: | |
165 | if (clock == 0 && i2c->last_clock == 1) { | |
166 | i2c->state = RECEIVING_BIT7; | |
167 | if (data == 0) | |
168 | i2c->buffer = i2c_recv(i2c->bus); | |
169 | else | |
170 | i2c_nack(i2c->bus); | |
171 | } else if (data == 1 && i2c->last_data == 0 && clock == 1) | |
172 | i2c_enter_stop(i2c); | |
173 | break; | |
174 | } | |
175 | ||
176 | i2c->last_data = data; | |
177 | i2c->last_clock = clock; | |
178 | } | |
179 | ||
180 | static int i2c_get_data(i2c_interface *i2c) | |
181 | { | |
182 | if (!i2c) | |
183 | return 0; | |
184 | ||
185 | switch (i2c->state) { | |
186 | case RECEIVING_BIT7 ... RECEIVING_BIT0: | |
187 | return (i2c->buffer >> 7); | |
188 | ||
189 | case WAITING_FOR_ACK: | |
190 | default: | |
191 | return 0; | |
192 | } | |
193 | } | |
194 | ||
195 | static i2c_interface *mixer_i2c; | |
196 | ||
197 | #ifdef HAS_AUDIO | |
198 | ||
199 | /* Audio register offsets */ | |
200 | #define MP_AUDIO_PLAYBACK_MODE 0x00 | |
201 | #define MP_AUDIO_CLOCK_DIV 0x18 | |
202 | #define MP_AUDIO_IRQ_STATUS 0x20 | |
203 | #define MP_AUDIO_IRQ_ENABLE 0x24 | |
204 | #define MP_AUDIO_TX_START_LO 0x28 | |
205 | #define MP_AUDIO_TX_THRESHOLD 0x2C | |
206 | #define MP_AUDIO_TX_STATUS 0x38 | |
207 | #define MP_AUDIO_TX_START_HI 0x40 | |
208 | ||
209 | /* Status register and IRQ enable bits */ | |
210 | #define MP_AUDIO_TX_HALF (1 << 6) | |
211 | #define MP_AUDIO_TX_FULL (1 << 7) | |
212 | ||
213 | /* Playback mode bits */ | |
214 | #define MP_AUDIO_16BIT_SAMPLE (1 << 0) | |
215 | #define MP_AUDIO_PLAYBACK_EN (1 << 7) | |
216 | #define MP_AUDIO_CLOCK_24MHZ (1 << 9) | |
4001a81e | 217 | #define MP_AUDIO_MONO (1 << 14) |
24859b68 AZ |
218 | |
219 | /* Wolfson 8750 I2C address */ | |
220 | #define MP_WM_ADDR 0x34 | |
221 | ||
b1d8e52e | 222 | static const char audio_name[] = "mv88w8618"; |
24859b68 AZ |
223 | |
224 | typedef struct musicpal_audio_state { | |
24859b68 AZ |
225 | qemu_irq irq; |
226 | uint32_t playback_mode; | |
227 | uint32_t status; | |
228 | uint32_t irq_enable; | |
229 | unsigned long phys_buf; | |
930c8682 | 230 | uint32_t target_buffer; |
24859b68 AZ |
231 | unsigned int threshold; |
232 | unsigned int play_pos; | |
233 | unsigned int last_free; | |
234 | uint32_t clock_div; | |
cdbe40ca | 235 | DeviceState *wm; |
24859b68 AZ |
236 | } musicpal_audio_state; |
237 | ||
238 | static void audio_callback(void *opaque, int free_out, int free_in) | |
239 | { | |
240 | musicpal_audio_state *s = opaque; | |
4f3cb3be | 241 | int16_t *codec_buffer; |
930c8682 | 242 | int8_t buf[4096]; |
a350e694 | 243 | int8_t *mem_buffer; |
24859b68 AZ |
244 | int pos, block_size; |
245 | ||
246 | if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) | |
247 | return; | |
248 | ||
249 | if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) | |
4001a81e AZ |
250 | free_out <<= 1; |
251 | ||
252 | if (!(s->playback_mode & MP_AUDIO_MONO)) | |
24859b68 AZ |
253 | free_out <<= 1; |
254 | ||
255 | block_size = s->threshold/2; | |
256 | if (free_out - s->last_free < block_size) | |
257 | return; | |
258 | ||
930c8682 PB |
259 | if (block_size > 4096) |
260 | return; | |
261 | ||
262 | cpu_physical_memory_read(s->target_buffer + s->play_pos, (void *)buf, | |
263 | block_size); | |
264 | mem_buffer = buf; | |
4001a81e AZ |
265 | if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) { |
266 | if (s->playback_mode & MP_AUDIO_MONO) { | |
267 | codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1); | |
268 | for (pos = 0; pos < block_size; pos += 2) { | |
a350e694 AZ |
269 | *codec_buffer++ = *(int16_t *)mem_buffer; |
270 | *codec_buffer++ = *(int16_t *)mem_buffer; | |
4f3cb3be | 271 | mem_buffer += 2; |
4001a81e AZ |
272 | } |
273 | } else | |
274 | memcpy(wm8750_dac_buffer(s->wm, block_size >> 2), | |
275 | (uint32_t *)mem_buffer, block_size); | |
276 | } else { | |
277 | if (s->playback_mode & MP_AUDIO_MONO) { | |
278 | codec_buffer = wm8750_dac_buffer(s->wm, block_size); | |
279 | for (pos = 0; pos < block_size; pos++) { | |
a350e694 AZ |
280 | *codec_buffer++ = cpu_to_le16(256 * *mem_buffer); |
281 | *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++); | |
4001a81e AZ |
282 | } |
283 | } else { | |
284 | codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1); | |
285 | for (pos = 0; pos < block_size; pos += 2) { | |
a350e694 AZ |
286 | *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++); |
287 | *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++); | |
4001a81e | 288 | } |
24859b68 | 289 | } |
662caa6f AZ |
290 | } |
291 | wm8750_dac_commit(s->wm); | |
24859b68 AZ |
292 | |
293 | s->last_free = free_out - block_size; | |
294 | ||
295 | if (s->play_pos == 0) { | |
296 | s->status |= MP_AUDIO_TX_HALF; | |
297 | s->play_pos = block_size; | |
298 | } else { | |
299 | s->status |= MP_AUDIO_TX_FULL; | |
300 | s->play_pos = 0; | |
301 | } | |
302 | ||
303 | if (s->status & s->irq_enable) | |
304 | qemu_irq_raise(s->irq); | |
305 | } | |
306 | ||
af83e09e AZ |
307 | static void musicpal_audio_clock_update(musicpal_audio_state *s) |
308 | { | |
309 | int rate; | |
310 | ||
311 | if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ) | |
312 | rate = 24576000 / 64; /* 24.576MHz */ | |
313 | else | |
314 | rate = 11289600 / 64; /* 11.2896MHz */ | |
315 | ||
316 | rate /= ((s->clock_div >> 8) & 0xff) + 1; | |
317 | ||
91834991 | 318 | wm8750_set_bclk_in(s->wm, rate); |
af83e09e AZ |
319 | } |
320 | ||
24859b68 AZ |
321 | static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset) |
322 | { | |
323 | musicpal_audio_state *s = opaque; | |
324 | ||
24859b68 AZ |
325 | switch (offset) { |
326 | case MP_AUDIO_PLAYBACK_MODE: | |
327 | return s->playback_mode; | |
328 | ||
329 | case MP_AUDIO_CLOCK_DIV: | |
330 | return s->clock_div; | |
331 | ||
332 | case MP_AUDIO_IRQ_STATUS: | |
333 | return s->status; | |
334 | ||
335 | case MP_AUDIO_IRQ_ENABLE: | |
336 | return s->irq_enable; | |
337 | ||
338 | case MP_AUDIO_TX_STATUS: | |
339 | return s->play_pos >> 2; | |
340 | ||
341 | default: | |
342 | return 0; | |
343 | } | |
344 | } | |
345 | ||
346 | static void musicpal_audio_write(void *opaque, target_phys_addr_t offset, | |
347 | uint32_t value) | |
348 | { | |
349 | musicpal_audio_state *s = opaque; | |
350 | ||
24859b68 AZ |
351 | switch (offset) { |
352 | case MP_AUDIO_PLAYBACK_MODE: | |
353 | if (value & MP_AUDIO_PLAYBACK_EN && | |
354 | !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) { | |
355 | s->status = 0; | |
356 | s->last_free = 0; | |
357 | s->play_pos = 0; | |
358 | } | |
359 | s->playback_mode = value; | |
af83e09e | 360 | musicpal_audio_clock_update(s); |
24859b68 AZ |
361 | break; |
362 | ||
363 | case MP_AUDIO_CLOCK_DIV: | |
364 | s->clock_div = value; | |
365 | s->last_free = 0; | |
366 | s->play_pos = 0; | |
af83e09e | 367 | musicpal_audio_clock_update(s); |
24859b68 AZ |
368 | break; |
369 | ||
370 | case MP_AUDIO_IRQ_STATUS: | |
371 | s->status &= ~value; | |
372 | break; | |
373 | ||
374 | case MP_AUDIO_IRQ_ENABLE: | |
375 | s->irq_enable = value; | |
376 | if (s->status & s->irq_enable) | |
377 | qemu_irq_raise(s->irq); | |
378 | break; | |
379 | ||
380 | case MP_AUDIO_TX_START_LO: | |
381 | s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF); | |
930c8682 | 382 | s->target_buffer = s->phys_buf; |
24859b68 AZ |
383 | s->play_pos = 0; |
384 | s->last_free = 0; | |
385 | break; | |
386 | ||
387 | case MP_AUDIO_TX_THRESHOLD: | |
388 | s->threshold = (value + 1) * 4; | |
389 | break; | |
390 | ||
391 | case MP_AUDIO_TX_START_HI: | |
392 | s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16); | |
930c8682 | 393 | s->target_buffer = s->phys_buf; |
24859b68 AZ |
394 | s->play_pos = 0; |
395 | s->last_free = 0; | |
396 | break; | |
397 | } | |
398 | } | |
399 | ||
400 | static void musicpal_audio_reset(void *opaque) | |
401 | { | |
402 | musicpal_audio_state *s = opaque; | |
403 | ||
404 | s->playback_mode = 0; | |
405 | s->status = 0; | |
406 | s->irq_enable = 0; | |
407 | } | |
408 | ||
409 | static CPUReadMemoryFunc *musicpal_audio_readfn[] = { | |
410 | musicpal_audio_read, | |
411 | musicpal_audio_read, | |
412 | musicpal_audio_read | |
413 | }; | |
414 | ||
415 | static CPUWriteMemoryFunc *musicpal_audio_writefn[] = { | |
416 | musicpal_audio_write, | |
417 | musicpal_audio_write, | |
418 | musicpal_audio_write | |
419 | }; | |
420 | ||
718ec0be | 421 | static i2c_interface *musicpal_audio_init(qemu_irq irq) |
24859b68 | 422 | { |
24859b68 AZ |
423 | musicpal_audio_state *s; |
424 | i2c_interface *i2c; | |
425 | int iomemtype; | |
426 | ||
24859b68 | 427 | s = qemu_mallocz(sizeof(musicpal_audio_state)); |
24859b68 AZ |
428 | s->irq = irq; |
429 | ||
430 | i2c = qemu_mallocz(sizeof(i2c_interface)); | |
02e2da45 | 431 | i2c->bus = i2c_init_bus(NULL, "i2c"); |
24859b68 AZ |
432 | i2c->current_addr = -1; |
433 | ||
cdbe40ca | 434 | s->wm = i2c_create_slave(i2c->bus, "wm8750", MP_WM_ADDR); |
24859b68 AZ |
435 | wm8750_data_req_set(s->wm, audio_callback, s); |
436 | ||
1eed09cb | 437 | iomemtype = cpu_register_io_memory(musicpal_audio_readfn, |
24859b68 | 438 | musicpal_audio_writefn, s); |
718ec0be | 439 | cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype); |
24859b68 | 440 | |
a08d4367 | 441 | qemu_register_reset(musicpal_audio_reset, s); |
24859b68 AZ |
442 | |
443 | return i2c; | |
444 | } | |
445 | #else /* !HAS_AUDIO */ | |
718ec0be | 446 | static i2c_interface *musicpal_audio_init(qemu_irq irq) |
24859b68 AZ |
447 | { |
448 | return NULL; | |
449 | } | |
450 | #endif /* !HAS_AUDIO */ | |
451 | ||
452 | /* Ethernet register offsets */ | |
453 | #define MP_ETH_SMIR 0x010 | |
454 | #define MP_ETH_PCXR 0x408 | |
455 | #define MP_ETH_SDCMR 0x448 | |
456 | #define MP_ETH_ICR 0x450 | |
457 | #define MP_ETH_IMR 0x458 | |
458 | #define MP_ETH_FRDP0 0x480 | |
459 | #define MP_ETH_FRDP1 0x484 | |
460 | #define MP_ETH_FRDP2 0x488 | |
461 | #define MP_ETH_FRDP3 0x48C | |
462 | #define MP_ETH_CRDP0 0x4A0 | |
463 | #define MP_ETH_CRDP1 0x4A4 | |
464 | #define MP_ETH_CRDP2 0x4A8 | |
465 | #define MP_ETH_CRDP3 0x4AC | |
466 | #define MP_ETH_CTDP0 0x4E0 | |
467 | #define MP_ETH_CTDP1 0x4E4 | |
468 | #define MP_ETH_CTDP2 0x4E8 | |
469 | #define MP_ETH_CTDP3 0x4EC | |
470 | ||
471 | /* MII PHY access */ | |
472 | #define MP_ETH_SMIR_DATA 0x0000FFFF | |
473 | #define MP_ETH_SMIR_ADDR 0x03FF0000 | |
474 | #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ | |
475 | #define MP_ETH_SMIR_RDVALID (1 << 27) | |
476 | ||
477 | /* PHY registers */ | |
478 | #define MP_ETH_PHY1_BMSR 0x00210000 | |
479 | #define MP_ETH_PHY1_PHYSID1 0x00410000 | |
480 | #define MP_ETH_PHY1_PHYSID2 0x00610000 | |
481 | ||
482 | #define MP_PHY_BMSR_LINK 0x0004 | |
483 | #define MP_PHY_BMSR_AUTONEG 0x0008 | |
484 | ||
485 | #define MP_PHY_88E3015 0x01410E20 | |
486 | ||
487 | /* TX descriptor status */ | |
488 | #define MP_ETH_TX_OWN (1 << 31) | |
489 | ||
490 | /* RX descriptor status */ | |
491 | #define MP_ETH_RX_OWN (1 << 31) | |
492 | ||
493 | /* Interrupt cause/mask bits */ | |
494 | #define MP_ETH_IRQ_RX_BIT 0 | |
495 | #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) | |
496 | #define MP_ETH_IRQ_TXHI_BIT 2 | |
497 | #define MP_ETH_IRQ_TXLO_BIT 3 | |
498 | ||
499 | /* Port config bits */ | |
500 | #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ | |
501 | ||
502 | /* SDMA command bits */ | |
503 | #define MP_ETH_CMD_TXHI (1 << 23) | |
504 | #define MP_ETH_CMD_TXLO (1 << 22) | |
505 | ||
506 | typedef struct mv88w8618_tx_desc { | |
507 | uint32_t cmdstat; | |
508 | uint16_t res; | |
509 | uint16_t bytes; | |
510 | uint32_t buffer; | |
511 | uint32_t next; | |
512 | } mv88w8618_tx_desc; | |
513 | ||
514 | typedef struct mv88w8618_rx_desc { | |
515 | uint32_t cmdstat; | |
516 | uint16_t bytes; | |
517 | uint16_t buffer_size; | |
518 | uint32_t buffer; | |
519 | uint32_t next; | |
520 | } mv88w8618_rx_desc; | |
521 | ||
522 | typedef struct mv88w8618_eth_state { | |
b47b50fa | 523 | SysBusDevice busdev; |
24859b68 AZ |
524 | qemu_irq irq; |
525 | uint32_t smir; | |
526 | uint32_t icr; | |
527 | uint32_t imr; | |
b946a153 | 528 | int mmio_index; |
24859b68 | 529 | int vlan_header; |
930c8682 PB |
530 | uint32_t tx_queue[2]; |
531 | uint32_t rx_queue[4]; | |
532 | uint32_t frx_queue[4]; | |
533 | uint32_t cur_rx[4]; | |
24859b68 AZ |
534 | VLANClientState *vc; |
535 | } mv88w8618_eth_state; | |
536 | ||
930c8682 PB |
537 | static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) |
538 | { | |
539 | cpu_to_le32s(&desc->cmdstat); | |
540 | cpu_to_le16s(&desc->bytes); | |
541 | cpu_to_le16s(&desc->buffer_size); | |
542 | cpu_to_le32s(&desc->buffer); | |
543 | cpu_to_le32s(&desc->next); | |
544 | cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); | |
545 | } | |
546 | ||
547 | static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) | |
548 | { | |
549 | cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); | |
550 | le32_to_cpus(&desc->cmdstat); | |
551 | le16_to_cpus(&desc->bytes); | |
552 | le16_to_cpus(&desc->buffer_size); | |
553 | le32_to_cpus(&desc->buffer); | |
554 | le32_to_cpus(&desc->next); | |
555 | } | |
556 | ||
e3f5ec2b | 557 | static int eth_can_receive(VLANClientState *vc) |
24859b68 AZ |
558 | { |
559 | return 1; | |
560 | } | |
561 | ||
4f1c942b | 562 | static ssize_t eth_receive(VLANClientState *vc, const uint8_t *buf, size_t size) |
24859b68 | 563 | { |
e3f5ec2b | 564 | mv88w8618_eth_state *s = vc->opaque; |
930c8682 PB |
565 | uint32_t desc_addr; |
566 | mv88w8618_rx_desc desc; | |
24859b68 AZ |
567 | int i; |
568 | ||
569 | for (i = 0; i < 4; i++) { | |
930c8682 PB |
570 | desc_addr = s->cur_rx[i]; |
571 | if (!desc_addr) | |
24859b68 AZ |
572 | continue; |
573 | do { | |
930c8682 PB |
574 | eth_rx_desc_get(desc_addr, &desc); |
575 | if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) { | |
576 | cpu_physical_memory_write(desc.buffer + s->vlan_header, | |
577 | buf, size); | |
578 | desc.bytes = size + s->vlan_header; | |
579 | desc.cmdstat &= ~MP_ETH_RX_OWN; | |
580 | s->cur_rx[i] = desc.next; | |
24859b68 AZ |
581 | |
582 | s->icr |= MP_ETH_IRQ_RX; | |
583 | if (s->icr & s->imr) | |
584 | qemu_irq_raise(s->irq); | |
930c8682 | 585 | eth_rx_desc_put(desc_addr, &desc); |
4f1c942b | 586 | return size; |
24859b68 | 587 | } |
930c8682 PB |
588 | desc_addr = desc.next; |
589 | } while (desc_addr != s->rx_queue[i]); | |
24859b68 | 590 | } |
4f1c942b | 591 | return size; |
24859b68 AZ |
592 | } |
593 | ||
930c8682 PB |
594 | static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) |
595 | { | |
596 | cpu_to_le32s(&desc->cmdstat); | |
597 | cpu_to_le16s(&desc->res); | |
598 | cpu_to_le16s(&desc->bytes); | |
599 | cpu_to_le32s(&desc->buffer); | |
600 | cpu_to_le32s(&desc->next); | |
601 | cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); | |
602 | } | |
603 | ||
604 | static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) | |
605 | { | |
606 | cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); | |
607 | le32_to_cpus(&desc->cmdstat); | |
608 | le16_to_cpus(&desc->res); | |
609 | le16_to_cpus(&desc->bytes); | |
610 | le32_to_cpus(&desc->buffer); | |
611 | le32_to_cpus(&desc->next); | |
612 | } | |
613 | ||
24859b68 AZ |
614 | static void eth_send(mv88w8618_eth_state *s, int queue_index) |
615 | { | |
930c8682 PB |
616 | uint32_t desc_addr = s->tx_queue[queue_index]; |
617 | mv88w8618_tx_desc desc; | |
618 | uint8_t buf[2048]; | |
619 | int len; | |
620 | ||
24859b68 AZ |
621 | |
622 | do { | |
930c8682 PB |
623 | eth_tx_desc_get(desc_addr, &desc); |
624 | if (desc.cmdstat & MP_ETH_TX_OWN) { | |
625 | len = desc.bytes; | |
626 | if (len < 2048) { | |
627 | cpu_physical_memory_read(desc.buffer, buf, len); | |
628 | qemu_send_packet(s->vc, buf, len); | |
629 | } | |
630 | desc.cmdstat &= ~MP_ETH_TX_OWN; | |
24859b68 | 631 | s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index); |
930c8682 | 632 | eth_tx_desc_put(desc_addr, &desc); |
24859b68 | 633 | } |
930c8682 PB |
634 | desc_addr = desc.next; |
635 | } while (desc_addr != s->tx_queue[queue_index]); | |
24859b68 AZ |
636 | } |
637 | ||
638 | static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset) | |
639 | { | |
640 | mv88w8618_eth_state *s = opaque; | |
641 | ||
24859b68 AZ |
642 | switch (offset) { |
643 | case MP_ETH_SMIR: | |
644 | if (s->smir & MP_ETH_SMIR_OPCODE) { | |
645 | switch (s->smir & MP_ETH_SMIR_ADDR) { | |
646 | case MP_ETH_PHY1_BMSR: | |
647 | return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG | | |
648 | MP_ETH_SMIR_RDVALID; | |
649 | case MP_ETH_PHY1_PHYSID1: | |
650 | return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; | |
651 | case MP_ETH_PHY1_PHYSID2: | |
652 | return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; | |
653 | default: | |
654 | return MP_ETH_SMIR_RDVALID; | |
655 | } | |
656 | } | |
657 | return 0; | |
658 | ||
659 | case MP_ETH_ICR: | |
660 | return s->icr; | |
661 | ||
662 | case MP_ETH_IMR: | |
663 | return s->imr; | |
664 | ||
665 | case MP_ETH_FRDP0 ... MP_ETH_FRDP3: | |
930c8682 | 666 | return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; |
24859b68 AZ |
667 | |
668 | case MP_ETH_CRDP0 ... MP_ETH_CRDP3: | |
930c8682 | 669 | return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; |
24859b68 AZ |
670 | |
671 | case MP_ETH_CTDP0 ... MP_ETH_CTDP3: | |
930c8682 | 672 | return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; |
24859b68 AZ |
673 | |
674 | default: | |
675 | return 0; | |
676 | } | |
677 | } | |
678 | ||
679 | static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset, | |
680 | uint32_t value) | |
681 | { | |
682 | mv88w8618_eth_state *s = opaque; | |
683 | ||
24859b68 AZ |
684 | switch (offset) { |
685 | case MP_ETH_SMIR: | |
686 | s->smir = value; | |
687 | break; | |
688 | ||
689 | case MP_ETH_PCXR: | |
690 | s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; | |
691 | break; | |
692 | ||
693 | case MP_ETH_SDCMR: | |
694 | if (value & MP_ETH_CMD_TXHI) | |
695 | eth_send(s, 1); | |
696 | if (value & MP_ETH_CMD_TXLO) | |
697 | eth_send(s, 0); | |
698 | if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) | |
699 | qemu_irq_raise(s->irq); | |
700 | break; | |
701 | ||
702 | case MP_ETH_ICR: | |
703 | s->icr &= value; | |
704 | break; | |
705 | ||
706 | case MP_ETH_IMR: | |
707 | s->imr = value; | |
708 | if (s->icr & s->imr) | |
709 | qemu_irq_raise(s->irq); | |
710 | break; | |
711 | ||
712 | case MP_ETH_FRDP0 ... MP_ETH_FRDP3: | |
930c8682 | 713 | s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value; |
24859b68 AZ |
714 | break; |
715 | ||
716 | case MP_ETH_CRDP0 ... MP_ETH_CRDP3: | |
717 | s->rx_queue[(offset - MP_ETH_CRDP0)/4] = | |
930c8682 | 718 | s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value; |
24859b68 AZ |
719 | break; |
720 | ||
721 | case MP_ETH_CTDP0 ... MP_ETH_CTDP3: | |
930c8682 | 722 | s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value; |
24859b68 AZ |
723 | break; |
724 | } | |
725 | } | |
726 | ||
727 | static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = { | |
728 | mv88w8618_eth_read, | |
729 | mv88w8618_eth_read, | |
730 | mv88w8618_eth_read | |
731 | }; | |
732 | ||
733 | static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = { | |
734 | mv88w8618_eth_write, | |
735 | mv88w8618_eth_write, | |
736 | mv88w8618_eth_write | |
737 | }; | |
738 | ||
b946a153 AL |
739 | static void eth_cleanup(VLANClientState *vc) |
740 | { | |
741 | mv88w8618_eth_state *s = vc->opaque; | |
742 | ||
743 | cpu_unregister_io_memory(s->mmio_index); | |
744 | ||
745 | qemu_free(s); | |
746 | } | |
747 | ||
b47b50fa | 748 | static void mv88w8618_eth_init(SysBusDevice *dev) |
24859b68 | 749 | { |
b47b50fa | 750 | mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev); |
0ae18cee | 751 | |
b47b50fa PB |
752 | sysbus_init_irq(dev, &s->irq); |
753 | s->vc = qdev_get_vlan_client(&dev->qdev, | |
463af534 | 754 | eth_can_receive, eth_receive, NULL, |
b946a153 | 755 | eth_cleanup, s); |
1eed09cb | 756 | s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn, |
b946a153 | 757 | mv88w8618_eth_writefn, s); |
b47b50fa | 758 | sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index); |
24859b68 AZ |
759 | } |
760 | ||
761 | /* LCD register offsets */ | |
762 | #define MP_LCD_IRQCTRL 0x180 | |
763 | #define MP_LCD_IRQSTAT 0x184 | |
764 | #define MP_LCD_SPICTRL 0x1ac | |
765 | #define MP_LCD_INST 0x1bc | |
766 | #define MP_LCD_DATA 0x1c0 | |
767 | ||
768 | /* Mode magics */ | |
769 | #define MP_LCD_SPI_DATA 0x00100011 | |
770 | #define MP_LCD_SPI_CMD 0x00104011 | |
771 | #define MP_LCD_SPI_INVALID 0x00000000 | |
772 | ||
773 | /* Commmands */ | |
774 | #define MP_LCD_INST_SETPAGE0 0xB0 | |
775 | /* ... */ | |
776 | #define MP_LCD_INST_SETPAGE7 0xB7 | |
777 | ||
778 | #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ | |
779 | ||
780 | typedef struct musicpal_lcd_state { | |
b47b50fa | 781 | SysBusDevice busdev; |
343ec8e4 | 782 | uint32_t brightness; |
24859b68 AZ |
783 | uint32_t mode; |
784 | uint32_t irqctrl; | |
785 | int page; | |
786 | int page_off; | |
787 | DisplayState *ds; | |
788 | uint8_t video_ram[128*64/8]; | |
789 | } musicpal_lcd_state; | |
790 | ||
343ec8e4 | 791 | static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col) |
24859b68 | 792 | { |
343ec8e4 BC |
793 | switch (s->brightness) { |
794 | case 7: | |
795 | return col; | |
796 | case 0: | |
24859b68 | 797 | return 0; |
24859b68 | 798 | default: |
343ec8e4 | 799 | return (col * s->brightness) / 7; |
24859b68 AZ |
800 | } |
801 | } | |
802 | ||
0266f2c7 AZ |
803 | #define SET_LCD_PIXEL(depth, type) \ |
804 | static inline void glue(set_lcd_pixel, depth) \ | |
805 | (musicpal_lcd_state *s, int x, int y, type col) \ | |
806 | { \ | |
807 | int dx, dy; \ | |
0e1f5a0c | 808 | type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \ |
0266f2c7 AZ |
809 | \ |
810 | for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ | |
811 | for (dx = 0; dx < 3; dx++, pixel++) \ | |
812 | *pixel = col; \ | |
24859b68 | 813 | } |
0266f2c7 AZ |
814 | SET_LCD_PIXEL(8, uint8_t) |
815 | SET_LCD_PIXEL(16, uint16_t) | |
816 | SET_LCD_PIXEL(32, uint32_t) | |
817 | ||
818 | #include "pixel_ops.h" | |
24859b68 AZ |
819 | |
820 | static void lcd_refresh(void *opaque) | |
821 | { | |
822 | musicpal_lcd_state *s = opaque; | |
0266f2c7 | 823 | int x, y, col; |
24859b68 | 824 | |
0e1f5a0c | 825 | switch (ds_get_bits_per_pixel(s->ds)) { |
0266f2c7 AZ |
826 | case 0: |
827 | return; | |
828 | #define LCD_REFRESH(depth, func) \ | |
829 | case depth: \ | |
343ec8e4 BC |
830 | col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ |
831 | scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ | |
832 | scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \ | |
0266f2c7 AZ |
833 | for (x = 0; x < 128; x++) \ |
834 | for (y = 0; y < 64; y++) \ | |
835 | if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \ | |
836 | glue(set_lcd_pixel, depth)(s, x, y, col); \ | |
837 | else \ | |
838 | glue(set_lcd_pixel, depth)(s, x, y, 0); \ | |
839 | break; | |
840 | LCD_REFRESH(8, rgb_to_pixel8) | |
841 | LCD_REFRESH(16, rgb_to_pixel16) | |
bf9b48af AL |
842 | LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ? |
843 | rgb_to_pixel32bgr : rgb_to_pixel32)) | |
0266f2c7 | 844 | default: |
2ac71179 | 845 | hw_error("unsupported colour depth %i\n", |
0e1f5a0c | 846 | ds_get_bits_per_pixel(s->ds)); |
0266f2c7 | 847 | } |
24859b68 AZ |
848 | |
849 | dpy_update(s->ds, 0, 0, 128*3, 64*3); | |
850 | } | |
851 | ||
167bc3d2 AZ |
852 | static void lcd_invalidate(void *opaque) |
853 | { | |
167bc3d2 AZ |
854 | } |
855 | ||
343ec8e4 BC |
856 | static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level) |
857 | { | |
858 | musicpal_lcd_state *s = (musicpal_lcd_state *) opaque; | |
859 | s->brightness &= ~(1 << irq); | |
860 | s->brightness |= level << irq; | |
861 | } | |
862 | ||
24859b68 AZ |
863 | static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset) |
864 | { | |
865 | musicpal_lcd_state *s = opaque; | |
866 | ||
24859b68 AZ |
867 | switch (offset) { |
868 | case MP_LCD_IRQCTRL: | |
869 | return s->irqctrl; | |
870 | ||
871 | default: | |
872 | return 0; | |
873 | } | |
874 | } | |
875 | ||
876 | static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset, | |
877 | uint32_t value) | |
878 | { | |
879 | musicpal_lcd_state *s = opaque; | |
880 | ||
24859b68 AZ |
881 | switch (offset) { |
882 | case MP_LCD_IRQCTRL: | |
883 | s->irqctrl = value; | |
884 | break; | |
885 | ||
886 | case MP_LCD_SPICTRL: | |
887 | if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) | |
888 | s->mode = value; | |
889 | else | |
890 | s->mode = MP_LCD_SPI_INVALID; | |
891 | break; | |
892 | ||
893 | case MP_LCD_INST: | |
894 | if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) { | |
895 | s->page = value - MP_LCD_INST_SETPAGE0; | |
896 | s->page_off = 0; | |
897 | } | |
898 | break; | |
899 | ||
900 | case MP_LCD_DATA: | |
901 | if (s->mode == MP_LCD_SPI_CMD) { | |
902 | if (value >= MP_LCD_INST_SETPAGE0 && | |
903 | value <= MP_LCD_INST_SETPAGE7) { | |
904 | s->page = value - MP_LCD_INST_SETPAGE0; | |
905 | s->page_off = 0; | |
906 | } | |
907 | } else if (s->mode == MP_LCD_SPI_DATA) { | |
908 | s->video_ram[s->page*128 + s->page_off] = value; | |
909 | s->page_off = (s->page_off + 1) & 127; | |
910 | } | |
911 | break; | |
912 | } | |
913 | } | |
914 | ||
915 | static CPUReadMemoryFunc *musicpal_lcd_readfn[] = { | |
916 | musicpal_lcd_read, | |
917 | musicpal_lcd_read, | |
918 | musicpal_lcd_read | |
919 | }; | |
920 | ||
921 | static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = { | |
922 | musicpal_lcd_write, | |
923 | musicpal_lcd_write, | |
924 | musicpal_lcd_write | |
925 | }; | |
926 | ||
b47b50fa | 927 | static void musicpal_lcd_init(SysBusDevice *dev) |
24859b68 | 928 | { |
b47b50fa | 929 | musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev); |
24859b68 AZ |
930 | int iomemtype; |
931 | ||
343ec8e4 BC |
932 | s->brightness = 7; |
933 | ||
1eed09cb | 934 | iomemtype = cpu_register_io_memory(musicpal_lcd_readfn, |
24859b68 | 935 | musicpal_lcd_writefn, s); |
b47b50fa | 936 | sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype); |
24859b68 | 937 | |
3023f332 AL |
938 | s->ds = graphic_console_init(lcd_refresh, lcd_invalidate, |
939 | NULL, NULL, s); | |
940 | qemu_console_resize(s->ds, 128*3, 64*3); | |
343ec8e4 BC |
941 | |
942 | qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3); | |
24859b68 AZ |
943 | } |
944 | ||
945 | /* PIC register offsets */ | |
946 | #define MP_PIC_STATUS 0x00 | |
947 | #define MP_PIC_ENABLE_SET 0x08 | |
948 | #define MP_PIC_ENABLE_CLR 0x0C | |
949 | ||
950 | typedef struct mv88w8618_pic_state | |
951 | { | |
b47b50fa | 952 | SysBusDevice busdev; |
24859b68 AZ |
953 | uint32_t level; |
954 | uint32_t enabled; | |
955 | qemu_irq parent_irq; | |
956 | } mv88w8618_pic_state; | |
957 | ||
958 | static void mv88w8618_pic_update(mv88w8618_pic_state *s) | |
959 | { | |
960 | qemu_set_irq(s->parent_irq, (s->level & s->enabled)); | |
961 | } | |
962 | ||
963 | static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) | |
964 | { | |
965 | mv88w8618_pic_state *s = opaque; | |
966 | ||
967 | if (level) | |
968 | s->level |= 1 << irq; | |
969 | else | |
970 | s->level &= ~(1 << irq); | |
971 | mv88w8618_pic_update(s); | |
972 | } | |
973 | ||
974 | static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset) | |
975 | { | |
976 | mv88w8618_pic_state *s = opaque; | |
977 | ||
24859b68 AZ |
978 | switch (offset) { |
979 | case MP_PIC_STATUS: | |
980 | return s->level & s->enabled; | |
981 | ||
982 | default: | |
983 | return 0; | |
984 | } | |
985 | } | |
986 | ||
987 | static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset, | |
988 | uint32_t value) | |
989 | { | |
990 | mv88w8618_pic_state *s = opaque; | |
991 | ||
24859b68 AZ |
992 | switch (offset) { |
993 | case MP_PIC_ENABLE_SET: | |
994 | s->enabled |= value; | |
995 | break; | |
996 | ||
997 | case MP_PIC_ENABLE_CLR: | |
998 | s->enabled &= ~value; | |
999 | s->level &= ~value; | |
1000 | break; | |
1001 | } | |
1002 | mv88w8618_pic_update(s); | |
1003 | } | |
1004 | ||
1005 | static void mv88w8618_pic_reset(void *opaque) | |
1006 | { | |
1007 | mv88w8618_pic_state *s = opaque; | |
1008 | ||
1009 | s->level = 0; | |
1010 | s->enabled = 0; | |
1011 | } | |
1012 | ||
1013 | static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = { | |
1014 | mv88w8618_pic_read, | |
1015 | mv88w8618_pic_read, | |
1016 | mv88w8618_pic_read | |
1017 | }; | |
1018 | ||
1019 | static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = { | |
1020 | mv88w8618_pic_write, | |
1021 | mv88w8618_pic_write, | |
1022 | mv88w8618_pic_write | |
1023 | }; | |
1024 | ||
b47b50fa | 1025 | static void mv88w8618_pic_init(SysBusDevice *dev) |
24859b68 | 1026 | { |
b47b50fa | 1027 | mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev); |
24859b68 | 1028 | int iomemtype; |
24859b68 | 1029 | |
067a3ddc | 1030 | qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32); |
b47b50fa | 1031 | sysbus_init_irq(dev, &s->parent_irq); |
1eed09cb | 1032 | iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn, |
24859b68 | 1033 | mv88w8618_pic_writefn, s); |
b47b50fa | 1034 | sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype); |
24859b68 | 1035 | |
a08d4367 | 1036 | qemu_register_reset(mv88w8618_pic_reset, s); |
24859b68 AZ |
1037 | } |
1038 | ||
1039 | /* PIT register offsets */ | |
1040 | #define MP_PIT_TIMER1_LENGTH 0x00 | |
1041 | /* ... */ | |
1042 | #define MP_PIT_TIMER4_LENGTH 0x0C | |
1043 | #define MP_PIT_CONTROL 0x10 | |
1044 | #define MP_PIT_TIMER1_VALUE 0x14 | |
1045 | /* ... */ | |
1046 | #define MP_PIT_TIMER4_VALUE 0x20 | |
1047 | #define MP_BOARD_RESET 0x34 | |
1048 | ||
1049 | /* Magic board reset value (probably some watchdog behind it) */ | |
1050 | #define MP_BOARD_RESET_MAGIC 0x10000 | |
1051 | ||
1052 | typedef struct mv88w8618_timer_state { | |
b47b50fa | 1053 | ptimer_state *ptimer; |
24859b68 AZ |
1054 | uint32_t limit; |
1055 | int freq; | |
1056 | qemu_irq irq; | |
1057 | } mv88w8618_timer_state; | |
1058 | ||
1059 | typedef struct mv88w8618_pit_state { | |
b47b50fa PB |
1060 | SysBusDevice busdev; |
1061 | mv88w8618_timer_state timer[4]; | |
24859b68 | 1062 | uint32_t control; |
24859b68 AZ |
1063 | } mv88w8618_pit_state; |
1064 | ||
1065 | static void mv88w8618_timer_tick(void *opaque) | |
1066 | { | |
1067 | mv88w8618_timer_state *s = opaque; | |
1068 | ||
1069 | qemu_irq_raise(s->irq); | |
1070 | } | |
1071 | ||
b47b50fa PB |
1072 | static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, |
1073 | uint32_t freq) | |
24859b68 | 1074 | { |
24859b68 AZ |
1075 | QEMUBH *bh; |
1076 | ||
b47b50fa | 1077 | sysbus_init_irq(dev, &s->irq); |
24859b68 AZ |
1078 | s->freq = freq; |
1079 | ||
1080 | bh = qemu_bh_new(mv88w8618_timer_tick, s); | |
b47b50fa | 1081 | s->ptimer = ptimer_init(bh); |
24859b68 AZ |
1082 | } |
1083 | ||
1084 | static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset) | |
1085 | { | |
1086 | mv88w8618_pit_state *s = opaque; | |
1087 | mv88w8618_timer_state *t; | |
1088 | ||
24859b68 AZ |
1089 | switch (offset) { |
1090 | case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE: | |
b47b50fa PB |
1091 | t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2]; |
1092 | return ptimer_get_count(t->ptimer); | |
24859b68 AZ |
1093 | |
1094 | default: | |
1095 | return 0; | |
1096 | } | |
1097 | } | |
1098 | ||
1099 | static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset, | |
1100 | uint32_t value) | |
1101 | { | |
1102 | mv88w8618_pit_state *s = opaque; | |
1103 | mv88w8618_timer_state *t; | |
1104 | int i; | |
1105 | ||
24859b68 AZ |
1106 | switch (offset) { |
1107 | case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH: | |
b47b50fa | 1108 | t = &s->timer[offset >> 2]; |
24859b68 | 1109 | t->limit = value; |
b47b50fa | 1110 | ptimer_set_limit(t->ptimer, t->limit, 1); |
24859b68 AZ |
1111 | break; |
1112 | ||
1113 | case MP_PIT_CONTROL: | |
1114 | for (i = 0; i < 4; i++) { | |
1115 | if (value & 0xf) { | |
b47b50fa PB |
1116 | t = &s->timer[i]; |
1117 | ptimer_set_limit(t->ptimer, t->limit, 0); | |
1118 | ptimer_set_freq(t->ptimer, t->freq); | |
1119 | ptimer_run(t->ptimer, 0); | |
24859b68 AZ |
1120 | } |
1121 | value >>= 4; | |
1122 | } | |
1123 | break; | |
1124 | ||
1125 | case MP_BOARD_RESET: | |
1126 | if (value == MP_BOARD_RESET_MAGIC) | |
1127 | qemu_system_reset_request(); | |
1128 | break; | |
1129 | } | |
1130 | } | |
1131 | ||
1132 | static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = { | |
1133 | mv88w8618_pit_read, | |
1134 | mv88w8618_pit_read, | |
1135 | mv88w8618_pit_read | |
1136 | }; | |
1137 | ||
1138 | static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = { | |
1139 | mv88w8618_pit_write, | |
1140 | mv88w8618_pit_write, | |
1141 | mv88w8618_pit_write | |
1142 | }; | |
1143 | ||
b47b50fa | 1144 | static void mv88w8618_pit_init(SysBusDevice *dev) |
24859b68 AZ |
1145 | { |
1146 | int iomemtype; | |
b47b50fa PB |
1147 | mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev); |
1148 | int i; | |
24859b68 | 1149 | |
24859b68 AZ |
1150 | /* Letting them all run at 1 MHz is likely just a pragmatic |
1151 | * simplification. */ | |
b47b50fa PB |
1152 | for (i = 0; i < 4; i++) { |
1153 | mv88w8618_timer_init(dev, &s->timer[i], 1000000); | |
1154 | } | |
24859b68 | 1155 | |
1eed09cb | 1156 | iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn, |
24859b68 | 1157 | mv88w8618_pit_writefn, s); |
b47b50fa | 1158 | sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype); |
24859b68 AZ |
1159 | } |
1160 | ||
1161 | /* Flash config register offsets */ | |
1162 | #define MP_FLASHCFG_CFGR0 0x04 | |
1163 | ||
1164 | typedef struct mv88w8618_flashcfg_state { | |
b47b50fa | 1165 | SysBusDevice busdev; |
24859b68 AZ |
1166 | uint32_t cfgr0; |
1167 | } mv88w8618_flashcfg_state; | |
1168 | ||
1169 | static uint32_t mv88w8618_flashcfg_read(void *opaque, | |
1170 | target_phys_addr_t offset) | |
1171 | { | |
1172 | mv88w8618_flashcfg_state *s = opaque; | |
1173 | ||
24859b68 AZ |
1174 | switch (offset) { |
1175 | case MP_FLASHCFG_CFGR0: | |
1176 | return s->cfgr0; | |
1177 | ||
1178 | default: | |
1179 | return 0; | |
1180 | } | |
1181 | } | |
1182 | ||
1183 | static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset, | |
1184 | uint32_t value) | |
1185 | { | |
1186 | mv88w8618_flashcfg_state *s = opaque; | |
1187 | ||
24859b68 AZ |
1188 | switch (offset) { |
1189 | case MP_FLASHCFG_CFGR0: | |
1190 | s->cfgr0 = value; | |
1191 | break; | |
1192 | } | |
1193 | } | |
1194 | ||
1195 | static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = { | |
1196 | mv88w8618_flashcfg_read, | |
1197 | mv88w8618_flashcfg_read, | |
1198 | mv88w8618_flashcfg_read | |
1199 | }; | |
1200 | ||
1201 | static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = { | |
1202 | mv88w8618_flashcfg_write, | |
1203 | mv88w8618_flashcfg_write, | |
1204 | mv88w8618_flashcfg_write | |
1205 | }; | |
1206 | ||
b47b50fa | 1207 | static void mv88w8618_flashcfg_init(SysBusDevice *dev) |
24859b68 AZ |
1208 | { |
1209 | int iomemtype; | |
b47b50fa | 1210 | mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev); |
24859b68 | 1211 | |
24859b68 | 1212 | s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ |
1eed09cb | 1213 | iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn, |
24859b68 | 1214 | mv88w8618_flashcfg_writefn, s); |
b47b50fa | 1215 | sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype); |
24859b68 AZ |
1216 | } |
1217 | ||
718ec0be | 1218 | /* Misc register offsets */ |
1219 | #define MP_MISC_BOARD_REVISION 0x18 | |
1220 | ||
1221 | #define MP_BOARD_REVISION 0x31 | |
1222 | ||
1223 | static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset) | |
1224 | { | |
1225 | switch (offset) { | |
1226 | case MP_MISC_BOARD_REVISION: | |
1227 | return MP_BOARD_REVISION; | |
1228 | ||
1229 | default: | |
1230 | return 0; | |
1231 | } | |
1232 | } | |
1233 | ||
1234 | static void musicpal_misc_write(void *opaque, target_phys_addr_t offset, | |
1235 | uint32_t value) | |
1236 | { | |
1237 | } | |
1238 | ||
1239 | static CPUReadMemoryFunc *musicpal_misc_readfn[] = { | |
1240 | musicpal_misc_read, | |
1241 | musicpal_misc_read, | |
1242 | musicpal_misc_read, | |
1243 | }; | |
1244 | ||
1245 | static CPUWriteMemoryFunc *musicpal_misc_writefn[] = { | |
1246 | musicpal_misc_write, | |
1247 | musicpal_misc_write, | |
1248 | musicpal_misc_write, | |
1249 | }; | |
1250 | ||
1251 | static void musicpal_misc_init(void) | |
1252 | { | |
1253 | int iomemtype; | |
1254 | ||
1eed09cb | 1255 | iomemtype = cpu_register_io_memory(musicpal_misc_readfn, |
718ec0be | 1256 | musicpal_misc_writefn, NULL); |
1257 | cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype); | |
1258 | } | |
1259 | ||
1260 | /* WLAN register offsets */ | |
1261 | #define MP_WLAN_MAGIC1 0x11c | |
1262 | #define MP_WLAN_MAGIC2 0x124 | |
1263 | ||
1264 | static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset) | |
1265 | { | |
1266 | switch (offset) { | |
1267 | /* Workaround to allow loading the binary-only wlandrv.ko crap | |
1268 | * from the original Freecom firmware. */ | |
1269 | case MP_WLAN_MAGIC1: | |
1270 | return ~3; | |
1271 | case MP_WLAN_MAGIC2: | |
1272 | return -1; | |
1273 | ||
1274 | default: | |
1275 | return 0; | |
1276 | } | |
1277 | } | |
1278 | ||
1279 | static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset, | |
1280 | uint32_t value) | |
1281 | { | |
1282 | } | |
1283 | ||
1284 | static CPUReadMemoryFunc *mv88w8618_wlan_readfn[] = { | |
1285 | mv88w8618_wlan_read, | |
1286 | mv88w8618_wlan_read, | |
1287 | mv88w8618_wlan_read, | |
1288 | }; | |
1289 | ||
1290 | static CPUWriteMemoryFunc *mv88w8618_wlan_writefn[] = { | |
1291 | mv88w8618_wlan_write, | |
1292 | mv88w8618_wlan_write, | |
1293 | mv88w8618_wlan_write, | |
1294 | }; | |
1295 | ||
b47b50fa | 1296 | static void mv88w8618_wlan_init(SysBusDevice *dev) |
718ec0be | 1297 | { |
1298 | int iomemtype; | |
24859b68 | 1299 | |
1eed09cb | 1300 | iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn, |
718ec0be | 1301 | mv88w8618_wlan_writefn, NULL); |
b47b50fa | 1302 | sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype); |
718ec0be | 1303 | } |
24859b68 | 1304 | |
718ec0be | 1305 | /* GPIO register offsets */ |
1306 | #define MP_GPIO_OE_LO 0x008 | |
1307 | #define MP_GPIO_OUT_LO 0x00c | |
1308 | #define MP_GPIO_IN_LO 0x010 | |
1309 | #define MP_GPIO_ISR_LO 0x020 | |
1310 | #define MP_GPIO_OE_HI 0x508 | |
1311 | #define MP_GPIO_OUT_HI 0x50c | |
1312 | #define MP_GPIO_IN_HI 0x510 | |
1313 | #define MP_GPIO_ISR_HI 0x520 | |
24859b68 AZ |
1314 | |
1315 | /* GPIO bits & masks */ | |
24859b68 | 1316 | #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 |
24859b68 AZ |
1317 | #define MP_GPIO_I2C_DATA_BIT 29 |
1318 | #define MP_GPIO_I2C_DATA (1 << MP_GPIO_I2C_DATA_BIT) | |
1319 | #define MP_GPIO_I2C_CLOCK_BIT 30 | |
1320 | ||
1321 | /* LCD brightness bits in GPIO_OE_HI */ | |
1322 | #define MP_OE_LCD_BRIGHTNESS 0x0007 | |
1323 | ||
343ec8e4 BC |
1324 | typedef struct musicpal_gpio_state { |
1325 | SysBusDevice busdev; | |
1326 | uint32_t lcd_brightness; | |
1327 | uint32_t out_state; | |
1328 | uint32_t in_state; | |
1329 | uint32_t isr; | |
1330 | uint32_t key_released; | |
1331 | uint32_t keys_event; /* store the received key event */ | |
1332 | qemu_irq irq; | |
1333 | qemu_irq out[3]; | |
1334 | } musicpal_gpio_state; | |
1335 | ||
1336 | static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { | |
1337 | int i; | |
1338 | uint32_t brightness; | |
1339 | ||
1340 | /* compute brightness ratio */ | |
1341 | switch (s->lcd_brightness) { | |
1342 | case 0x00000007: | |
1343 | brightness = 0; | |
1344 | break; | |
1345 | ||
1346 | case 0x00020000: | |
1347 | brightness = 1; | |
1348 | break; | |
1349 | ||
1350 | case 0x00020001: | |
1351 | brightness = 2; | |
1352 | break; | |
1353 | ||
1354 | case 0x00040000: | |
1355 | brightness = 3; | |
1356 | break; | |
1357 | ||
1358 | case 0x00010006: | |
1359 | brightness = 4; | |
1360 | break; | |
1361 | ||
1362 | case 0x00020005: | |
1363 | brightness = 5; | |
1364 | break; | |
1365 | ||
1366 | case 0x00040003: | |
1367 | brightness = 6; | |
1368 | break; | |
1369 | ||
1370 | case 0x00030004: | |
1371 | default: | |
1372 | brightness = 7; | |
1373 | } | |
1374 | ||
1375 | /* set lcd brightness GPIOs */ | |
1376 | for (i = 0; i <= 2; i++) | |
1377 | qemu_set_irq(s->out[i], (brightness >> i) & 1); | |
1378 | } | |
1379 | ||
1380 | static void musicpal_gpio_keys_update(musicpal_gpio_state *s) | |
1381 | { | |
1382 | int gpio_mask = 0; | |
1383 | ||
1384 | /* transform the key state for GPIO usage */ | |
1385 | gpio_mask |= (s->keys_event & 15) << 8; | |
1386 | gpio_mask |= ((s->keys_event >> 4) & 15) << 19; | |
1387 | ||
1388 | /* update GPIO state */ | |
1389 | if (s->key_released) { | |
1390 | s->in_state |= gpio_mask; | |
1391 | } else { | |
1392 | s->in_state &= ~gpio_mask; | |
1393 | s->isr = gpio_mask; | |
1394 | qemu_irq_raise(s->irq); | |
1395 | } | |
1396 | } | |
1397 | ||
1398 | static void musicpal_gpio_irq(void *opaque, int irq, int level) | |
1399 | { | |
1400 | musicpal_gpio_state *s = (musicpal_gpio_state *) opaque; | |
1401 | ||
1402 | /* receives keys bits */ | |
1403 | if (irq <= 7) { | |
1404 | s->keys_event &= ~(1 << irq); | |
1405 | s->keys_event |= level << irq; | |
1406 | return; | |
1407 | } | |
1408 | ||
1409 | /* receives key press/release */ | |
1410 | if (irq == 8) { | |
1411 | s->key_released = level; | |
1412 | return; | |
1413 | } | |
1414 | ||
1415 | /* a key has been transmited */ | |
1416 | if (irq == 9 && level == 1) | |
1417 | musicpal_gpio_keys_update(s); | |
1418 | } | |
1419 | ||
718ec0be | 1420 | static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset) |
24859b68 | 1421 | { |
343ec8e4 BC |
1422 | musicpal_gpio_state *s = (musicpal_gpio_state *) opaque; |
1423 | ||
24859b68 | 1424 | switch (offset) { |
24859b68 | 1425 | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
343ec8e4 | 1426 | return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS; |
24859b68 AZ |
1427 | |
1428 | case MP_GPIO_OUT_LO: | |
343ec8e4 | 1429 | return s->out_state & 0xFFFF; |
24859b68 | 1430 | case MP_GPIO_OUT_HI: |
343ec8e4 | 1431 | return s->out_state >> 16; |
24859b68 AZ |
1432 | |
1433 | case MP_GPIO_IN_LO: | |
343ec8e4 | 1434 | return s->in_state & 0xFFFF; |
24859b68 AZ |
1435 | case MP_GPIO_IN_HI: |
1436 | /* Update received I2C data */ | |
343ec8e4 | 1437 | s->in_state = (s->in_state & ~MP_GPIO_I2C_DATA) | |
24859b68 | 1438 | (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT); |
343ec8e4 | 1439 | return s->in_state >> 16; |
24859b68 | 1440 | |
24859b68 | 1441 | case MP_GPIO_ISR_LO: |
343ec8e4 | 1442 | return s->isr & 0xFFFF; |
24859b68 | 1443 | case MP_GPIO_ISR_HI: |
343ec8e4 | 1444 | return s->isr >> 16; |
24859b68 | 1445 | |
24859b68 AZ |
1446 | default: |
1447 | return 0; | |
1448 | } | |
1449 | } | |
1450 | ||
718ec0be | 1451 | static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset, |
1452 | uint32_t value) | |
24859b68 | 1453 | { |
343ec8e4 | 1454 | musicpal_gpio_state *s = (musicpal_gpio_state *) opaque; |
24859b68 AZ |
1455 | switch (offset) { |
1456 | case MP_GPIO_OE_HI: /* used for LCD brightness control */ | |
343ec8e4 | 1457 | s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | |
24859b68 | 1458 | (value & MP_OE_LCD_BRIGHTNESS); |
343ec8e4 | 1459 | musicpal_gpio_brightness_update(s); |
24859b68 AZ |
1460 | break; |
1461 | ||
1462 | case MP_GPIO_OUT_LO: | |
343ec8e4 | 1463 | s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); |
24859b68 AZ |
1464 | break; |
1465 | case MP_GPIO_OUT_HI: | |
343ec8e4 BC |
1466 | s->out_state = (s->out_state & 0xFFFF) | (value << 16); |
1467 | s->lcd_brightness = (s->lcd_brightness & 0xFFFF) | | |
1468 | (s->out_state & MP_GPIO_LCD_BRIGHTNESS); | |
1469 | musicpal_gpio_brightness_update(s); | |
24859b68 | 1470 | i2c_state_update(mixer_i2c, |
343ec8e4 BC |
1471 | (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1, |
1472 | (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); | |
24859b68 AZ |
1473 | break; |
1474 | ||
1475 | } | |
1476 | } | |
1477 | ||
718ec0be | 1478 | static CPUReadMemoryFunc *musicpal_gpio_readfn[] = { |
1479 | musicpal_gpio_read, | |
1480 | musicpal_gpio_read, | |
1481 | musicpal_gpio_read, | |
1482 | }; | |
1483 | ||
1484 | static CPUWriteMemoryFunc *musicpal_gpio_writefn[] = { | |
1485 | musicpal_gpio_write, | |
1486 | musicpal_gpio_write, | |
1487 | musicpal_gpio_write, | |
1488 | }; | |
1489 | ||
343ec8e4 | 1490 | static void musicpal_gpio_reset(musicpal_gpio_state *s) |
718ec0be | 1491 | { |
343ec8e4 BC |
1492 | s->in_state = 0xffffffff; |
1493 | s->key_released = 0; | |
1494 | s->keys_event = 0; | |
1495 | s->isr = 0; | |
1496 | } | |
1497 | ||
1498 | static void musicpal_gpio_init(SysBusDevice *dev) | |
1499 | { | |
1500 | musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev); | |
718ec0be | 1501 | int iomemtype; |
1502 | ||
343ec8e4 BC |
1503 | sysbus_init_irq(dev, &s->irq); |
1504 | ||
1eed09cb | 1505 | iomemtype = cpu_register_io_memory(musicpal_gpio_readfn, |
343ec8e4 BC |
1506 | musicpal_gpio_writefn, s); |
1507 | sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype); | |
1508 | ||
1509 | musicpal_gpio_reset(s); | |
1510 | ||
1511 | qdev_init_gpio_out(&dev->qdev, s->out, 3); | |
1512 | qdev_init_gpio_in(&dev->qdev, musicpal_gpio_irq, 10); | |
718ec0be | 1513 | } |
1514 | ||
24859b68 | 1515 | /* Keyboard codes & masks */ |
7c6ce4ba | 1516 | #define KEY_RELEASED 0x80 |
24859b68 AZ |
1517 | #define KEY_CODE 0x7f |
1518 | ||
1519 | #define KEYCODE_TAB 0x0f | |
1520 | #define KEYCODE_ENTER 0x1c | |
1521 | #define KEYCODE_F 0x21 | |
1522 | #define KEYCODE_M 0x32 | |
1523 | ||
1524 | #define KEYCODE_EXTENDED 0xe0 | |
1525 | #define KEYCODE_UP 0x48 | |
1526 | #define KEYCODE_DOWN 0x50 | |
1527 | #define KEYCODE_LEFT 0x4b | |
1528 | #define KEYCODE_RIGHT 0x4d | |
1529 | ||
343ec8e4 BC |
1530 | #define MP_KEY_WHEEL_VOL (1) |
1531 | #define MP_KEY_WHEEL_VOL_INV (1 << 1) | |
1532 | #define MP_KEY_WHEEL_NAV (1 << 2) | |
1533 | #define MP_KEY_WHEEL_NAV_INV (1 << 3) | |
1534 | #define MP_KEY_BTN_FAVORITS (1 << 4) | |
1535 | #define MP_KEY_BTN_MENU (1 << 5) | |
1536 | #define MP_KEY_BTN_VOLUME (1 << 6) | |
1537 | #define MP_KEY_BTN_NAVIGATION (1 << 7) | |
1538 | ||
1539 | typedef struct musicpal_key_state { | |
1540 | SysBusDevice busdev; | |
1541 | uint32_t kbd_extended; | |
1542 | uint32_t keys_state; | |
1543 | qemu_irq out[10]; | |
1544 | } musicpal_key_state; | |
1545 | ||
24859b68 AZ |
1546 | static void musicpal_key_event(void *opaque, int keycode) |
1547 | { | |
343ec8e4 | 1548 | musicpal_key_state *s = (musicpal_key_state *) opaque; |
24859b68 | 1549 | uint32_t event = 0; |
343ec8e4 | 1550 | int i; |
24859b68 AZ |
1551 | |
1552 | if (keycode == KEYCODE_EXTENDED) { | |
343ec8e4 | 1553 | s->kbd_extended = 1; |
24859b68 AZ |
1554 | return; |
1555 | } | |
1556 | ||
343ec8e4 | 1557 | if (s->kbd_extended) |
24859b68 AZ |
1558 | switch (keycode & KEY_CODE) { |
1559 | case KEYCODE_UP: | |
343ec8e4 | 1560 | event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; |
24859b68 AZ |
1561 | break; |
1562 | ||
1563 | case KEYCODE_DOWN: | |
343ec8e4 | 1564 | event = MP_KEY_WHEEL_NAV; |
24859b68 AZ |
1565 | break; |
1566 | ||
1567 | case KEYCODE_LEFT: | |
343ec8e4 | 1568 | event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; |
24859b68 AZ |
1569 | break; |
1570 | ||
1571 | case KEYCODE_RIGHT: | |
343ec8e4 | 1572 | event = MP_KEY_WHEEL_VOL; |
24859b68 AZ |
1573 | break; |
1574 | } | |
7c6ce4ba | 1575 | else { |
24859b68 AZ |
1576 | switch (keycode & KEY_CODE) { |
1577 | case KEYCODE_F: | |
343ec8e4 | 1578 | event = MP_KEY_BTN_FAVORITS; |
24859b68 AZ |
1579 | break; |
1580 | ||
1581 | case KEYCODE_TAB: | |
343ec8e4 | 1582 | event = MP_KEY_BTN_VOLUME; |
24859b68 AZ |
1583 | break; |
1584 | ||
1585 | case KEYCODE_ENTER: | |
343ec8e4 | 1586 | event = MP_KEY_BTN_NAVIGATION; |
24859b68 AZ |
1587 | break; |
1588 | ||
1589 | case KEYCODE_M: | |
343ec8e4 | 1590 | event = MP_KEY_BTN_MENU; |
24859b68 AZ |
1591 | break; |
1592 | } | |
7c6ce4ba | 1593 | /* Do not repeat already pressed buttons */ |
343ec8e4 | 1594 | if (!(keycode & KEY_RELEASED) && !(s->keys_state & event)) |
7c6ce4ba AZ |
1595 | event = 0; |
1596 | } | |
24859b68 | 1597 | |
7c6ce4ba | 1598 | if (event) { |
343ec8e4 BC |
1599 | |
1600 | /* transmit key event on GPIOS */ | |
1601 | for (i = 0; i <= 7; i++) | |
1602 | qemu_set_irq(s->out[i], (event >> i) & 1); | |
1603 | ||
1604 | /* handle key press/release */ | |
7c6ce4ba | 1605 | if (keycode & KEY_RELEASED) { |
343ec8e4 BC |
1606 | s->keys_state |= event; |
1607 | qemu_irq_raise(s->out[8]); | |
7c6ce4ba | 1608 | } else { |
343ec8e4 BC |
1609 | s->keys_state &= ~event; |
1610 | qemu_irq_lower(s->out[8]); | |
7c6ce4ba | 1611 | } |
343ec8e4 BC |
1612 | |
1613 | /* signal that a key event occured */ | |
1614 | qemu_irq_pulse(s->out[9]); | |
24859b68 AZ |
1615 | } |
1616 | ||
343ec8e4 BC |
1617 | s->kbd_extended = 0; |
1618 | } | |
1619 | ||
1620 | static void musicpal_key_init(SysBusDevice *dev) | |
1621 | { | |
1622 | musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev); | |
1623 | ||
1624 | sysbus_init_mmio(dev, 0x0, 0); | |
1625 | ||
1626 | s->kbd_extended = 0; | |
1627 | s->keys_state = 0; | |
1628 | ||
1629 | /* 8 key event GPIO + 1 key press/release + 1 strobe */ | |
1630 | qdev_init_gpio_out(&dev->qdev, s->out, 10); | |
1631 | ||
1632 | qemu_add_kbd_event_handler(musicpal_key_event, s); | |
24859b68 AZ |
1633 | } |
1634 | ||
24859b68 AZ |
1635 | static struct arm_boot_info musicpal_binfo = { |
1636 | .loader_start = 0x0, | |
1637 | .board_id = 0x20e, | |
1638 | }; | |
1639 | ||
fbe1b595 | 1640 | static void musicpal_init(ram_addr_t ram_size, |
3023f332 | 1641 | const char *boot_device, |
24859b68 AZ |
1642 | const char *kernel_filename, const char *kernel_cmdline, |
1643 | const char *initrd_filename, const char *cpu_model) | |
1644 | { | |
1645 | CPUState *env; | |
b47b50fa PB |
1646 | qemu_irq *cpu_pic; |
1647 | qemu_irq pic[32]; | |
1648 | DeviceState *dev; | |
343ec8e4 BC |
1649 | DeviceState *lcd_dev; |
1650 | DeviceState *key_dev; | |
b47b50fa | 1651 | int i; |
24859b68 | 1652 | unsigned long flash_size; |
751c6a17 | 1653 | DriveInfo *dinfo; |
24859b68 AZ |
1654 | |
1655 | if (!cpu_model) | |
1656 | cpu_model = "arm926"; | |
1657 | ||
1658 | env = cpu_init(cpu_model); | |
1659 | if (!env) { | |
1660 | fprintf(stderr, "Unable to find CPU definition\n"); | |
1661 | exit(1); | |
1662 | } | |
b47b50fa | 1663 | cpu_pic = arm_pic_init_cpu(env); |
24859b68 AZ |
1664 | |
1665 | /* For now we use a fixed - the original - RAM size */ | |
1666 | cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE, | |
1667 | qemu_ram_alloc(MP_RAM_DEFAULT_SIZE)); | |
1668 | ||
1669 | sram_off = qemu_ram_alloc(MP_SRAM_SIZE); | |
1670 | cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off); | |
1671 | ||
b47b50fa PB |
1672 | dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE, |
1673 | cpu_pic[ARM_PIC_CPU_IRQ]); | |
1674 | for (i = 0; i < 32; i++) { | |
067a3ddc | 1675 | pic[i] = qdev_get_gpio_in(dev, i); |
b47b50fa PB |
1676 | } |
1677 | sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ], | |
1678 | pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], | |
1679 | pic[MP_TIMER4_IRQ], NULL); | |
24859b68 AZ |
1680 | |
1681 | if (serial_hds[0]) | |
b6cd0ea1 | 1682 | serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, |
24859b68 AZ |
1683 | serial_hds[0], 1); |
1684 | if (serial_hds[1]) | |
b6cd0ea1 | 1685 | serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, |
24859b68 AZ |
1686 | serial_hds[1], 1); |
1687 | ||
1688 | /* Register flash */ | |
751c6a17 GH |
1689 | dinfo = drive_get(IF_PFLASH, 0, 0); |
1690 | if (dinfo) { | |
1691 | flash_size = bdrv_getlength(dinfo->bdrv); | |
24859b68 AZ |
1692 | if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && |
1693 | flash_size != 32*1024*1024) { | |
1694 | fprintf(stderr, "Invalid flash image size\n"); | |
1695 | exit(1); | |
1696 | } | |
1697 | ||
1698 | /* | |
1699 | * The original U-Boot accesses the flash at 0xFE000000 instead of | |
1700 | * 0xFF800000 (if there is 8 MB flash). So remap flash access if the | |
1701 | * image is smaller than 32 MB. | |
1702 | */ | |
1703 | pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size), | |
751c6a17 | 1704 | dinfo->bdrv, 0x10000, |
24859b68 AZ |
1705 | (flash_size + 0xffff) >> 16, |
1706 | MP_FLASH_SIZE_MAX / flash_size, | |
1707 | 2, 0x00BF, 0x236D, 0x0000, 0x0000, | |
1708 | 0x5555, 0x2AAA); | |
1709 | } | |
b47b50fa | 1710 | sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL); |
24859b68 | 1711 | |
b47b50fa PB |
1712 | qemu_check_nic_model(&nd_table[0], "mv88w8618"); |
1713 | dev = qdev_create(NULL, "mv88w8618_eth"); | |
ee6847d1 | 1714 | dev->nd = &nd_table[0]; |
b47b50fa PB |
1715 | qdev_init(dev); |
1716 | sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE); | |
1717 | sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]); | |
24859b68 | 1718 | |
718ec0be | 1719 | mixer_i2c = musicpal_audio_init(pic[MP_AUDIO_IRQ]); |
1720 | ||
b47b50fa | 1721 | sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); |
718ec0be | 1722 | |
1723 | musicpal_misc_init(); | |
343ec8e4 BC |
1724 | |
1725 | dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]); | |
1726 | lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL); | |
1727 | key_dev = sysbus_create_simple("musicpal_key", 0, NULL); | |
1728 | ||
1729 | for (i = 0; i < 3; i++) | |
1730 | qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); | |
1731 | ||
1732 | for (i = 0; i < 10; i++) | |
1733 | qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i)); | |
24859b68 AZ |
1734 | |
1735 | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; | |
1736 | musicpal_binfo.kernel_filename = kernel_filename; | |
1737 | musicpal_binfo.kernel_cmdline = kernel_cmdline; | |
1738 | musicpal_binfo.initrd_filename = initrd_filename; | |
b0f6edb1 | 1739 | arm_load_kernel(env, &musicpal_binfo); |
24859b68 AZ |
1740 | } |
1741 | ||
f80f9ec9 | 1742 | static QEMUMachine musicpal_machine = { |
4b32e168 AL |
1743 | .name = "musicpal", |
1744 | .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)", | |
1745 | .init = musicpal_init, | |
24859b68 | 1746 | }; |
b47b50fa | 1747 | |
f80f9ec9 AL |
1748 | static void musicpal_machine_init(void) |
1749 | { | |
1750 | qemu_register_machine(&musicpal_machine); | |
1751 | } | |
1752 | ||
1753 | machine_init(musicpal_machine_init); | |
1754 | ||
b47b50fa PB |
1755 | static void musicpal_register_devices(void) |
1756 | { | |
1757 | sysbus_register_dev("mv88w8618_pic", sizeof(mv88w8618_pic_state), | |
1758 | mv88w8618_pic_init); | |
1759 | sysbus_register_dev("mv88w8618_pit", sizeof(mv88w8618_pit_state), | |
1760 | mv88w8618_pit_init); | |
1761 | sysbus_register_dev("mv88w8618_flashcfg", sizeof(mv88w8618_flashcfg_state), | |
1762 | mv88w8618_flashcfg_init); | |
1763 | sysbus_register_dev("mv88w8618_eth", sizeof(mv88w8618_eth_state), | |
1764 | mv88w8618_eth_init); | |
1765 | sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice), | |
1766 | mv88w8618_wlan_init); | |
1767 | sysbus_register_dev("musicpal_lcd", sizeof(musicpal_lcd_state), | |
1768 | musicpal_lcd_init); | |
343ec8e4 BC |
1769 | sysbus_register_dev("musicpal_gpio", sizeof(musicpal_gpio_state), |
1770 | musicpal_gpio_init); | |
1771 | sysbus_register_dev("musicpal_key", sizeof(musicpal_key_state), | |
1772 | musicpal_key_init); | |
b47b50fa PB |
1773 | } |
1774 | ||
1775 | device_init(musicpal_register_devices) |