[qemu.git] / hw / net / mipsnet.c

#include "hw/hw.h"
#include "net/net.h"
#include "trace.h"
#include "hw/sysbus.h"

/* MIPSnet register offsets */

#define MIPSNET_DEV_ID		0x00
#define MIPSNET_BUSY		0x08
#define MIPSNET_RX_DATA_COUNT	0x0c
#define MIPSNET_TX_DATA_COUNT	0x10
#define MIPSNET_INT_CTL		0x14
# define MIPSNET_INTCTL_TXDONE		0x00000001
# define MIPSNET_INTCTL_RXDONE		0x00000002
# define MIPSNET_INTCTL_TESTBIT		0x80000000
#define MIPSNET_INTERRUPT_INFO	0x18
#define MIPSNET_RX_DATA_BUFFER	0x1c
#define MIPSNET_TX_DATA_BUFFER	0x20

#define MAX_ETH_FRAME_SIZE	1514

#define TYPE_MIPS_NET "mipsnet"
#define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET)

typedef struct MIPSnetState {
    SysBusDevice parent_obj;

    uint32_t busy;
    uint32_t rx_count;
    uint32_t rx_read;
    uint32_t tx_count;
    uint32_t tx_written;
    uint32_t intctl;
    uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
    uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
    MemoryRegion io;
    qemu_irq irq;
    NICState *nic;
    NICConf conf;
} MIPSnetState;

static void mipsnet_reset(MIPSnetState *s)
{
    s->busy = 1;
    s->rx_count = 0;
    s->rx_read = 0;
    s->tx_count = 0;
    s->tx_written = 0;
    s->intctl = 0;
    memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
    memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
}

static void mipsnet_update_irq(MIPSnetState *s)
{
    int isr = !!s->intctl;
    trace_mipsnet_irq(isr, s->intctl);
    qemu_set_irq(s->irq, isr);
}

static int mipsnet_buffer_full(MIPSnetState *s)
{
    if (s->rx_count >= MAX_ETH_FRAME_SIZE)
        return 1;
    return 0;
}

static int mipsnet_can_receive(NetClientState *nc)
{
    MIPSnetState *s = qemu_get_nic_opaque(nc);

    if (s->busy)
        return 0;
    return !mipsnet_buffer_full(s);
}

static ssize_t mipsnet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
    MIPSnetState *s = qemu_get_nic_opaque(nc);

    trace_mipsnet_receive(size);
    if (!mipsnet_can_receive(nc))
        return -1;

    s->busy = 1;

    /* Just accept everything. */

    /* Write packet data. */
    memcpy(s->rx_buffer, buf, size);

    s->rx_count = size;
    s->rx_read = 0;

    /* Now we can signal we have received something. */
    s->intctl |= MIPSNET_INTCTL_RXDONE;
    mipsnet_update_irq(s);

    return size;
}

static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr,
                                    unsigned int size)
{
    MIPSnetState *s = opaque;
    int ret = 0;

    addr &= 0x3f;
    switch (addr) {
    case MIPSNET_DEV_ID:
	ret = be32_to_cpu(0x4d495053);		/* MIPS */
        break;
    case MIPSNET_DEV_ID + 4:
	ret = be32_to_cpu(0x4e455430);		/* NET0 */
        break;
    case MIPSNET_BUSY:
	ret = s->busy;
        break;
    case MIPSNET_RX_DATA_COUNT:
	ret = s->rx_count;
        break;
    case MIPSNET_TX_DATA_COUNT:
	ret = s->tx_count;
        break;
    case MIPSNET_INT_CTL:
	ret = s->intctl;
        s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
        break;
    case MIPSNET_INTERRUPT_INFO:
        /* XXX: This seems to be a per-VPE interrupt number. */
	ret = 0;
        break;
    case MIPSNET_RX_DATA_BUFFER:
        if (s->rx_count) {
            s->rx_count--;
            ret = s->rx_buffer[s->rx_read++];
        }
        break;
    /* Reads as zero. */
    case MIPSNET_TX_DATA_BUFFER:
    default:
        break;
    }
    trace_mipsnet_read(addr, ret);
    return ret;
}

static void mipsnet_ioport_write(void *opaque, hwaddr addr,
                                 uint64_t val, unsigned int size)
{
    MIPSnetState *s = opaque;

    addr &= 0x3f;
    trace_mipsnet_write(addr, val);
    switch (addr) {
    case MIPSNET_TX_DATA_COUNT:
	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
        s->tx_written = 0;
        break;
    case MIPSNET_INT_CTL:
        if (val & MIPSNET_INTCTL_TXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_TXDONE;
        } else if (val & MIPSNET_INTCTL_RXDONE) {
            s->intctl &= ~MIPSNET_INTCTL_RXDONE;
        } else if (val & MIPSNET_INTCTL_TESTBIT) {
            mipsnet_reset(s);
            s->intctl |= MIPSNET_INTCTL_TESTBIT;
        } else if (!val) {
            /* ACK testbit interrupt, flag was cleared on read. */
        }
        s->busy = !!s->intctl;
        mipsnet_update_irq(s);
        break;
    case MIPSNET_TX_DATA_BUFFER:
        s->tx_buffer[s->tx_written++] = val;
        if (s->tx_written == s->tx_count) {
            /* Send buffer. */
            trace_mipsnet_send(s->tx_count);
            qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, s->tx_count);
            s->tx_count = s->tx_written = 0;
            s->intctl |= MIPSNET_INTCTL_TXDONE;
            s->busy = 1;
            mipsnet_update_irq(s);
        }
        break;
    /* Read-only registers */
    case MIPSNET_DEV_ID:
    case MIPSNET_BUSY:
    case MIPSNET_RX_DATA_COUNT:
    case MIPSNET_INTERRUPT_INFO:
    case MIPSNET_RX_DATA_BUFFER:
    default:
        break;
    }
}

static const VMStateDescription vmstate_mipsnet = {
    .name = "mipsnet",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(busy, MIPSnetState),
        VMSTATE_UINT32(rx_count, MIPSnetState),
        VMSTATE_UINT32(rx_read, MIPSnetState),
        VMSTATE_UINT32(tx_count, MIPSnetState),
        VMSTATE_UINT32(tx_written, MIPSnetState),
        VMSTATE_UINT32(intctl, MIPSnetState),
        VMSTATE_BUFFER(rx_buffer, MIPSnetState),
        VMSTATE_BUFFER(tx_buffer, MIPSnetState),
        VMSTATE_END_OF_LIST()
    }
};

static void mipsnet_cleanup(NetClientState *nc)
{
    MIPSnetState *s = qemu_get_nic_opaque(nc);

    s->nic = NULL;
}

static NetClientInfo net_mipsnet_info = {
    .type = NET_CLIENT_OPTIONS_KIND_NIC,
    .size = sizeof(NICState),
    .can_receive = mipsnet_can_receive,
    .receive = mipsnet_receive,
    .cleanup = mipsnet_cleanup,
};

static const MemoryRegionOps mipsnet_ioport_ops = {
    .read = mipsnet_ioport_read,
    .write = mipsnet_ioport_write,
    .impl.min_access_size = 1,
    .impl.max_access_size = 4,
};

static int mipsnet_sysbus_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    MIPSnetState *s = MIPS_NET(dev);

    memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s,
                          "mipsnet-io", 36);
    sysbus_init_mmio(sbd, &s->io);
    sysbus_init_irq(sbd, &s->irq);

    s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
                          object_get_typename(OBJECT(dev)), dev->id, s);
    qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);

    return 0;
}

static void mipsnet_sysbus_reset(DeviceState *dev)
{
    MIPSnetState *s = MIPS_NET(dev);
    mipsnet_reset(s);
}

static Property mipsnet_properties[] = {
    DEFINE_NIC_PROPERTIES(MIPSnetState, conf),
    DEFINE_PROP_END_OF_LIST(),
};

static void mipsnet_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = mipsnet_sysbus_init;
    set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
    dc->desc = "MIPS Simulator network device";
    dc->reset = mipsnet_sysbus_reset;
    dc->vmsd = &vmstate_mipsnet;
    dc->props = mipsnet_properties;
}

static const TypeInfo mipsnet_info = {
    .name          = TYPE_MIPS_NET,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MIPSnetState),
    .class_init    = mipsnet_class_init,
};

static void mipsnet_register_types(void)
{
    type_register_static(&mipsnet_info);
}

type_init(mipsnet_register_types)
Commit	Line	Data
83c9f4ca	1	#include "hw/hw.h"
1422e32d	2	#include "net/net.h"
83818f7c	3	#include "trace.h"
83c9f4ca	4	#include "hw/sysbus.h"
f0fc6f8f	5
f0fc6f8f TS	6	/* MIPSnet register offsets */
	7
	8	#define MIPSNET_DEV_ID 0x00
f0fc6f8f TS	9	#define MIPSNET_BUSY 0x08
	10	#define MIPSNET_RX_DATA_COUNT 0x0c
	11	#define MIPSNET_TX_DATA_COUNT 0x10
	12	#define MIPSNET_INT_CTL 0x14
	13	# define MIPSNET_INTCTL_TXDONE 0x00000001
	14	# define MIPSNET_INTCTL_RXDONE 0x00000002
	15	# define MIPSNET_INTCTL_TESTBIT 0x80000000
	16	#define MIPSNET_INTERRUPT_INFO 0x18
	17	#define MIPSNET_RX_DATA_BUFFER 0x1c
	18	#define MIPSNET_TX_DATA_BUFFER 0x20
	19
	20	#define MAX_ETH_FRAME_SIZE 1514
	21
a4dbb8bd AF	22	#define TYPE_MIPS_NET "mipsnet"
	23	#define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET)
	24
f0fc6f8f	25	typedef struct MIPSnetState {
a4dbb8bd	26	SysBusDevice parent_obj;
d118d64a	27
f0fc6f8f TS	28	uint32_t busy;
	29	uint32_t rx_count;
	30	uint32_t rx_read;
	31	uint32_t tx_count;
	32	uint32_t tx_written;
	33	uint32_t intctl;
	34	uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
	35	uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
d118d64a	36	MemoryRegion io;
f0fc6f8f	37	qemu_irq irq;
1f30d10a MM	38	NICState *nic;
1f30d10a MM	39	NICConf conf;
f0fc6f8f TS	40	} MIPSnetState;
	41
	42	static void mipsnet_reset(MIPSnetState *s)
	43	{
	44	s->busy = 1;
	45	s->rx_count = 0;
	46	s->rx_read = 0;
	47	s->tx_count = 0;
	48	s->tx_written = 0;
	49	s->intctl = 0;
	50	memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
	51	memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
	52	}
	53
	54	static void mipsnet_update_irq(MIPSnetState *s)
	55	{
	56	int isr = !!s->intctl;
83818f7c	57	trace_mipsnet_irq(isr, s->intctl);
f0fc6f8f TS	58	qemu_set_irq(s->irq, isr);
	59	}
	60
	61	static int mipsnet_buffer_full(MIPSnetState *s)
	62	{
	63	if (s->rx_count >= MAX_ETH_FRAME_SIZE)
	64	return 1;
	65	return 0;
	66	}
	67
4e68f7a0	68	static int mipsnet_can_receive(NetClientState *nc)
f0fc6f8f	69	{
cc1f0f45	70	MIPSnetState *s = qemu_get_nic_opaque(nc);
f0fc6f8f TS	71
	72	if (s->busy)
	73	return 0;
	74	return !mipsnet_buffer_full(s);
	75	}
	76
4e68f7a0	77	static ssize_t mipsnet_receive(NetClientState nc, const uint8_t buf, size_t size)
f0fc6f8f	78	{
cc1f0f45	79	MIPSnetState *s = qemu_get_nic_opaque(nc);
f0fc6f8f	80
83818f7c	81	trace_mipsnet_receive(size);
1f30d10a	82	if (!mipsnet_can_receive(nc))
4f1c942b	83	return -1;
f0fc6f8f TS	84
	85	s->busy = 1;
	86
	87	/* Just accept everything. */
	88
	89	/* Write packet data. */
	90	memcpy(s->rx_buffer, buf, size);
	91
	92	s->rx_count = size;
	93	s->rx_read = 0;
	94
	95	/* Now we can signal we have received something. */
	96	s->intctl \|= MIPSNET_INTCTL_RXDONE;
	97	mipsnet_update_irq(s);
4f1c942b MM	98
4f1c942b MM	99	return size;
f0fc6f8f TS	100	}
f0fc6f8f TS	101
a8170e5e	102	static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr,
d118d64a	103	unsigned int size)
f0fc6f8f TS	104	{
	105	MIPSnetState *s = opaque;
	106	int ret = 0;
f0fc6f8f TS	107
	108	addr &= 0x3f;
	109	switch (addr) {
	110	case MIPSNET_DEV_ID:
9b595395	111	ret = be32_to_cpu(0x4d495053); /* MIPS */
f0fc6f8f TS	112	break;
f0fc6f8f TS	113	case MIPSNET_DEV_ID + 4:
9b595395	114	ret = be32_to_cpu(0x4e455430); /* NET0 */
f0fc6f8f TS	115	break;
	116	case MIPSNET_BUSY:
	117	ret = s->busy;
	118	break;
	119	case MIPSNET_RX_DATA_COUNT:
	120	ret = s->rx_count;
	121	break;
	122	case MIPSNET_TX_DATA_COUNT:
	123	ret = s->tx_count;
	124	break;
	125	case MIPSNET_INT_CTL:
	126	ret = s->intctl;
	127	s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
	128	break;
	129	case MIPSNET_INTERRUPT_INFO:
	130	/* XXX: This seems to be a per-VPE interrupt number. */
	131	ret = 0;
	132	break;
	133	case MIPSNET_RX_DATA_BUFFER:
	134	if (s->rx_count) {
	135	s->rx_count--;
	136	ret = s->rx_buffer[s->rx_read++];
	137	}
	138	break;
	139	/* Reads as zero. */
	140	case MIPSNET_TX_DATA_BUFFER:
	141	default:
	142	break;
	143	}
83818f7c	144	trace_mipsnet_read(addr, ret);
f0fc6f8f TS	145	return ret;
	146	}
	147
a8170e5e	148	static void mipsnet_ioport_write(void *opaque, hwaddr addr,
d118d64a	149	uint64_t val, unsigned int size)
f0fc6f8f TS	150	{
	151	MIPSnetState *s = opaque;
	152
	153	addr &= 0x3f;
83818f7c	154	trace_mipsnet_write(addr, val);
f0fc6f8f TS	155	switch (addr) {
	156	case MIPSNET_TX_DATA_COUNT:
	157	s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
	158	s->tx_written = 0;
	159	break;
	160	case MIPSNET_INT_CTL:
	161	if (val & MIPSNET_INTCTL_TXDONE) {
	162	s->intctl &= ~MIPSNET_INTCTL_TXDONE;
	163	} else if (val & MIPSNET_INTCTL_RXDONE) {
	164	s->intctl &= ~MIPSNET_INTCTL_RXDONE;
	165	} else if (val & MIPSNET_INTCTL_TESTBIT) {
	166	mipsnet_reset(s);
	167	s->intctl \|= MIPSNET_INTCTL_TESTBIT;
	168	} else if (!val) {
	169	/* ACK testbit interrupt, flag was cleared on read. */
	170	}
	171	s->busy = !!s->intctl;
	172	mipsnet_update_irq(s);
	173	break;
	174	case MIPSNET_TX_DATA_BUFFER:
	175	s->tx_buffer[s->tx_written++] = val;
	176	if (s->tx_written == s->tx_count) {
	177	/* Send buffer. */
83818f7c	178	trace_mipsnet_send(s->tx_count);
b356f76d	179	qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, s->tx_count);
f0fc6f8f TS	180	s->tx_count = s->tx_written = 0;
	181	s->intctl \|= MIPSNET_INTCTL_TXDONE;
	182	s->busy = 1;
	183	mipsnet_update_irq(s);
	184	}
	185	break;
	186	/* Read-only registers */
	187	case MIPSNET_DEV_ID:
	188	case MIPSNET_BUSY:
	189	case MIPSNET_RX_DATA_COUNT:
	190	case MIPSNET_INTERRUPT_INFO:
	191	case MIPSNET_RX_DATA_BUFFER:
	192	default:
	193	break;
	194	}
	195	}
	196
c7298ab2 JQ	197	static const VMStateDescription vmstate_mipsnet = {
	198	.name = "mipsnet",
	199	.version_id = 0,
	200	.minimum_version_id = 0,
	201	.minimum_version_id_old = 0,
	202	.fields = (VMStateField[]) {
	203	VMSTATE_UINT32(busy, MIPSnetState),
	204	VMSTATE_UINT32(rx_count, MIPSnetState),
	205	VMSTATE_UINT32(rx_read, MIPSnetState),
	206	VMSTATE_UINT32(tx_count, MIPSnetState),
	207	VMSTATE_UINT32(tx_written, MIPSnetState),
	208	VMSTATE_UINT32(intctl, MIPSnetState),
	209	VMSTATE_BUFFER(rx_buffer, MIPSnetState),
	210	VMSTATE_BUFFER(tx_buffer, MIPSnetState),
	211	VMSTATE_END_OF_LIST()
	212	}
	213	};
f0fc6f8f	214
4e68f7a0	215	static void mipsnet_cleanup(NetClientState *nc)
b946a153	216	{
cc1f0f45	217	MIPSnetState *s = qemu_get_nic_opaque(nc);
b946a153	218
d118d64a	219	s->nic = NULL;
b946a153 AL	220	}
b946a153 AL	221
1f30d10a	222	static NetClientInfo net_mipsnet_info = {
2be64a68	223	.type = NET_CLIENT_OPTIONS_KIND_NIC,
1f30d10a MM	224	.size = sizeof(NICState),
	225	.can_receive = mipsnet_can_receive,
	226	.receive = mipsnet_receive,
	227	.cleanup = mipsnet_cleanup,
	228	};
	229
a348f108	230	static const MemoryRegionOps mipsnet_ioport_ops = {
d118d64a HP	231	.read = mipsnet_ioport_read,
	232	.write = mipsnet_ioport_write,
	233	.impl.min_access_size = 1,
	234	.impl.max_access_size = 4,
	235	};
0ae18cee	236
a4dbb8bd	237	static int mipsnet_sysbus_init(SysBusDevice *sbd)
d118d64a	238	{
a4dbb8bd AF	239	DeviceState *dev = DEVICE(sbd);
a4dbb8bd AF	240	MIPSnetState *s = MIPS_NET(dev);
f0fc6f8f	241
eedfac6f PB	242	memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s,
eedfac6f PB	243	"mipsnet-io", 36);
a4dbb8bd AF	244	sysbus_init_mmio(sbd, &s->io);
a4dbb8bd AF	245	sysbus_init_irq(sbd, &s->irq);
f0fc6f8f	246
d118d64a	247	s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
a4dbb8bd	248	object_get_typename(OBJECT(dev)), dev->id, s);
b356f76d	249	qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1f30d10a	250
d118d64a HP	251	return 0;
d118d64a HP	252	}
f0fc6f8f	253
d118d64a HP	254	static void mipsnet_sysbus_reset(DeviceState *dev)
d118d64a HP	255	{
a4dbb8bd	256	MIPSnetState *s = MIPS_NET(dev);
d118d64a HP	257	mipsnet_reset(s);
d118d64a HP	258	}
1f30d10a	259
999e12bb AL	260	static Property mipsnet_properties[] = {
	261	DEFINE_NIC_PROPERTIES(MIPSnetState, conf),
	262	DEFINE_PROP_END_OF_LIST(),
	263	};
	264
	265	static void mipsnet_class_init(ObjectClass klass, void data)
	266	{
39bffca2	267	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	268	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	269
	270	k->init = mipsnet_sysbus_init;
125ee0ed	271	set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
39bffca2 AL	272	dc->desc = "MIPS Simulator network device";
	273	dc->reset = mipsnet_sysbus_reset;
	274	dc->vmsd = &vmstate_mipsnet;
	275	dc->props = mipsnet_properties;
999e12bb AL	276	}
999e12bb AL	277
8c43a6f0	278	static const TypeInfo mipsnet_info = {
a4dbb8bd	279	.name = TYPE_MIPS_NET,
39bffca2 AL	280	.parent = TYPE_SYS_BUS_DEVICE,
	281	.instance_size = sizeof(MIPSnetState),
	282	.class_init = mipsnet_class_init,
d118d64a	283	};
f0fc6f8f	284
83f7d43a	285	static void mipsnet_register_types(void)
d118d64a	286	{
39bffca2	287	type_register_static(&mipsnet_info);
f0fc6f8f	288	}
d118d64a	289
83f7d43a	290	type_init(mipsnet_register_types)