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[qemu.git] / hw / net / vmxnet3.h
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786fd2b0
DF		 1/*
2 * QEMU VMWARE VMXNET3 paravirtual NIC interface definitions
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Authors:
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
15 *
16 */
17
18#ifndef _QEMU_VMXNET3_H
19#define _QEMU_VMXNET3_H
20
21#define VMXNET3_DEVICE_MAX_TX_QUEUES 8
22#define VMXNET3_DEVICE_MAX_RX_QUEUES 8 /* Keep this value as a power of 2 */
23
24/*
25 * VMWARE headers we got from Linux kernel do not fully comply QEMU coding
26 * standards in sense of types and defines used.
27 * Since we didn't want to change VMWARE code, following set of typedefs
28 * and defines needed to compile these headers with QEMU introduced.
29 */
30#define u64 uint64_t
31#define u32 uint32_t
32#define u16 uint16_t
33#define u8 uint8_t
34#define __le16 uint16_t
35#define __le32 uint32_t
36#define __le64 uint64_t
786fd2b0
DF		 37
38#if defined(HOST_WORDS_BIGENDIAN)
786fd2b0
DF		 39#define __BIG_ENDIAN_BITFIELD
40#else
786fd2b0
DF		 41#endif
42
43/*
44 * Following is an interface definition for
45 * VMXNET3 device as provided by VMWARE
46 * See original copyright from Linux kernel v3.2.8
47 * header file drivers/net/vmxnet3/vmxnet3_defs.h below.
48 */
49
50/*
51 * Linux driver for VMware's vmxnet3 ethernet NIC.
52 *
53 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
54 *
55 * This program is free software; you can redistribute it and/or modify it
56 * under the terms of the GNU General Public License as published by the
57 * Free Software Foundation; version 2 of the License and no later version.
58 *
59 * This program is distributed in the hope that it will be useful, but
60 * WITHOUT ANY WARRANTY; without even the implied warranty of
61 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
62 * NON INFRINGEMENT. See the GNU General Public License for more
63 * details.
64 *
65 * You should have received a copy of the GNU General Public License
66 * along with this program; if not, write to the Free Software
67 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
68 *
69 * The full GNU General Public License is included in this distribution in
70 * the file called "COPYING".
71 *
72 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
73 *
74 */
75
76struct UPT1_TxStats {
77 u64 TSOPktsTxOK; /* TSO pkts post-segmentation */
78 u64 TSOBytesTxOK;
79 u64 ucastPktsTxOK;
80 u64 ucastBytesTxOK;
81 u64 mcastPktsTxOK;
82 u64 mcastBytesTxOK;
83 u64 bcastPktsTxOK;
84 u64 bcastBytesTxOK;
85 u64 pktsTxError;
86 u64 pktsTxDiscard;
87};
88
89struct UPT1_RxStats {
90 u64 LROPktsRxOK; /* LRO pkts */
91 u64 LROBytesRxOK; /* bytes from LRO pkts */
92 /* the following counters are for pkts from the wire, i.e., pre-LRO */
93 u64 ucastPktsRxOK;
94 u64 ucastBytesRxOK;
95 u64 mcastPktsRxOK;
96 u64 mcastBytesRxOK;
97 u64 bcastPktsRxOK;
98 u64 bcastBytesRxOK;
99 u64 pktsRxOutOfBuf;
100 u64 pktsRxError;
101};
102
103/* interrupt moderation level */
104enum {
105 UPT1_IML_NONE = 0, /* no interrupt moderation */
106 UPT1_IML_HIGHEST = 7, /* least intr generated */
107 UPT1_IML_ADAPTIVE = 8, /* adpative intr moderation */
108};
109/* values for UPT1_RSSConf.hashFunc */
110enum {
111 UPT1_RSS_HASH_TYPE_NONE = 0x0,
112 UPT1_RSS_HASH_TYPE_IPV4 = 0x01,
113 UPT1_RSS_HASH_TYPE_TCP_IPV4 = 0x02,
114 UPT1_RSS_HASH_TYPE_IPV6 = 0x04,
115 UPT1_RSS_HASH_TYPE_TCP_IPV6 = 0x08,
116};
117
118enum {
119 UPT1_RSS_HASH_FUNC_NONE = 0x0,
120 UPT1_RSS_HASH_FUNC_TOEPLITZ = 0x01,
121};
122
123#define UPT1_RSS_MAX_KEY_SIZE 40
124#define UPT1_RSS_MAX_IND_TABLE_SIZE 128
125
126struct UPT1_RSSConf {
127 u16 hashType;
128 u16 hashFunc;
129 u16 hashKeySize;
130 u16 indTableSize;
131 u8 hashKey[UPT1_RSS_MAX_KEY_SIZE];
132 u8 indTable[UPT1_RSS_MAX_IND_TABLE_SIZE];
133};
134
135/* features */
136enum {
389dd807
DF		 137 UPT1_F_RXCSUM = 0x0001, /* rx csum verification */
138 UPT1_F_RSS = 0x0002,
139 UPT1_F_RXVLAN = 0x0004, /* VLAN tag stripping */
140 UPT1_F_LRO = 0x0008,
786fd2b0
DF		 141};
142
143/* all registers are 32 bit wide */
144/* BAR 1 */
145enum {
146 VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */
147 VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */
148 VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */
149 VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */
150 VMXNET3_REG_CMD = 0x20, /* Command */
151 VMXNET3_REG_MACL = 0x28, /* MAC Address Low */
152 VMXNET3_REG_MACH = 0x30, /* MAC Address High */
153 VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */
154 VMXNET3_REG_ECR = 0x40 /* Event Cause Register */
155};
156
157/* BAR 0 */
158enum {
159 VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */
160 VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */
161 VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */
162 VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */
163};
164
165#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
166#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
167
168#define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
169#define VMXNET3_REG_ALIGN_MASK 0x7
170
171/* I/O Mapped access to registers */
172#define VMXNET3_IO_TYPE_PT 0
173#define VMXNET3_IO_TYPE_VD 1
174#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
175#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
176#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
177
178enum {
179 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
180 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, /* 0xCAFE0000 */
181 VMXNET3_CMD_QUIESCE_DEV, /* 0xCAFE0001 */
182 VMXNET3_CMD_RESET_DEV, /* 0xCAFE0002 */
183 VMXNET3_CMD_UPDATE_RX_MODE, /* 0xCAFE0003 */
184 VMXNET3_CMD_UPDATE_MAC_FILTERS, /* 0xCAFE0004 */
185 VMXNET3_CMD_UPDATE_VLAN_FILTERS, /* 0xCAFE0005 */
186 VMXNET3_CMD_UPDATE_RSSIDT, /* 0xCAFE0006 */
187 VMXNET3_CMD_UPDATE_IML, /* 0xCAFE0007 */
188 VMXNET3_CMD_UPDATE_PMCFG, /* 0xCAFE0008 */
189 VMXNET3_CMD_UPDATE_FEATURE, /* 0xCAFE0009 */
190 VMXNET3_CMD_LOAD_PLUGIN, /* 0xCAFE000A */
191
192 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
193 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, /* 0xF00D0000 */
194 VMXNET3_CMD_GET_STATS, /* 0xF00D0001 */
195 VMXNET3_CMD_GET_LINK, /* 0xF00D0002 */
196 VMXNET3_CMD_GET_PERM_MAC_LO, /* 0xF00D0003 */
197 VMXNET3_CMD_GET_PERM_MAC_HI, /* 0xF00D0004 */
198 VMXNET3_CMD_GET_DID_LO, /* 0xF00D0005 */
199 VMXNET3_CMD_GET_DID_HI, /* 0xF00D0006 */
200 VMXNET3_CMD_GET_DEV_EXTRA_INFO, /* 0xF00D0007 */
201 VMXNET3_CMD_GET_CONF_INTR /* 0xF00D0008 */
202};
203
204/*
205 * Little Endian layout of bitfields -
206 * Byte 0 : 7.....len.....0
207 * Byte 1 : rsvd gen 13.len.8
208 * Byte 2 : 5.msscof.0 ext1 dtype
209 * Byte 3 : 13...msscof...6
210 *
211 * Big Endian layout of bitfields -
212 * Byte 0: 13...msscof...6
213 * Byte 1 : 5.msscof.0 ext1 dtype
214 * Byte 2 : rsvd gen 13.len.8
215 * Byte 3 : 7.....len.....0
216 *
217 * Thus, le32_to_cpu on the dword will allow the big endian driver to read
218 * the bit fields correctly. And cpu_to_le32 will convert bitfields
219 * bit fields written by big endian driver to format required by device.
220 */
221
222struct Vmxnet3_TxDesc {
223 __le64 addr;
224
225#ifdef __BIG_ENDIAN_BITFIELD
226 u32 msscof:14; /* MSS, checksum offset, flags */
227 u32 ext1:1;
228 u32 dtype:1; /* descriptor type */
229 u32 rsvd:1;
230 u32 gen:1; /* generation bit */
231 u32 len:14;
232#else
233 u32 len:14;
234 u32 gen:1; /* generation bit */
235 u32 rsvd:1;
236 u32 dtype:1; /* descriptor type */
237 u32 ext1:1;
238 u32 msscof:14; /* MSS, checksum offset, flags */
239#endif /* __BIG_ENDIAN_BITFIELD */
240
241#ifdef __BIG_ENDIAN_BITFIELD
242 u32 tci:16; /* Tag to Insert */
243 u32 ti:1; /* VLAN Tag Insertion */
244 u32 ext2:1;
245 u32 cq:1; /* completion request */
246 u32 eop:1; /* End Of Packet */
247 u32 om:2; /* offload mode */
248 u32 hlen:10; /* header len */
249#else
250 u32 hlen:10; /* header len */
251 u32 om:2; /* offload mode */
252 u32 eop:1; /* End Of Packet */
253 u32 cq:1; /* completion request */
254 u32 ext2:1;
255 u32 ti:1; /* VLAN Tag Insertion */
256 u32 tci:16; /* Tag to Insert */
257#endif /* __BIG_ENDIAN_BITFIELD */
258};
259
260/* TxDesc.OM values */
261#define VMXNET3_OM_NONE 0
262#define VMXNET3_OM_CSUM 2
263#define VMXNET3_OM_TSO 3
264
265/* fields in TxDesc we access w/o using bit fields */
266#define VMXNET3_TXD_EOP_SHIFT 12
267#define VMXNET3_TXD_CQ_SHIFT 13
268#define VMXNET3_TXD_GEN_SHIFT 14
269#define VMXNET3_TXD_EOP_DWORD_SHIFT 3
270#define VMXNET3_TXD_GEN_DWORD_SHIFT 2
271
272#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
273#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
274#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
275
276#define VMXNET3_HDR_COPY_SIZE 128
277
278
279struct Vmxnet3_TxDataDesc {
280 u8 data[VMXNET3_HDR_COPY_SIZE];
281};
282
283#define VMXNET3_TCD_GEN_SHIFT 31
284#define VMXNET3_TCD_GEN_SIZE 1
285#define VMXNET3_TCD_TXIDX_SHIFT 0
286#define VMXNET3_TCD_TXIDX_SIZE 12
287#define VMXNET3_TCD_GEN_DWORD_SHIFT 3
288
289struct Vmxnet3_TxCompDesc {
290 u32 txdIdx:12; /* Index of the EOP TxDesc */
291 u32 ext1:20;
292
293 __le32 ext2;
294 __le32 ext3;
295
296 u32 rsvd:24;
297 u32 type:7; /* completion type */
298 u32 gen:1; /* generation bit */
299};
300
301struct Vmxnet3_RxDesc {
302 __le64 addr;
303
304#ifdef __BIG_ENDIAN_BITFIELD
305 u32 gen:1; /* Generation bit */
306 u32 rsvd:15;
307 u32 dtype:1; /* Descriptor type */
308 u32 btype:1; /* Buffer Type */
309 u32 len:14;
310#else
311 u32 len:14;
312 u32 btype:1; /* Buffer Type */
313 u32 dtype:1; /* Descriptor type */
314 u32 rsvd:15;
315 u32 gen:1; /* Generation bit */
316#endif
317 u32 ext1;
318};
319
320/* values of RXD.BTYPE */
321#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
322#define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
323
324/* fields in RxDesc we access w/o using bit fields */
325#define VMXNET3_RXD_BTYPE_SHIFT 14
326#define VMXNET3_RXD_GEN_SHIFT 31
327
328struct Vmxnet3_RxCompDesc {
329#ifdef __BIG_ENDIAN_BITFIELD
330 u32 ext2:1;
331 u32 cnc:1; /* Checksum Not Calculated */
332 u32 rssType:4; /* RSS hash type used */
333 u32 rqID:10; /* rx queue/ring ID */
334 u32 sop:1; /* Start of Packet */
335 u32 eop:1; /* End of Packet */
336 u32 ext1:2;
337 u32 rxdIdx:12; /* Index of the RxDesc */
338#else
339 u32 rxdIdx:12; /* Index of the RxDesc */
340 u32 ext1:2;
341 u32 eop:1; /* End of Packet */
342 u32 sop:1; /* Start of Packet */
343 u32 rqID:10; /* rx queue/ring ID */
344 u32 rssType:4; /* RSS hash type used */
345 u32 cnc:1; /* Checksum Not Calculated */
346 u32 ext2:1;
347#endif /* __BIG_ENDIAN_BITFIELD */
348
349 __le32 rssHash; /* RSS hash value */
350
351#ifdef __BIG_ENDIAN_BITFIELD
352 u32 tci:16; /* Tag stripped */
353 u32 ts:1; /* Tag is stripped */
354 u32 err:1; /* Error */
355 u32 len:14; /* data length */
356#else
357 u32 len:14; /* data length */
358 u32 err:1; /* Error */
359 u32 ts:1; /* Tag is stripped */
360 u32 tci:16; /* Tag stripped */
361#endif /* __BIG_ENDIAN_BITFIELD */
362
363
364#ifdef __BIG_ENDIAN_BITFIELD
365 u32 gen:1; /* generation bit */
366 u32 type:7; /* completion type */
367 u32 fcs:1; /* Frame CRC correct */
368 u32 frg:1; /* IP Fragment */
369 u32 v4:1; /* IPv4 */
370 u32 v6:1; /* IPv6 */
371 u32 ipc:1; /* IP Checksum Correct */
372 u32 tcp:1; /* TCP packet */
373 u32 udp:1; /* UDP packet */
374 u32 tuc:1; /* TCP/UDP Checksum Correct */
375 u32 csum:16;
376#else
377 u32 csum:16;
378 u32 tuc:1; /* TCP/UDP Checksum Correct */
379 u32 udp:1; /* UDP packet */
380 u32 tcp:1; /* TCP packet */
381 u32 ipc:1; /* IP Checksum Correct */
382 u32 v6:1; /* IPv6 */
383 u32 v4:1; /* IPv4 */
384 u32 frg:1; /* IP Fragment */
385 u32 fcs:1; /* Frame CRC correct */
386 u32 type:7; /* completion type */
387 u32 gen:1; /* generation bit */
388#endif /* __BIG_ENDIAN_BITFIELD */
389};
390
391/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
392#define VMXNET3_RCD_TUC_SHIFT 16
393#define VMXNET3_RCD_IPC_SHIFT 19
394
395/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
396#define VMXNET3_RCD_TYPE_SHIFT 56
397#define VMXNET3_RCD_GEN_SHIFT 63
398
399/* csum OK for TCP/UDP pkts over IP */
400#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
401 1 << VMXNET3_RCD_IPC_SHIFT)
402#define VMXNET3_TXD_GEN_SIZE 1
403#define VMXNET3_TXD_EOP_SIZE 1
404
405/* value of RxCompDesc.rssType */
406enum {
407 VMXNET3_RCD_RSS_TYPE_NONE = 0,
408 VMXNET3_RCD_RSS_TYPE_IPV4 = 1,
409 VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2,
410 VMXNET3_RCD_RSS_TYPE_IPV6 = 3,
411 VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4,
412};
413
414
415/* a union for accessing all cmd/completion descriptors */
416union Vmxnet3_GenericDesc {
417 __le64 qword[2];
418 __le32 dword[4];
419 __le16 word[8];
420 struct Vmxnet3_TxDesc txd;
421 struct Vmxnet3_RxDesc rxd;
422 struct Vmxnet3_TxCompDesc tcd;
423 struct Vmxnet3_RxCompDesc rcd;
424};
425
426#define VMXNET3_INIT_GEN 1
427
428/* Max size of a single tx buffer */
429#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
430
431/* # of tx desc needed for a tx buffer size */
432#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
433 VMXNET3_MAX_TX_BUF_SIZE)
434
435/* max # of tx descs for a non-tso pkt */
436#define VMXNET3_MAX_TXD_PER_PKT 16
437
438/* Max size of a single rx buffer */
439#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
440/* Minimum size of a type 0 buffer */
441#define VMXNET3_MIN_T0_BUF_SIZE 128
442#define VMXNET3_MAX_CSUM_OFFSET 1024
443
444/* Ring base address alignment */
445#define VMXNET3_RING_BA_ALIGN 512
446#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
447
448/* Ring size must be a multiple of 32 */
449#define VMXNET3_RING_SIZE_ALIGN 32
450#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
451
452/* Max ring size */
453#define VMXNET3_TX_RING_MAX_SIZE 4096
454#define VMXNET3_TC_RING_MAX_SIZE 4096
455#define VMXNET3_RX_RING_MAX_SIZE 4096
456#define VMXNET3_RC_RING_MAX_SIZE 8192
457
458/* a list of reasons for queue stop */
459
460enum {
461 VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */
462 VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */
463 VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */
464 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */
465 VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */
466 VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */
467 VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */
468 VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */
469};
470
471/* completion descriptor types */
472#define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
473#define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
474
475enum {
476 VMXNET3_GOS_BITS_UNK = 0, /* unknown */
477 VMXNET3_GOS_BITS_32 = 1,
478 VMXNET3_GOS_BITS_64 = 2,
479};
480
481#define VMXNET3_GOS_TYPE_UNK 0 /* unknown */
482#define VMXNET3_GOS_TYPE_LINUX 1
483#define VMXNET3_GOS_TYPE_WIN 2
484#define VMXNET3_GOS_TYPE_SOLARIS 3
485#define VMXNET3_GOS_TYPE_FREEBSD 4
486#define VMXNET3_GOS_TYPE_PXE 5
487
488struct Vmxnet3_GOSInfo {
489#ifdef __BIG_ENDIAN_BITFIELD
490 u32 gosMisc:10; /* other info about gos */
491 u32 gosVer:16; /* gos version */
492 u32 gosType:4; /* which guest */
493 u32 gosBits:2; /* 32-bit or 64-bit? */
494#else
495 u32 gosBits:2; /* 32-bit or 64-bit? */
496 u32 gosType:4; /* which guest */
497 u32 gosVer:16; /* gos version */
498 u32 gosMisc:10; /* other info about gos */
499#endif /* __BIG_ENDIAN_BITFIELD */
500};
501
502struct Vmxnet3_DriverInfo {
503 __le32 version;
504 struct Vmxnet3_GOSInfo gos;
505 __le32 vmxnet3RevSpt;
506 __le32 uptVerSpt;
507};
508
509
510#define VMXNET3_REV1_MAGIC 0xbabefee1
511
512/*
513 * QueueDescPA must be 128 bytes aligned. It points to an array of
514 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
515 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
516 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
517 */
518#define VMXNET3_QUEUE_DESC_ALIGN 128
519
520
521struct Vmxnet3_MiscConf {
522 struct Vmxnet3_DriverInfo driverInfo;
523 __le64 uptFeatures;
524 __le64 ddPA; /* driver data PA */
525 __le64 queueDescPA; /* queue descriptor table PA */
526 __le32 ddLen; /* driver data len */
527 __le32 queueDescLen; /* queue desc. table len in bytes */
528 __le32 mtu;
529 __le16 maxNumRxSG;
530 u8 numTxQueues;
531 u8 numRxQueues;
532 __le32 reserved[4];
533};
534
535
536struct Vmxnet3_TxQueueConf {
537 __le64 txRingBasePA;
538 __le64 dataRingBasePA;
539 __le64 compRingBasePA;
540 __le64 ddPA; /* driver data */
541 __le64 reserved;
542 __le32 txRingSize; /* # of tx desc */
543 __le32 dataRingSize; /* # of data desc */
544 __le32 compRingSize; /* # of comp desc */
545 __le32 ddLen; /* size of driver data */
546 u8 intrIdx;
547 u8 _pad[7];
548};
549
550
551struct Vmxnet3_RxQueueConf {
552 __le64 rxRingBasePA[2];
553 __le64 compRingBasePA;
554 __le64 ddPA; /* driver data */
555 __le64 reserved;
556 __le32 rxRingSize[2]; /* # of rx desc */
557 __le32 compRingSize; /* # of rx comp desc */
558 __le32 ddLen; /* size of driver data */
559 u8 intrIdx;
560 u8 _pad[7];
561};
562
563
564enum vmxnet3_intr_mask_mode {
565 VMXNET3_IMM_AUTO = 0,
566 VMXNET3_IMM_ACTIVE = 1,
567 VMXNET3_IMM_LAZY = 2
568};
569
570enum vmxnet3_intr_type {
571 VMXNET3_IT_AUTO = 0,
572 VMXNET3_IT_INTX = 1,
573 VMXNET3_IT_MSI = 2,
574 VMXNET3_IT_MSIX = 3
575};
576
577#define VMXNET3_MAX_TX_QUEUES 8
578#define VMXNET3_MAX_RX_QUEUES 16
579/* addition 1 for events */
580#define VMXNET3_MAX_INTRS 25
581
582/* value of intrCtrl */
583#define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
584
585
586struct Vmxnet3_IntrConf {
587 bool autoMask;
588 u8 numIntrs; /* # of interrupts */
589 u8 eventIntrIdx;
590 u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for
591 * each intr */
592 __le32 intrCtrl;
593 __le32 reserved[2];
594};
595
596/* one bit per VLAN ID, the size is in the units of u32 */
597#define VMXNET3_VFT_SIZE (4096/(sizeof(uint32_t)*8))
598
599
600struct Vmxnet3_QueueStatus {
601 bool stopped;
602 u8 _pad[3];
603 __le32 error;
604};
605
606
607struct Vmxnet3_TxQueueCtrl {
608 __le32 txNumDeferred;
609 __le32 txThreshold;
610 __le64 reserved;
611};
612
613
614struct Vmxnet3_RxQueueCtrl {
615 bool updateRxProd;
616 u8 _pad[7];
617 __le64 reserved;
618};
619
620enum {
621 VMXNET3_RXM_UCAST = 0x01, /* unicast only */
622 VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */
623 VMXNET3_RXM_BCAST = 0x04, /* broadcast only */
624 VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */
625 VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */
626};
627
628struct Vmxnet3_RxFilterConf {
629 __le32 rxMode; /* VMXNET3_RXM_xxx */
630 __le16 mfTableLen; /* size of the multicast filter table */
631 __le16 _pad1;
632 __le64 mfTablePA; /* PA of the multicast filters table */
633 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
634};
635
636
637#define VMXNET3_PM_MAX_FILTERS 6
638#define VMXNET3_PM_MAX_PATTERN_SIZE 128
639#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
640
641#define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */
642#define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching
643 * filters */
644
645
646struct Vmxnet3_PM_PktFilter {
647 u8 maskSize;
648 u8 patternSize;
649 u8 mask[VMXNET3_PM_MAX_MASK_SIZE];
650 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
651 u8 pad[6];
652};
653
654
655struct Vmxnet3_PMConf {
656 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
657 u8 numFilters;
658 u8 pad[5];
659 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
660};
661
662
663struct Vmxnet3_VariableLenConfDesc {
664 __le32 confVer;
665 __le32 confLen;
666 __le64 confPA;
667};
668
669
670struct Vmxnet3_TxQueueDesc {
671 struct Vmxnet3_TxQueueCtrl ctrl;
672 struct Vmxnet3_TxQueueConf conf;
673
674 /* Driver read after a GET command */
675 struct Vmxnet3_QueueStatus status;
676 struct UPT1_TxStats stats;
677 u8 _pad[88]; /* 128 aligned */
678};
679
680
681struct Vmxnet3_RxQueueDesc {
682 struct Vmxnet3_RxQueueCtrl ctrl;
683 struct Vmxnet3_RxQueueConf conf;
684 /* Driver read after a GET commad */
685 struct Vmxnet3_QueueStatus status;
686 struct UPT1_RxStats stats;
687 u8 __pad[88]; /* 128 aligned */
688};
689
690
691struct Vmxnet3_DSDevRead {
692 /* read-only region for device, read by dev in response to a SET cmd */
693 struct Vmxnet3_MiscConf misc;
694 struct Vmxnet3_IntrConf intrConf;
695 struct Vmxnet3_RxFilterConf rxFilterConf;
696 struct Vmxnet3_VariableLenConfDesc rssConfDesc;
697 struct Vmxnet3_VariableLenConfDesc pmConfDesc;
698 struct Vmxnet3_VariableLenConfDesc pluginConfDesc;
699};
700
701/* All structures in DriverShared are padded to multiples of 8 bytes */
702struct Vmxnet3_DriverShared {
703 __le32 magic;
704 /* make devRead start at 64bit boundaries */
705 __le32 pad;
706 struct Vmxnet3_DSDevRead devRead;
707 __le32 ecr;
708 __le32 reserved[5];
709};
710
711
712#define VMXNET3_ECR_RQERR (1 << 0)
713#define VMXNET3_ECR_TQERR (1 << 1)
714#define VMXNET3_ECR_LINK (1 << 2)
715#define VMXNET3_ECR_DIC (1 << 3)
716#define VMXNET3_ECR_DEBUG (1 << 4)
717
718/* flip the gen bit of a ring */
719#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
720
721/* only use this if moving the idx won't affect the gen bit */
722#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
723 do {\
724 (idx)++;\
725 if (unlikely((idx) == (ring_size))) {\
726 (idx) = 0;\
727 } \
728 } while (0)
729
730#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
731 (vfTable[vid >> 5] |= (1 << (vid & 31)))
732#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
733 (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
734
735#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
736 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
737
738#define VMXNET3_MAX_MTU 9000
739#define VMXNET3_MIN_MTU 60
740
741#define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */
742#define VMXNET3_LINK_DOWN 0
743
744#undef u64
745#undef u32
746#undef u16
747#undef u8
748#undef __le16
749#undef __le32
750#undef __le64
786fd2b0
DF		 751#if defined(HOST_WORDS_BIGENDIAN)
752#undef __BIG_ENDIAN_BITFIELD
753#endif
754
755#endif
Qemu copy for testing