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hw/onenand: Minor spacing fixes
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7e7c5e4c
AZ		 1/*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
fad6cb1a 17 * You should have received a copy of the GNU General Public License along
8167ee88 18 * with this program; if not, see <http://www.gnu.org/licenses/>.
7e7c5e4c
AZ		 19 */
20
21#include "qemu-common.h"
22#include "sysemu.h"
23#include "omap.h"
24#include "arm-misc.h"
25#include "irq.h"
26#include "console.h"
27#include "boards.h"
28#include "i2c.h"
29#include "devices.h"
30#include "flash.h"
31#include "hw.h"
1ae26a18 32#include "bt.h"
ca20cf32 33#include "loader.h"
af5a75f4 34#include "blockdev.h"
d09871f6 35#include "tusb6010.h"
500954e3 36#include "sysbus.h"
7e7c5e4c
AZ		 37
38/* Nokia N8x0 support */
39struct n800_s {
40 struct omap_mpu_state_s *cpu;
41
42 struct rfbi_chip_s blizzard;
e927bb00
AZ		 43 struct {
44 void *opaque;
45 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
bc24a225 46 uWireSlave *chip;
e927bb00 47 } ts;
7e7c5e4c
AZ		 48 i2c_bus *i2c;
49
50 int keymap[0x80];
c4f05c8c 51 DeviceState *kbd;
7e7c5e4c 52
bc24a225 53 TUSBState *usb;
7e7c5e4c
AZ		 54 void *retu;
55 void *tahvo;
500954e3 56 DeviceState *nand;
7e7c5e4c
AZ		 57};
58
59/* GPIO pins */
e927bb00 60#define N8X0_TUSB_ENABLE_GPIO 0
7e7c5e4c
AZ		 61#define N800_MMC2_WP_GPIO 8
62#define N800_UNKNOWN_GPIO0 9 /* out */
0941041e 63#define N810_MMC2_VIOSD_GPIO 9
99570a40 64#define N810_HEADSET_AMP_GPIO 10
7e7c5e4c 65#define N800_CAM_TURN_GPIO 12
e927bb00 66#define N810_GPS_RESET_GPIO 12
7e7c5e4c
AZ		 67#define N800_BLIZZARD_POWERDOWN_GPIO 15
68#define N800_MMC1_WP_GPIO 23
0941041e 69#define N810_MMC2_VSD_GPIO 23
7e7c5e4c 70#define N8X0_ONENAND_GPIO 26
e927bb00 71#define N810_BLIZZARD_RESET_GPIO 30
7e7c5e4c
AZ		 72#define N800_UNKNOWN_GPIO2 53 /* out */
73#define N8X0_TUSB_INT_GPIO 58
e927bb00
AZ		 74#define N8X0_BT_WKUP_GPIO 61
75#define N8X0_STI_GPIO 62
7e7c5e4c 76#define N8X0_CBUS_SEL_GPIO 64
e927bb00
AZ		 77#define N8X0_CBUS_DAT_GPIO 65
78#define N8X0_CBUS_CLK_GPIO 66
79#define N8X0_WLAN_IRQ_GPIO 87
80#define N8X0_BT_RESET_GPIO 92
81#define N8X0_TEA5761_CS_GPIO 93
7e7c5e4c 82#define N800_UNKNOWN_GPIO 94
e927bb00 83#define N810_TSC_RESET_GPIO 94
7e7c5e4c 84#define N800_CAM_ACT_GPIO 95
e927bb00
AZ		 85#define N810_GPS_WAKEUP_GPIO 95
86#define N8X0_MMC_CS_GPIO 96
87#define N8X0_WLAN_PWR_GPIO 97
7e7c5e4c 88#define N8X0_BT_HOST_WKUP_GPIO 98
99570a40 89#define N810_SPEAKER_AMP_GPIO 101
7e7c5e4c
AZ		 90#define N810_KB_LOCK_GPIO 102
91#define N800_TSC_TS_GPIO 103
e927bb00
AZ		 92#define N810_TSC_TS_GPIO 106
93#define N8X0_HEADPHONE_GPIO 107
7e7c5e4c
AZ		 94#define N8X0_RETU_GPIO 108
95#define N800_TSC_KP_IRQ_GPIO 109
96#define N810_KEYBOARD_GPIO 109
97#define N800_BAT_COVER_GPIO 110
98#define N810_SLIDE_GPIO 110
99#define N8X0_TAHVO_GPIO 111
100#define N800_UNKNOWN_GPIO4 112 /* out */
e927bb00 101#define N810_SLEEPX_LED_GPIO 112
1d4e547b 102#define N800_TSC_RESET_GPIO 118 /* ? */
99570a40 103#define N810_AIC33_RESET_GPIO 118
1d4e547b 104#define N800_TSC_UNKNOWN_GPIO 119 /* out */
7e7c5e4c
AZ		 105#define N8X0_TMP105_GPIO 125
106
107/* Config */
c580d92b 108#define BT_UART 0
7e7c5e4c
AZ		 109#define XLDR_LL_UART 1
110
1d4e547b
AZ		 111/* Addresses on the I2C bus 0 */
112#define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
113#define N8X0_TCM825x_ADDR 0x29 /* Camera */
114#define N810_LP5521_ADDR 0x32 /* LEDs */
115#define N810_TSL2563_ADDR 0x3d /* Light sensor */
116#define N810_LM8323_ADDR 0x45 /* Keyboard */
117/* Addresses on the I2C bus 1 */
118#define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
119#define N8X0_MENELAUS_ADDR 0x72 /* Power management */
7e7c5e4c
AZ		 120
121/* Chipselects on GPMC NOR interface */
122#define N8X0_ONENAND_CS 0
123#define N8X0_USB_ASYNC_CS 1
124#define N8X0_USB_SYNC_CS 4
125
c580d92b
AZ		 126#define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
127
7e7c5e4c
AZ		 128static void n800_mmc_cs_cb(void *opaque, int line, int level)
129{
130 /* TODO: this seems to actually be connected to the menelaus, to
131 * which also both MMC slots connect. */
132 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
133
134 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
135}
136
e927bb00 137static void n8x0_gpio_setup(struct n800_s *s)
7e7c5e4c
AZ		 138{
139 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
77831c20 140 qdev_connect_gpio_out(s->cpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
7e7c5e4c 141
77831c20 142 qemu_irq_lower(qdev_get_gpio_in(s->cpu->gpio, N800_BAT_COVER_GPIO));
7e7c5e4c
AZ		 143}
144
c580d92b
AZ		 145#define MAEMO_CAL_HEADER(...) \
146 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
147 __VA_ARGS__, \
148 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
149
150static const uint8_t n8x0_cal_wlan_mac[] = {
151 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
152 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
153 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
154 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
155 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
156 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
157};
158
159static const uint8_t n8x0_cal_bt_id[] = {
160 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
161 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
162 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
163 N8X0_BD_ADDR,
164};
165
7e7c5e4c
AZ		 166static void n8x0_nand_setup(struct n800_s *s)
167{
c580d92b 168 char *otp_region;
af5a75f4 169 DriveInfo *dinfo;
c580d92b 170
500954e3
JR		 171 s->nand = qdev_create(NULL, "onenand");
172 qdev_prop_set_uint16(s->nand, "manufacturer_id", NAND_MFR_SAMSUNG);
5923ba42 173 /* Either 0x40 or 0x48 are OK for the device ID */
500954e3
JR		 174 qdev_prop_set_uint16(s->nand, "device_id", 0x48);
175 qdev_prop_set_uint16(s->nand, "version_id", 0);
176 qdev_prop_set_int32(s->nand, "shift", 1);
177 dinfo = drive_get(IF_MTD, 0, 0);
178 if (dinfo && dinfo->bdrv) {
179 qdev_prop_set_drive_nofail(s->nand, "drive", dinfo->bdrv);
180 }
181 qdev_init_nofail(s->nand);
182 sysbus_connect_irq(sysbus_from_qdev(s->nand), 0,
183 qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
184 omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS,
185 sysbus_mmio_get_region(sysbus_from_qdev(s->nand), 0),
186 NULL, NULL,
187 s->nand);
c580d92b
AZ		 188 otp_region = onenand_raw_otp(s->nand);
189
190 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
191 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
192 /* XXX: in theory should also update the OOB for both pages */
7e7c5e4c
AZ		 193}
194
e927bb00 195static void n8x0_i2c_setup(struct n800_s *s)
7e7c5e4c 196{
697454eb 197 DeviceState *dev;
77831c20 198 qemu_irq tmp_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TMP105_GPIO);
7e7c5e4c
AZ		 199
200 /* Attach the CPU on one end of our I2C bus. */
201 s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
202
203 /* Attach a menelaus PM chip */
d3356811
PB		 204 dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR);
205 qdev_connect_gpio_out(dev, 3, s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]);
7e7c5e4c
AZ		 206
207 /* Attach a TMP105 PM chip (A0 wired to ground) */
697454eb
PB		 208 dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR);
209 qdev_connect_gpio_out(dev, 0, tmp_irq);
7e7c5e4c
AZ		 210}
211
212/* Touchscreen and keypad controller */
bc24a225 213static MouseTransformInfo n800_pointercal = {
e927bb00
AZ		 214 .x = 800,
215 .y = 480,
216 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
217};
218
bc24a225 219static MouseTransformInfo n810_pointercal = {
e927bb00
AZ		 220 .x = 800,
221 .y = 480,
222 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
223};
224
7e7c5e4c
AZ		 225#define RETU_KEYCODE 61 /* F3 */
226
227static void n800_key_event(void *opaque, int keycode)
228{
229 struct n800_s *s = (struct n800_s *) opaque;
230 int code = s->keymap[keycode & 0x7f];
231
232 if (code == -1) {
233 if ((keycode & 0x7f) == RETU_KEYCODE)
234 retu_key_event(s->retu, !(keycode & 0x80));
235 return;
236 }
237
e927bb00 238 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
7e7c5e4c
AZ		 239}
240
241static const int n800_keys[16] = {
242 -1,
243 72, /* Up */
244 63, /* Home (F5) */
245 -1,
246 75, /* Left */
247 28, /* Enter */
248 77, /* Right */
249 -1,
1d4e547b 250 1, /* Cycle (ESC) */
7e7c5e4c
AZ		 251 80, /* Down */
252 62, /* Menu (F4) */
253 -1,
254 66, /* Zoom- (F8) */
1d4e547b 255 64, /* FullScreen (F6) */
7e7c5e4c
AZ		 256 65, /* Zoom+ (F7) */
257 -1,
258};
259
e927bb00 260static void n800_tsc_kbd_setup(struct n800_s *s)
7e7c5e4c
AZ		 261{
262 int i;
263
264 /* XXX: are the three pins inverted inside the chip between the
265 * tsc and the cpu (N4111)? */
b9d38e95 266 qemu_irq penirq = NULL; /* NC */
77831c20
JR		 267 qemu_irq kbirq = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_KP_IRQ_GPIO);
268 qemu_irq dav = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_TS_GPIO);
7e7c5e4c 269
22d83b14 270 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
e927bb00
AZ		 271 s->ts.opaque = s->ts.chip->opaque;
272 s->ts.txrx = tsc210x_txrx;
7e7c5e4c
AZ		 273
274 for (i = 0; i < 0x80; i ++)
275 s->keymap[i] = -1;
276 for (i = 0; i < 0x10; i ++)
277 if (n800_keys[i] >= 0)
278 s->keymap[n800_keys[i]] = i;
279
280 qemu_add_kbd_event_handler(n800_key_event, s);
281
e927bb00
AZ		 282 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
283}
284
285static void n810_tsc_setup(struct n800_s *s)
286{
77831c20 287 qemu_irq pintdav = qdev_get_gpio_in(s->cpu->gpio, N810_TSC_TS_GPIO);
e927bb00
AZ		 288
289 s->ts.opaque = tsc2005_init(pintdav);
290 s->ts.txrx = tsc2005_txrx;
291
292 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
7e7c5e4c
AZ		 293}
294
1d4e547b
AZ		 295/* N810 Keyboard controller */
296static void n810_key_event(void *opaque, int keycode)
297{
298 struct n800_s *s = (struct n800_s *) opaque;
299 int code = s->keymap[keycode & 0x7f];
300
301 if (code == -1) {
302 if ((keycode & 0x7f) == RETU_KEYCODE)
303 retu_key_event(s->retu, !(keycode & 0x80));
304 return;
305 }
306
307 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
308}
309
310#define M 0
311
312static int n810_keys[0x80] = {
313 [0x01] = 16, /* Q */
314 [0x02] = 37, /* K */
315 [0x03] = 24, /* O */
316 [0x04] = 25, /* P */
317 [0x05] = 14, /* Backspace */
318 [0x06] = 30, /* A */
319 [0x07] = 31, /* S */
320 [0x08] = 32, /* D */
321 [0x09] = 33, /* F */
322 [0x0a] = 34, /* G */
323 [0x0b] = 35, /* H */
324 [0x0c] = 36, /* J */
325
326 [0x11] = 17, /* W */
327 [0x12] = 62, /* Menu (F4) */
328 [0x13] = 38, /* L */
329 [0x14] = 40, /* ' (Apostrophe) */
330 [0x16] = 44, /* Z */
331 [0x17] = 45, /* X */
332 [0x18] = 46, /* C */
333 [0x19] = 47, /* V */
334 [0x1a] = 48, /* B */
335 [0x1b] = 49, /* N */
336 [0x1c] = 42, /* Shift (Left shift) */
337 [0x1f] = 65, /* Zoom+ (F7) */
338
339 [0x21] = 18, /* E */
340 [0x22] = 39, /* ; (Semicolon) */
341 [0x23] = 12, /* - (Minus) */
342 [0x24] = 13, /* = (Equal) */
343 [0x2b] = 56, /* Fn (Left Alt) */
344 [0x2c] = 50, /* M */
345 [0x2f] = 66, /* Zoom- (F8) */
346
347 [0x31] = 19, /* R */
348 [0x32] = 29 | M, /* Right Ctrl */
349 [0x34] = 57, /* Space */
350 [0x35] = 51, /* , (Comma) */
351 [0x37] = 72 | M, /* Up */
352 [0x3c] = 82 | M, /* Compose (Insert) */
353 [0x3f] = 64, /* FullScreen (F6) */
354
355 [0x41] = 20, /* T */
356 [0x44] = 52, /* . (Dot) */
357 [0x46] = 77 | M, /* Right */
358 [0x4f] = 63, /* Home (F5) */
359 [0x51] = 21, /* Y */
360 [0x53] = 80 | M, /* Down */
361 [0x55] = 28, /* Enter */
362 [0x5f] = 1, /* Cycle (ESC) */
363
364 [0x61] = 22, /* U */
365 [0x64] = 75 | M, /* Left */
366
367 [0x71] = 23, /* I */
368#if 0
369 [0x75] = 28 | M, /* KP Enter (KP Enter) */
370#else
371 [0x75] = 15, /* KP Enter (Tab) */
372#endif
373};
374
375#undef M
376
377static void n810_kbd_setup(struct n800_s *s)
378{
77831c20 379 qemu_irq kbd_irq = qdev_get_gpio_in(s->cpu->gpio, N810_KEYBOARD_GPIO);
1d4e547b
AZ		 380 int i;
381
382 for (i = 0; i < 0x80; i ++)
383 s->keymap[i] = -1;
384 for (i = 0; i < 0x80; i ++)
385 if (n810_keys[i] > 0)
386 s->keymap[n810_keys[i]] = i;
387
388 qemu_add_kbd_event_handler(n810_key_event, s);
389
390 /* Attach the LM8322 keyboard to the I2C bus,
391 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
c4f05c8c
PM		 392 s->kbd = i2c_create_slave(s->i2c, "lm8323", N810_LM8323_ADDR);
393 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
1d4e547b
AZ		 394}
395
7e7c5e4c
AZ		 396/* LCD MIPI DBI-C controller (URAL) */
397struct mipid_s {
398 int resp[4];
399 int param[4];
400 int p;
401 int pm;
402 int cmd;
403
404 int sleep;
405 int booster;
406 int te;
407 int selfcheck;
408 int partial;
409 int normal;
410 int vscr;
411 int invert;
412 int onoff;
413 int gamma;
414 uint32_t id;
415};
416
417static void mipid_reset(struct mipid_s *s)
418{
419 if (!s->sleep)
420 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
421
422 s->pm = 0;
423 s->cmd = 0;
424
425 s->sleep = 1;
426 s->booster = 0;
427 s->selfcheck =
428 (1 << 7) | /* Register loading OK. */
429 (1 << 5) | /* The chip is attached. */
430 (1 << 4); /* Display glass still in one piece. */
431 s->te = 0;
432 s->partial = 0;
433 s->normal = 1;
434 s->vscr = 0;
435 s->invert = 0;
436 s->onoff = 1;
437 s->gamma = 0;
438}
439
e927bb00 440static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
7e7c5e4c
AZ		 441{
442 struct mipid_s *s = (struct mipid_s *) opaque;
443 uint8_t ret;
444
e927bb00 445 if (len > 9)
2ac71179 446 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
e927bb00 447
b1503cda 448 if (s->p >= ARRAY_SIZE(s->resp))
7e7c5e4c
AZ		 449 ret = 0;
450 else
451 ret = s->resp[s->p ++];
452 if (s->pm --> 0)
453 s->param[s->pm] = cmd;
454 else
455 s->cmd = cmd;
456
457 switch (s->cmd) {
458 case 0x00: /* NOP */
459 break;
460
461 case 0x01: /* SWRESET */
462 mipid_reset(s);
463 break;
464
465 case 0x02: /* BSTROFF */
466 s->booster = 0;
467 break;
468 case 0x03: /* BSTRON */
469 s->booster = 1;
470 break;
471
472 case 0x04: /* RDDID */
473 s->p = 0;
474 s->resp[0] = (s->id >> 16) & 0xff;
475 s->resp[1] = (s->id >> 8) & 0xff;
476 s->resp[2] = (s->id >> 0) & 0xff;
477 break;
478
479 case 0x06: /* RD_RED */
480 case 0x07: /* RD_GREEN */
481 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
482 * for the bootloader one needs to change this. */
483 case 0x08: /* RD_BLUE */
484 s->p = 0;
485 /* TODO: return first pixel components */
486 s->resp[0] = 0x01;
487 break;
488
489 case 0x09: /* RDDST */
490 s->p = 0;
491 s->resp[0] = s->booster << 7;
492 s->resp[1] = (5 << 4) | (s->partial << 2) |
493 (s->sleep << 1) | s->normal;
494 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
495 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
496 s->resp[3] = s->gamma << 6;
497 break;
498
499 case 0x0a: /* RDDPM */
500 s->p = 0;
501 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
502 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
503 break;
504 case 0x0b: /* RDDMADCTR */
505 s->p = 0;
506 s->resp[0] = 0;
507 break;
508 case 0x0c: /* RDDCOLMOD */
509 s->p = 0;
510 s->resp[0] = 5; /* 65K colours */
511 break;
512 case 0x0d: /* RDDIM */
513 s->p = 0;
514 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
515 break;
516 case 0x0e: /* RDDSM */
517 s->p = 0;
518 s->resp[0] = s->te << 7;
519 break;
520 case 0x0f: /* RDDSDR */
521 s->p = 0;
522 s->resp[0] = s->selfcheck;
523 break;
524
525 case 0x10: /* SLPIN */
526 s->sleep = 1;
527 break;
528 case 0x11: /* SLPOUT */
529 s->sleep = 0;
530 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
531 break;
532
533 case 0x12: /* PTLON */
534 s->partial = 1;
535 s->normal = 0;
536 s->vscr = 0;
537 break;
538 case 0x13: /* NORON */
539 s->partial = 0;
540 s->normal = 1;
541 s->vscr = 0;
542 break;
543
544 case 0x20: /* INVOFF */
545 s->invert = 0;
546 break;
547 case 0x21: /* INVON */
548 s->invert = 1;
549 break;
550
551 case 0x22: /* APOFF */
552 case 0x23: /* APON */
553 goto bad_cmd;
554
555 case 0x25: /* WRCNTR */
556 if (s->pm < 0)
557 s->pm = 1;
558 goto bad_cmd;
559
560 case 0x26: /* GAMSET */
561 if (!s->pm)
562 s->gamma = ffs(s->param[0] & 0xf) - 1;
563 else if (s->pm < 0)
564 s->pm = 1;
565 break;
566
567 case 0x28: /* DISPOFF */
568 s->onoff = 0;
569 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
570 break;
571 case 0x29: /* DISPON */
572 s->onoff = 1;
573 fprintf(stderr, "%s: Display on\n", __FUNCTION__);
574 break;
575
576 case 0x2a: /* CASET */
577 case 0x2b: /* RASET */
578 case 0x2c: /* RAMWR */
579 case 0x2d: /* RGBSET */
580 case 0x2e: /* RAMRD */
581 case 0x30: /* PTLAR */
582 case 0x33: /* SCRLAR */
583 goto bad_cmd;
584
585 case 0x34: /* TEOFF */
586 s->te = 0;
587 break;
588 case 0x35: /* TEON */
589 if (!s->pm)
590 s->te = 1;
591 else if (s->pm < 0)
592 s->pm = 1;
593 break;
594
595 case 0x36: /* MADCTR */
596 goto bad_cmd;
597
598 case 0x37: /* VSCSAD */
599 s->partial = 0;
600 s->normal = 0;
601 s->vscr = 1;
602 break;
603
604 case 0x38: /* IDMOFF */
605 case 0x39: /* IDMON */
606 case 0x3a: /* COLMOD */
607 goto bad_cmd;
608
609 case 0xb0: /* CLKINT / DISCTL */
610 case 0xb1: /* CLKEXT */
611 if (s->pm < 0)
612 s->pm = 2;
613 break;
614
615 case 0xb4: /* FRMSEL */
616 break;
617
618 case 0xb5: /* FRM8SEL */
619 case 0xb6: /* TMPRNG / INIESC */
620 case 0xb7: /* TMPHIS / NOP2 */
621 case 0xb8: /* TMPREAD / MADCTL */
622 case 0xba: /* DISTCTR */
623 case 0xbb: /* EPVOL */
624 goto bad_cmd;
625
626 case 0xbd: /* Unknown */
627 s->p = 0;
628 s->resp[0] = 0;
629 s->resp[1] = 1;
630 break;
631
632 case 0xc2: /* IFMOD */
633 if (s->pm < 0)
634 s->pm = 2;
635 break;
636
637 case 0xc6: /* PWRCTL */
638 case 0xc7: /* PPWRCTL */
639 case 0xd0: /* EPWROUT */
640 case 0xd1: /* EPWRIN */
641 case 0xd4: /* RDEV */
642 case 0xd5: /* RDRR */
643 goto bad_cmd;
644
645 case 0xda: /* RDID1 */
646 s->p = 0;
647 s->resp[0] = (s->id >> 16) & 0xff;
648 break;
649 case 0xdb: /* RDID2 */
650 s->p = 0;
651 s->resp[0] = (s->id >> 8) & 0xff;
652 break;
653 case 0xdc: /* RDID3 */
654 s->p = 0;
655 s->resp[0] = (s->id >> 0) & 0xff;
656 break;
657
658 default:
659 bad_cmd:
660 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
661 break;
662 }
663
664 return ret;
665}
666
667static void *mipid_init(void)
668{
7267c094 669 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
7e7c5e4c
AZ		 670
671 s->id = 0x838f03;
672 mipid_reset(s);
673
674 return s;
675}
676
e927bb00 677static void n8x0_spi_setup(struct n800_s *s)
7e7c5e4c 678{
e927bb00 679 void *tsc = s->ts.opaque;
7e7c5e4c
AZ		 680 void *mipid = mipid_init();
681
e927bb00 682 omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
7e7c5e4c
AZ		 683 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
684}
685
686/* This task is normally performed by the bootloader. If we're loading
687 * a kernel directly, we need to enable the Blizzard ourselves. */
688static void n800_dss_init(struct rfbi_chip_s *chip)
689{
690 uint8_t *fb_blank;
691
692 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
693 chip->write(chip->opaque, 1, 0x64);
694 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
695 chip->write(chip->opaque, 1, 0x1e);
696 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
697 chip->write(chip->opaque, 1, 0xe0);
698 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
699 chip->write(chip->opaque, 1, 0x01);
700 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
701 chip->write(chip->opaque, 1, 0x06);
702 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
703 chip->write(chip->opaque, 1, 1); /* Enable bit */
704
705 chip->write(chip->opaque, 0, 0x6c);
706 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
707 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
708 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
709 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
710 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
711 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
712 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
713 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
714 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
715 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
716 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
717 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
718 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
719 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
720 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
721 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
722 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
723 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
724
7267c094 725 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
7e7c5e4c
AZ		 726 /* Display Memory Data Port */
727 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
7267c094 728 g_free(fb_blank);
7e7c5e4c
AZ		 729}
730
3023f332 731static void n8x0_dss_setup(struct n800_s *s)
7e7c5e4c 732{
b9d38e95 733 s->blizzard.opaque = s1d13745_init(NULL);
7e7c5e4c
AZ		 734 s->blizzard.block = s1d13745_write_block;
735 s->blizzard.write = s1d13745_write;
736 s->blizzard.read = s1d13745_read;
737
738 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
739}
740
e927bb00 741static void n8x0_cbus_setup(struct n800_s *s)
7e7c5e4c 742{
77831c20
JR		 743 qemu_irq dat_out = qdev_get_gpio_in(s->cpu->gpio, N8X0_CBUS_DAT_GPIO);
744 qemu_irq retu_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_RETU_GPIO);
745 qemu_irq tahvo_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TAHVO_GPIO);
7e7c5e4c 746
bc24a225 747 CBus *cbus = cbus_init(dat_out);
7e7c5e4c 748
77831c20
JR		 749 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
750 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
751 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
7e7c5e4c
AZ		 752
753 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
754 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
755}
756
58a26b47
AZ		 757static void n8x0_uart_setup(struct n800_s *s)
758{
759 CharDriverState *radio = uart_hci_init(
77831c20 760 qdev_get_gpio_in(s->cpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
58a26b47 761
77831c20 762 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_RESET_GPIO,
58a26b47 763 csrhci_pins_get(radio)[csrhci_pin_reset]);
77831c20 764 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_WKUP_GPIO,
58a26b47
AZ		 765 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
766
767 omap_uart_attach(s->cpu->uart[BT_UART], radio);
768}
769
e927bb00 770static void n8x0_usb_power_cb(void *opaque, int line, int level)
942ac052
AZ		 771{
772 struct n800_s *s = opaque;
773
774 tusb6010_power(s->usb, level);
775}
776
e927bb00 777static void n8x0_usb_setup(struct n800_s *s)
942ac052 778{
77831c20 779 qemu_irq tusb_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TUSB_INT_GPIO);
e927bb00 780 qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
bc24a225 781 TUSBState *tusb = tusb6010_init(tusb_irq);
942ac052
AZ		 782
783 /* Using the NOR interface */
784 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
b9d38e95 785 tusb6010_async_io(tusb), NULL, NULL, tusb);
942ac052 786 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS,
b9d38e95 787 tusb6010_sync_io(tusb), NULL, NULL, tusb);
942ac052
AZ		 788
789 s->usb = tusb;
77831c20 790 qdev_connect_gpio_out(s->cpu->gpio, N8X0_TUSB_ENABLE_GPIO, tusb_pwr);
942ac052
AZ		 791}
792
d238db7f
AZ		 793/* Setup done before the main bootloader starts by some early setup code
794 * - used when we want to run the main bootloader in emulation. This
795 * isn't documented. */
796static uint32_t n800_pinout[104] = {
797 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
798 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
799 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
800 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
801 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
802 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
803 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
804 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
805 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
806 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
807 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
808 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
809 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
810 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
811 0x00000000, 0x00000038, 0x00340000, 0x00000000,
812 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
813 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
814 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
815 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
816 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
817 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
818 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
819 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
820 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
821 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
822 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
823};
824
825static void n800_setup_nolo_tags(void *sram_base)
826{
827 int i;
828 uint32_t *p = sram_base + 0x8000;
829 uint32_t *v = sram_base + 0xa000;
830
831 memset(p, 0, 0x3000);
832
833 strcpy((void *) (p + 0), "QEMU N800");
834
835 strcpy((void *) (p + 8), "F5");
836
837 stl_raw(p + 10, 0x04f70000);
838 strcpy((void *) (p + 9), "RX-34");
839
840 /* RAM size in MB? */
841 stl_raw(p + 12, 0x80);
842
843 /* Pointer to the list of tags */
844 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
845
846 /* The NOLO tags start here */
847 p = sram_base + 0x9000;
848#define ADD_TAG(tag, len) \
849 stw_raw((uint16_t *) p + 0, tag); \
850 stw_raw((uint16_t *) p + 1, len); p ++; \
851 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
852
853 /* OMAP STI console? Pin out settings? */
854 ADD_TAG(0x6e01, 414);
b1503cda 855 for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
d238db7f
AZ		 856 stl_raw(v ++, n800_pinout[i]);
857
858 /* Kernel memsize? */
859 ADD_TAG(0x6e05, 1);
860 stl_raw(v ++, 2);
861
862 /* NOLO serial console */
863 ADD_TAG(0x6e02, 4);
864 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
865
866#if 0
867 /* CBUS settings (Retu/AVilma) */
868 ADD_TAG(0x6e03, 6);
869 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
870 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
871 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
872 v += 2;
873#endif
874
875 /* Nokia ASIC BB5 (Retu/Tahvo) */
876 ADD_TAG(0x6e0a, 4);
877 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
878 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
879 v ++;
880
881 /* LCD console? */
882 ADD_TAG(0x6e04, 4);
883 stw_raw((uint16_t *) v + 0, 30); /* ??? */
884 stw_raw((uint16_t *) v + 1, 24); /* ??? */
885 v ++;
886
887#if 0
888 /* LCD settings */
889 ADD_TAG(0x6e06, 2);
890 stw_raw((uint16_t *) (v ++), 15); /* ??? */
891#endif
892
893 /* I^2C (Menelaus) */
894 ADD_TAG(0x6e07, 4);
895 stl_raw(v ++, 0x00720000); /* ??? */
896
897 /* Unknown */
898 ADD_TAG(0x6e0b, 6);
899 stw_raw((uint16_t *) v + 0, 94); /* ??? */
900 stw_raw((uint16_t *) v + 1, 23); /* ??? */
901 stw_raw((uint16_t *) v + 2, 0); /* ??? */
902 v += 2;
903
904 /* OMAP gpio switch info */
905 ADD_TAG(0x6e0c, 80);
906 strcpy((void *) v, "bat_cover"); v += 3;
907 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
908 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
909 v += 2;
910 strcpy((void *) v, "cam_act"); v += 3;
911 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
912 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
913 v += 2;
914 strcpy((void *) v, "cam_turn"); v += 3;
915 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
916 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
917 v += 2;
918 strcpy((void *) v, "headphone"); v += 3;
919 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
920 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
921 v += 2;
922
923 /* Bluetooth */
924 ADD_TAG(0x6e0e, 12);
925 stl_raw(v ++, 0x5c623d01); /* ??? */
926 stl_raw(v ++, 0x00000201); /* ??? */
927 stl_raw(v ++, 0x00000000); /* ??? */
928
929 /* CX3110x WLAN settings */
930 ADD_TAG(0x6e0f, 8);
931 stl_raw(v ++, 0x00610025); /* ??? */
932 stl_raw(v ++, 0xffff0057); /* ??? */
933
934 /* MMC host settings */
935 ADD_TAG(0x6e10, 12);
936 stl_raw(v ++, 0xffff000f); /* ??? */
937 stl_raw(v ++, 0xffffffff); /* ??? */
938 stl_raw(v ++, 0x00000060); /* ??? */
939
940 /* OneNAND chip select */
941 ADD_TAG(0x6e11, 10);
942 stl_raw(v ++, 0x00000401); /* ??? */
943 stl_raw(v ++, 0x0002003a); /* ??? */
944 stl_raw(v ++, 0x00000002); /* ??? */
945
946 /* TEA5761 sensor settings */
947 ADD_TAG(0x6e12, 2);
948 stl_raw(v ++, 93); /* GPIO num ??? */
949
950#if 0
951 /* Unknown tag */
952 ADD_TAG(6e09, 0);
953
954 /* Kernel UART / console */
955 ADD_TAG(6e12, 0);
956#endif
957
958 /* End of the list */
959 stl_raw(p ++, 0x00000000);
960 stl_raw(p ++, 0x00000000);
961}
962
7e7c5e4c
AZ		 963/* This task is normally performed by the bootloader. If we're loading
964 * a kernel directly, we need to set up GPMC mappings ourselves. */
965static void n800_gpmc_init(struct n800_s *s)
966{
967 uint32_t config7 =
968 (0xf << 8) | /* MASKADDRESS */
969 (1 << 6) | /* CSVALID */
970 (4 << 0); /* BASEADDRESS */
971
972 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
973 (void *) &config7, sizeof(config7));
974}
975
976/* Setup sequence done by the bootloader */
e927bb00 977static void n8x0_boot_init(void *opaque)
7e7c5e4c
AZ		 978{
979 struct n800_s *s = (struct n800_s *) opaque;
980 uint32_t buf;
981
982 /* PRCM setup */
983#define omap_writel(addr, val) \
984 buf = (val); \
985 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
986
987 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
988 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
989 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
990 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
991 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
992 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
993 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
994 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
995 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
996 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
997 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
998 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
999 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
1000 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
1001 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
1002 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
1003 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
1004 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
1005 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
1006 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
1007 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
1008 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
1009 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
1010 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
1011 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1012 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1013 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1014 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1015 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1016 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1017 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1018 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1019 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1020 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1021 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1022 (0x78 << 12) | (6 << 8));
1023 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1024
1025 /* GPMC setup */
1026 n800_gpmc_init(s);
1027
1028 /* Video setup */
1029 n800_dss_init(&s->blizzard);
1030
1031 /* CPU setup */
7e7c5e4c 1032 s->cpu->env->GE = 0x5;
0941041e
AZ		 1033
1034 /* If the machine has a slided keyboard, open it */
1035 if (s->kbd)
77831c20 1036 qemu_irq_raise(qdev_get_gpio_in(s->cpu->gpio, N810_SLIDE_GPIO));
7e7c5e4c
AZ		 1037}
1038
1039#define OMAP_TAG_NOKIA_BT 0x4e01
1040#define OMAP_TAG_WLAN_CX3110X 0x4e02
1041#define OMAP_TAG_CBUS 0x4e03
1042#define OMAP_TAG_EM_ASIC_BB5 0x4e04
1043
e927bb00
AZ		 1044static struct omap_gpiosw_info_s {
1045 const char *name;
1046 int line;
1047 int type;
1048} n800_gpiosw_info[] = {
1049 {
1050 "bat_cover", N800_BAT_COVER_GPIO,
1051 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1052 }, {
1053 "cam_act", N800_CAM_ACT_GPIO,
1054 OMAP_GPIOSW_TYPE_ACTIVITY,
1055 }, {
1056 "cam_turn", N800_CAM_TURN_GPIO,
1057 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1058 }, {
1059 "headphone", N8X0_HEADPHONE_GPIO,
1060 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1061 },
b9d38e95 1062 { NULL }
e927bb00
AZ		 1063}, n810_gpiosw_info[] = {
1064 {
1065 "gps_reset", N810_GPS_RESET_GPIO,
1066 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1067 }, {
1068 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1069 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1070 }, {
1071 "headphone", N8X0_HEADPHONE_GPIO,
1072 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1073 }, {
1074 "kb_lock", N810_KB_LOCK_GPIO,
1075 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1076 }, {
1077 "sleepx_led", N810_SLEEPX_LED_GPIO,
1078 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1079 }, {
1080 "slide", N810_SLIDE_GPIO,
1081 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1082 },
b9d38e95 1083 { NULL }
e927bb00
AZ		 1084};
1085
1086static struct omap_partition_info_s {
1087 uint32_t offset;
1088 uint32_t size;
1089 int mask;
1090 const char *name;
1091} n800_part_info[] = {
1092 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1093 { 0x00020000, 0x00060000, 0x0, "config" },
1094 { 0x00080000, 0x00200000, 0x0, "kernel" },
1095 { 0x00280000, 0x00200000, 0x3, "initfs" },
1096 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1097
b9d38e95 1098 { 0, 0, 0, NULL }
e927bb00
AZ		 1099}, n810_part_info[] = {
1100 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1101 { 0x00020000, 0x00060000, 0x0, "config" },
1102 { 0x00080000, 0x00220000, 0x0, "kernel" },
1103 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1104 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1105
b9d38e95 1106 { 0, 0, 0, NULL }
e927bb00
AZ		 1107};
1108
c227f099 1109static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
c580d92b 1110
e927bb00 1111static int n8x0_atag_setup(void *p, int model)
7e7c5e4c
AZ		 1112{
1113 uint8_t *b;
1114 uint16_t *w;
1115 uint32_t *l;
e927bb00
AZ		 1116 struct omap_gpiosw_info_s *gpiosw;
1117 struct omap_partition_info_s *partition;
1118 const char *tag;
7e7c5e4c
AZ		 1119
1120 w = p;
1121
1122 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1123 stw_raw(w ++, 4); /* u16 len */
1124 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1125 w ++;
1126
e927bb00
AZ		 1127#if 0
1128 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
7e7c5e4c 1129 stw_raw(w ++, 4); /* u16 len */
c580d92b 1130 stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
e927bb00
AZ		 1131 stw_raw(w ++, 115200); /* u32 console_speed */
1132#endif
1133
1134 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1135 stw_raw(w ++, 36); /* u16 len */
1136 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1137 w += 8;
1138 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1139 w += 8;
1140 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1141 stw_raw(w ++, 24); /* u8 data_lines */
7e7c5e4c
AZ		 1142
1143 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1144 stw_raw(w ++, 8); /* u16 len */
1145 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1146 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1147 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1148 w ++;
1149
e927bb00
AZ		 1150 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1151 stw_raw(w ++, 4); /* u16 len */
1152 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1153 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1154
1155 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1156 for (; gpiosw->name; gpiosw ++) {
1157 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1158 stw_raw(w ++, 20); /* u16 len */
1159 strcpy((void *) w, gpiosw->name); /* char name[12] */
1160 w += 6;
1161 stw_raw(w ++, gpiosw->line); /* u16 gpio */
1162 stw_raw(w ++, gpiosw->type);
1163 stw_raw(w ++, 0);
1164 stw_raw(w ++, 0);
1165 }
7e7c5e4c
AZ		 1166
1167 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1168 stw_raw(w ++, 12); /* u16 len */
1169 b = (void *) w;
1170 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
e927bb00 1171 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
7e7c5e4c 1172 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
e927bb00 1173 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
c580d92b
AZ		 1174 stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1175 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
7e7c5e4c
AZ		 1176 b += 6;
1177 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1178 w = (void *) b;
1179
1180 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1181 stw_raw(w ++, 8); /* u16 len */
1182 stw_raw(w ++, 0x25); /* u8 chip_type */
e927bb00
AZ		 1183 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1184 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
7e7c5e4c
AZ		 1185 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1186
1187 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1188 stw_raw(w ++, 16); /* u16 len */
e927bb00
AZ		 1189 if (model == 810) {
1190 stw_raw(w ++, 0x23f); /* unsigned flags */
1191 stw_raw(w ++, -1); /* s16 power_pin */
1192 stw_raw(w ++, -1); /* s16 switch_pin */
1193 stw_raw(w ++, -1); /* s16 wp_pin */
1194 stw_raw(w ++, 0x240); /* unsigned flags */
1195 stw_raw(w ++, 0xc000); /* s16 power_pin */
1196 stw_raw(w ++, 0x0248); /* s16 switch_pin */
1197 stw_raw(w ++, 0xc000); /* s16 wp_pin */
1198 } else {
1199 stw_raw(w ++, 0xf); /* unsigned flags */
1200 stw_raw(w ++, -1); /* s16 power_pin */
1201 stw_raw(w ++, -1); /* s16 switch_pin */
1202 stw_raw(w ++, -1); /* s16 wp_pin */
1203 stw_raw(w ++, 0); /* unsigned flags */
1204 stw_raw(w ++, 0); /* s16 power_pin */
1205 stw_raw(w ++, 0); /* s16 switch_pin */
1206 stw_raw(w ++, 0); /* s16 wp_pin */
1207 }
7e7c5e4c
AZ		 1208
1209 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1210 stw_raw(w ++, 4); /* u16 len */
e927bb00 1211 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
7e7c5e4c
AZ		 1212 w ++;
1213
e927bb00
AZ		 1214 partition = (model == 810) ? n810_part_info : n800_part_info;
1215 for (; partition->name; partition ++) {
1216 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1217 stw_raw(w ++, 28); /* u16 len */
1218 strcpy((void *) w, partition->name); /* char name[16] */
1219 l = (void *) (w + 8);
1220 stl_raw(l ++, partition->size); /* unsigned int size */
1221 stl_raw(l ++, partition->offset); /* unsigned int offset */
1222 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1223 w = (void *) l;
1224 }
7e7c5e4c
AZ		 1225
1226 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1227 stw_raw(w ++, 12); /* u16 len */
1228#if 0
1229 strcpy((void *) w, "por"); /* char reason_str[12] */
1230 strcpy((void *) w, "charger"); /* char reason_str[12] */
1231 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1232 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1233 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1234 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1235 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1236 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1237 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1238 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1239#else
1240 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1241#endif
1242 w += 6;
1243
e927bb00 1244 tag = (model == 810) ? "RX-44" : "RX-34";
7e7c5e4c
AZ		 1245 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1246 stw_raw(w ++, 24); /* u16 len */
1247 strcpy((void *) w, "product"); /* char component[12] */
1248 w += 6;
e927bb00 1249 strcpy((void *) w, tag); /* char version[12] */
7e7c5e4c
AZ		 1250 w += 6;
1251
1252 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1253 stw_raw(w ++, 24); /* u16 len */
1254 strcpy((void *) w, "hw-build"); /* char component[12] */
1255 w += 6;
e927bb00 1256 strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */
7e7c5e4c
AZ		 1257 w += 6;
1258
e927bb00 1259 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
7e7c5e4c
AZ		 1260 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1261 stw_raw(w ++, 24); /* u16 len */
1262 strcpy((void *) w, "nolo"); /* char component[12] */
1263 w += 6;
e927bb00 1264 strcpy((void *) w, tag); /* char version[12] */
7e7c5e4c 1265 w += 6;
7e7c5e4c
AZ		 1266
1267 return (void *) w - p;
1268}
1269
462a8bc6 1270static int n800_atag_setup(const struct arm_boot_info *info, void *p)
e927bb00
AZ		 1271{
1272 return n8x0_atag_setup(p, 800);
1273}
7e7c5e4c 1274
462a8bc6 1275static int n810_atag_setup(const struct arm_boot_info *info, void *p)
e927bb00
AZ		 1276{
1277 return n8x0_atag_setup(p, 810);
1278}
1279
c227f099 1280static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
3023f332 1281 const char *kernel_filename,
e927bb00
AZ		 1282 const char *kernel_cmdline, const char *initrd_filename,
1283 const char *cpu_model, struct arm_boot_info *binfo, int model)
7e7c5e4c 1284{
7267c094 1285 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
e927bb00 1286 int sdram_size = binfo->ram_size;
09218951 1287 DisplayState *ds;
7e7c5e4c 1288
3023f332 1289 s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
7e7c5e4c 1290
0941041e
AZ		 1291 /* Setup peripherals
1292 *
1293 * Believed external peripherals layout in the N810:
1294 * (spi bus 1)
1295 * tsc2005
1296 * lcd_mipid
1297 * (spi bus 2)
1298 * Conexant cx3110x (WLAN)
1299 * optional: pc2400m (WiMAX)
1300 * (i2c bus 0)
1301 * TLV320AIC33 (audio codec)
1302 * TCM825x (camera by Toshiba)
1303 * lp5521 (clever LEDs)
1304 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1305 * lm8323 (keypad, manf 00, rev 04)
1306 * (i2c bus 1)
1307 * tmp105 (temperature sensor, hwmon)
1308 * menelaus (pm)
d238db7f
AZ		 1309 * (somewhere on i2c - maybe N800-only)
1310 * tea5761 (FM tuner)
1311 * (serial 0)
1312 * GPS
1313 * (some serial port)
1314 * csr41814 (Bluetooth)
0941041e 1315 */
e927bb00 1316 n8x0_gpio_setup(s);
7e7c5e4c 1317 n8x0_nand_setup(s);
e927bb00
AZ		 1318 n8x0_i2c_setup(s);
1319 if (model == 800)
1320 n800_tsc_kbd_setup(s);
1d4e547b 1321 else if (model == 810) {
e927bb00 1322 n810_tsc_setup(s);
1d4e547b
AZ		 1323 n810_kbd_setup(s);
1324 }
e927bb00 1325 n8x0_spi_setup(s);
3023f332 1326 n8x0_dss_setup(s);
e927bb00 1327 n8x0_cbus_setup(s);
58a26b47 1328 n8x0_uart_setup(s);
942ac052 1329 if (usb_enabled)
e927bb00 1330 n8x0_usb_setup(s);
7e7c5e4c 1331
7e7c5e4c
AZ		 1332 if (kernel_filename) {
1333 /* Or at the linux loader. */
e927bb00
AZ		 1334 binfo->kernel_filename = kernel_filename;
1335 binfo->kernel_cmdline = kernel_cmdline;
1336 binfo->initrd_filename = initrd_filename;
1337 arm_load_kernel(s->cpu->env, binfo);
7e7c5e4c 1338
a08d4367 1339 qemu_register_reset(n8x0_boot_init, s);
7e7c5e4c
AZ		 1340 }
1341
2e55e842 1342 if (option_rom[0].name && (boot_device[0] == 'n' || !kernel_filename)) {
dcac9679 1343 int rom_size;
5c130f65 1344 uint8_t nolo_tags[0x10000];
d238db7f
AZ		 1345 /* No, wait, better start at the ROM. */
1346 s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000;
1347
1348 /* This is intended for loading the `secondary.bin' program from
1349 * Nokia images (the NOLO bootloader). The entry point seems
1350 * to be at OMAP2_Q2_BASE + 0x400000.
1351 *
1352 * The `2nd.bin' files contain some kind of earlier boot code and
1353 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1354 *
1355 * The code above is for loading the `zImage' file from Nokia
1356 * images. */
2e55e842 1357 rom_size = load_image_targphys(option_rom[0].name,
dcac9679
PB		 1358 OMAP2_Q2_BASE + 0x400000,
1359 sdram_size - 0x400000);
1360 printf("%i bytes of image loaded\n", rom_size);
d238db7f 1361
5c130f65
PB		 1362 n800_setup_nolo_tags(nolo_tags);
1363 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
d238db7f 1364 }
c60e08d9
PB		 1365 /* FIXME: We shouldn't really be doing this here. The LCD controller
1366 will set the size once configured, so this just sets an initial
1367 size until the guest activates the display. */
09218951 1368 ds = get_displaystate();
7b5d76da 1369 ds->surface = qemu_resize_displaysurface(ds, 800, 480);
7d957bd8 1370 dpy_resize(ds);
7e7c5e4c
AZ		 1371}
1372
e927bb00
AZ		 1373static struct arm_boot_info n800_binfo = {
1374 .loader_start = OMAP2_Q2_BASE,
1375 /* Actually two chips of 0x4000000 bytes each */
1376 .ram_size = 0x08000000,
1377 .board_id = 0x4f7,
1378 .atag_board = n800_atag_setup,
1379};
1380
1381static struct arm_boot_info n810_binfo = {
1382 .loader_start = OMAP2_Q2_BASE,
1383 /* Actually two chips of 0x4000000 bytes each */
1384 .ram_size = 0x08000000,
1385 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1386 * used by some older versions of the bootloader and 5555 is used
1387 * instead (including versions that shipped with many devices). */
1388 .board_id = 0x60c,
1389 .atag_board = n810_atag_setup,
1390};
1391
c227f099 1392static void n800_init(ram_addr_t ram_size,
3023f332 1393 const char *boot_device,
e927bb00
AZ		 1394 const char *kernel_filename, const char *kernel_cmdline,
1395 const char *initrd_filename, const char *cpu_model)
1396{
3023f332 1397 return n8x0_init(ram_size, boot_device,
e927bb00
AZ		 1398 kernel_filename, kernel_cmdline, initrd_filename,
1399 cpu_model, &n800_binfo, 800);
1400}
1401
c227f099 1402static void n810_init(ram_addr_t ram_size,
3023f332 1403 const char *boot_device,
e927bb00
AZ		 1404 const char *kernel_filename, const char *kernel_cmdline,
1405 const char *initrd_filename, const char *cpu_model)
1406{
3023f332 1407 return n8x0_init(ram_size, boot_device,
e927bb00
AZ		 1408 kernel_filename, kernel_cmdline, initrd_filename,
1409 cpu_model, &n810_binfo, 810);
1410}
1411
f80f9ec9 1412static QEMUMachine n800_machine = {
4b32e168
AL		 1413 .name = "n800",
1414 .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1415 .init = n800_init,
7e7c5e4c 1416};
e927bb00 1417
f80f9ec9 1418static QEMUMachine n810_machine = {
4b32e168
AL		 1419 .name = "n810",
1420 .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1421 .init = n810_init,
e927bb00 1422};
f80f9ec9
AL		 1423
1424static void nseries_machine_init(void)
1425{
1426 qemu_register_machine(&n800_machine);
1427 qemu_register_machine(&n810_machine);
1428}
1429
1430machine_init(nseries_machine_init);
Qemu copy for testing