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hw/omap1.c: Separate PWT from omap_mpu_state
[qemu.git] / hw / omap1.c
CommitLineData
c3d2689d
AZ		 1/*
2 * TI OMAP processors emulation.
3 *
b4e3104b 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
c3d2689d
AZ		 5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
827df9f3
AZ		 8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
c3d2689d
AZ		 10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
fad6cb1a 16 * You should have received a copy of the GNU General Public License along
8167ee88 17 * with this program; if not, see <http://www.gnu.org/licenses/>.
c3d2689d 18 */
87ecb68b
PB		 19#include "hw.h"
20#include "arm-misc.h"
21#include "omap.h"
22#include "sysemu.h"
23#include "qemu-timer.h"
827df9f3 24#include "qemu-char.h"
afbb5194 25#include "soc_dma.h"
87ecb68b
PB		 26/* We use pc-style serial ports. */
27#include "pc.h"
2446333c 28#include "blockdev.h"
45416789 29#include "range.h"
77831c20 30#include "sysbus.h"
c3d2689d 31
827df9f3 32/* Should signal the TCMI/GPMC */
c227f099 33uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
66450b15 34{
02645926
AZ		 35 uint8_t ret;
36
66450b15 37 OMAP_8B_REG(addr);
b854bc19 38 cpu_physical_memory_read(addr, (void *) &ret, 1);
02645926 39 return ret;
66450b15
AZ		 40}
41
c227f099 42void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
66450b15
AZ		 43 uint32_t value)
44{
b854bc19
AZ		 45 uint8_t val8 = value;
46
66450b15 47 OMAP_8B_REG(addr);
b854bc19 48 cpu_physical_memory_write(addr, (void *) &val8, 1);
66450b15
AZ		 49}
50
c227f099 51uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
c3d2689d 52{
b854bc19
AZ		 53 uint16_t ret;
54
c3d2689d 55 OMAP_16B_REG(addr);
b854bc19
AZ		 56 cpu_physical_memory_read(addr, (void *) &ret, 2);
57 return ret;
c3d2689d
AZ		 58}
59
c227f099 60void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 61 uint32_t value)
62{
b854bc19
AZ		 63 uint16_t val16 = value;
64
c3d2689d 65 OMAP_16B_REG(addr);
b854bc19 66 cpu_physical_memory_write(addr, (void *) &val16, 2);
c3d2689d
AZ		 67}
68
c227f099 69uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
c3d2689d 70{
b854bc19
AZ		 71 uint32_t ret;
72
c3d2689d 73 OMAP_32B_REG(addr);
b854bc19
AZ		 74 cpu_physical_memory_read(addr, (void *) &ret, 4);
75 return ret;
c3d2689d
AZ		 76}
77
c227f099 78void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 79 uint32_t value)
80{
81 OMAP_32B_REG(addr);
b854bc19 82 cpu_physical_memory_write(addr, (void *) &value, 4);
c3d2689d
AZ		 83}
84
c3d2689d
AZ		 85/* MPU OS timers */
86struct omap_mpu_timer_s {
4b3fedf3 87 MemoryRegion iomem;
c3d2689d
AZ		 88 qemu_irq irq;
89 omap_clk clk;
c3d2689d
AZ		 90 uint32_t val;
91 int64_t time;
92 QEMUTimer *timer;
e856f2ad 93 QEMUBH *tick;
c3d2689d
AZ		 94 int64_t rate;
95 int it_ena;
96
97 int enable;
98 int ptv;
99 int ar;
100 int st;
101 uint32_t reset_val;
102};
103
104static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
105{
74475455 106 uint64_t distance = qemu_get_clock_ns(vm_clock) - timer->time;
c3d2689d
AZ		 107
108 if (timer->st && timer->enable && timer->rate)
109 return timer->val - muldiv64(distance >> (timer->ptv + 1),
6ee093c9 110 timer->rate, get_ticks_per_sec());
c3d2689d
AZ		 111 else
112 return timer->val;
113}
114
115static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
116{
117 timer->val = omap_timer_read(timer);
74475455 118 timer->time = qemu_get_clock_ns(vm_clock);
c3d2689d
AZ		 119}
120
121static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
122{
123 int64_t expires;
124
125 if (timer->enable && timer->st && timer->rate) {
126 timer->val = timer->reset_val; /* Should skip this on clk enable */
b8b137d6 127 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
6ee093c9 128 get_ticks_per_sec(), timer->rate);
b854bc19
AZ		 129
130 /* If timer expiry would be sooner than in about 1 ms and
131 * auto-reload isn't set, then fire immediately. This is a hack
132 * to make systems like PalmOS run in acceptable time. PalmOS
133 * sets the interval to a very low value and polls the status bit
134 * in a busy loop when it wants to sleep just a couple of CPU
135 * ticks. */
6ee093c9 136 if (expires > (get_ticks_per_sec() >> 10) || timer->ar)
b854bc19 137 qemu_mod_timer(timer->timer, timer->time + expires);
e856f2ad
AZ		 138 else
139 qemu_bh_schedule(timer->tick);
c3d2689d
AZ		 140 } else
141 qemu_del_timer(timer->timer);
142}
143
e856f2ad 144static void omap_timer_fire(void *opaque)
c3d2689d 145{
e856f2ad 146 struct omap_mpu_timer_s *timer = opaque;
c3d2689d
AZ		 147
148 if (!timer->ar) {
149 timer->val = 0;
150 timer->st = 0;
151 }
152
153 if (timer->it_ena)
106627d0
AZ		 154 /* Edge-triggered irq */
155 qemu_irq_pulse(timer->irq);
e856f2ad
AZ		 156}
157
158static void omap_timer_tick(void *opaque)
159{
160 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
161
162 omap_timer_sync(timer);
163 omap_timer_fire(timer);
c3d2689d
AZ		 164 omap_timer_update(timer);
165}
166
167static void omap_timer_clk_update(void *opaque, int line, int on)
168{
169 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
170
171 omap_timer_sync(timer);
172 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
173 omap_timer_update(timer);
174}
175
176static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
177{
178 omap_clk_adduser(timer->clk,
179 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
180 timer->rate = omap_clk_getrate(timer->clk);
181}
182
4b3fedf3
AK		 183static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr,
184 unsigned size)
c3d2689d
AZ		 185{
186 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
c3d2689d 187
4b3fedf3
AK		 188 if (size != 4) {
189 return omap_badwidth_read32(opaque, addr);
190 }
191
8da3ff18 192 switch (addr) {
c3d2689d
AZ		 193 case 0x00: /* CNTL_TIMER */
194 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
195
196 case 0x04: /* LOAD_TIM */
197 break;
198
199 case 0x08: /* READ_TIM */
200 return omap_timer_read(s);
201 }
202
203 OMAP_BAD_REG(addr);
204 return 0;
205}
206
c227f099 207static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 208 uint64_t value, unsigned size)
c3d2689d
AZ		 209{
210 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
c3d2689d 211
4b3fedf3
AK		 212 if (size != 4) {
213 return omap_badwidth_write32(opaque, addr, value);
214 }
215
8da3ff18 216 switch (addr) {
c3d2689d
AZ		 217 case 0x00: /* CNTL_TIMER */
218 omap_timer_sync(s);
219 s->enable = (value >> 5) & 1;
220 s->ptv = (value >> 2) & 7;
221 s->ar = (value >> 1) & 1;
222 s->st = value & 1;
223 omap_timer_update(s);
224 return;
225
226 case 0x04: /* LOAD_TIM */
227 s->reset_val = value;
228 return;
229
230 case 0x08: /* READ_TIM */
231 OMAP_RO_REG(addr);
232 break;
233
234 default:
235 OMAP_BAD_REG(addr);
236 }
237}
238
4b3fedf3
AK		 239static const MemoryRegionOps omap_mpu_timer_ops = {
240 .read = omap_mpu_timer_read,
241 .write = omap_mpu_timer_write,
242 .endianness = DEVICE_LITTLE_ENDIAN,
c3d2689d
AZ		 243};
244
245static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
246{
247 qemu_del_timer(s->timer);
248 s->enable = 0;
249 s->reset_val = 31337;
250 s->val = 0;
251 s->ptv = 0;
252 s->ar = 0;
253 s->st = 0;
254 s->it_ena = 1;
255}
256
4b3fedf3
AK		 257static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
258 target_phys_addr_t base,
c3d2689d
AZ		 259 qemu_irq irq, omap_clk clk)
260{
c3d2689d 261 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
7267c094 262 g_malloc0(sizeof(struct omap_mpu_timer_s));
c3d2689d
AZ		 263
264 s->irq = irq;
265 s->clk = clk;
74475455 266 s->timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, s);
e856f2ad 267 s->tick = qemu_bh_new(omap_timer_fire, s);
c3d2689d
AZ		 268 omap_mpu_timer_reset(s);
269 omap_timer_clk_setup(s);
270
4b3fedf3
AK		 271 memory_region_init_io(&s->iomem, &omap_mpu_timer_ops, s,
272 "omap-mpu-timer", 0x100);
273
274 memory_region_add_subregion(system_memory, base, &s->iomem);
c3d2689d
AZ		 275
276 return s;
277}
278
279/* Watchdog timer */
280struct omap_watchdog_timer_s {
281 struct omap_mpu_timer_s timer;
4b3fedf3 282 MemoryRegion iomem;
c3d2689d
AZ		 283 uint8_t last_wr;
284 int mode;
285 int free;
286 int reset;
287};
288
4b3fedf3
AK		 289static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr,
290 unsigned size)
c3d2689d
AZ		 291{
292 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
c3d2689d 293
4b3fedf3
AK		 294 if (size != 2) {
295 return omap_badwidth_read16(opaque, addr);
296 }
297
8da3ff18 298 switch (addr) {
c3d2689d
AZ		 299 case 0x00: /* CNTL_TIMER */
300 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
301 (s->timer.st << 7) | (s->free << 1);
302
303 case 0x04: /* READ_TIMER */
304 return omap_timer_read(&s->timer);
305
306 case 0x08: /* TIMER_MODE */
307 return s->mode << 15;
308 }
309
310 OMAP_BAD_REG(addr);
311 return 0;
312}
313
c227f099 314static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 315 uint64_t value, unsigned size)
c3d2689d
AZ		 316{
317 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
c3d2689d 318
4b3fedf3
AK		 319 if (size != 2) {
320 return omap_badwidth_write16(opaque, addr, value);
321 }
322
8da3ff18 323 switch (addr) {
c3d2689d
AZ		 324 case 0x00: /* CNTL_TIMER */
325 omap_timer_sync(&s->timer);
326 s->timer.ptv = (value >> 9) & 7;
327 s->timer.ar = (value >> 8) & 1;
328 s->timer.st = (value >> 7) & 1;
329 s->free = (value >> 1) & 1;
330 omap_timer_update(&s->timer);
331 break;
332
333 case 0x04: /* LOAD_TIMER */
334 s->timer.reset_val = value & 0xffff;
335 break;
336
337 case 0x08: /* TIMER_MODE */
338 if (!s->mode && ((value >> 15) & 1))
339 omap_clk_get(s->timer.clk);
340 s->mode |= (value >> 15) & 1;
341 if (s->last_wr == 0xf5) {
342 if ((value & 0xff) == 0xa0) {
d8f699cb
AZ		 343 if (s->mode) {
344 s->mode = 0;
345 omap_clk_put(s->timer.clk);
346 }
c3d2689d
AZ		 347 } else {
348 /* XXX: on T|E hardware somehow this has no effect,
349 * on Zire 71 it works as specified. */
350 s->reset = 1;
351 qemu_system_reset_request();
352 }
353 }
354 s->last_wr = value & 0xff;
355 break;
356
357 default:
358 OMAP_BAD_REG(addr);
359 }
360}
361
4b3fedf3
AK		 362static const MemoryRegionOps omap_wd_timer_ops = {
363 .read = omap_wd_timer_read,
364 .write = omap_wd_timer_write,
365 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 366};
367
368static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
369{
370 qemu_del_timer(s->timer.timer);
371 if (!s->mode)
372 omap_clk_get(s->timer.clk);
373 s->mode = 1;
374 s->free = 1;
375 s->reset = 0;
376 s->timer.enable = 1;
377 s->timer.it_ena = 1;
378 s->timer.reset_val = 0xffff;
379 s->timer.val = 0;
380 s->timer.st = 0;
381 s->timer.ptv = 0;
382 s->timer.ar = 0;
383 omap_timer_update(&s->timer);
384}
385
4b3fedf3
AK		 386static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
387 target_phys_addr_t base,
c3d2689d
AZ		 388 qemu_irq irq, omap_clk clk)
389{
c3d2689d 390 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
7267c094 391 g_malloc0(sizeof(struct omap_watchdog_timer_s));
c3d2689d
AZ		 392
393 s->timer.irq = irq;
394 s->timer.clk = clk;
74475455 395 s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
c3d2689d
AZ		 396 omap_wd_timer_reset(s);
397 omap_timer_clk_setup(&s->timer);
398
4b3fedf3
AK		 399 memory_region_init_io(&s->iomem, &omap_wd_timer_ops, s,
400 "omap-wd-timer", 0x100);
401 memory_region_add_subregion(memory, base, &s->iomem);
c3d2689d
AZ		 402
403 return s;
404}
405
406/* 32-kHz timer */
407struct omap_32khz_timer_s {
408 struct omap_mpu_timer_s timer;
4b3fedf3 409 MemoryRegion iomem;
c3d2689d
AZ		 410};
411
4b3fedf3
AK		 412static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,
413 unsigned size)
c3d2689d
AZ		 414{
415 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
cf965d24 416 int offset = addr & OMAP_MPUI_REG_MASK;
c3d2689d 417
4b3fedf3
AK		 418 if (size != 4) {
419 return omap_badwidth_read32(opaque, addr);
420 }
421
c3d2689d
AZ		 422 switch (offset) {
423 case 0x00: /* TVR */
424 return s->timer.reset_val;
425
426 case 0x04: /* TCR */
427 return omap_timer_read(&s->timer);
428
429 case 0x08: /* CR */
430 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
431
432 default:
433 break;
434 }
435 OMAP_BAD_REG(addr);
436 return 0;
437}
438
c227f099 439static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 440 uint64_t value, unsigned size)
c3d2689d
AZ		 441{
442 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
cf965d24 443 int offset = addr & OMAP_MPUI_REG_MASK;
c3d2689d 444
4b3fedf3
AK		 445 if (size != 4) {
446 return omap_badwidth_write32(opaque, addr, value);
447 }
448
c3d2689d
AZ		 449 switch (offset) {
450 case 0x00: /* TVR */
451 s->timer.reset_val = value & 0x00ffffff;
452 break;
453
454 case 0x04: /* TCR */
455 OMAP_RO_REG(addr);
456 break;
457
458 case 0x08: /* CR */
459 s->timer.ar = (value >> 3) & 1;
460 s->timer.it_ena = (value >> 2) & 1;
461 if (s->timer.st != (value & 1) || (value & 2)) {
462 omap_timer_sync(&s->timer);
463 s->timer.enable = value & 1;
464 s->timer.st = value & 1;
465 omap_timer_update(&s->timer);
466 }
467 break;
468
469 default:
470 OMAP_BAD_REG(addr);
471 }
472}
473
4b3fedf3
AK		 474static const MemoryRegionOps omap_os_timer_ops = {
475 .read = omap_os_timer_read,
476 .write = omap_os_timer_write,
477 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 478};
479
480static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
481{
482 qemu_del_timer(s->timer.timer);
483 s->timer.enable = 0;
484 s->timer.it_ena = 0;
485 s->timer.reset_val = 0x00ffffff;
486 s->timer.val = 0;
487 s->timer.st = 0;
488 s->timer.ptv = 0;
489 s->timer.ar = 1;
490}
491
4b3fedf3
AK		 492static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
493 target_phys_addr_t base,
c3d2689d
AZ		 494 qemu_irq irq, omap_clk clk)
495{
c3d2689d 496 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
7267c094 497 g_malloc0(sizeof(struct omap_32khz_timer_s));
c3d2689d
AZ		 498
499 s->timer.irq = irq;
500 s->timer.clk = clk;
74475455 501 s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
c3d2689d
AZ		 502 omap_os_timer_reset(s);
503 omap_timer_clk_setup(&s->timer);
504
4b3fedf3
AK		 505 memory_region_init_io(&s->iomem, &omap_os_timer_ops, s,
506 "omap-os-timer", 0x800);
507 memory_region_add_subregion(memory, base, &s->iomem);
c3d2689d
AZ		 508
509 return s;
510}
511
512/* Ultra Low-Power Device Module */
4b3fedf3
AK		 513static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
514 unsigned size)
c3d2689d
AZ		 515{
516 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 517 uint16_t ret;
518
4b3fedf3
AK		 519 if (size != 2) {
520 return omap_badwidth_read16(opaque, addr);
521 }
522
8da3ff18 523 switch (addr) {
c3d2689d 524 case 0x14: /* IT_STATUS */
8da3ff18
PB		 525 ret = s->ulpd_pm_regs[addr >> 2];
526 s->ulpd_pm_regs[addr >> 2] = 0;
0919ac78 527 qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
c3d2689d
AZ		 528 return ret;
529
530 case 0x18: /* Reserved */
531 case 0x1c: /* Reserved */
532 case 0x20: /* Reserved */
533 case 0x28: /* Reserved */
534 case 0x2c: /* Reserved */
535 OMAP_BAD_REG(addr);
536 case 0x00: /* COUNTER_32_LSB */
537 case 0x04: /* COUNTER_32_MSB */
538 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
539 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
540 case 0x10: /* GAUGING_CTRL */
541 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
542 case 0x30: /* CLOCK_CTRL */
543 case 0x34: /* SOFT_REQ */
544 case 0x38: /* COUNTER_32_FIQ */
545 case 0x3c: /* DPLL_CTRL */
546 case 0x40: /* STATUS_REQ */
547 /* XXX: check clk::usecount state for every clock */
548 case 0x48: /* LOCL_TIME */
549 case 0x4c: /* APLL_CTRL */
550 case 0x50: /* POWER_CTRL */
8da3ff18 551 return s->ulpd_pm_regs[addr >> 2];
c3d2689d
AZ		 552 }
553
554 OMAP_BAD_REG(addr);
555 return 0;
556}
557
558static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
559 uint16_t diff, uint16_t value)
560{
561 if (diff & (1 << 4)) /* USB_MCLK_EN */
562 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
563 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
564 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
565}
566
567static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
568 uint16_t diff, uint16_t value)
569{
570 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
571 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
572 if (diff & (1 << 1)) /* SOFT_COM_REQ */
573 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
574 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
575 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
576 if (diff & (1 << 3)) /* SOFT_USB_REQ */
577 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
578}
579
c227f099 580static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 581 uint64_t value, unsigned size)
c3d2689d
AZ		 582{
583 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 584 int64_t now, ticks;
585 int div, mult;
586 static const int bypass_div[4] = { 1, 2, 4, 4 };
587 uint16_t diff;
588
4b3fedf3
AK		 589 if (size != 2) {
590 return omap_badwidth_write16(opaque, addr, value);
591 }
592
8da3ff18 593 switch (addr) {
c3d2689d
AZ		 594 case 0x00: /* COUNTER_32_LSB */
595 case 0x04: /* COUNTER_32_MSB */
596 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
597 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
598 case 0x14: /* IT_STATUS */
599 case 0x40: /* STATUS_REQ */
600 OMAP_RO_REG(addr);
601 break;
602
603 case 0x10: /* GAUGING_CTRL */
604 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
8da3ff18 605 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
74475455 606 now = qemu_get_clock_ns(vm_clock);
c3d2689d
AZ		 607
608 if (value & 1)
609 s->ulpd_gauge_start = now;
610 else {
611 now -= s->ulpd_gauge_start;
612
613 /* 32-kHz ticks */
6ee093c9 614 ticks = muldiv64(now, 32768, get_ticks_per_sec());
c3d2689d
AZ		 615 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
616 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
617 if (ticks >> 32) /* OVERFLOW_32K */
618 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
619
620 /* High frequency ticks */
6ee093c9 621 ticks = muldiv64(now, 12000000, get_ticks_per_sec());
c3d2689d
AZ		 622 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
623 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
624 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
625 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
626
627 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
0919ac78 628 qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
c3d2689d
AZ		 629 }
630 }
8da3ff18 631 s->ulpd_pm_regs[addr >> 2] = value;
c3d2689d
AZ		 632 break;
633
634 case 0x18: /* Reserved */
635 case 0x1c: /* Reserved */
636 case 0x20: /* Reserved */
637 case 0x28: /* Reserved */
638 case 0x2c: /* Reserved */
639 OMAP_BAD_REG(addr);
640 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
641 case 0x38: /* COUNTER_32_FIQ */
642 case 0x48: /* LOCL_TIME */
643 case 0x50: /* POWER_CTRL */
8da3ff18 644 s->ulpd_pm_regs[addr >> 2] = value;
c3d2689d
AZ		 645 break;
646
647 case 0x30: /* CLOCK_CTRL */
8da3ff18
PB		 648 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
649 s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
c3d2689d
AZ		 650 omap_ulpd_clk_update(s, diff, value);
651 break;
652
653 case 0x34: /* SOFT_REQ */
8da3ff18
PB		 654 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
655 s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
c3d2689d
AZ		 656 omap_ulpd_req_update(s, diff, value);
657 break;
658
659 case 0x3c: /* DPLL_CTRL */
660 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
661 * omitted altogether, probably a typo. */
662 /* This register has identical semantics with DPLL(1:3) control
663 * registers, see omap_dpll_write() */
8da3ff18
PB		 664 diff = s->ulpd_pm_regs[addr >> 2] & value;
665 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
c3d2689d
AZ		 666 if (diff & (0x3ff << 2)) {
667 if (value & (1 << 4)) { /* PLL_ENABLE */
668 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
669 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
670 } else {
671 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
672 mult = 1;
673 }
674 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
675 }
676
677 /* Enter the desired mode. */
8da3ff18
PB		 678 s->ulpd_pm_regs[addr >> 2] =
679 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
680 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
c3d2689d
AZ		 681
682 /* Act as if the lock is restored. */
8da3ff18 683 s->ulpd_pm_regs[addr >> 2] |= 2;
c3d2689d
AZ		 684 break;
685
686 case 0x4c: /* APLL_CTRL */
8da3ff18
PB		 687 diff = s->ulpd_pm_regs[addr >> 2] & value;
688 s->ulpd_pm_regs[addr >> 2] = value & 0xf;
c3d2689d
AZ		 689 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
690 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
691 (value & (1 << 0)) ? "apll" : "dpll4"));
692 break;
693
694 default:
695 OMAP_BAD_REG(addr);
696 }
697}
698
4b3fedf3
AK		 699static const MemoryRegionOps omap_ulpd_pm_ops = {
700 .read = omap_ulpd_pm_read,
701 .write = omap_ulpd_pm_write,
702 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 703};
704
705static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
706{
707 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
708 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
709 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
710 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
711 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
712 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
713 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
714 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
715 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
716 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
717 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
718 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
719 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
720 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
721 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
722 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
723 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
724 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
725 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
726 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
727 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
728 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
729 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
730}
731
4b3fedf3
AK		 732static void omap_ulpd_pm_init(MemoryRegion *system_memory,
733 target_phys_addr_t base,
c3d2689d
AZ		 734 struct omap_mpu_state_s *mpu)
735{
4b3fedf3
AK		 736 memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
737 "omap-ulpd-pm", 0x800);
738 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
c3d2689d
AZ		 739 omap_ulpd_pm_reset(mpu);
740}
741
742/* OMAP Pin Configuration */
4b3fedf3
AK		 743static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr,
744 unsigned size)
c3d2689d
AZ		 745{
746 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 747
4b3fedf3
AK		 748 if (size != 4) {
749 return omap_badwidth_read32(opaque, addr);
750 }
751
8da3ff18 752 switch (addr) {
c3d2689d
AZ		 753 case 0x00: /* FUNC_MUX_CTRL_0 */
754 case 0x04: /* FUNC_MUX_CTRL_1 */
755 case 0x08: /* FUNC_MUX_CTRL_2 */
8da3ff18 756 return s->func_mux_ctrl[addr >> 2];
c3d2689d
AZ		 757
758 case 0x0c: /* COMP_MODE_CTRL_0 */
759 return s->comp_mode_ctrl[0];
760
761 case 0x10: /* FUNC_MUX_CTRL_3 */
762 case 0x14: /* FUNC_MUX_CTRL_4 */
763 case 0x18: /* FUNC_MUX_CTRL_5 */
764 case 0x1c: /* FUNC_MUX_CTRL_6 */
765 case 0x20: /* FUNC_MUX_CTRL_7 */
766 case 0x24: /* FUNC_MUX_CTRL_8 */
767 case 0x28: /* FUNC_MUX_CTRL_9 */
768 case 0x2c: /* FUNC_MUX_CTRL_A */
769 case 0x30: /* FUNC_MUX_CTRL_B */
770 case 0x34: /* FUNC_MUX_CTRL_C */
771 case 0x38: /* FUNC_MUX_CTRL_D */
8da3ff18 772 return s->func_mux_ctrl[(addr >> 2) - 1];
c3d2689d
AZ		 773
774 case 0x40: /* PULL_DWN_CTRL_0 */
775 case 0x44: /* PULL_DWN_CTRL_1 */
776 case 0x48: /* PULL_DWN_CTRL_2 */
777 case 0x4c: /* PULL_DWN_CTRL_3 */
8da3ff18 778 return s->pull_dwn_ctrl[(addr & 0xf) >> 2];
c3d2689d
AZ		 779
780 case 0x50: /* GATE_INH_CTRL_0 */
781 return s->gate_inh_ctrl[0];
782
783 case 0x60: /* VOLTAGE_CTRL_0 */
784 return s->voltage_ctrl[0];
785
786 case 0x70: /* TEST_DBG_CTRL_0 */
787 return s->test_dbg_ctrl[0];
788
789 case 0x80: /* MOD_CONF_CTRL_0 */
790 return s->mod_conf_ctrl[0];
791 }
792
793 OMAP_BAD_REG(addr);
794 return 0;
795}
796
797static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
798 uint32_t diff, uint32_t value)
799{
800 if (s->compat1509) {
801 if (diff & (1 << 9)) /* BLUETOOTH */
802 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
803 (~value >> 9) & 1);
804 if (diff & (1 << 7)) /* USB.CLKO */
805 omap_clk_onoff(omap_findclk(s, "usb.clko"),
806 (value >> 7) & 1);
807 }
808}
809
810static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
811 uint32_t diff, uint32_t value)
812{
813 if (s->compat1509) {
814 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
815 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
816 (value >> 31) & 1);
817 if (diff & (1 << 1)) /* CLK32K */
818 omap_clk_onoff(omap_findclk(s, "clk32k_out"),
819 (~value >> 1) & 1);
820 }
821}
822
823static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
824 uint32_t diff, uint32_t value)
825{
826 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
827 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
828 omap_findclk(s, ((value >> 31) & 1) ?
829 "ck_48m" : "armper_ck"));
830 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
831 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
832 omap_findclk(s, ((value >> 30) & 1) ?
833 "ck_48m" : "armper_ck"));
834 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
835 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
836 omap_findclk(s, ((value >> 29) & 1) ?
837 "ck_48m" : "armper_ck"));
838 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
839 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
840 omap_findclk(s, ((value >> 23) & 1) ?
841 "ck_48m" : "armper_ck"));
842 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
843 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
844 omap_findclk(s, ((value >> 12) & 1) ?
845 "ck_48m" : "armper_ck"));
846 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
847 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
848}
849
c227f099 850static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 851 uint64_t value, unsigned size)
c3d2689d
AZ		 852{
853 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 854 uint32_t diff;
855
4b3fedf3
AK		 856 if (size != 4) {
857 return omap_badwidth_write32(opaque, addr, value);
858 }
859
8da3ff18 860 switch (addr) {
c3d2689d 861 case 0x00: /* FUNC_MUX_CTRL_0 */
8da3ff18
PB		 862 diff = s->func_mux_ctrl[addr >> 2] ^ value;
863 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 864 omap_pin_funcmux0_update(s, diff, value);
865 return;
866
867 case 0x04: /* FUNC_MUX_CTRL_1 */
8da3ff18
PB		 868 diff = s->func_mux_ctrl[addr >> 2] ^ value;
869 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 870 omap_pin_funcmux1_update(s, diff, value);
871 return;
872
873 case 0x08: /* FUNC_MUX_CTRL_2 */
8da3ff18 874 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 875 return;
876
877 case 0x0c: /* COMP_MODE_CTRL_0 */
878 s->comp_mode_ctrl[0] = value;
879 s->compat1509 = (value != 0x0000eaef);
880 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
881 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
882 return;
883
884 case 0x10: /* FUNC_MUX_CTRL_3 */
885 case 0x14: /* FUNC_MUX_CTRL_4 */
886 case 0x18: /* FUNC_MUX_CTRL_5 */
887 case 0x1c: /* FUNC_MUX_CTRL_6 */
888 case 0x20: /* FUNC_MUX_CTRL_7 */
889 case 0x24: /* FUNC_MUX_CTRL_8 */
890 case 0x28: /* FUNC_MUX_CTRL_9 */
891 case 0x2c: /* FUNC_MUX_CTRL_A */
892 case 0x30: /* FUNC_MUX_CTRL_B */
893 case 0x34: /* FUNC_MUX_CTRL_C */
894 case 0x38: /* FUNC_MUX_CTRL_D */
8da3ff18 895 s->func_mux_ctrl[(addr >> 2) - 1] = value;
c3d2689d
AZ		 896 return;
897
898 case 0x40: /* PULL_DWN_CTRL_0 */
899 case 0x44: /* PULL_DWN_CTRL_1 */
900 case 0x48: /* PULL_DWN_CTRL_2 */
901 case 0x4c: /* PULL_DWN_CTRL_3 */
8da3ff18 902 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value;
c3d2689d
AZ		 903 return;
904
905 case 0x50: /* GATE_INH_CTRL_0 */
906 s->gate_inh_ctrl[0] = value;
907 return;
908
909 case 0x60: /* VOLTAGE_CTRL_0 */
910 s->voltage_ctrl[0] = value;
911 return;
912
913 case 0x70: /* TEST_DBG_CTRL_0 */
914 s->test_dbg_ctrl[0] = value;
915 return;
916
917 case 0x80: /* MOD_CONF_CTRL_0 */
918 diff = s->mod_conf_ctrl[0] ^ value;
919 s->mod_conf_ctrl[0] = value;
920 omap_pin_modconf1_update(s, diff, value);
921 return;
922
923 default:
924 OMAP_BAD_REG(addr);
925 }
926}
927
4b3fedf3
AK		 928static const MemoryRegionOps omap_pin_cfg_ops = {
929 .read = omap_pin_cfg_read,
930 .write = omap_pin_cfg_write,
931 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 932};
933
934static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
935{
936 /* Start in Compatibility Mode. */
937 mpu->compat1509 = 1;
938 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
939 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
940 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
941 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
942 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
943 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
944 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
945 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
946 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
947 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
948}
949
4b3fedf3
AK		 950static void omap_pin_cfg_init(MemoryRegion *system_memory,
951 target_phys_addr_t base,
c3d2689d
AZ		 952 struct omap_mpu_state_s *mpu)
953{
4b3fedf3
AK		 954 memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
955 "omap-pin-cfg", 0x800);
956 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
c3d2689d
AZ		 957 omap_pin_cfg_reset(mpu);
958}
959
960/* Device Identification, Die Identification */
4b3fedf3
AK		 961static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr,
962 unsigned size)
c3d2689d
AZ		 963{
964 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
965
4b3fedf3
AK		 966 if (size != 4) {
967 return omap_badwidth_read32(opaque, addr);
968 }
969
c3d2689d
AZ		 970 switch (addr) {
971 case 0xfffe1800: /* DIE_ID_LSB */
972 return 0xc9581f0e;
973 case 0xfffe1804: /* DIE_ID_MSB */
974 return 0xa8858bfa;
975
976 case 0xfffe2000: /* PRODUCT_ID_LSB */
977 return 0x00aaaafc;
978 case 0xfffe2004: /* PRODUCT_ID_MSB */
979 return 0xcafeb574;
980
981 case 0xfffed400: /* JTAG_ID_LSB */
982 switch (s->mpu_model) {
983 case omap310:
984 return 0x03310315;
985 case omap1510:
986 return 0x03310115;
827df9f3 987 default:
2ac71179 988 hw_error("%s: bad mpu model\n", __FUNCTION__);
c3d2689d
AZ		 989 }
990 break;
991
992 case 0xfffed404: /* JTAG_ID_MSB */
993 switch (s->mpu_model) {
994 case omap310:
995 return 0xfb57402f;
996 case omap1510:
997 return 0xfb47002f;
827df9f3 998 default:
2ac71179 999 hw_error("%s: bad mpu model\n", __FUNCTION__);
c3d2689d
AZ		 1000 }
1001 break;
1002 }
1003
1004 OMAP_BAD_REG(addr);
1005 return 0;
1006}
1007
c227f099 1008static void omap_id_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 1009 uint64_t value, unsigned size)
c3d2689d 1010{
4b3fedf3
AK		 1011 if (size != 4) {
1012 return omap_badwidth_write32(opaque, addr, value);
1013 }
1014
c3d2689d
AZ		 1015 OMAP_BAD_REG(addr);
1016}
1017
4b3fedf3
AK		 1018static const MemoryRegionOps omap_id_ops = {
1019 .read = omap_id_read,
1020 .write = omap_id_write,
1021 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1022};
1023
4b3fedf3 1024static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
c3d2689d 1025{
4b3fedf3
AK		 1026 memory_region_init_io(&mpu->id_iomem, &omap_id_ops, mpu,
1027 "omap-id", 0x100000000ULL);
1028 memory_region_init_alias(&mpu->id_iomem_e18, "omap-id-e18", &mpu->id_iomem,
1029 0xfffe1800, 0x800);
1030 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
1031 memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-ed4", &mpu->id_iomem,
1032 0xfffed400, 0x100);
1033 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
1034 if (!cpu_is_omap15xx(mpu)) {
1035 memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-e20",
1036 &mpu->id_iomem, 0xfffe2000, 0x800);
1037 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
1038 }
c3d2689d
AZ		 1039}
1040
1041/* MPUI Control (Dummy) */
4b3fedf3
AK		 1042static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr,
1043 unsigned size)
c3d2689d
AZ		 1044{
1045 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1046
4b3fedf3
AK		 1047 if (size != 4) {
1048 return omap_badwidth_read32(opaque, addr);
1049 }
1050
8da3ff18 1051 switch (addr) {
c3d2689d
AZ		 1052 case 0x00: /* CTRL */
1053 return s->mpui_ctrl;
1054 case 0x04: /* DEBUG_ADDR */
1055 return 0x01ffffff;
1056 case 0x08: /* DEBUG_DATA */
1057 return 0xffffffff;
1058 case 0x0c: /* DEBUG_FLAG */
1059 return 0x00000800;
1060 case 0x10: /* STATUS */
1061 return 0x00000000;
1062
1063 /* Not in OMAP310 */
1064 case 0x14: /* DSP_STATUS */
1065 case 0x18: /* DSP_BOOT_CONFIG */
1066 return 0x00000000;
1067 case 0x1c: /* DSP_MPUI_CONFIG */
1068 return 0x0000ffff;
1069 }
1070
1071 OMAP_BAD_REG(addr);
1072 return 0;
1073}
1074
c227f099 1075static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 1076 uint64_t value, unsigned size)
c3d2689d
AZ		 1077{
1078 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1079
4b3fedf3
AK		 1080 if (size != 4) {
1081 return omap_badwidth_write32(opaque, addr, value);
1082 }
1083
8da3ff18 1084 switch (addr) {
c3d2689d
AZ		 1085 case 0x00: /* CTRL */
1086 s->mpui_ctrl = value & 0x007fffff;
1087 break;
1088
1089 case 0x04: /* DEBUG_ADDR */
1090 case 0x08: /* DEBUG_DATA */
1091 case 0x0c: /* DEBUG_FLAG */
1092 case 0x10: /* STATUS */
1093 /* Not in OMAP310 */
1094 case 0x14: /* DSP_STATUS */
1095 OMAP_RO_REG(addr);
1096 case 0x18: /* DSP_BOOT_CONFIG */
1097 case 0x1c: /* DSP_MPUI_CONFIG */
1098 break;
1099
1100 default:
1101 OMAP_BAD_REG(addr);
1102 }
1103}
1104
4b3fedf3
AK		 1105static const MemoryRegionOps omap_mpui_ops = {
1106 .read = omap_mpui_read,
1107 .write = omap_mpui_write,
1108 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1109};
1110
1111static void omap_mpui_reset(struct omap_mpu_state_s *s)
1112{
1113 s->mpui_ctrl = 0x0003ff1b;
1114}
1115
4b3fedf3 1116static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base,
c3d2689d
AZ		 1117 struct omap_mpu_state_s *mpu)
1118{
4b3fedf3
AK		 1119 memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
1120 "omap-mpui", 0x100);
1121 memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
c3d2689d
AZ		 1122
1123 omap_mpui_reset(mpu);
1124}
1125
1126/* TIPB Bridges */
1127struct omap_tipb_bridge_s {
c3d2689d 1128 qemu_irq abort;
4b3fedf3 1129 MemoryRegion iomem;
c3d2689d
AZ		 1130
1131 int width_intr;
1132 uint16_t control;
1133 uint16_t alloc;
1134 uint16_t buffer;
1135 uint16_t enh_control;
1136};
1137
4b3fedf3
AK		 1138static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr,
1139 unsigned size)
c3d2689d
AZ		 1140{
1141 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
c3d2689d 1142
4b3fedf3
AK		 1143 if (size < 2) {
1144 return omap_badwidth_read16(opaque, addr);
1145 }
1146
8da3ff18 1147 switch (addr) {
c3d2689d
AZ		 1148 case 0x00: /* TIPB_CNTL */
1149 return s->control;
1150 case 0x04: /* TIPB_BUS_ALLOC */
1151 return s->alloc;
1152 case 0x08: /* MPU_TIPB_CNTL */
1153 return s->buffer;
1154 case 0x0c: /* ENHANCED_TIPB_CNTL */
1155 return s->enh_control;
1156 case 0x10: /* ADDRESS_DBG */
1157 case 0x14: /* DATA_DEBUG_LOW */
1158 case 0x18: /* DATA_DEBUG_HIGH */
1159 return 0xffff;
1160 case 0x1c: /* DEBUG_CNTR_SIG */
1161 return 0x00f8;
1162 }
1163
1164 OMAP_BAD_REG(addr);
1165 return 0;
1166}
1167
c227f099 1168static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 1169 uint64_t value, unsigned size)
c3d2689d
AZ		 1170{
1171 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
c3d2689d 1172
4b3fedf3
AK		 1173 if (size < 2) {
1174 return omap_badwidth_write16(opaque, addr, value);
1175 }
1176
8da3ff18 1177 switch (addr) {
c3d2689d
AZ		 1178 case 0x00: /* TIPB_CNTL */
1179 s->control = value & 0xffff;
1180 break;
1181
1182 case 0x04: /* TIPB_BUS_ALLOC */
1183 s->alloc = value & 0x003f;
1184 break;
1185
1186 case 0x08: /* MPU_TIPB_CNTL */
1187 s->buffer = value & 0x0003;
1188 break;
1189
1190 case 0x0c: /* ENHANCED_TIPB_CNTL */
1191 s->width_intr = !(value & 2);
1192 s->enh_control = value & 0x000f;
1193 break;
1194
1195 case 0x10: /* ADDRESS_DBG */
1196 case 0x14: /* DATA_DEBUG_LOW */
1197 case 0x18: /* DATA_DEBUG_HIGH */
1198 case 0x1c: /* DEBUG_CNTR_SIG */
1199 OMAP_RO_REG(addr);
1200 break;
1201
1202 default:
1203 OMAP_BAD_REG(addr);
1204 }
1205}
1206
4b3fedf3
AK		 1207static const MemoryRegionOps omap_tipb_bridge_ops = {
1208 .read = omap_tipb_bridge_read,
1209 .write = omap_tipb_bridge_write,
1210 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1211};
1212
1213static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1214{
1215 s->control = 0xffff;
1216 s->alloc = 0x0009;
1217 s->buffer = 0x0000;
1218 s->enh_control = 0x000f;
1219}
1220
4b3fedf3
AK		 1221static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
1222 MemoryRegion *memory, target_phys_addr_t base,
1223 qemu_irq abort_irq, omap_clk clk)
c3d2689d 1224{
c3d2689d 1225 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
7267c094 1226 g_malloc0(sizeof(struct omap_tipb_bridge_s));
c3d2689d
AZ		 1227
1228 s->abort = abort_irq;
c3d2689d
AZ		 1229 omap_tipb_bridge_reset(s);
1230
4b3fedf3
AK		 1231 memory_region_init_io(&s->iomem, &omap_tipb_bridge_ops, s,
1232 "omap-tipb-bridge", 0x100);
1233 memory_region_add_subregion(memory, base, &s->iomem);
c3d2689d
AZ		 1234
1235 return s;
1236}
1237
1238/* Dummy Traffic Controller's Memory Interface */
e7aa0ae0
AK		 1239static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr,
1240 unsigned size)
c3d2689d
AZ		 1241{
1242 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1243 uint32_t ret;
1244
e7aa0ae0
AK		 1245 if (size != 4) {
1246 return omap_badwidth_read32(opaque, addr);
1247 }
1248
8da3ff18 1249 switch (addr) {
d8f699cb
AZ		 1250 case 0x00: /* IMIF_PRIO */
1251 case 0x04: /* EMIFS_PRIO */
1252 case 0x08: /* EMIFF_PRIO */
1253 case 0x0c: /* EMIFS_CONFIG */
1254 case 0x10: /* EMIFS_CS0_CONFIG */
1255 case 0x14: /* EMIFS_CS1_CONFIG */
1256 case 0x18: /* EMIFS_CS2_CONFIG */
1257 case 0x1c: /* EMIFS_CS3_CONFIG */
1258 case 0x24: /* EMIFF_MRS */
1259 case 0x28: /* TIMEOUT1 */
1260 case 0x2c: /* TIMEOUT2 */
1261 case 0x30: /* TIMEOUT3 */
1262 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1263 case 0x40: /* EMIFS_CFG_DYN_WAIT */
8da3ff18 1264 return s->tcmi_regs[addr >> 2];
c3d2689d 1265
d8f699cb 1266 case 0x20: /* EMIFF_SDRAM_CONFIG */
8da3ff18
PB		 1267 ret = s->tcmi_regs[addr >> 2];
1268 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
c3d2689d
AZ		 1269 /* XXX: We can try using the VGA_DIRTY flag for this */
1270 return ret;
1271 }
1272
1273 OMAP_BAD_REG(addr);
1274 return 0;
1275}
1276
c227f099 1277static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
e7aa0ae0 1278 uint64_t value, unsigned size)
c3d2689d
AZ		 1279{
1280 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1281
e7aa0ae0
AK		 1282 if (size != 4) {
1283 return omap_badwidth_write32(opaque, addr, value);
1284 }
1285
8da3ff18 1286 switch (addr) {
d8f699cb
AZ		 1287 case 0x00: /* IMIF_PRIO */
1288 case 0x04: /* EMIFS_PRIO */
1289 case 0x08: /* EMIFF_PRIO */
1290 case 0x10: /* EMIFS_CS0_CONFIG */
1291 case 0x14: /* EMIFS_CS1_CONFIG */
1292 case 0x18: /* EMIFS_CS2_CONFIG */
1293 case 0x1c: /* EMIFS_CS3_CONFIG */
1294 case 0x20: /* EMIFF_SDRAM_CONFIG */
1295 case 0x24: /* EMIFF_MRS */
1296 case 0x28: /* TIMEOUT1 */
1297 case 0x2c: /* TIMEOUT2 */
1298 case 0x30: /* TIMEOUT3 */
1299 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1300 case 0x40: /* EMIFS_CFG_DYN_WAIT */
8da3ff18 1301 s->tcmi_regs[addr >> 2] = value;
c3d2689d 1302 break;
d8f699cb 1303 case 0x0c: /* EMIFS_CONFIG */
8da3ff18 1304 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4);
c3d2689d
AZ		 1305 break;
1306
1307 default:
1308 OMAP_BAD_REG(addr);
1309 }
1310}
1311
e7aa0ae0
AK		 1312static const MemoryRegionOps omap_tcmi_ops = {
1313 .read = omap_tcmi_read,
1314 .write = omap_tcmi_write,
1315 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1316};
1317
1318static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1319{
1320 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1321 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1322 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1323 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1324 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1325 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1326 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1327 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1328 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1329 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1330 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1331 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1332 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1333 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1334 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1335}
1336
e7aa0ae0 1337static void omap_tcmi_init(MemoryRegion *memory, target_phys_addr_t base,
c3d2689d
AZ		 1338 struct omap_mpu_state_s *mpu)
1339{
e7aa0ae0
AK		 1340 memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
1341 "omap-tcmi", 0x100);
1342 memory_region_add_subregion(memory, base, &mpu->tcmi_iomem);
c3d2689d
AZ		 1343 omap_tcmi_reset(mpu);
1344}
1345
1346/* Digital phase-locked loops control */
e7aa0ae0
AK		 1347static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr,
1348 unsigned size)
c3d2689d
AZ		 1349{
1350 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
c3d2689d 1351
e7aa0ae0
AK		 1352 if (size != 2) {
1353 return omap_badwidth_read16(opaque, addr);
1354 }
1355
8da3ff18 1356 if (addr == 0x00) /* CTL_REG */
c3d2689d
AZ		 1357 return s->mode;
1358
1359 OMAP_BAD_REG(addr);
1360 return 0;
1361}
1362
c227f099 1363static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
e7aa0ae0 1364 uint64_t value, unsigned size)
c3d2689d
AZ		 1365{
1366 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1367 uint16_t diff;
c3d2689d
AZ		 1368 static const int bypass_div[4] = { 1, 2, 4, 4 };
1369 int div, mult;
1370
e7aa0ae0
AK		 1371 if (size != 2) {
1372 return omap_badwidth_write16(opaque, addr, value);
1373 }
1374
8da3ff18 1375 if (addr == 0x00) { /* CTL_REG */
c3d2689d
AZ		 1376 /* See omap_ulpd_pm_write() too */
1377 diff = s->mode & value;
1378 s->mode = value & 0x2fff;
1379 if (diff & (0x3ff << 2)) {
1380 if (value & (1 << 4)) { /* PLL_ENABLE */
1381 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1382 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1383 } else {
1384 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1385 mult = 1;
1386 }
1387 omap_clk_setrate(s->dpll, div, mult);
1388 }
1389
1390 /* Enter the desired mode. */
1391 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1392
1393 /* Act as if the lock is restored. */
1394 s->mode |= 2;
1395 } else {
1396 OMAP_BAD_REG(addr);
1397 }
1398}
1399
e7aa0ae0
AK		 1400static const MemoryRegionOps omap_dpll_ops = {
1401 .read = omap_dpll_read,
1402 .write = omap_dpll_write,
1403 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1404};
1405
1406static void omap_dpll_reset(struct dpll_ctl_s *s)
1407{
1408 s->mode = 0x2002;
1409 omap_clk_setrate(s->dpll, 1, 1);
1410}
1411
e7aa0ae0
AK		 1412static void omap_dpll_init(MemoryRegion *memory, struct dpll_ctl_s *s,
1413 target_phys_addr_t base, omap_clk clk)
c3d2689d 1414{
e7aa0ae0 1415 memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
c3d2689d 1416
c3d2689d
AZ		 1417 s->dpll = clk;
1418 omap_dpll_reset(s);
1419
e7aa0ae0 1420 memory_region_add_subregion(memory, base, &s->iomem);
c3d2689d
AZ		 1421}
1422
c3d2689d 1423/* MPU Clock/Reset/Power Mode Control */
e7aa0ae0
AK		 1424static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr,
1425 unsigned size)
c3d2689d
AZ		 1426{
1427 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1428
e7aa0ae0
AK		 1429 if (size != 2) {
1430 return omap_badwidth_read16(opaque, addr);
1431 }
1432
8da3ff18 1433 switch (addr) {
c3d2689d
AZ		 1434 case 0x00: /* ARM_CKCTL */
1435 return s->clkm.arm_ckctl;
1436
1437 case 0x04: /* ARM_IDLECT1 */
1438 return s->clkm.arm_idlect1;
1439
1440 case 0x08: /* ARM_IDLECT2 */
1441 return s->clkm.arm_idlect2;
1442
1443 case 0x0c: /* ARM_EWUPCT */
1444 return s->clkm.arm_ewupct;
1445
1446 case 0x10: /* ARM_RSTCT1 */
1447 return s->clkm.arm_rstct1;
1448
1449 case 0x14: /* ARM_RSTCT2 */
1450 return s->clkm.arm_rstct2;
1451
1452 case 0x18: /* ARM_SYSST */
d8f699cb 1453 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
c3d2689d
AZ		 1454
1455 case 0x1c: /* ARM_CKOUT1 */
1456 return s->clkm.arm_ckout1;
1457
1458 case 0x20: /* ARM_CKOUT2 */
1459 break;
1460 }
1461
1462 OMAP_BAD_REG(addr);
1463 return 0;
1464}
1465
1466static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
1467 uint16_t diff, uint16_t value)
1468{
1469 omap_clk clk;
1470
1471 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
1472 if (value & (1 << 14))
1473 /* Reserved */;
1474 else {
1475 clk = omap_findclk(s, "arminth_ck");
1476 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1477 }
1478 }
1479 if (diff & (1 << 12)) { /* ARM_TIMXO */
1480 clk = omap_findclk(s, "armtim_ck");
1481 if (value & (1 << 12))
1482 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
1483 else
1484 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1485 }
1486 /* XXX: en_dspck */
1487 if (diff & (3 << 10)) { /* DSPMMUDIV */
1488 clk = omap_findclk(s, "dspmmu_ck");
1489 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
1490 }
1491 if (diff & (3 << 8)) { /* TCDIV */
1492 clk = omap_findclk(s, "tc_ck");
1493 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
1494 }
1495 if (diff & (3 << 6)) { /* DSPDIV */
1496 clk = omap_findclk(s, "dsp_ck");
1497 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
1498 }
1499 if (diff & (3 << 4)) { /* ARMDIV */
1500 clk = omap_findclk(s, "arm_ck");
1501 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
1502 }
1503 if (diff & (3 << 2)) { /* LCDDIV */
1504 clk = omap_findclk(s, "lcd_ck");
1505 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
1506 }
1507 if (diff & (3 << 0)) { /* PERDIV */
1508 clk = omap_findclk(s, "armper_ck");
1509 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
1510 }
1511}
1512
1513static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
1514 uint16_t diff, uint16_t value)
1515{
1516 omap_clk clk;
1517
1518 if (value & (1 << 11)) /* SETARM_IDLE */
1519 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
1520 if (!(value & (1 << 10))) /* WKUP_MODE */
1521 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
1522
1523#define SET_CANIDLE(clock, bit) \
1524 if (diff & (1 << bit)) { \
1525 clk = omap_findclk(s, clock); \
1526 omap_clk_canidle(clk, (value >> bit) & 1); \
1527 }
1528 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
1529 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
1530 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
1531 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
1532 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
1533 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
1534 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
1535 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
1536 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
1537 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
1538 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
1539 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
1540 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
1541 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
1542}
1543
1544static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
1545 uint16_t diff, uint16_t value)
1546{
1547 omap_clk clk;
1548
1549#define SET_ONOFF(clock, bit) \
1550 if (diff & (1 << bit)) { \
1551 clk = omap_findclk(s, clock); \
1552 omap_clk_onoff(clk, (value >> bit) & 1); \
1553 }
1554 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
1555 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
1556 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
1557 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
1558 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
1559 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
1560 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
1561 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
1562 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
1563 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
1564 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
1565}
1566
1567static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
1568 uint16_t diff, uint16_t value)
1569{
1570 omap_clk clk;
1571
1572 if (diff & (3 << 4)) { /* TCLKOUT */
1573 clk = omap_findclk(s, "tclk_out");
1574 switch ((value >> 4) & 3) {
1575 case 1:
1576 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
1577 omap_clk_onoff(clk, 1);
1578 break;
1579 case 2:
1580 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1581 omap_clk_onoff(clk, 1);
1582 break;
1583 default:
1584 omap_clk_onoff(clk, 0);
1585 }
1586 }
1587 if (diff & (3 << 2)) { /* DCLKOUT */
1588 clk = omap_findclk(s, "dclk_out");
1589 switch ((value >> 2) & 3) {
1590 case 0:
1591 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
1592 break;
1593 case 1:
1594 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
1595 break;
1596 case 2:
1597 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
1598 break;
1599 case 3:
1600 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1601 break;
1602 }
1603 }
1604 if (diff & (3 << 0)) { /* ACLKOUT */
1605 clk = omap_findclk(s, "aclk_out");
1606 switch ((value >> 0) & 3) {
1607 case 1:
1608 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1609 omap_clk_onoff(clk, 1);
1610 break;
1611 case 2:
1612 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
1613 omap_clk_onoff(clk, 1);
1614 break;
1615 case 3:
1616 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1617 omap_clk_onoff(clk, 1);
1618 break;
1619 default:
1620 omap_clk_onoff(clk, 0);
1621 }
1622 }
1623}
1624
c227f099 1625static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
e7aa0ae0 1626 uint64_t value, unsigned size)
c3d2689d
AZ		 1627{
1628 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1629 uint16_t diff;
1630 omap_clk clk;
1631 static const char *clkschemename[8] = {
1632 "fully synchronous", "fully asynchronous", "synchronous scalable",
1633 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
1634 };
1635
e7aa0ae0
AK		 1636 if (size != 2) {
1637 return omap_badwidth_write16(opaque, addr, value);
1638 }
1639
8da3ff18 1640 switch (addr) {
c3d2689d
AZ		 1641 case 0x00: /* ARM_CKCTL */
1642 diff = s->clkm.arm_ckctl ^ value;
1643 s->clkm.arm_ckctl = value & 0x7fff;
1644 omap_clkm_ckctl_update(s, diff, value);
1645 return;
1646
1647 case 0x04: /* ARM_IDLECT1 */
1648 diff = s->clkm.arm_idlect1 ^ value;
1649 s->clkm.arm_idlect1 = value & 0x0fff;
1650 omap_clkm_idlect1_update(s, diff, value);
1651 return;
1652
1653 case 0x08: /* ARM_IDLECT2 */
1654 diff = s->clkm.arm_idlect2 ^ value;
1655 s->clkm.arm_idlect2 = value & 0x07ff;
1656 omap_clkm_idlect2_update(s, diff, value);
1657 return;
1658
1659 case 0x0c: /* ARM_EWUPCT */
c3d2689d
AZ		 1660 s->clkm.arm_ewupct = value & 0x003f;
1661 return;
1662
1663 case 0x10: /* ARM_RSTCT1 */
1664 diff = s->clkm.arm_rstct1 ^ value;
1665 s->clkm.arm_rstct1 = value & 0x0007;
1666 if (value & 9) {
1667 qemu_system_reset_request();
1668 s->clkm.cold_start = 0xa;
1669 }
1670 if (diff & ~value & 4) { /* DSP_RST */
1671 omap_mpui_reset(s);
1672 omap_tipb_bridge_reset(s->private_tipb);
1673 omap_tipb_bridge_reset(s->public_tipb);
1674 }
1675 if (diff & 2) { /* DSP_EN */
1676 clk = omap_findclk(s, "dsp_ck");
1677 omap_clk_canidle(clk, (~value >> 1) & 1);
1678 }
1679 return;
1680
1681 case 0x14: /* ARM_RSTCT2 */
1682 s->clkm.arm_rstct2 = value & 0x0001;
1683 return;
1684
1685 case 0x18: /* ARM_SYSST */
1686 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
1687 s->clkm.clocking_scheme = (value >> 11) & 7;
1688 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
1689 clkschemename[s->clkm.clocking_scheme]);
1690 }
1691 s->clkm.cold_start &= value & 0x3f;
1692 return;
1693
1694 case 0x1c: /* ARM_CKOUT1 */
1695 diff = s->clkm.arm_ckout1 ^ value;
1696 s->clkm.arm_ckout1 = value & 0x003f;
1697 omap_clkm_ckout1_update(s, diff, value);
1698 return;
1699
1700 case 0x20: /* ARM_CKOUT2 */
1701 default:
1702 OMAP_BAD_REG(addr);
1703 }
1704}
1705
e7aa0ae0
AK		 1706static const MemoryRegionOps omap_clkm_ops = {
1707 .read = omap_clkm_read,
1708 .write = omap_clkm_write,
1709 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1710};
1711
e7aa0ae0
AK		 1712static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr,
1713 unsigned size)
c3d2689d
AZ		 1714{
1715 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1716
e7aa0ae0
AK		 1717 if (size != 2) {
1718 return omap_badwidth_read16(opaque, addr);
1719 }
1720
8da3ff18 1721 switch (addr) {
c3d2689d
AZ		 1722 case 0x04: /* DSP_IDLECT1 */
1723 return s->clkm.dsp_idlect1;
1724
1725 case 0x08: /* DSP_IDLECT2 */
1726 return s->clkm.dsp_idlect2;
1727
1728 case 0x14: /* DSP_RSTCT2 */
1729 return s->clkm.dsp_rstct2;
1730
1731 case 0x18: /* DSP_SYSST */
d8f699cb 1732 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
c3d2689d
AZ		 1733 (s->env->halted << 6); /* Quite useless... */
1734 }
1735
1736 OMAP_BAD_REG(addr);
1737 return 0;
1738}
1739
1740static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
1741 uint16_t diff, uint16_t value)
1742{
1743 omap_clk clk;
1744
1745 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
1746}
1747
1748static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
1749 uint16_t diff, uint16_t value)
1750{
1751 omap_clk clk;
1752
1753 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
1754}
1755
c227f099 1756static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
e7aa0ae0 1757 uint64_t value, unsigned size)
c3d2689d
AZ		 1758{
1759 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1760 uint16_t diff;
1761
e7aa0ae0
AK		 1762 if (size != 2) {
1763 return omap_badwidth_write16(opaque, addr, value);
1764 }
1765
8da3ff18 1766 switch (addr) {
c3d2689d
AZ		 1767 case 0x04: /* DSP_IDLECT1 */
1768 diff = s->clkm.dsp_idlect1 ^ value;
1769 s->clkm.dsp_idlect1 = value & 0x01f7;
1770 omap_clkdsp_idlect1_update(s, diff, value);
1771 break;
1772
1773 case 0x08: /* DSP_IDLECT2 */
1774 s->clkm.dsp_idlect2 = value & 0x0037;
1775 diff = s->clkm.dsp_idlect1 ^ value;
1776 omap_clkdsp_idlect2_update(s, diff, value);
1777 break;
1778
1779 case 0x14: /* DSP_RSTCT2 */
1780 s->clkm.dsp_rstct2 = value & 0x0001;
1781 break;
1782
1783 case 0x18: /* DSP_SYSST */
1784 s->clkm.cold_start &= value & 0x3f;
1785 break;
1786
1787 default:
1788 OMAP_BAD_REG(addr);
1789 }
1790}
1791
e7aa0ae0
AK		 1792static const MemoryRegionOps omap_clkdsp_ops = {
1793 .read = omap_clkdsp_read,
1794 .write = omap_clkdsp_write,
1795 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1796};
1797
1798static void omap_clkm_reset(struct omap_mpu_state_s *s)
1799{
1800 if (s->wdt && s->wdt->reset)
1801 s->clkm.cold_start = 0x6;
1802 s->clkm.clocking_scheme = 0;
1803 omap_clkm_ckctl_update(s, ~0, 0x3000);
1804 s->clkm.arm_ckctl = 0x3000;
d8f699cb 1805 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
c3d2689d 1806 s->clkm.arm_idlect1 = 0x0400;
d8f699cb 1807 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
c3d2689d
AZ		 1808 s->clkm.arm_idlect2 = 0x0100;
1809 s->clkm.arm_ewupct = 0x003f;
1810 s->clkm.arm_rstct1 = 0x0000;
1811 s->clkm.arm_rstct2 = 0x0000;
1812 s->clkm.arm_ckout1 = 0x0015;
1813 s->clkm.dpll1_mode = 0x2002;
1814 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
1815 s->clkm.dsp_idlect1 = 0x0040;
1816 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
1817 s->clkm.dsp_idlect2 = 0x0000;
1818 s->clkm.dsp_rstct2 = 0x0000;
1819}
1820
e7aa0ae0 1821static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base,
c227f099 1822 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
c3d2689d 1823{
e7aa0ae0
AK		 1824 memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
1825 "omap-clkm", 0x100);
1826 memory_region_init_io(&s->clkdsp_iomem, &omap_clkdsp_ops, s,
1827 "omap-clkdsp", 0x1000);
c3d2689d 1828
d8f699cb
AZ		 1829 s->clkm.arm_idlect1 = 0x03ff;
1830 s->clkm.arm_idlect2 = 0x0100;
1831 s->clkm.dsp_idlect1 = 0x0002;
c3d2689d 1832 omap_clkm_reset(s);
d8f699cb 1833 s->clkm.cold_start = 0x3a;
c3d2689d 1834
e7aa0ae0
AK		 1835 memory_region_add_subregion(memory, mpu_base, &s->clkm_iomem);
1836 memory_region_add_subregion(memory, dsp_base, &s->clkdsp_iomem);
c3d2689d
AZ		 1837}
1838
fe71e81a
AZ		 1839/* MPU I/O */
1840struct omap_mpuio_s {
fe71e81a
AZ		 1841 qemu_irq irq;
1842 qemu_irq kbd_irq;
1843 qemu_irq *in;
1844 qemu_irq handler[16];
1845 qemu_irq wakeup;
e7aa0ae0 1846 MemoryRegion iomem;
fe71e81a
AZ		 1847
1848 uint16_t inputs;
1849 uint16_t outputs;
1850 uint16_t dir;
1851 uint16_t edge;
1852 uint16_t mask;
1853 uint16_t ints;
1854
1855 uint16_t debounce;
1856 uint16_t latch;
1857 uint8_t event;
1858
1859 uint8_t buttons[5];
1860 uint8_t row_latch;
1861 uint8_t cols;
1862 int kbd_mask;
1863 int clk;
1864};
1865
1866static void omap_mpuio_set(void *opaque, int line, int level)
1867{
1868 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
1869 uint16_t prev = s->inputs;
1870
1871 if (level)
1872 s->inputs |= 1 << line;
1873 else
1874 s->inputs &= ~(1 << line);
1875
1876 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
1877 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
1878 s->ints |= 1 << line;
1879 qemu_irq_raise(s->irq);
1880 /* TODO: wakeup */
1881 }
1882 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
1883 (s->event >> 1) == line) /* PIN_SELECT */
1884 s->latch = s->inputs;
1885 }
1886}
1887
1888static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
1889{
1890 int i;
1891 uint8_t *row, rows = 0, cols = ~s->cols;
1892
38a34e1d 1893 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
fe71e81a 1894 if (*row & cols)
38a34e1d 1895 rows |= i;
fe71e81a 1896
cf6d9118
AZ		 1897 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
1898 s->row_latch = ~rows;
fe71e81a
AZ		 1899}
1900
e7aa0ae0
AK		 1901static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr,
1902 unsigned size)
fe71e81a
AZ		 1903{
1904 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
cf965d24 1905 int offset = addr & OMAP_MPUI_REG_MASK;
fe71e81a
AZ		 1906 uint16_t ret;
1907
e7aa0ae0
AK		 1908 if (size != 2) {
1909 return omap_badwidth_read16(opaque, addr);
1910 }
1911
fe71e81a
AZ		 1912 switch (offset) {
1913 case 0x00: /* INPUT_LATCH */
1914 return s->inputs;
1915
1916 case 0x04: /* OUTPUT_REG */
1917 return s->outputs;
1918
1919 case 0x08: /* IO_CNTL */
1920 return s->dir;
1921
1922 case 0x10: /* KBR_LATCH */
1923 return s->row_latch;
1924
1925 case 0x14: /* KBC_REG */
1926 return s->cols;
1927
1928 case 0x18: /* GPIO_EVENT_MODE_REG */
1929 return s->event;
1930
1931 case 0x1c: /* GPIO_INT_EDGE_REG */
1932 return s->edge;
1933
1934 case 0x20: /* KBD_INT */
cf6d9118 1935 return (~s->row_latch & 0x1f) && !s->kbd_mask;
fe71e81a
AZ		 1936
1937 case 0x24: /* GPIO_INT */
1938 ret = s->ints;
8e129e07
AZ		 1939 s->ints &= s->mask;
1940 if (ret)
1941 qemu_irq_lower(s->irq);
fe71e81a
AZ		 1942 return ret;
1943
1944 case 0x28: /* KBD_MASKIT */
1945 return s->kbd_mask;
1946
1947 case 0x2c: /* GPIO_MASKIT */
1948 return s->mask;
1949
1950 case 0x30: /* GPIO_DEBOUNCING_REG */
1951 return s->debounce;
1952
1953 case 0x34: /* GPIO_LATCH_REG */
1954 return s->latch;
1955 }
1956
1957 OMAP_BAD_REG(addr);
1958 return 0;
1959}
1960
c227f099 1961static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
e7aa0ae0 1962 uint64_t value, unsigned size)
fe71e81a
AZ		 1963{
1964 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
cf965d24 1965 int offset = addr & OMAP_MPUI_REG_MASK;
fe71e81a
AZ		 1966 uint16_t diff;
1967 int ln;
1968
e7aa0ae0
AK		 1969 if (size != 2) {
1970 return omap_badwidth_write16(opaque, addr, value);
1971 }
1972
fe71e81a
AZ		 1973 switch (offset) {
1974 case 0x04: /* OUTPUT_REG */
d8f699cb 1975 diff = (s->outputs ^ value) & ~s->dir;
fe71e81a 1976 s->outputs = value;
fe71e81a
AZ		 1977 while ((ln = ffs(diff))) {
1978 ln --;
1979 if (s->handler[ln])
1980 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
1981 diff &= ~(1 << ln);
1982 }
1983 break;
1984
1985 case 0x08: /* IO_CNTL */
1986 diff = s->outputs & (s->dir ^ value);
1987 s->dir = value;
1988
1989 value = s->outputs & ~s->dir;
1990 while ((ln = ffs(diff))) {
1991 ln --;
1992 if (s->handler[ln])
1993 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
1994 diff &= ~(1 << ln);
1995 }
1996 break;
1997
1998 case 0x14: /* KBC_REG */
1999 s->cols = value;
2000 omap_mpuio_kbd_update(s);
2001 break;
2002
2003 case 0x18: /* GPIO_EVENT_MODE_REG */
2004 s->event = value & 0x1f;
2005 break;
2006
2007 case 0x1c: /* GPIO_INT_EDGE_REG */
2008 s->edge = value;
2009 break;
2010
2011 case 0x28: /* KBD_MASKIT */
2012 s->kbd_mask = value & 1;
2013 omap_mpuio_kbd_update(s);
2014 break;
2015
2016 case 0x2c: /* GPIO_MASKIT */
2017 s->mask = value;
2018 break;
2019
2020 case 0x30: /* GPIO_DEBOUNCING_REG */
2021 s->debounce = value & 0x1ff;
2022 break;
2023
2024 case 0x00: /* INPUT_LATCH */
2025 case 0x10: /* KBR_LATCH */
2026 case 0x20: /* KBD_INT */
2027 case 0x24: /* GPIO_INT */
2028 case 0x34: /* GPIO_LATCH_REG */
2029 OMAP_RO_REG(addr);
2030 return;
2031
2032 default:
2033 OMAP_BAD_REG(addr);
2034 return;
2035 }
2036}
2037
e7aa0ae0
AK		 2038static const MemoryRegionOps omap_mpuio_ops = {
2039 .read = omap_mpuio_read,
2040 .write = omap_mpuio_write,
2041 .endianness = DEVICE_NATIVE_ENDIAN,
fe71e81a
AZ		 2042};
2043
9596ebb7 2044static void omap_mpuio_reset(struct omap_mpuio_s *s)
fe71e81a
AZ		 2045{
2046 s->inputs = 0;
2047 s->outputs = 0;
2048 s->dir = ~0;
2049 s->event = 0;
2050 s->edge = 0;
2051 s->kbd_mask = 0;
2052 s->mask = 0;
2053 s->debounce = 0;
2054 s->latch = 0;
2055 s->ints = 0;
2056 s->row_latch = 0x1f;
38a34e1d 2057 s->clk = 1;
fe71e81a
AZ		 2058}
2059
2060static void omap_mpuio_onoff(void *opaque, int line, int on)
2061{
2062 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2063
2064 s->clk = on;
2065 if (on)
2066 omap_mpuio_kbd_update(s);
2067}
2068
3b204c81 2069static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
e7aa0ae0 2070 target_phys_addr_t base,
fe71e81a
AZ		 2071 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2072 omap_clk clk)
2073{
fe71e81a 2074 struct omap_mpuio_s *s = (struct omap_mpuio_s *)
7267c094 2075 g_malloc0(sizeof(struct omap_mpuio_s));
fe71e81a 2076
fe71e81a
AZ		 2077 s->irq = gpio_int;
2078 s->kbd_irq = kbd_int;
2079 s->wakeup = wakeup;
2080 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2081 omap_mpuio_reset(s);
2082
e7aa0ae0
AK		 2083 memory_region_init_io(&s->iomem, &omap_mpuio_ops, s,
2084 "omap-mpuio", 0x800);
2085 memory_region_add_subregion(memory, base, &s->iomem);
fe71e81a
AZ		 2086
2087 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
2088
2089 return s;
2090}
2091
2092qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2093{
2094 return s->in;
2095}
2096
2097void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2098{
2099 if (line >= 16 || line < 0)
2ac71179 2100 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
fe71e81a
AZ		 2101 s->handler[line] = handler;
2102}
2103
2104void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2105{
2106 if (row >= 5 || row < 0)
2ac71179 2107 hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
fe71e81a
AZ		 2108
2109 if (down)
38a34e1d 2110 s->buttons[row] |= 1 << col;
fe71e81a 2111 else
38a34e1d 2112 s->buttons[row] &= ~(1 << col);
fe71e81a
AZ		 2113
2114 omap_mpuio_kbd_update(s);
2115}
2116
d951f6ff
AZ		 2117/* MicroWire Interface */
2118struct omap_uwire_s {
a4ebbd18 2119 MemoryRegion iomem;
d951f6ff
AZ		 2120 qemu_irq txirq;
2121 qemu_irq rxirq;
2122 qemu_irq txdrq;
2123
2124 uint16_t txbuf;
2125 uint16_t rxbuf;
2126 uint16_t control;
2127 uint16_t setup[5];
2128
bc24a225 2129 uWireSlave *chip[4];
d951f6ff
AZ		 2130};
2131
2132static void omap_uwire_transfer_start(struct omap_uwire_s *s)
2133{
2134 int chipselect = (s->control >> 10) & 3; /* INDEX */
bc24a225 2135 uWireSlave *slave = s->chip[chipselect];
d951f6ff
AZ		 2136
2137 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
2138 if (s->control & (1 << 12)) /* CS_CMD */
2139 if (slave && slave->send)
2140 slave->send(slave->opaque,
2141 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
2142 s->control &= ~(1 << 14); /* CSRB */
2143 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2144 * a DRQ. When is the level IRQ supposed to be reset? */
2145 }
2146
2147 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
2148 if (s->control & (1 << 12)) /* CS_CMD */
2149 if (slave && slave->receive)
2150 s->rxbuf = slave->receive(slave->opaque);
2151 s->control |= 1 << 15; /* RDRB */
2152 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2153 * a DRQ. When is the level IRQ supposed to be reset? */
2154 }
2155}
2156
a4ebbd18
AK		 2157static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr,
2158 unsigned size)
d951f6ff
AZ		 2159{
2160 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
cf965d24 2161 int offset = addr & OMAP_MPUI_REG_MASK;
d951f6ff 2162
a4ebbd18
AK		 2163 if (size != 2) {
2164 return omap_badwidth_read16(opaque, addr);
2165 }
2166
d951f6ff
AZ		 2167 switch (offset) {
2168 case 0x00: /* RDR */
2169 s->control &= ~(1 << 15); /* RDRB */
2170 return s->rxbuf;
2171
2172 case 0x04: /* CSR */
2173 return s->control;
2174
2175 case 0x08: /* SR1 */
2176 return s->setup[0];
2177 case 0x0c: /* SR2 */
2178 return s->setup[1];
2179 case 0x10: /* SR3 */
2180 return s->setup[2];
2181 case 0x14: /* SR4 */
2182 return s->setup[3];
2183 case 0x18: /* SR5 */
2184 return s->setup[4];
2185 }
2186
2187 OMAP_BAD_REG(addr);
2188 return 0;
2189}
2190
c227f099 2191static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
a4ebbd18 2192 uint64_t value, unsigned size)
d951f6ff
AZ		 2193{
2194 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
cf965d24 2195 int offset = addr & OMAP_MPUI_REG_MASK;
d951f6ff 2196
a4ebbd18
AK		 2197 if (size != 2) {
2198 return omap_badwidth_write16(opaque, addr, value);
2199 }
2200
d951f6ff
AZ		 2201 switch (offset) {
2202 case 0x00: /* TDR */
2203 s->txbuf = value; /* TD */
d951f6ff
AZ		 2204 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
2205 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
cf965d24
AZ		 2206 (s->control & (1 << 12)))) { /* CS_CMD */
2207 s->control |= 1 << 14; /* CSRB */
d951f6ff 2208 omap_uwire_transfer_start(s);
cf965d24 2209 }
d951f6ff
AZ		 2210 break;
2211
2212 case 0x04: /* CSR */
2213 s->control = value & 0x1fff;
2214 if (value & (1 << 13)) /* START */
2215 omap_uwire_transfer_start(s);
2216 break;
2217
2218 case 0x08: /* SR1 */
2219 s->setup[0] = value & 0x003f;
2220 break;
2221
2222 case 0x0c: /* SR2 */
2223 s->setup[1] = value & 0x0fc0;
2224 break;
2225
2226 case 0x10: /* SR3 */
2227 s->setup[2] = value & 0x0003;
2228 break;
2229
2230 case 0x14: /* SR4 */
2231 s->setup[3] = value & 0x0001;
2232 break;
2233
2234 case 0x18: /* SR5 */
2235 s->setup[4] = value & 0x000f;
2236 break;
2237
2238 default:
2239 OMAP_BAD_REG(addr);
2240 return;
2241 }
2242}
2243
a4ebbd18
AK		 2244static const MemoryRegionOps omap_uwire_ops = {
2245 .read = omap_uwire_read,
2246 .write = omap_uwire_write,
2247 .endianness = DEVICE_NATIVE_ENDIAN,
d951f6ff
AZ		 2248};
2249
9596ebb7 2250static void omap_uwire_reset(struct omap_uwire_s *s)
d951f6ff 2251{
66450b15 2252 s->control = 0;
d951f6ff
AZ		 2253 s->setup[0] = 0;
2254 s->setup[1] = 0;
2255 s->setup[2] = 0;
2256 s->setup[3] = 0;
2257 s->setup[4] = 0;
2258}
2259
0919ac78
PM		 2260static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
2261 target_phys_addr_t base,
2262 qemu_irq txirq, qemu_irq rxirq,
2263 qemu_irq dma,
2264 omap_clk clk)
d951f6ff 2265{
d951f6ff 2266 struct omap_uwire_s *s = (struct omap_uwire_s *)
7267c094 2267 g_malloc0(sizeof(struct omap_uwire_s));
d951f6ff 2268
0919ac78
PM		 2269 s->txirq = txirq;
2270 s->rxirq = rxirq;
d951f6ff
AZ		 2271 s->txdrq = dma;
2272 omap_uwire_reset(s);
2273
a4ebbd18
AK		 2274 memory_region_init_io(&s->iomem, &omap_uwire_ops, s, "omap-uwire", 0x800);
2275 memory_region_add_subregion(system_memory, base, &s->iomem);
d951f6ff
AZ		 2276
2277 return s;
2278}
2279
2280void omap_uwire_attach(struct omap_uwire_s *s,
bc24a225 2281 uWireSlave *slave, int chipselect)
d951f6ff 2282{
827df9f3
AZ		 2283 if (chipselect < 0 || chipselect > 3) {
2284 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
2285 exit(-1);
2286 }
d951f6ff
AZ		 2287
2288 s->chip[chipselect] = slave;
2289}
2290
66450b15 2291/* Pseudonoise Pulse-Width Light Modulator */
8717d88a
JR		 2292struct omap_pwl_s {
2293 MemoryRegion iomem;
2294 uint8_t output;
2295 uint8_t level;
2296 uint8_t enable;
2297 int clk;
2298};
2299
2300static void omap_pwl_update(struct omap_pwl_s *s)
66450b15 2301{
8717d88a 2302 int output = (s->clk && s->enable) ? s->level : 0;
66450b15 2303
8717d88a
JR		 2304 if (output != s->output) {
2305 s->output = output;
66450b15
AZ		 2306 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
2307 }
2308}
2309
a4ebbd18
AK		 2310static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr,
2311 unsigned size)
66450b15 2312{
8717d88a 2313 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
cf965d24 2314 int offset = addr & OMAP_MPUI_REG_MASK;
66450b15 2315
a4ebbd18
AK		 2316 if (size != 1) {
2317 return omap_badwidth_read8(opaque, addr);
2318 }
2319
66450b15
AZ		 2320 switch (offset) {
2321 case 0x00: /* PWL_LEVEL */
8717d88a 2322 return s->level;
66450b15 2323 case 0x04: /* PWL_CTRL */
8717d88a 2324 return s->enable;
66450b15
AZ		 2325 }
2326 OMAP_BAD_REG(addr);
2327 return 0;
2328}
2329
c227f099 2330static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
a4ebbd18 2331 uint64_t value, unsigned size)
66450b15 2332{
8717d88a 2333 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
cf965d24 2334 int offset = addr & OMAP_MPUI_REG_MASK;
66450b15 2335
a4ebbd18
AK		 2336 if (size != 1) {
2337 return omap_badwidth_write8(opaque, addr, value);
2338 }
2339
66450b15
AZ		 2340 switch (offset) {
2341 case 0x00: /* PWL_LEVEL */
8717d88a 2342 s->level = value;
66450b15
AZ		 2343 omap_pwl_update(s);
2344 break;
2345 case 0x04: /* PWL_CTRL */
8717d88a 2346 s->enable = value & 1;
66450b15
AZ		 2347 omap_pwl_update(s);
2348 break;
2349 default:
2350 OMAP_BAD_REG(addr);
2351 return;
2352 }
2353}
2354
a4ebbd18
AK		 2355static const MemoryRegionOps omap_pwl_ops = {
2356 .read = omap_pwl_read,
2357 .write = omap_pwl_write,
2358 .endianness = DEVICE_NATIVE_ENDIAN,
66450b15
AZ		 2359};
2360
8717d88a 2361static void omap_pwl_reset(struct omap_pwl_s *s)
66450b15 2362{
8717d88a
JR		 2363 s->output = 0;
2364 s->level = 0;
2365 s->enable = 0;
2366 s->clk = 1;
66450b15
AZ		 2367 omap_pwl_update(s);
2368}
2369
2370static void omap_pwl_clk_update(void *opaque, int line, int on)
2371{
8717d88a 2372 struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
66450b15 2373
8717d88a 2374 s->clk = on;
66450b15
AZ		 2375 omap_pwl_update(s);
2376}
2377
8717d88a
JR		 2378static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
2379 target_phys_addr_t base,
2380 omap_clk clk)
66450b15 2381{
8717d88a
JR		 2382 struct omap_pwl_s *s = g_malloc0(sizeof(*s));
2383
66450b15
AZ		 2384 omap_pwl_reset(s);
2385
8717d88a 2386 memory_region_init_io(&s->iomem, &omap_pwl_ops, s,
a4ebbd18 2387 "omap-pwl", 0x800);
8717d88a 2388 memory_region_add_subregion(system_memory, base, &s->iomem);
66450b15
AZ		 2389
2390 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
8717d88a 2391 return s;
66450b15
AZ		 2392}
2393
f34c417b 2394/* Pulse-Width Tone module */
03759534
JR		 2395struct omap_pwt_s {
2396 MemoryRegion iomem;
2397 uint8_t frc;
2398 uint8_t vrc;
2399 uint8_t gcr;
2400 omap_clk clk;
2401};
2402
a4ebbd18
AK		 2403static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr,
2404 unsigned size)
f34c417b 2405{
03759534 2406 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
cf965d24 2407 int offset = addr & OMAP_MPUI_REG_MASK;
f34c417b 2408
a4ebbd18
AK		 2409 if (size != 1) {
2410 return omap_badwidth_read8(opaque, addr);
2411 }
2412
f34c417b
AZ		 2413 switch (offset) {
2414 case 0x00: /* FRC */
03759534 2415 return s->frc;
f34c417b 2416 case 0x04: /* VCR */
03759534 2417 return s->vrc;
f34c417b 2418 case 0x08: /* GCR */
03759534 2419 return s->gcr;
f34c417b
AZ		 2420 }
2421 OMAP_BAD_REG(addr);
2422 return 0;
2423}
2424
c227f099 2425static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
a4ebbd18 2426 uint64_t value, unsigned size)
f34c417b 2427{
03759534 2428 struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
cf965d24 2429 int offset = addr & OMAP_MPUI_REG_MASK;
f34c417b 2430
a4ebbd18
AK		 2431 if (size != 1) {
2432 return omap_badwidth_write8(opaque, addr, value);
2433 }
2434
f34c417b
AZ		 2435 switch (offset) {
2436 case 0x00: /* FRC */
03759534 2437 s->frc = value & 0x3f;
f34c417b
AZ		 2438 break;
2439 case 0x04: /* VRC */
03759534 2440 if ((value ^ s->vrc) & 1) {
f34c417b
AZ		 2441 if (value & 1)
2442 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
2443 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
03759534 2444 ((omap_clk_getrate(s->clk) >> 3) /
f34c417b 2445 /* Pre-multiplexer divider */
03759534 2446 ((s->gcr & 2) ? 1 : 154) /
f34c417b
AZ		 2447 /* Octave multiplexer */
2448 (2 << (value & 3)) *
2449 /* 101/107 divider */
2450 ((value & (1 << 2)) ? 101 : 107) *
2451 /* 49/55 divider */
2452 ((value & (1 << 3)) ? 49 : 55) *
2453 /* 50/63 divider */
2454 ((value & (1 << 4)) ? 50 : 63) *
2455 /* 80/127 divider */
2456 ((value & (1 << 5)) ? 80 : 127) /
2457 (107 * 55 * 63 * 127)));
2458 else
2459 printf("%s: silence!\n", __FUNCTION__);
2460 }
03759534 2461 s->vrc = value & 0x7f;
f34c417b
AZ		 2462 break;
2463 case 0x08: /* GCR */
03759534 2464 s->gcr = value & 3;
f34c417b
AZ		 2465 break;
2466 default:
2467 OMAP_BAD_REG(addr);
2468 return;
2469 }
2470}
2471
a4ebbd18
AK		 2472static const MemoryRegionOps omap_pwt_ops = {
2473 .read =omap_pwt_read,
2474 .write = omap_pwt_write,
2475 .endianness = DEVICE_NATIVE_ENDIAN,
f34c417b
AZ		 2476};
2477
03759534 2478static void omap_pwt_reset(struct omap_pwt_s *s)
f34c417b 2479{
03759534
JR		 2480 s->frc = 0;
2481 s->vrc = 0;
2482 s->gcr = 0;
f34c417b
AZ		 2483}
2484
03759534
JR		 2485static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
2486 target_phys_addr_t base,
2487 omap_clk clk)
f34c417b 2488{
03759534
JR		 2489 struct omap_pwt_s *s = g_malloc0(sizeof(*s));
2490 s->clk = clk;
f34c417b
AZ		 2491 omap_pwt_reset(s);
2492
03759534 2493 memory_region_init_io(&s->iomem, &omap_pwt_ops, s,
a4ebbd18 2494 "omap-pwt", 0x800);
03759534
JR		 2495 memory_region_add_subregion(system_memory, base, &s->iomem);
2496 return s;
f34c417b
AZ		 2497}
2498
5c1c390f
AZ		 2499/* Real-time Clock module */
2500struct omap_rtc_s {
a4ebbd18 2501 MemoryRegion iomem;
5c1c390f
AZ		 2502 qemu_irq irq;
2503 qemu_irq alarm;
2504 QEMUTimer *clk;
2505
2506 uint8_t interrupts;
2507 uint8_t status;
2508 int16_t comp_reg;
2509 int running;
2510 int pm_am;
2511 int auto_comp;
2512 int round;
5c1c390f
AZ		 2513 struct tm alarm_tm;
2514 time_t alarm_ti;
2515
2516 struct tm current_tm;
2517 time_t ti;
2518 uint64_t tick;
2519};
2520
2521static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
2522{
106627d0 2523 /* s->alarm is level-triggered */
5c1c390f
AZ		 2524 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
2525}
2526
2527static void omap_rtc_alarm_update(struct omap_rtc_s *s)
2528{
0cd2df75 2529 s->alarm_ti = mktimegm(&s->alarm_tm);
5c1c390f
AZ		 2530 if (s->alarm_ti == -1)
2531 printf("%s: conversion failed\n", __FUNCTION__);
2532}
2533
a4ebbd18
AK		 2534static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr,
2535 unsigned size)
5c1c390f
AZ		 2536{
2537 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
cf965d24 2538 int offset = addr & OMAP_MPUI_REG_MASK;
5c1c390f
AZ		 2539 uint8_t i;
2540
a4ebbd18
AK		 2541 if (size != 1) {
2542 return omap_badwidth_read8(opaque, addr);
2543 }
2544
5c1c390f
AZ		 2545 switch (offset) {
2546 case 0x00: /* SECONDS_REG */
abd0c6bd 2547 return to_bcd(s->current_tm.tm_sec);
5c1c390f
AZ		 2548
2549 case 0x04: /* MINUTES_REG */
abd0c6bd 2550 return to_bcd(s->current_tm.tm_min);
5c1c390f
AZ		 2551
2552 case 0x08: /* HOURS_REG */
2553 if (s->pm_am)
2554 return ((s->current_tm.tm_hour > 11) << 7) |
abd0c6bd 2555 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
5c1c390f 2556 else
abd0c6bd 2557 return to_bcd(s->current_tm.tm_hour);
5c1c390f
AZ		 2558
2559 case 0x0c: /* DAYS_REG */
abd0c6bd 2560 return to_bcd(s->current_tm.tm_mday);
5c1c390f
AZ		 2561
2562 case 0x10: /* MONTHS_REG */
abd0c6bd 2563 return to_bcd(s->current_tm.tm_mon + 1);
5c1c390f
AZ		 2564
2565 case 0x14: /* YEARS_REG */
abd0c6bd 2566 return to_bcd(s->current_tm.tm_year % 100);
5c1c390f
AZ		 2567
2568 case 0x18: /* WEEK_REG */
2569 return s->current_tm.tm_wday;
2570
2571 case 0x20: /* ALARM_SECONDS_REG */
abd0c6bd 2572 return to_bcd(s->alarm_tm.tm_sec);
5c1c390f
AZ		 2573
2574 case 0x24: /* ALARM_MINUTES_REG */
abd0c6bd 2575 return to_bcd(s->alarm_tm.tm_min);
5c1c390f
AZ		 2576
2577 case 0x28: /* ALARM_HOURS_REG */
2578 if (s->pm_am)
2579 return ((s->alarm_tm.tm_hour > 11) << 7) |
abd0c6bd 2580 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
5c1c390f 2581 else
abd0c6bd 2582 return to_bcd(s->alarm_tm.tm_hour);
5c1c390f
AZ		 2583
2584 case 0x2c: /* ALARM_DAYS_REG */
abd0c6bd 2585 return to_bcd(s->alarm_tm.tm_mday);
5c1c390f
AZ		 2586
2587 case 0x30: /* ALARM_MONTHS_REG */
abd0c6bd 2588 return to_bcd(s->alarm_tm.tm_mon + 1);
5c1c390f
AZ		 2589
2590 case 0x34: /* ALARM_YEARS_REG */
abd0c6bd 2591 return to_bcd(s->alarm_tm.tm_year % 100);
5c1c390f
AZ		 2592
2593 case 0x40: /* RTC_CTRL_REG */
2594 return (s->pm_am << 3) | (s->auto_comp << 2) |
2595 (s->round << 1) | s->running;
2596
2597 case 0x44: /* RTC_STATUS_REG */
2598 i = s->status;
2599 s->status &= ~0x3d;
2600 return i;
2601
2602 case 0x48: /* RTC_INTERRUPTS_REG */
2603 return s->interrupts;
2604
2605 case 0x4c: /* RTC_COMP_LSB_REG */
2606 return ((uint16_t) s->comp_reg) & 0xff;
2607
2608 case 0x50: /* RTC_COMP_MSB_REG */
2609 return ((uint16_t) s->comp_reg) >> 8;
2610 }
2611
2612 OMAP_BAD_REG(addr);
2613 return 0;
2614}
2615
c227f099 2616static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
a4ebbd18 2617 uint64_t value, unsigned size)
5c1c390f
AZ		 2618{
2619 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
cf965d24 2620 int offset = addr & OMAP_MPUI_REG_MASK;
5c1c390f
AZ		 2621 struct tm new_tm;
2622 time_t ti[2];
2623
a4ebbd18
AK		 2624 if (size != 1) {
2625 return omap_badwidth_write8(opaque, addr, value);
2626 }
2627
5c1c390f
AZ		 2628 switch (offset) {
2629 case 0x00: /* SECONDS_REG */
eb38c52c 2630#ifdef ALMDEBUG
5c1c390f
AZ		 2631 printf("RTC SEC_REG <-- %02x\n", value);
2632#endif
2633 s->ti -= s->current_tm.tm_sec;
abd0c6bd 2634 s->ti += from_bcd(value);
5c1c390f
AZ		 2635 return;
2636
2637 case 0x04: /* MINUTES_REG */
eb38c52c 2638#ifdef ALMDEBUG
5c1c390f
AZ		 2639 printf("RTC MIN_REG <-- %02x\n", value);
2640#endif
2641 s->ti -= s->current_tm.tm_min * 60;
abd0c6bd 2642 s->ti += from_bcd(value) * 60;
5c1c390f
AZ		 2643 return;
2644
2645 case 0x08: /* HOURS_REG */
eb38c52c 2646#ifdef ALMDEBUG
5c1c390f
AZ		 2647 printf("RTC HRS_REG <-- %02x\n", value);
2648#endif
2649 s->ti -= s->current_tm.tm_hour * 3600;
2650 if (s->pm_am) {
abd0c6bd 2651 s->ti += (from_bcd(value & 0x3f) & 12) * 3600;
5c1c390f
AZ		 2652 s->ti += ((value >> 7) & 1) * 43200;
2653 } else
abd0c6bd 2654 s->ti += from_bcd(value & 0x3f) * 3600;
5c1c390f
AZ		 2655 return;
2656
2657 case 0x0c: /* DAYS_REG */
eb38c52c 2658#ifdef ALMDEBUG
5c1c390f
AZ		 2659 printf("RTC DAY_REG <-- %02x\n", value);
2660#endif
2661 s->ti -= s->current_tm.tm_mday * 86400;
abd0c6bd 2662 s->ti += from_bcd(value) * 86400;
5c1c390f
AZ		 2663 return;
2664
2665 case 0x10: /* MONTHS_REG */
eb38c52c 2666#ifdef ALMDEBUG
5c1c390f
AZ		 2667 printf("RTC MTH_REG <-- %02x\n", value);
2668#endif
2669 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
abd0c6bd 2670 new_tm.tm_mon = from_bcd(value);
0cd2df75
AJ		 2671 ti[0] = mktimegm(&s->current_tm);
2672 ti[1] = mktimegm(&new_tm);
5c1c390f
AZ		 2673
2674 if (ti[0] != -1 && ti[1] != -1) {
2675 s->ti -= ti[0];
2676 s->ti += ti[1];
2677 } else {
2678 /* A less accurate version */
2679 s->ti -= s->current_tm.tm_mon * 2592000;
abd0c6bd 2680 s->ti += from_bcd(value) * 2592000;
5c1c390f
AZ		 2681 }
2682 return;
2683
2684 case 0x14: /* YEARS_REG */
eb38c52c 2685#ifdef ALMDEBUG
5c1c390f
AZ		 2686 printf("RTC YRS_REG <-- %02x\n", value);
2687#endif
2688 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
abd0c6bd 2689 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100);
0cd2df75
AJ		 2690 ti[0] = mktimegm(&s->current_tm);
2691 ti[1] = mktimegm(&new_tm);
5c1c390f
AZ		 2692
2693 if (ti[0] != -1 && ti[1] != -1) {
2694 s->ti -= ti[0];
2695 s->ti += ti[1];
2696 } else {
2697 /* A less accurate version */
2698 s->ti -= (s->current_tm.tm_year % 100) * 31536000;
abd0c6bd 2699 s->ti += from_bcd(value) * 31536000;
5c1c390f
AZ		 2700 }
2701 return;
2702
2703 case 0x18: /* WEEK_REG */
2704 return; /* Ignored */
2705
2706 case 0x20: /* ALARM_SECONDS_REG */
eb38c52c 2707#ifdef ALMDEBUG
5c1c390f
AZ		 2708 printf("ALM SEC_REG <-- %02x\n", value);
2709#endif
abd0c6bd 2710 s->alarm_tm.tm_sec = from_bcd(value);
5c1c390f
AZ		 2711 omap_rtc_alarm_update(s);
2712 return;
2713
2714 case 0x24: /* ALARM_MINUTES_REG */
eb38c52c 2715#ifdef ALMDEBUG
5c1c390f
AZ		 2716 printf("ALM MIN_REG <-- %02x\n", value);
2717#endif
abd0c6bd 2718 s->alarm_tm.tm_min = from_bcd(value);
5c1c390f
AZ		 2719 omap_rtc_alarm_update(s);
2720 return;
2721
2722 case 0x28: /* ALARM_HOURS_REG */
eb38c52c 2723#ifdef ALMDEBUG
5c1c390f
AZ		 2724 printf("ALM HRS_REG <-- %02x\n", value);
2725#endif
2726 if (s->pm_am)
2727 s->alarm_tm.tm_hour =
abd0c6bd 2728 ((from_bcd(value & 0x3f)) % 12) +
5c1c390f
AZ		 2729 ((value >> 7) & 1) * 12;
2730 else
abd0c6bd 2731 s->alarm_tm.tm_hour = from_bcd(value);
5c1c390f
AZ		 2732 omap_rtc_alarm_update(s);
2733 return;
2734
2735 case 0x2c: /* ALARM_DAYS_REG */
eb38c52c 2736#ifdef ALMDEBUG
5c1c390f
AZ		 2737 printf("ALM DAY_REG <-- %02x\n", value);
2738#endif
abd0c6bd 2739 s->alarm_tm.tm_mday = from_bcd(value);
5c1c390f
AZ		 2740 omap_rtc_alarm_update(s);
2741 return;
2742
2743 case 0x30: /* ALARM_MONTHS_REG */
eb38c52c 2744#ifdef ALMDEBUG
5c1c390f
AZ		 2745 printf("ALM MON_REG <-- %02x\n", value);
2746#endif
abd0c6bd 2747 s->alarm_tm.tm_mon = from_bcd(value);
5c1c390f
AZ		 2748 omap_rtc_alarm_update(s);
2749 return;
2750
2751 case 0x34: /* ALARM_YEARS_REG */
eb38c52c 2752#ifdef ALMDEBUG
5c1c390f
AZ		 2753 printf("ALM YRS_REG <-- %02x\n", value);
2754#endif
abd0c6bd 2755 s->alarm_tm.tm_year = from_bcd(value);
5c1c390f
AZ		 2756 omap_rtc_alarm_update(s);
2757 return;
2758
2759 case 0x40: /* RTC_CTRL_REG */
eb38c52c 2760#ifdef ALMDEBUG
5c1c390f
AZ		 2761 printf("RTC CONTROL <-- %02x\n", value);
2762#endif
2763 s->pm_am = (value >> 3) & 1;
2764 s->auto_comp = (value >> 2) & 1;
2765 s->round = (value >> 1) & 1;
2766 s->running = value & 1;
2767 s->status &= 0xfd;
2768 s->status |= s->running << 1;
2769 return;
2770
2771 case 0x44: /* RTC_STATUS_REG */
eb38c52c 2772#ifdef ALMDEBUG
5c1c390f
AZ		 2773 printf("RTC STATUSL <-- %02x\n", value);
2774#endif
2775 s->status &= ~((value & 0xc0) ^ 0x80);
2776 omap_rtc_interrupts_update(s);
2777 return;
2778
2779 case 0x48: /* RTC_INTERRUPTS_REG */
eb38c52c 2780#ifdef ALMDEBUG
5c1c390f
AZ		 2781 printf("RTC INTRS <-- %02x\n", value);
2782#endif
2783 s->interrupts = value;
2784 return;
2785
2786 case 0x4c: /* RTC_COMP_LSB_REG */
eb38c52c 2787#ifdef ALMDEBUG
5c1c390f
AZ		 2788 printf("RTC COMPLSB <-- %02x\n", value);
2789#endif
2790 s->comp_reg &= 0xff00;
2791 s->comp_reg |= 0x00ff & value;
2792 return;
2793
2794 case 0x50: /* RTC_COMP_MSB_REG */
eb38c52c 2795#ifdef ALMDEBUG
5c1c390f
AZ		 2796 printf("RTC COMPMSB <-- %02x\n", value);
2797#endif
2798 s->comp_reg &= 0x00ff;
2799 s->comp_reg |= 0xff00 & (value << 8);
2800 return;
2801
2802 default:
2803 OMAP_BAD_REG(addr);
2804 return;
2805 }
2806}
2807
a4ebbd18
AK		 2808static const MemoryRegionOps omap_rtc_ops = {
2809 .read = omap_rtc_read,
2810 .write = omap_rtc_write,
2811 .endianness = DEVICE_NATIVE_ENDIAN,
5c1c390f
AZ		 2812};
2813
2814static void omap_rtc_tick(void *opaque)
2815{
2816 struct omap_rtc_s *s = opaque;
2817
2818 if (s->round) {
2819 /* Round to nearest full minute. */
2820 if (s->current_tm.tm_sec < 30)
2821 s->ti -= s->current_tm.tm_sec;
2822 else
2823 s->ti += 60 - s->current_tm.tm_sec;
2824
2825 s->round = 0;
2826 }
2827
f6503059 2828 memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
5c1c390f
AZ		 2829
2830 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
2831 s->status |= 0x40;
2832 omap_rtc_interrupts_update(s);
2833 }
2834
2835 if (s->interrupts & 0x04)
2836 switch (s->interrupts & 3) {
2837 case 0:
2838 s->status |= 0x04;
106627d0 2839 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 2840 break;
2841 case 1:
2842 if (s->current_tm.tm_sec)
2843 break;
2844 s->status |= 0x08;
106627d0 2845 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 2846 break;
2847 case 2:
2848 if (s->current_tm.tm_sec || s->current_tm.tm_min)
2849 break;
2850 s->status |= 0x10;
106627d0 2851 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 2852 break;
2853 case 3:
2854 if (s->current_tm.tm_sec ||
2855 s->current_tm.tm_min || s->current_tm.tm_hour)
2856 break;
2857 s->status |= 0x20;
106627d0 2858 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 2859 break;
2860 }
2861
2862 /* Move on */
2863 if (s->running)
2864 s->ti ++;
2865 s->tick += 1000;
2866
2867 /*
2868 * Every full hour add a rough approximation of the compensation
2869 * register to the 32kHz Timer (which drives the RTC) value.
2870 */
2871 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
2872 s->tick += s->comp_reg * 1000 / 32768;
2873
2874 qemu_mod_timer(s->clk, s->tick);
2875}
2876
9596ebb7 2877static void omap_rtc_reset(struct omap_rtc_s *s)
5c1c390f 2878{
f6503059
AZ		 2879 struct tm tm;
2880
5c1c390f
AZ		 2881 s->interrupts = 0;
2882 s->comp_reg = 0;
2883 s->running = 0;
2884 s->pm_am = 0;
2885 s->auto_comp = 0;
2886 s->round = 0;
7bd427d8 2887 s->tick = qemu_get_clock_ms(rt_clock);
5c1c390f
AZ		 2888 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
2889 s->alarm_tm.tm_mday = 0x01;
2890 s->status = 1 << 7;
f6503059 2891 qemu_get_timedate(&tm, 0);
0cd2df75 2892 s->ti = mktimegm(&tm);
5c1c390f
AZ		 2893
2894 omap_rtc_alarm_update(s);
2895 omap_rtc_tick(s);
2896}
2897
a4ebbd18 2898static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
0919ac78
PM		 2899 target_phys_addr_t base,
2900 qemu_irq timerirq, qemu_irq alarmirq,
2901 omap_clk clk)
5c1c390f 2902{
5c1c390f 2903 struct omap_rtc_s *s = (struct omap_rtc_s *)
7267c094 2904 g_malloc0(sizeof(struct omap_rtc_s));
5c1c390f 2905
0919ac78
PM		 2906 s->irq = timerirq;
2907 s->alarm = alarmirq;
7bd427d8 2908 s->clk = qemu_new_timer_ms(rt_clock, omap_rtc_tick, s);
5c1c390f
AZ		 2909
2910 omap_rtc_reset(s);
2911
a4ebbd18
AK		 2912 memory_region_init_io(&s->iomem, &omap_rtc_ops, s,
2913 "omap-rtc", 0x800);
2914 memory_region_add_subregion(system_memory, base, &s->iomem);
5c1c390f
AZ		 2915
2916 return s;
2917}
2918
d8f699cb
AZ		 2919/* Multi-channel Buffered Serial Port interfaces */
2920struct omap_mcbsp_s {
a4ebbd18 2921 MemoryRegion iomem;
d8f699cb
AZ		 2922 qemu_irq txirq;
2923 qemu_irq rxirq;
2924 qemu_irq txdrq;
2925 qemu_irq rxdrq;
2926
2927 uint16_t spcr[2];
2928 uint16_t rcr[2];
2929 uint16_t xcr[2];
2930 uint16_t srgr[2];
2931 uint16_t mcr[2];
2932 uint16_t pcr;
2933 uint16_t rcer[8];
2934 uint16_t xcer[8];
2935 int tx_rate;
2936 int rx_rate;
2937 int tx_req;
73560bc8 2938 int rx_req;
d8f699cb 2939
bc24a225 2940 I2SCodec *codec;
73560bc8
AZ		 2941 QEMUTimer *source_timer;
2942 QEMUTimer *sink_timer;
d8f699cb
AZ		 2943};
2944
2945static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
2946{
2947 int irq;
2948
2949 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
2950 case 0:
2951 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
2952 break;
2953 case 3:
2954 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
2955 break;
2956 default:
2957 irq = 0;
2958 break;
2959 }
2960
106627d0
AZ		 2961 if (irq)
2962 qemu_irq_pulse(s->rxirq);
d8f699cb
AZ		 2963
2964 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
2965 case 0:
2966 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
2967 break;
2968 case 3:
2969 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
2970 break;
2971 default:
2972 irq = 0;
2973 break;
2974 }
2975
106627d0
AZ		 2976 if (irq)
2977 qemu_irq_pulse(s->txirq);
d8f699cb
AZ		 2978}
2979
73560bc8 2980static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
d8f699cb 2981{
73560bc8
AZ		 2982 if ((s->spcr[0] >> 1) & 1) /* RRDY */
2983 s->spcr[0] |= 1 << 2; /* RFULL */
2984 s->spcr[0] |= 1 << 1; /* RRDY */
2985 qemu_irq_raise(s->rxdrq);
2986 omap_mcbsp_intr_update(s);
d8f699cb
AZ		 2987}
2988
73560bc8 2989static void omap_mcbsp_source_tick(void *opaque)
d8f699cb 2990{
73560bc8
AZ		 2991 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
2992 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
2993
2994 if (!s->rx_rate)
d8f699cb 2995 return;
73560bc8
AZ		 2996 if (s->rx_req)
2997 printf("%s: Rx FIFO overrun\n", __FUNCTION__);
d8f699cb 2998
73560bc8 2999 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
d8f699cb 3000
73560bc8 3001 omap_mcbsp_rx_newdata(s);
74475455 3002 qemu_mod_timer(s->source_timer, qemu_get_clock_ns(vm_clock) +
6ee093c9 3003 get_ticks_per_sec());
d8f699cb
AZ		 3004}
3005
3006static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
3007{
73560bc8
AZ		 3008 if (!s->codec || !s->codec->rts)
3009 omap_mcbsp_source_tick(s);
3010 else if (s->codec->in.len) {
3011 s->rx_req = s->codec->in.len;
3012 omap_mcbsp_rx_newdata(s);
d8f699cb 3013 }
d8f699cb
AZ		 3014}
3015
3016static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
73560bc8
AZ		 3017{
3018 qemu_del_timer(s->source_timer);
3019}
3020
3021static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
d8f699cb
AZ		 3022{
3023 s->spcr[0] &= ~(1 << 1); /* RRDY */
3024 qemu_irq_lower(s->rxdrq);
3025 omap_mcbsp_intr_update(s);
3026}
3027
73560bc8
AZ		 3028static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
3029{
3030 s->spcr[1] |= 1 << 1; /* XRDY */
3031 qemu_irq_raise(s->txdrq);
3032 omap_mcbsp_intr_update(s);
3033}
3034
3035static void omap_mcbsp_sink_tick(void *opaque)
d8f699cb 3036{
73560bc8
AZ		 3037 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3038 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3039
3040 if (!s->tx_rate)
d8f699cb 3041 return;
73560bc8
AZ		 3042 if (s->tx_req)
3043 printf("%s: Tx FIFO underrun\n", __FUNCTION__);
3044
3045 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
3046
3047 omap_mcbsp_tx_newdata(s);
74475455 3048 qemu_mod_timer(s->sink_timer, qemu_get_clock_ns(vm_clock) +
6ee093c9 3049 get_ticks_per_sec());
73560bc8
AZ		 3050}
3051
3052static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
3053{
3054 if (!s->codec || !s->codec->cts)
3055 omap_mcbsp_sink_tick(s);
3056 else if (s->codec->out.size) {
3057 s->tx_req = s->codec->out.size;
3058 omap_mcbsp_tx_newdata(s);
3059 }
3060}
3061
3062static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
3063{
3064 s->spcr[1] &= ~(1 << 1); /* XRDY */
3065 qemu_irq_lower(s->txdrq);
3066 omap_mcbsp_intr_update(s);
3067 if (s->codec && s->codec->cts)
3068 s->codec->tx_swallow(s->codec->opaque);
d8f699cb
AZ		 3069}
3070
3071static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
3072{
73560bc8
AZ		 3073 s->tx_req = 0;
3074 omap_mcbsp_tx_done(s);
3075 qemu_del_timer(s->sink_timer);
3076}
3077
3078static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
3079{
3080 int prev_rx_rate, prev_tx_rate;
3081 int rx_rate = 0, tx_rate = 0;
3082 int cpu_rate = 1500000; /* XXX */
3083
3084 /* TODO: check CLKSTP bit */
3085 if (s->spcr[1] & (1 << 6)) { /* GRST */
3086 if (s->spcr[0] & (1 << 0)) { /* RRST */
3087 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3088 (s->pcr & (1 << 8))) { /* CLKRM */
3089 if (~s->pcr & (1 << 7)) /* SCLKME */
3090 rx_rate = cpu_rate /
3091 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3092 } else
3093 if (s->codec)
3094 rx_rate = s->codec->rx_rate;
3095 }
3096
3097 if (s->spcr[1] & (1 << 0)) { /* XRST */
3098 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3099 (s->pcr & (1 << 9))) { /* CLKXM */
3100 if (~s->pcr & (1 << 7)) /* SCLKME */
3101 tx_rate = cpu_rate /
3102 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3103 } else
3104 if (s->codec)
3105 tx_rate = s->codec->tx_rate;
3106 }
3107 }
3108 prev_tx_rate = s->tx_rate;
3109 prev_rx_rate = s->rx_rate;
3110 s->tx_rate = tx_rate;
3111 s->rx_rate = rx_rate;
3112
3113 if (s->codec)
3114 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3115
3116 if (!prev_tx_rate && tx_rate)
3117 omap_mcbsp_tx_start(s);
3118 else if (s->tx_rate && !tx_rate)
3119 omap_mcbsp_tx_stop(s);
3120
3121 if (!prev_rx_rate && rx_rate)
3122 omap_mcbsp_rx_start(s);
3123 else if (prev_tx_rate && !tx_rate)
3124 omap_mcbsp_rx_stop(s);
d8f699cb
AZ		 3125}
3126
a4ebbd18
AK		 3127static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr,
3128 unsigned size)
d8f699cb
AZ		 3129{
3130 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3131 int offset = addr & OMAP_MPUI_REG_MASK;
3132 uint16_t ret;
3133
a4ebbd18
AK		 3134 if (size != 2) {
3135 return omap_badwidth_read16(opaque, addr);
3136 }
3137
d8f699cb
AZ		 3138 switch (offset) {
3139 case 0x00: /* DRR2 */
3140 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
3141 return 0x0000;
3142 /* Fall through. */
3143 case 0x02: /* DRR1 */
73560bc8 3144 if (s->rx_req < 2) {
d8f699cb 3145 printf("%s: Rx FIFO underrun\n", __FUNCTION__);
73560bc8 3146 omap_mcbsp_rx_done(s);
d8f699cb 3147 } else {
73560bc8
AZ		 3148 s->tx_req -= 2;
3149 if (s->codec && s->codec->in.len >= 2) {
3150 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
3151 ret |= s->codec->in.fifo[s->codec->in.start ++];
3152 s->codec->in.len -= 2;
3153 } else
3154 ret = 0x0000;
3155 if (!s->tx_req)
3156 omap_mcbsp_rx_done(s);
d8f699cb
AZ		 3157 return ret;
3158 }
3159 return 0x0000;
3160
3161 case 0x04: /* DXR2 */
3162 case 0x06: /* DXR1 */
3163 return 0x0000;
3164
3165 case 0x08: /* SPCR2 */
3166 return s->spcr[1];
3167 case 0x0a: /* SPCR1 */
3168 return s->spcr[0];
3169 case 0x0c: /* RCR2 */
3170 return s->rcr[1];
3171 case 0x0e: /* RCR1 */
3172 return s->rcr[0];
3173 case 0x10: /* XCR2 */
3174 return s->xcr[1];
3175 case 0x12: /* XCR1 */
3176 return s->xcr[0];
3177 case 0x14: /* SRGR2 */
3178 return s->srgr[1];
3179 case 0x16: /* SRGR1 */
3180 return s->srgr[0];
3181 case 0x18: /* MCR2 */
3182 return s->mcr[1];
3183 case 0x1a: /* MCR1 */
3184 return s->mcr[0];
3185 case 0x1c: /* RCERA */
3186 return s->rcer[0];
3187 case 0x1e: /* RCERB */
3188 return s->rcer[1];
3189 case 0x20: /* XCERA */
3190 return s->xcer[0];
3191 case 0x22: /* XCERB */
3192 return s->xcer[1];
3193 case 0x24: /* PCR0 */
3194 return s->pcr;
3195 case 0x26: /* RCERC */
3196 return s->rcer[2];
3197 case 0x28: /* RCERD */
3198 return s->rcer[3];
3199 case 0x2a: /* XCERC */
3200 return s->xcer[2];
3201 case 0x2c: /* XCERD */
3202 return s->xcer[3];
3203 case 0x2e: /* RCERE */
3204 return s->rcer[4];
3205 case 0x30: /* RCERF */
3206 return s->rcer[5];
3207 case 0x32: /* XCERE */
3208 return s->xcer[4];
3209 case 0x34: /* XCERF */
3210 return s->xcer[5];
3211 case 0x36: /* RCERG */
3212 return s->rcer[6];
3213 case 0x38: /* RCERH */
3214 return s->rcer[7];
3215 case 0x3a: /* XCERG */
3216 return s->xcer[6];
3217 case 0x3c: /* XCERH */
3218 return s->xcer[7];
3219 }
3220
3221 OMAP_BAD_REG(addr);
3222 return 0;
3223}
3224
c227f099 3225static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
d8f699cb
AZ		 3226 uint32_t value)
3227{
3228 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3229 int offset = addr & OMAP_MPUI_REG_MASK;
3230
3231 switch (offset) {
3232 case 0x00: /* DRR2 */
3233 case 0x02: /* DRR1 */
3234 OMAP_RO_REG(addr);
3235 return;
3236
3237 case 0x04: /* DXR2 */
3238 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3239 return;
3240 /* Fall through. */
3241 case 0x06: /* DXR1 */
73560bc8
AZ		 3242 if (s->tx_req > 1) {
3243 s->tx_req -= 2;
3244 if (s->codec && s->codec->cts) {
d8f699cb
AZ		 3245 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
3246 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
d8f699cb 3247 }
73560bc8
AZ		 3248 if (s->tx_req < 2)
3249 omap_mcbsp_tx_done(s);
d8f699cb
AZ		 3250 } else
3251 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
3252 return;
3253
3254 case 0x08: /* SPCR2 */
3255 s->spcr[1] &= 0x0002;
3256 s->spcr[1] |= 0x03f9 & value;
3257 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
73560bc8 3258 if (~value & 1) /* XRST */
d8f699cb 3259 s->spcr[1] &= ~6;
d8f699cb
AZ		 3260 omap_mcbsp_req_update(s);
3261 return;
3262 case 0x0a: /* SPCR1 */
3263 s->spcr[0] &= 0x0006;
3264 s->spcr[0] |= 0xf8f9 & value;
3265 if (value & (1 << 15)) /* DLB */
3266 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
3267 if (~value & 1) { /* RRST */
3268 s->spcr[0] &= ~6;
73560bc8
AZ		 3269 s->rx_req = 0;
3270 omap_mcbsp_rx_done(s);
d8f699cb 3271 }
d8f699cb
AZ		 3272 omap_mcbsp_req_update(s);
3273 return;
3274
3275 case 0x0c: /* RCR2 */
3276 s->rcr[1] = value & 0xffff;
3277 return;
3278 case 0x0e: /* RCR1 */
3279 s->rcr[0] = value & 0x7fe0;
3280 return;
3281 case 0x10: /* XCR2 */
3282 s->xcr[1] = value & 0xffff;
3283 return;
3284 case 0x12: /* XCR1 */
3285 s->xcr[0] = value & 0x7fe0;
3286 return;
3287 case 0x14: /* SRGR2 */
3288 s->srgr[1] = value & 0xffff;
73560bc8 3289 omap_mcbsp_req_update(s);
d8f699cb
AZ		 3290 return;
3291 case 0x16: /* SRGR1 */
3292 s->srgr[0] = value & 0xffff;
73560bc8 3293 omap_mcbsp_req_update(s);
d8f699cb
AZ		 3294 return;
3295 case 0x18: /* MCR2 */
3296 s->mcr[1] = value & 0x03e3;
3297 if (value & 3) /* XMCM */
3298 printf("%s: Tx channel selection mode enable attempt\n",
3299 __FUNCTION__);
3300 return;
3301 case 0x1a: /* MCR1 */
3302 s->mcr[0] = value & 0x03e1;
3303 if (value & 1) /* RMCM */
3304 printf("%s: Rx channel selection mode enable attempt\n",
3305 __FUNCTION__);
3306 return;
3307 case 0x1c: /* RCERA */
3308 s->rcer[0] = value & 0xffff;
3309 return;
3310 case 0x1e: /* RCERB */
3311 s->rcer[1] = value & 0xffff;
3312 return;
3313 case 0x20: /* XCERA */
3314 s->xcer[0] = value & 0xffff;
3315 return;
3316 case 0x22: /* XCERB */
3317 s->xcer[1] = value & 0xffff;
3318 return;
3319 case 0x24: /* PCR0 */
3320 s->pcr = value & 0x7faf;
3321 return;
3322 case 0x26: /* RCERC */
3323 s->rcer[2] = value & 0xffff;
3324 return;
3325 case 0x28: /* RCERD */
3326 s->rcer[3] = value & 0xffff;
3327 return;
3328 case 0x2a: /* XCERC */
3329 s->xcer[2] = value & 0xffff;
3330 return;
3331 case 0x2c: /* XCERD */
3332 s->xcer[3] = value & 0xffff;
3333 return;
3334 case 0x2e: /* RCERE */
3335 s->rcer[4] = value & 0xffff;
3336 return;
3337 case 0x30: /* RCERF */
3338 s->rcer[5] = value & 0xffff;
3339 return;
3340 case 0x32: /* XCERE */
3341 s->xcer[4] = value & 0xffff;
3342 return;
3343 case 0x34: /* XCERF */
3344 s->xcer[5] = value & 0xffff;
3345 return;
3346 case 0x36: /* RCERG */
3347 s->rcer[6] = value & 0xffff;
3348 return;
3349 case 0x38: /* RCERH */
3350 s->rcer[7] = value & 0xffff;
3351 return;
3352 case 0x3a: /* XCERG */
3353 s->xcer[6] = value & 0xffff;
3354 return;
3355 case 0x3c: /* XCERH */
3356 s->xcer[7] = value & 0xffff;
3357 return;
3358 }
3359
3360 OMAP_BAD_REG(addr);
3361}
3362
c227f099 3363static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
73560bc8
AZ		 3364 uint32_t value)
3365{
3366 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3367 int offset = addr & OMAP_MPUI_REG_MASK;
3368
3369 if (offset == 0x04) { /* DXR */
3370 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3371 return;
3372 if (s->tx_req > 3) {
3373 s->tx_req -= 4;
3374 if (s->codec && s->codec->cts) {
3375 s->codec->out.fifo[s->codec->out.len ++] =
3376 (value >> 24) & 0xff;
3377 s->codec->out.fifo[s->codec->out.len ++] =
3378 (value >> 16) & 0xff;
3379 s->codec->out.fifo[s->codec->out.len ++] =
3380 (value >> 8) & 0xff;
3381 s->codec->out.fifo[s->codec->out.len ++] =
3382 (value >> 0) & 0xff;
3383 }
3384 if (s->tx_req < 4)
3385 omap_mcbsp_tx_done(s);
3386 } else
3387 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
3388 return;
3389 }
3390
3391 omap_badwidth_write16(opaque, addr, value);
3392}
3393
a4ebbd18
AK		 3394static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr,
3395 uint64_t value, unsigned size)
3396{
3397 switch (size) {
3398 case 2: return omap_mcbsp_writeh(opaque, addr, value);
3399 case 4: return omap_mcbsp_writew(opaque, addr, value);
3400 default: return omap_badwidth_write16(opaque, addr, value);
3401 }
3402}
d8f699cb 3403
a4ebbd18
AK		 3404static const MemoryRegionOps omap_mcbsp_ops = {
3405 .read = omap_mcbsp_read,
3406 .write = omap_mcbsp_write,
3407 .endianness = DEVICE_NATIVE_ENDIAN,
d8f699cb
AZ		 3408};
3409
3410static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
3411{
3412 memset(&s->spcr, 0, sizeof(s->spcr));
3413 memset(&s->rcr, 0, sizeof(s->rcr));
3414 memset(&s->xcr, 0, sizeof(s->xcr));
3415 s->srgr[0] = 0x0001;
3416 s->srgr[1] = 0x2000;
3417 memset(&s->mcr, 0, sizeof(s->mcr));
3418 memset(&s->pcr, 0, sizeof(s->pcr));
3419 memset(&s->rcer, 0, sizeof(s->rcer));
3420 memset(&s->xcer, 0, sizeof(s->xcer));
3421 s->tx_req = 0;
73560bc8 3422 s->rx_req = 0;
d8f699cb
AZ		 3423 s->tx_rate = 0;
3424 s->rx_rate = 0;
73560bc8
AZ		 3425 qemu_del_timer(s->source_timer);
3426 qemu_del_timer(s->sink_timer);
d8f699cb
AZ		 3427}
3428
0919ac78
PM		 3429static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
3430 target_phys_addr_t base,
3431 qemu_irq txirq, qemu_irq rxirq,
3432 qemu_irq *dma, omap_clk clk)
d8f699cb 3433{
d8f699cb 3434 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
7267c094 3435 g_malloc0(sizeof(struct omap_mcbsp_s));
d8f699cb 3436
0919ac78
PM		 3437 s->txirq = txirq;
3438 s->rxirq = rxirq;
d8f699cb
AZ		 3439 s->txdrq = dma[0];
3440 s->rxdrq = dma[1];
74475455
PB		 3441 s->sink_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_sink_tick, s);
3442 s->source_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_source_tick, s);
d8f699cb
AZ		 3443 omap_mcbsp_reset(s);
3444
a4ebbd18
AK		 3445 memory_region_init_io(&s->iomem, &omap_mcbsp_ops, s, "omap-mcbsp", 0x800);
3446 memory_region_add_subregion(system_memory, base, &s->iomem);
d8f699cb
AZ		 3447
3448 return s;
3449}
3450
9596ebb7 3451static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
d8f699cb
AZ		 3452{
3453 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3454
73560bc8
AZ		 3455 if (s->rx_rate) {
3456 s->rx_req = s->codec->in.len;
3457 omap_mcbsp_rx_newdata(s);
3458 }
d8f699cb
AZ		 3459}
3460
9596ebb7 3461static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
d8f699cb
AZ		 3462{
3463 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3464
73560bc8
AZ		 3465 if (s->tx_rate) {
3466 s->tx_req = s->codec->out.size;
3467 omap_mcbsp_tx_newdata(s);
3468 }
d8f699cb
AZ		 3469}
3470
bc24a225 3471void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
d8f699cb
AZ		 3472{
3473 s->codec = slave;
3474 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
3475 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
3476}
3477
f9d43072
AZ		 3478/* LED Pulse Generators */
3479struct omap_lpg_s {
60fe76e3 3480 MemoryRegion iomem;
f9d43072
AZ		 3481 QEMUTimer *tm;
3482
3483 uint8_t control;
3484 uint8_t power;
3485 int64_t on;
3486 int64_t period;
3487 int clk;
3488 int cycle;
3489};
3490
3491static void omap_lpg_tick(void *opaque)
3492{
3493 struct omap_lpg_s *s = opaque;
3494
3495 if (s->cycle)
7bd427d8 3496 qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->period - s->on);
f9d43072 3497 else
7bd427d8 3498 qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->on);
f9d43072
AZ		 3499
3500 s->cycle = !s->cycle;
3501 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
3502}
3503
3504static void omap_lpg_update(struct omap_lpg_s *s)
3505{
3506 int64_t on, period = 1, ticks = 1000;
3507 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
3508
3509 if (~s->control & (1 << 6)) /* LPGRES */
3510 on = 0;
3511 else if (s->control & (1 << 7)) /* PERM_ON */
3512 on = period;
3513 else {
3514 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
3515 256 / 32);
3516 on = (s->clk && s->power) ? muldiv64(ticks,
3517 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
3518 }
3519
3520 qemu_del_timer(s->tm);
3521 if (on == period && s->on < s->period)
3522 printf("%s: LED is on\n", __FUNCTION__);
3523 else if (on == 0 && s->on)
3524 printf("%s: LED is off\n", __FUNCTION__);
3525 else if (on && (on != s->on || period != s->period)) {
3526 s->cycle = 0;
3527 s->on = on;
3528 s->period = period;
3529 omap_lpg_tick(s);
3530 return;
3531 }
3532
3533 s->on = on;
3534 s->period = period;
3535}
3536
3537static void omap_lpg_reset(struct omap_lpg_s *s)
3538{
3539 s->control = 0x00;
3540 s->power = 0x00;
3541 s->clk = 1;
3542 omap_lpg_update(s);
3543}
3544
60fe76e3
AK		 3545static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr,
3546 unsigned size)
f9d43072
AZ		 3547{
3548 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3549 int offset = addr & OMAP_MPUI_REG_MASK;
3550
60fe76e3
AK		 3551 if (size != 1) {
3552 return omap_badwidth_read8(opaque, addr);
3553 }
3554
f9d43072
AZ		 3555 switch (offset) {
3556 case 0x00: /* LCR */
3557 return s->control;
3558
3559 case 0x04: /* PMR */
3560 return s->power;
3561 }
3562
3563 OMAP_BAD_REG(addr);
3564 return 0;
3565}
3566
c227f099 3567static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
60fe76e3 3568 uint64_t value, unsigned size)
f9d43072
AZ		 3569{
3570 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3571 int offset = addr & OMAP_MPUI_REG_MASK;
3572
60fe76e3
AK		 3573 if (size != 1) {
3574 return omap_badwidth_write8(opaque, addr, value);
3575 }
3576
f9d43072
AZ		 3577 switch (offset) {
3578 case 0x00: /* LCR */
3579 if (~value & (1 << 6)) /* LPGRES */
3580 omap_lpg_reset(s);
3581 s->control = value & 0xff;
3582 omap_lpg_update(s);
3583 return;
3584
3585 case 0x04: /* PMR */
3586 s->power = value & 0x01;
3587 omap_lpg_update(s);
3588 return;
3589
3590 default:
3591 OMAP_BAD_REG(addr);
3592 return;
3593 }
3594}
3595
60fe76e3
AK		 3596static const MemoryRegionOps omap_lpg_ops = {
3597 .read = omap_lpg_read,
3598 .write = omap_lpg_write,
3599 .endianness = DEVICE_NATIVE_ENDIAN,
f9d43072
AZ		 3600};
3601
3602static void omap_lpg_clk_update(void *opaque, int line, int on)
3603{
3604 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3605
3606 s->clk = on;
3607 omap_lpg_update(s);
3608}
3609
60fe76e3
AK		 3610static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
3611 target_phys_addr_t base, omap_clk clk)
f9d43072 3612{
f9d43072 3613 struct omap_lpg_s *s = (struct omap_lpg_s *)
7267c094 3614 g_malloc0(sizeof(struct omap_lpg_s));
f9d43072 3615
7bd427d8 3616 s->tm = qemu_new_timer_ms(rt_clock, omap_lpg_tick, s);
f9d43072
AZ		 3617
3618 omap_lpg_reset(s);
3619
60fe76e3
AK		 3620 memory_region_init_io(&s->iomem, &omap_lpg_ops, s, "omap-lpg", 0x800);
3621 memory_region_add_subregion(system_memory, base, &s->iomem);
f9d43072
AZ		 3622
3623 omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
3624
3625 return s;
3626}
3627
3628/* MPUI Peripheral Bridge configuration */
60fe76e3
AK		 3629static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr,
3630 unsigned size)
f9d43072 3631{
60fe76e3
AK		 3632 if (size != 2) {
3633 return omap_badwidth_read16(opaque, addr);
3634 }
3635
f9d43072
AZ		 3636 if (addr == OMAP_MPUI_BASE) /* CMR */
3637 return 0xfe4d;
3638
3639 OMAP_BAD_REG(addr);
3640 return 0;
3641}
3642
60fe76e3
AK		 3643static void omap_mpui_io_write(void *opaque, target_phys_addr_t addr,
3644 uint64_t value, unsigned size)
3645{
3646 /* FIXME: infinite loop */
3647 omap_badwidth_write16(opaque, addr, value);
3648}
f9d43072 3649
60fe76e3
AK		 3650static const MemoryRegionOps omap_mpui_io_ops = {
3651 .read = omap_mpui_io_read,
3652 .write = omap_mpui_io_write,
3653 .endianness = DEVICE_NATIVE_ENDIAN,
f9d43072
AZ		 3654};
3655
60fe76e3
AK		 3656static void omap_setup_mpui_io(MemoryRegion *system_memory,
3657 struct omap_mpu_state_s *mpu)
f9d43072 3658{
60fe76e3
AK		 3659 memory_region_init_io(&mpu->mpui_io_iomem, &omap_mpui_io_ops, mpu,
3660 "omap-mpui-io", 0x7fff);
3661 memory_region_add_subregion(system_memory, OMAP_MPUI_BASE,
3662 &mpu->mpui_io_iomem);
f9d43072
AZ		 3663}
3664
c3d2689d 3665/* General chip reset */
827df9f3 3666static void omap1_mpu_reset(void *opaque)
c3d2689d
AZ		 3667{
3668 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
3669
c3d2689d
AZ		 3670 omap_dma_reset(mpu->dma);
3671 omap_mpu_timer_reset(mpu->timer[0]);
3672 omap_mpu_timer_reset(mpu->timer[1]);
3673 omap_mpu_timer_reset(mpu->timer[2]);
3674 omap_wd_timer_reset(mpu->wdt);
3675 omap_os_timer_reset(mpu->os_timer);
3676 omap_lcdc_reset(mpu->lcd);
3677 omap_ulpd_pm_reset(mpu);
3678 omap_pin_cfg_reset(mpu);
3679 omap_mpui_reset(mpu);
3680 omap_tipb_bridge_reset(mpu->private_tipb);
3681 omap_tipb_bridge_reset(mpu->public_tipb);
3682 omap_dpll_reset(&mpu->dpll[0]);
3683 omap_dpll_reset(&mpu->dpll[1]);
3684 omap_dpll_reset(&mpu->dpll[2]);
d951f6ff
AZ		 3685 omap_uart_reset(mpu->uart[0]);
3686 omap_uart_reset(mpu->uart[1]);
3687 omap_uart_reset(mpu->uart[2]);
b30bb3a2 3688 omap_mmc_reset(mpu->mmc);
fe71e81a 3689 omap_mpuio_reset(mpu->mpuio);
d951f6ff 3690 omap_uwire_reset(mpu->microwire);
8717d88a 3691 omap_pwl_reset(mpu->pwl);
03759534 3692 omap_pwt_reset(mpu->pwt);
827df9f3 3693 omap_i2c_reset(mpu->i2c[0]);
5c1c390f 3694 omap_rtc_reset(mpu->rtc);
d8f699cb
AZ		 3695 omap_mcbsp_reset(mpu->mcbsp1);
3696 omap_mcbsp_reset(mpu->mcbsp2);
3697 omap_mcbsp_reset(mpu->mcbsp3);
f9d43072
AZ		 3698 omap_lpg_reset(mpu->led[0]);
3699 omap_lpg_reset(mpu->led[1]);
8ef6367e 3700 omap_clkm_reset(mpu);
c3d2689d
AZ		 3701 cpu_reset(mpu->env);
3702}
3703
cf965d24 3704static const struct omap_map_s {
c227f099
AL		 3705 target_phys_addr_t phys_dsp;
3706 target_phys_addr_t phys_mpu;
cf965d24
AZ		 3707 uint32_t size;
3708 const char *name;
3709} omap15xx_dsp_mm[] = {
3710 /* Strobe 0 */
3711 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
3712 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
3713 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
3714 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
3715 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
3716 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
3717 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
3718 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
3719 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
3720 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
3721 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
3722 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
3723 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
3724 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
3725 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
3726 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
3727 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
3728 /* Strobe 1 */
3729 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
3730
3731 { 0 }
3732};
3733
763b946c
AK		 3734static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
3735 const struct omap_map_s *map)
cf965d24 3736{
763b946c 3737 MemoryRegion *io;
cf965d24
AZ		 3738
3739 for (; map->phys_dsp; map ++) {
763b946c
AK		 3740 io = g_new(MemoryRegion, 1);
3741 memory_region_init_alias(io, map->name,
3742 system_memory, map->phys_mpu, map->size);
3743 memory_region_add_subregion(system_memory, map->phys_dsp, io);
cf965d24
AZ		 3744 }
3745}
3746
827df9f3 3747void omap_mpu_wakeup(void *opaque, int irq, int req)
c3d2689d
AZ		 3748{
3749 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
3750
fe71e81a
AZ		 3751 if (mpu->env->halted)
3752 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
c3d2689d
AZ		 3753}
3754
827df9f3 3755static const struct dma_irq_map omap1_dma_irq_map[] = {
089b7c0a
AZ		 3756 { 0, OMAP_INT_DMA_CH0_6 },
3757 { 0, OMAP_INT_DMA_CH1_7 },
3758 { 0, OMAP_INT_DMA_CH2_8 },
3759 { 0, OMAP_INT_DMA_CH3 },
3760 { 0, OMAP_INT_DMA_CH4 },
3761 { 0, OMAP_INT_DMA_CH5 },
3762 { 1, OMAP_INT_1610_DMA_CH6 },
3763 { 1, OMAP_INT_1610_DMA_CH7 },
3764 { 1, OMAP_INT_1610_DMA_CH8 },
3765 { 1, OMAP_INT_1610_DMA_CH9 },
3766 { 1, OMAP_INT_1610_DMA_CH10 },
3767 { 1, OMAP_INT_1610_DMA_CH11 },
3768 { 1, OMAP_INT_1610_DMA_CH12 },
3769 { 1, OMAP_INT_1610_DMA_CH13 },
3770 { 1, OMAP_INT_1610_DMA_CH14 },
3771 { 1, OMAP_INT_1610_DMA_CH15 }
3772};
3773
b4e3104b
AZ		 3774/* DMA ports for OMAP1 */
3775static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
c227f099 3776 target_phys_addr_t addr)
b4e3104b 3777{
45416789 3778 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
b4e3104b
AZ		 3779}
3780
3781static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
c227f099 3782 target_phys_addr_t addr)
b4e3104b 3783{
45416789
BS		 3784 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
3785 addr);
b4e3104b
AZ		 3786}
3787
3788static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
c227f099 3789 target_phys_addr_t addr)
b4e3104b 3790{
45416789 3791 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
b4e3104b
AZ		 3792}
3793
3794static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
c227f099 3795 target_phys_addr_t addr)
b4e3104b 3796{
45416789 3797 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
b4e3104b
AZ		 3798}
3799
3800static int omap_validate_local_addr(struct omap_mpu_state_s *s,
c227f099 3801 target_phys_addr_t addr)
b4e3104b 3802{
45416789 3803 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
b4e3104b
AZ		 3804}
3805
3806static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
c227f099 3807 target_phys_addr_t addr)
b4e3104b 3808{
45416789 3809 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
b4e3104b
AZ		 3810}
3811
4b3fedf3
AK		 3812struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
3813 unsigned long sdram_size,
3023f332 3814 const char *core)
c3d2689d 3815{
089b7c0a 3816 int i;
c3d2689d 3817 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
7267c094 3818 g_malloc0(sizeof(struct omap_mpu_state_s));
106627d0 3819 qemu_irq *cpu_irq;
089b7c0a 3820 qemu_irq dma_irqs[6];
751c6a17 3821 DriveInfo *dinfo;
0919ac78 3822 SysBusDevice *busdev;
106627d0 3823
aaed909a
FB		 3824 if (!core)
3825 core = "ti925t";
c3d2689d
AZ		 3826
3827 /* Core */
3828 s->mpu_model = omap310;
aaed909a
FB		 3829 s->env = cpu_init(core);
3830 if (!s->env) {
3831 fprintf(stderr, "Unable to find CPU definition\n");
3832 exit(1);
3833 }
c3d2689d
AZ		 3834 s->sdram_size = sdram_size;
3835 s->sram_size = OMAP15XX_SRAM_SIZE;
3836
fe71e81a
AZ		 3837 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
3838
c3d2689d
AZ		 3839 /* Clocks */
3840 omap_clk_init(s);
3841
3842 /* Memory-mapped stuff */
2654c962
AK		 3843 memory_region_init_ram(&s->emiff_ram, NULL, "omap1.dram", s->sdram_size);
3844 memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram);
3845 memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size);
3846 memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
c3d2689d 3847
e7aa0ae0 3848 omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
c3d2689d 3849
106627d0 3850 cpu_irq = arm_pic_init_cpu(s->env);
0919ac78
PM		 3851 s->ih[0] = qdev_create(NULL, "omap-intc");
3852 qdev_prop_set_uint32(s->ih[0], "size", 0x100);
3853 qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck"));
3854 qdev_init_nofail(s->ih[0]);
3855 busdev = sysbus_from_qdev(s->ih[0]);
3856 sysbus_connect_irq(busdev, 0, cpu_irq[ARM_PIC_CPU_IRQ]);
3857 sysbus_connect_irq(busdev, 1, cpu_irq[ARM_PIC_CPU_FIQ]);
3858 sysbus_mmio_map(busdev, 0, 0xfffecb00);
3859 s->ih[1] = qdev_create(NULL, "omap-intc");
3860 qdev_prop_set_uint32(s->ih[1], "size", 0x800);
3861 qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck"));
3862 qdev_init_nofail(s->ih[1]);
3863 busdev = sysbus_from_qdev(s->ih[1]);
3864 sysbus_connect_irq(busdev, 0,
3865 qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
3866 /* The second interrupt controller's FIQ output is not wired up */
3867 sysbus_mmio_map(busdev, 0, 0xfffe0000);
3868
3869 for (i = 0; i < 6; i++) {
3870 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih],
3871 omap1_dma_irq_map[i].intr);
3872 }
7405165e 3873 s->dma = omap_dma_init(0xfffed800, dma_irqs, system_memory,
0919ac78 3874 qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD),
089b7c0a
AZ		 3875 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
3876
c3d2689d
AZ		 3877 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
3878 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
3879 s->port[imif ].addr_valid = omap_validate_imif_addr;
3880 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
3881 s->port[local ].addr_valid = omap_validate_local_addr;
3882 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
3883
afbb5194 3884 /* Register SDRAM and SRAM DMA ports for fast transfers. */
2654c962
AK		 3885 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram),
3886 OMAP_EMIFF_BASE, s->sdram_size);
3887 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram),
90aeba9d 3888 OMAP_IMIF_BASE, s->sram_size);
afbb5194 3889
4b3fedf3 3890 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500,
0919ac78 3891 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1),
c3d2689d 3892 omap_findclk(s, "mputim_ck"));
4b3fedf3 3893 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600,
0919ac78 3894 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2),
c3d2689d 3895 omap_findclk(s, "mputim_ck"));
4b3fedf3 3896 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700,
0919ac78 3897 qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3),
c3d2689d
AZ		 3898 omap_findclk(s, "mputim_ck"));
3899
4b3fedf3 3900 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
0919ac78 3901 qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER),
c3d2689d
AZ		 3902 omap_findclk(s, "armwdt_ck"));
3903
4b3fedf3 3904 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
0919ac78 3905 qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER),
c3d2689d
AZ		 3906 omap_findclk(s, "clk32-kHz"));
3907
30af1ec7 3908 s->lcd = omap_lcdc_init(system_memory, 0xfffec000,
0919ac78
PM		 3909 qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL),
3910 omap_dma_get_lcdch(s->dma),
3911 omap_findclk(s, "lcd_ck"));
c3d2689d 3912
4b3fedf3
AK		 3913 omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
3914 omap_pin_cfg_init(system_memory, 0xfffe1000, s);
3915 omap_id_init(system_memory, s);
c3d2689d 3916
4b3fedf3 3917 omap_mpui_init(system_memory, 0xfffec900, s);
c3d2689d 3918
4b3fedf3 3919 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
0919ac78 3920 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV),
c3d2689d 3921 omap_findclk(s, "tipb_ck"));
4b3fedf3 3922 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
0919ac78 3923 qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB),
c3d2689d
AZ		 3924 omap_findclk(s, "tipb_ck"));
3925
e7aa0ae0 3926 omap_tcmi_init(system_memory, 0xfffecc00, s);
c3d2689d 3927
0919ac78
PM		 3928 s->uart[0] = omap_uart_init(0xfffb0000,
3929 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1),
c3d2689d 3930 omap_findclk(s, "uart1_ck"),
827df9f3
AZ		 3931 omap_findclk(s, "uart1_ck"),
3932 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
6a8aabd3 3933 "uart1",
c3d2689d 3934 serial_hds[0]);
0919ac78
PM		 3935 s->uart[1] = omap_uart_init(0xfffb0800,
3936 qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2),
c3d2689d 3937 omap_findclk(s, "uart2_ck"),
827df9f3
AZ		 3938 omap_findclk(s, "uart2_ck"),
3939 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
6a8aabd3 3940 "uart2",
b9d38e95 3941 serial_hds[0] ? serial_hds[1] : NULL);
0919ac78
PM		 3942 s->uart[2] = omap_uart_init(0xfffb9800,
3943 qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3),
c3d2689d 3944 omap_findclk(s, "uart3_ck"),
827df9f3
AZ		 3945 omap_findclk(s, "uart3_ck"),
3946 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
6a8aabd3 3947 "uart3",
b9d38e95 3948 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
c3d2689d 3949
e7aa0ae0
AK		 3950 omap_dpll_init(system_memory,
3951 &s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
3952 omap_dpll_init(system_memory,
3953 &s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
3954 omap_dpll_init(system_memory,
3955 &s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
c3d2689d 3956
751c6a17
GH		 3957 dinfo = drive_get(IF_SD, 0, 0);
3958 if (!dinfo) {
e4bcb14c
TS		 3959 fprintf(stderr, "qemu: missing SecureDigital device\n");
3960 exit(1);
3961 }
c304fed7 3962 s->mmc = omap_mmc_init(0xfffb7800, system_memory, dinfo->bdrv,
0919ac78
PM		 3963 qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN),
3964 &s->drq[OMAP_DMA_MMC_TX],
9d413d1d 3965 omap_findclk(s, "mmc_ck"));
b30bb3a2 3966
e7aa0ae0 3967 s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000,
0919ac78
PM		 3968 qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD),
3969 qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO),
3970 s->wakeup, omap_findclk(s, "clk32-kHz"));
fe71e81a 3971
77831c20
JR		 3972 s->gpio = qdev_create(NULL, "omap-gpio");
3973 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
bdbc1b3c 3974 qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck"));
77831c20
JR		 3975 qdev_init_nofail(s->gpio);
3976 sysbus_connect_irq(sysbus_from_qdev(s->gpio), 0,
0919ac78 3977 qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
77831c20 3978 sysbus_mmio_map(sysbus_from_qdev(s->gpio), 0, 0xfffce000);
64330148 3979
0919ac78
PM		 3980 s->microwire = omap_uwire_init(system_memory, 0xfffb3000,
3981 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX),
3982 qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX),
d951f6ff
AZ		 3983 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
3984
8717d88a
JR		 3985 s->pwl = omap_pwl_init(system_memory, 0xfffb5800,
3986 omap_findclk(s, "armxor_ck"));
03759534
JR		 3987 s->pwt = omap_pwt_init(system_memory, 0xfffb6000,
3988 omap_findclk(s, "armxor_ck"));
66450b15 3989
74878139 3990 s->i2c[0] = omap_i2c_init(system_memory, 0xfffb3800,
0919ac78 3991 qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C),
4a2c8ac2
AZ		 3992 &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
3993
a4ebbd18 3994 s->rtc = omap_rtc_init(system_memory, 0xfffb4800,
0919ac78
PM		 3995 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER),
3996 qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM),
5c1c390f 3997 omap_findclk(s, "clk32-kHz"));
02645926 3998
0919ac78
PM		 3999 s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800,
4000 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX),
4001 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX),
d8f699cb 4002 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
0919ac78
PM		 4003 s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000,
4004 qdev_get_gpio_in(s->ih[0],
4005 OMAP_INT_310_McBSP2_TX),
4006 qdev_get_gpio_in(s->ih[0],
4007 OMAP_INT_310_McBSP2_RX),
d8f699cb 4008 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
0919ac78
PM		 4009 s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000,
4010 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX),
4011 qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX),
d8f699cb
AZ		 4012 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
4013
60fe76e3
AK		 4014 s->led[0] = omap_lpg_init(system_memory,
4015 0xfffbd000, omap_findclk(s, "clk32-kHz"));
4016 s->led[1] = omap_lpg_init(system_memory,
4017 0xfffbd800, omap_findclk(s, "clk32-kHz"));
f9d43072 4018
02645926 4019 /* Register mappings not currenlty implemented:
02645926
AZ		 4020 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4021 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4022 * USB W2FC fffb4000 - fffb47ff
4023 * Camera Interface fffb6800 - fffb6fff
02645926
AZ		 4024 * USB Host fffba000 - fffba7ff
4025 * FAC fffba800 - fffbafff
4026 * HDQ/1-Wire fffbc000 - fffbc7ff
b854bc19 4027 * TIPB switches fffbc800 - fffbcfff
02645926
AZ		 4028 * Mailbox fffcf000 - fffcf7ff
4029 * Local bus IF fffec100 - fffec1ff
4030 * Local bus MMU fffec200 - fffec2ff
4031 * DSP MMU fffed200 - fffed2ff
4032 */
4033
763b946c 4034 omap_setup_dsp_mapping(system_memory, omap15xx_dsp_mm);
60fe76e3 4035 omap_setup_mpui_io(system_memory, s);
cf965d24 4036
a08d4367 4037 qemu_register_reset(omap1_mpu_reset, s);
c3d2689d
AZ		 4038
4039 return s;
4040}
Qemu copy for testing