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hw/omap2.c : separate sdrc (sdram controller)
[qemu.git] / hw / omap1.c
CommitLineData
c3d2689d
AZ		 1/*
2 * TI OMAP processors emulation.
3 *
b4e3104b 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
c3d2689d
AZ		 5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
827df9f3
AZ		 8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
c3d2689d
AZ		 10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
fad6cb1a 16 * You should have received a copy of the GNU General Public License along
8167ee88 17 * with this program; if not, see <http://www.gnu.org/licenses/>.
c3d2689d 18 */
87ecb68b
PB		 19#include "hw.h"
20#include "arm-misc.h"
21#include "omap.h"
22#include "sysemu.h"
23#include "qemu-timer.h"
827df9f3 24#include "qemu-char.h"
afbb5194 25#include "soc_dma.h"
87ecb68b
PB		 26/* We use pc-style serial ports. */
27#include "pc.h"
c3d2689d 28
827df9f3 29/* Should signal the TCMI/GPMC */
c227f099 30uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
66450b15 31{
02645926
AZ		 32 uint8_t ret;
33
66450b15 34 OMAP_8B_REG(addr);
b854bc19 35 cpu_physical_memory_read(addr, (void *) &ret, 1);
02645926 36 return ret;
66450b15
AZ		 37}
38
c227f099 39void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
66450b15
AZ		 40 uint32_t value)
41{
b854bc19
AZ		 42 uint8_t val8 = value;
43
66450b15 44 OMAP_8B_REG(addr);
b854bc19 45 cpu_physical_memory_write(addr, (void *) &val8, 1);
66450b15
AZ		 46}
47
c227f099 48uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
c3d2689d 49{
b854bc19
AZ		 50 uint16_t ret;
51
c3d2689d 52 OMAP_16B_REG(addr);
b854bc19
AZ		 53 cpu_physical_memory_read(addr, (void *) &ret, 2);
54 return ret;
c3d2689d
AZ		 55}
56
c227f099 57void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 58 uint32_t value)
59{
b854bc19
AZ		 60 uint16_t val16 = value;
61
c3d2689d 62 OMAP_16B_REG(addr);
b854bc19 63 cpu_physical_memory_write(addr, (void *) &val16, 2);
c3d2689d
AZ		 64}
65
c227f099 66uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
c3d2689d 67{
b854bc19
AZ		 68 uint32_t ret;
69
c3d2689d 70 OMAP_32B_REG(addr);
b854bc19
AZ		 71 cpu_physical_memory_read(addr, (void *) &ret, 4);
72 return ret;
c3d2689d
AZ		 73}
74
c227f099 75void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 76 uint32_t value)
77{
78 OMAP_32B_REG(addr);
b854bc19 79 cpu_physical_memory_write(addr, (void *) &value, 4);
c3d2689d
AZ		 80}
81
c3d2689d 82/* Interrupt Handlers */
106627d0 83struct omap_intr_handler_bank_s {
c3d2689d 84 uint32_t irqs;
106627d0 85 uint32_t inputs;
c3d2689d 86 uint32_t mask;
c3d2689d 87 uint32_t fiq;
106627d0 88 uint32_t sens_edge;
827df9f3 89 uint32_t swi;
106627d0 90 unsigned char priority[32];
c3d2689d
AZ		 91};
92
106627d0
AZ		 93struct omap_intr_handler_s {
94 qemu_irq *pins;
95 qemu_irq parent_intr[2];
106627d0 96 unsigned char nbanks;
827df9f3 97 int level_only;
c3d2689d 98
106627d0
AZ		 99 /* state */
100 uint32_t new_agr[2];
101 int sir_intr[2];
827df9f3
AZ		 102 int autoidle;
103 uint32_t mask;
104 struct omap_intr_handler_bank_s bank[];
106627d0 105};
c3d2689d 106
106627d0
AZ		 107static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
108{
109 int i, j, sir_intr, p_intr, p, f;
110 uint32_t level;
111 sir_intr = 0;
112 p_intr = 255;
113
114 /* Find the interrupt line with the highest dynamic priority.
115 * Note: 0 denotes the hightest priority.
116 * If all interrupts have the same priority, the default order is IRQ_N,
117 * IRQ_N-1,...,IRQ_0. */
118 for (j = 0; j < s->nbanks; ++j) {
827df9f3
AZ		 119 level = s->bank[j].irqs & ~s->bank[j].mask &
120 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
106627d0
AZ		 121 for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
122 level >>= f) {
827df9f3 123 p = s->bank[j].priority[i];
106627d0
AZ		 124 if (p <= p_intr) {
125 p_intr = p;
126 sir_intr = 32 * j + i;
127 }
128 f = ffs(level >> 1);
129 }
cfa0b71d 130 }
106627d0 131 s->sir_intr[is_fiq] = sir_intr;
c3d2689d
AZ		 132}
133
106627d0 134static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
c3d2689d 135{
106627d0
AZ		 136 int i;
137 uint32_t has_intr = 0;
c3d2689d 138
106627d0 139 for (i = 0; i < s->nbanks; ++i)
827df9f3
AZ		 140 has_intr |= s->bank[i].irqs & ~s->bank[i].mask &
141 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);
c3d2689d 142
827df9f3 143 if (s->new_agr[is_fiq] & has_intr & s->mask) {
106627d0
AZ		 144 s->new_agr[is_fiq] = 0;
145 omap_inth_sir_update(s, is_fiq);
146 qemu_set_irq(s->parent_intr[is_fiq], 1);
c3d2689d 147 }
c3d2689d
AZ		 148}
149
150#define INT_FALLING_EDGE 0
151#define INT_LOW_LEVEL 1
152
153static void omap_set_intr(void *opaque, int irq, int req)
154{
155 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
156 uint32_t rise;
157
827df9f3 158 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
106627d0
AZ		 159 int n = irq & 31;
160
c3d2689d 161 if (req) {
106627d0
AZ		 162 rise = ~bank->irqs & (1 << n);
163 if (~bank->sens_edge & (1 << n))
827df9f3 164 rise &= ~bank->inputs;
106627d0
AZ		 165
166 bank->inputs |= (1 << n);
167 if (rise) {
168 bank->irqs |= rise;
169 omap_inth_update(ih, 0);
170 omap_inth_update(ih, 1);
171 }
c3d2689d 172 } else {
106627d0
AZ		 173 rise = bank->sens_edge & bank->irqs & (1 << n);
174 bank->irqs &= ~rise;
175 bank->inputs &= ~(1 << n);
c3d2689d
AZ		 176 }
177}
178
827df9f3
AZ		 179/* Simplified version with no edge detection */
180static void omap_set_intr_noedge(void *opaque, int irq, int req)
181{
182 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
183 uint32_t rise;
184
185 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
186 int n = irq & 31;
187
188 if (req) {
189 rise = ~bank->inputs & (1 << n);
190 if (rise) {
191 bank->irqs |= bank->inputs |= rise;
192 omap_inth_update(ih, 0);
193 omap_inth_update(ih, 1);
194 }
195 } else
196 bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
197}
198
c227f099 199static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 200{
201 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
8da3ff18 202 int i, offset = addr;
106627d0
AZ		 203 int bank_no = offset >> 8;
204 int line_no;
827df9f3 205 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
106627d0 206 offset &= 0xff;
c3d2689d
AZ		 207
208 switch (offset) {
209 case 0x00: /* ITR */
106627d0 210 return bank->irqs;
c3d2689d
AZ		 211
212 case 0x04: /* MIR */
106627d0 213 return bank->mask;
c3d2689d
AZ		 214
215 case 0x10: /* SIR_IRQ_CODE */
106627d0
AZ		 216 case 0x14: /* SIR_FIQ_CODE */
217 if (bank_no != 0)
218 break;
219 line_no = s->sir_intr[(offset - 0x10) >> 2];
827df9f3 220 bank = &s->bank[line_no >> 5];
106627d0
AZ		 221 i = line_no & 31;
222 if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
223 bank->irqs &= ~(1 << i);
f2df5260 224 return line_no;
c3d2689d
AZ		 225
226 case 0x18: /* CONTROL_REG */
106627d0
AZ		 227 if (bank_no != 0)
228 break;
c3d2689d
AZ		 229 return 0;
230
231 case 0x1c: /* ILR0 */
232 case 0x20: /* ILR1 */
233 case 0x24: /* ILR2 */
234 case 0x28: /* ILR3 */
235 case 0x2c: /* ILR4 */
236 case 0x30: /* ILR5 */
237 case 0x34: /* ILR6 */
238 case 0x38: /* ILR7 */
239 case 0x3c: /* ILR8 */
240 case 0x40: /* ILR9 */
241 case 0x44: /* ILR10 */
242 case 0x48: /* ILR11 */
243 case 0x4c: /* ILR12 */
244 case 0x50: /* ILR13 */
245 case 0x54: /* ILR14 */
246 case 0x58: /* ILR15 */
247 case 0x5c: /* ILR16 */
248 case 0x60: /* ILR17 */
249 case 0x64: /* ILR18 */
250 case 0x68: /* ILR19 */
251 case 0x6c: /* ILR20 */
252 case 0x70: /* ILR21 */
253 case 0x74: /* ILR22 */
254 case 0x78: /* ILR23 */
255 case 0x7c: /* ILR24 */
256 case 0x80: /* ILR25 */
257 case 0x84: /* ILR26 */
258 case 0x88: /* ILR27 */
259 case 0x8c: /* ILR28 */
260 case 0x90: /* ILR29 */
261 case 0x94: /* ILR30 */
262 case 0x98: /* ILR31 */
263 i = (offset - 0x1c) >> 2;
106627d0
AZ		 264 return (bank->priority[i] << 2) |
265 (((bank->sens_edge >> i) & 1) << 1) |
266 ((bank->fiq >> i) & 1);
c3d2689d
AZ		 267
268 case 0x9c: /* ISR */
269 return 0x00000000;
270
c3d2689d 271 }
106627d0 272 OMAP_BAD_REG(addr);
c3d2689d
AZ		 273 return 0;
274}
275
c227f099 276static void omap_inth_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 277 uint32_t value)
278{
279 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
8da3ff18 280 int i, offset = addr;
106627d0 281 int bank_no = offset >> 8;
827df9f3 282 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
106627d0 283 offset &= 0xff;
c3d2689d
AZ		 284
285 switch (offset) {
286 case 0x00: /* ITR */
106627d0
AZ		 287 /* Important: ignore the clearing if the IRQ is level-triggered and
288 the input bit is 1 */
289 bank->irqs &= value | (bank->inputs & bank->sens_edge);
c3d2689d
AZ		 290 return;
291
292 case 0x04: /* MIR */
106627d0
AZ		 293 bank->mask = value;
294 omap_inth_update(s, 0);
295 omap_inth_update(s, 1);
c3d2689d
AZ		 296 return;
297
298 case 0x10: /* SIR_IRQ_CODE */
299 case 0x14: /* SIR_FIQ_CODE */
300 OMAP_RO_REG(addr);
301 break;
302
303 case 0x18: /* CONTROL_REG */
106627d0
AZ		 304 if (bank_no != 0)
305 break;
306 if (value & 2) {
307 qemu_set_irq(s->parent_intr[1], 0);
308 s->new_agr[1] = ~0;
309 omap_inth_update(s, 1);
310 }
311 if (value & 1) {
312 qemu_set_irq(s->parent_intr[0], 0);
313 s->new_agr[0] = ~0;
314 omap_inth_update(s, 0);
315 }
c3d2689d
AZ		 316 return;
317
318 case 0x1c: /* ILR0 */
319 case 0x20: /* ILR1 */
320 case 0x24: /* ILR2 */
321 case 0x28: /* ILR3 */
322 case 0x2c: /* ILR4 */
323 case 0x30: /* ILR5 */
324 case 0x34: /* ILR6 */
325 case 0x38: /* ILR7 */
326 case 0x3c: /* ILR8 */
327 case 0x40: /* ILR9 */
328 case 0x44: /* ILR10 */
329 case 0x48: /* ILR11 */
330 case 0x4c: /* ILR12 */
331 case 0x50: /* ILR13 */
332 case 0x54: /* ILR14 */
333 case 0x58: /* ILR15 */
334 case 0x5c: /* ILR16 */
335 case 0x60: /* ILR17 */
336 case 0x64: /* ILR18 */
337 case 0x68: /* ILR19 */
338 case 0x6c: /* ILR20 */
339 case 0x70: /* ILR21 */
340 case 0x74: /* ILR22 */
341 case 0x78: /* ILR23 */
342 case 0x7c: /* ILR24 */
343 case 0x80: /* ILR25 */
344 case 0x84: /* ILR26 */
345 case 0x88: /* ILR27 */
346 case 0x8c: /* ILR28 */
347 case 0x90: /* ILR29 */
348 case 0x94: /* ILR30 */
349 case 0x98: /* ILR31 */
350 i = (offset - 0x1c) >> 2;
106627d0
AZ		 351 bank->priority[i] = (value >> 2) & 0x1f;
352 bank->sens_edge &= ~(1 << i);
353 bank->sens_edge |= ((value >> 1) & 1) << i;
354 bank->fiq &= ~(1 << i);
355 bank->fiq |= (value & 1) << i;
c3d2689d
AZ		 356 return;
357
358 case 0x9c: /* ISR */
359 for (i = 0; i < 32; i ++)
360 if (value & (1 << i)) {
106627d0 361 omap_set_intr(s, 32 * bank_no + i, 1);
c3d2689d
AZ		 362 return;
363 }
364 return;
c3d2689d 365 }
106627d0 366 OMAP_BAD_REG(addr);
c3d2689d
AZ		 367}
368
d60efc6b 369static CPUReadMemoryFunc * const omap_inth_readfn[] = {
c3d2689d
AZ		 370 omap_badwidth_read32,
371 omap_badwidth_read32,
372 omap_inth_read,
373};
374
d60efc6b 375static CPUWriteMemoryFunc * const omap_inth_writefn[] = {
c3d2689d
AZ		 376 omap_inth_write,
377 omap_inth_write,
378 omap_inth_write,
379};
380
106627d0 381void omap_inth_reset(struct omap_intr_handler_s *s)
c3d2689d 382{
106627d0
AZ		 383 int i;
384
385 for (i = 0; i < s->nbanks; ++i){
827df9f3
AZ		 386 s->bank[i].irqs = 0x00000000;
387 s->bank[i].mask = 0xffffffff;
388 s->bank[i].sens_edge = 0x00000000;
389 s->bank[i].fiq = 0x00000000;
390 s->bank[i].inputs = 0x00000000;
391 s->bank[i].swi = 0x00000000;
392 memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));
393
394 if (s->level_only)
395 s->bank[i].sens_edge = 0xffffffff;
106627d0 396 }
c3d2689d 397
106627d0
AZ		 398 s->new_agr[0] = ~0;
399 s->new_agr[1] = ~0;
400 s->sir_intr[0] = 0;
401 s->sir_intr[1] = 0;
827df9f3
AZ		 402 s->autoidle = 0;
403 s->mask = ~0;
106627d0
AZ		 404
405 qemu_set_irq(s->parent_intr[0], 0);
406 qemu_set_irq(s->parent_intr[1], 0);
c3d2689d
AZ		 407}
408
c227f099 409struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
827df9f3 410 unsigned long size, unsigned char nbanks, qemu_irq **pins,
106627d0 411 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
c3d2689d
AZ		 412{
413 int iomemtype;
414 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
106627d0
AZ		 415 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
416 sizeof(struct omap_intr_handler_bank_s) * nbanks);
c3d2689d 417
106627d0
AZ		 418 s->parent_intr[0] = parent_irq;
419 s->parent_intr[1] = parent_fiq;
106627d0
AZ		 420 s->nbanks = nbanks;
421 s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
827df9f3
AZ		 422 if (pins)
423 *pins = s->pins;
106627d0 424
c3d2689d
AZ		 425 omap_inth_reset(s);
426
1eed09cb 427 iomemtype = cpu_register_io_memory(omap_inth_readfn,
c3d2689d 428 omap_inth_writefn, s);
8da3ff18 429 cpu_register_physical_memory(base, size, iomemtype);
c3d2689d
AZ		 430
431 return s;
432}
433
c227f099 434static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
827df9f3
AZ		 435{
436 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
8da3ff18 437 int offset = addr;
827df9f3 438 int bank_no, line_no;
b9d38e95 439 struct omap_intr_handler_bank_s *bank = NULL;
827df9f3
AZ		 440
441 if ((offset & 0xf80) == 0x80) {
442 bank_no = (offset & 0x60) >> 5;
443 if (bank_no < s->nbanks) {
444 offset &= ~0x60;
445 bank = &s->bank[bank_no];
446 }
447 }
448
449 switch (offset) {
450 case 0x00: /* INTC_REVISION */
451 return 0x21;
452
453 case 0x10: /* INTC_SYSCONFIG */
454 return (s->autoidle >> 2) & 1;
455
456 case 0x14: /* INTC_SYSSTATUS */
457 return 1; /* RESETDONE */
458
459 case 0x40: /* INTC_SIR_IRQ */
460 return s->sir_intr[0];
461
462 case 0x44: /* INTC_SIR_FIQ */
463 return s->sir_intr[1];
464
465 case 0x48: /* INTC_CONTROL */
466 return (!s->mask) << 2; /* GLOBALMASK */
467
468 case 0x4c: /* INTC_PROTECTION */
469 return 0;
470
471 case 0x50: /* INTC_IDLE */
472 return s->autoidle & 3;
473
474 /* Per-bank registers */
475 case 0x80: /* INTC_ITR */
476 return bank->inputs;
477
478 case 0x84: /* INTC_MIR */
479 return bank->mask;
480
481 case 0x88: /* INTC_MIR_CLEAR */
482 case 0x8c: /* INTC_MIR_SET */
483 return 0;
484
485 case 0x90: /* INTC_ISR_SET */
486 return bank->swi;
487
488 case 0x94: /* INTC_ISR_CLEAR */
489 return 0;
490
491 case 0x98: /* INTC_PENDING_IRQ */
492 return bank->irqs & ~bank->mask & ~bank->fiq;
493
494 case 0x9c: /* INTC_PENDING_FIQ */
495 return bank->irqs & ~bank->mask & bank->fiq;
496
497 /* Per-line registers */
498 case 0x100 ... 0x300: /* INTC_ILR */
499 bank_no = (offset - 0x100) >> 7;
500 if (bank_no > s->nbanks)
501 break;
502 bank = &s->bank[bank_no];
503 line_no = (offset & 0x7f) >> 2;
504 return (bank->priority[line_no] << 2) |
505 ((bank->fiq >> line_no) & 1);
506 }
507 OMAP_BAD_REG(addr);
508 return 0;
509}
510
c227f099 511static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
827df9f3
AZ		 512 uint32_t value)
513{
514 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
8da3ff18 515 int offset = addr;
827df9f3 516 int bank_no, line_no;
b9d38e95 517 struct omap_intr_handler_bank_s *bank = NULL;
827df9f3
AZ		 518
519 if ((offset & 0xf80) == 0x80) {
520 bank_no = (offset & 0x60) >> 5;
521 if (bank_no < s->nbanks) {
522 offset &= ~0x60;
523 bank = &s->bank[bank_no];
524 }
525 }
526
527 switch (offset) {
528 case 0x10: /* INTC_SYSCONFIG */
529 s->autoidle &= 4;
530 s->autoidle |= (value & 1) << 2;
531 if (value & 2) /* SOFTRESET */
532 omap_inth_reset(s);
533 return;
534
535 case 0x48: /* INTC_CONTROL */
536 s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */
537 if (value & 2) { /* NEWFIQAGR */
538 qemu_set_irq(s->parent_intr[1], 0);
539 s->new_agr[1] = ~0;
540 omap_inth_update(s, 1);
541 }
542 if (value & 1) { /* NEWIRQAGR */
543 qemu_set_irq(s->parent_intr[0], 0);
544 s->new_agr[0] = ~0;
545 omap_inth_update(s, 0);
546 }
547 return;
548
549 case 0x4c: /* INTC_PROTECTION */
550 /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
551 * for every register, see Chapter 3 and 4 for privileged mode. */
552 if (value & 1)
553 fprintf(stderr, "%s: protection mode enable attempt\n",
554 __FUNCTION__);
555 return;
556
557 case 0x50: /* INTC_IDLE */
558 s->autoidle &= ~3;
559 s->autoidle |= value & 3;
560 return;
561
562 /* Per-bank registers */
563 case 0x84: /* INTC_MIR */
564 bank->mask = value;
565 omap_inth_update(s, 0);
566 omap_inth_update(s, 1);
567 return;
568
569 case 0x88: /* INTC_MIR_CLEAR */
570 bank->mask &= ~value;
571 omap_inth_update(s, 0);
572 omap_inth_update(s, 1);
573 return;
574
575 case 0x8c: /* INTC_MIR_SET */
576 bank->mask |= value;
577 return;
578
579 case 0x90: /* INTC_ISR_SET */
580 bank->irqs |= bank->swi |= value;
581 omap_inth_update(s, 0);
582 omap_inth_update(s, 1);
583 return;
584
585 case 0x94: /* INTC_ISR_CLEAR */
586 bank->swi &= ~value;
587 bank->irqs = bank->swi & bank->inputs;
588 return;
589
590 /* Per-line registers */
591 case 0x100 ... 0x300: /* INTC_ILR */
592 bank_no = (offset - 0x100) >> 7;
593 if (bank_no > s->nbanks)
594 break;
595 bank = &s->bank[bank_no];
596 line_no = (offset & 0x7f) >> 2;
597 bank->priority[line_no] = (value >> 2) & 0x3f;
598 bank->fiq &= ~(1 << line_no);
599 bank->fiq |= (value & 1) << line_no;
600 return;
601
602 case 0x00: /* INTC_REVISION */
603 case 0x14: /* INTC_SYSSTATUS */
604 case 0x40: /* INTC_SIR_IRQ */
605 case 0x44: /* INTC_SIR_FIQ */
606 case 0x80: /* INTC_ITR */
607 case 0x98: /* INTC_PENDING_IRQ */
608 case 0x9c: /* INTC_PENDING_FIQ */
609 OMAP_RO_REG(addr);
610 return;
611 }
612 OMAP_BAD_REG(addr);
613}
614
d60efc6b 615static CPUReadMemoryFunc * const omap2_inth_readfn[] = {
827df9f3
AZ		 616 omap_badwidth_read32,
617 omap_badwidth_read32,
618 omap2_inth_read,
619};
620
d60efc6b 621static CPUWriteMemoryFunc * const omap2_inth_writefn[] = {
827df9f3
AZ		 622 omap2_inth_write,
623 omap2_inth_write,
624 omap2_inth_write,
625};
626
c227f099 627struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
827df9f3
AZ		 628 int size, int nbanks, qemu_irq **pins,
629 qemu_irq parent_irq, qemu_irq parent_fiq,
630 omap_clk fclk, omap_clk iclk)
631{
632 int iomemtype;
633 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
634 qemu_mallocz(sizeof(struct omap_intr_handler_s) +
635 sizeof(struct omap_intr_handler_bank_s) * nbanks);
636
637 s->parent_intr[0] = parent_irq;
638 s->parent_intr[1] = parent_fiq;
827df9f3
AZ		 639 s->nbanks = nbanks;
640 s->level_only = 1;
641 s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
642 if (pins)
643 *pins = s->pins;
644
645 omap_inth_reset(s);
646
1eed09cb 647 iomemtype = cpu_register_io_memory(omap2_inth_readfn,
827df9f3 648 omap2_inth_writefn, s);
8da3ff18 649 cpu_register_physical_memory(base, size, iomemtype);
827df9f3
AZ		 650
651 return s;
652}
653
c3d2689d
AZ		 654/* MPU OS timers */
655struct omap_mpu_timer_s {
656 qemu_irq irq;
657 omap_clk clk;
c3d2689d
AZ		 658 uint32_t val;
659 int64_t time;
660 QEMUTimer *timer;
e856f2ad 661 QEMUBH *tick;
c3d2689d
AZ		 662 int64_t rate;
663 int it_ena;
664
665 int enable;
666 int ptv;
667 int ar;
668 int st;
669 uint32_t reset_val;
670};
671
672static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
673{
674 uint64_t distance = qemu_get_clock(vm_clock) - timer->time;
675
676 if (timer->st && timer->enable && timer->rate)
677 return timer->val - muldiv64(distance >> (timer->ptv + 1),
6ee093c9 678 timer->rate, get_ticks_per_sec());
c3d2689d
AZ		 679 else
680 return timer->val;
681}
682
683static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
684{
685 timer->val = omap_timer_read(timer);
686 timer->time = qemu_get_clock(vm_clock);
687}
688
689static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
690{
691 int64_t expires;
692
693 if (timer->enable && timer->st && timer->rate) {
694 timer->val = timer->reset_val; /* Should skip this on clk enable */
b8b137d6 695 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
6ee093c9 696 get_ticks_per_sec(), timer->rate);
b854bc19
AZ		 697
698 /* If timer expiry would be sooner than in about 1 ms and
699 * auto-reload isn't set, then fire immediately. This is a hack
700 * to make systems like PalmOS run in acceptable time. PalmOS
701 * sets the interval to a very low value and polls the status bit
702 * in a busy loop when it wants to sleep just a couple of CPU
703 * ticks. */
6ee093c9 704 if (expires > (get_ticks_per_sec() >> 10) || timer->ar)
b854bc19 705 qemu_mod_timer(timer->timer, timer->time + expires);
e856f2ad
AZ		 706 else
707 qemu_bh_schedule(timer->tick);
c3d2689d
AZ		 708 } else
709 qemu_del_timer(timer->timer);
710}
711
e856f2ad 712static void omap_timer_fire(void *opaque)
c3d2689d 713{
e856f2ad 714 struct omap_mpu_timer_s *timer = opaque;
c3d2689d
AZ		 715
716 if (!timer->ar) {
717 timer->val = 0;
718 timer->st = 0;
719 }
720
721 if (timer->it_ena)
106627d0
AZ		 722 /* Edge-triggered irq */
723 qemu_irq_pulse(timer->irq);
e856f2ad
AZ		 724}
725
726static void omap_timer_tick(void *opaque)
727{
728 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
729
730 omap_timer_sync(timer);
731 omap_timer_fire(timer);
c3d2689d
AZ		 732 omap_timer_update(timer);
733}
734
735static void omap_timer_clk_update(void *opaque, int line, int on)
736{
737 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
738
739 omap_timer_sync(timer);
740 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
741 omap_timer_update(timer);
742}
743
744static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
745{
746 omap_clk_adduser(timer->clk,
747 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
748 timer->rate = omap_clk_getrate(timer->clk);
749}
750
c227f099 751static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 752{
753 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
c3d2689d 754
8da3ff18 755 switch (addr) {
c3d2689d
AZ		 756 case 0x00: /* CNTL_TIMER */
757 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
758
759 case 0x04: /* LOAD_TIM */
760 break;
761
762 case 0x08: /* READ_TIM */
763 return omap_timer_read(s);
764 }
765
766 OMAP_BAD_REG(addr);
767 return 0;
768}
769
c227f099 770static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 771 uint32_t value)
772{
773 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
c3d2689d 774
8da3ff18 775 switch (addr) {
c3d2689d
AZ		 776 case 0x00: /* CNTL_TIMER */
777 omap_timer_sync(s);
778 s->enable = (value >> 5) & 1;
779 s->ptv = (value >> 2) & 7;
780 s->ar = (value >> 1) & 1;
781 s->st = value & 1;
782 omap_timer_update(s);
783 return;
784
785 case 0x04: /* LOAD_TIM */
786 s->reset_val = value;
787 return;
788
789 case 0x08: /* READ_TIM */
790 OMAP_RO_REG(addr);
791 break;
792
793 default:
794 OMAP_BAD_REG(addr);
795 }
796}
797
d60efc6b 798static CPUReadMemoryFunc * const omap_mpu_timer_readfn[] = {
c3d2689d
AZ		 799 omap_badwidth_read32,
800 omap_badwidth_read32,
801 omap_mpu_timer_read,
802};
803
d60efc6b 804static CPUWriteMemoryFunc * const omap_mpu_timer_writefn[] = {
c3d2689d
AZ		 805 omap_badwidth_write32,
806 omap_badwidth_write32,
807 omap_mpu_timer_write,
808};
809
810static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
811{
812 qemu_del_timer(s->timer);
813 s->enable = 0;
814 s->reset_val = 31337;
815 s->val = 0;
816 s->ptv = 0;
817 s->ar = 0;
818 s->st = 0;
819 s->it_ena = 1;
820}
821
c227f099 822struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
c3d2689d
AZ		 823 qemu_irq irq, omap_clk clk)
824{
825 int iomemtype;
826 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
827 qemu_mallocz(sizeof(struct omap_mpu_timer_s));
828
829 s->irq = irq;
830 s->clk = clk;
c3d2689d 831 s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s);
e856f2ad 832 s->tick = qemu_bh_new(omap_timer_fire, s);
c3d2689d
AZ		 833 omap_mpu_timer_reset(s);
834 omap_timer_clk_setup(s);
835
1eed09cb 836 iomemtype = cpu_register_io_memory(omap_mpu_timer_readfn,
c3d2689d 837 omap_mpu_timer_writefn, s);
8da3ff18 838 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 839
840 return s;
841}
842
843/* Watchdog timer */
844struct omap_watchdog_timer_s {
845 struct omap_mpu_timer_s timer;
846 uint8_t last_wr;
847 int mode;
848 int free;
849 int reset;
850};
851
c227f099 852static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 853{
854 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
c3d2689d 855
8da3ff18 856 switch (addr) {
c3d2689d
AZ		 857 case 0x00: /* CNTL_TIMER */
858 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
859 (s->timer.st << 7) | (s->free << 1);
860
861 case 0x04: /* READ_TIMER */
862 return omap_timer_read(&s->timer);
863
864 case 0x08: /* TIMER_MODE */
865 return s->mode << 15;
866 }
867
868 OMAP_BAD_REG(addr);
869 return 0;
870}
871
c227f099 872static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 873 uint32_t value)
874{
875 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
c3d2689d 876
8da3ff18 877 switch (addr) {
c3d2689d
AZ		 878 case 0x00: /* CNTL_TIMER */
879 omap_timer_sync(&s->timer);
880 s->timer.ptv = (value >> 9) & 7;
881 s->timer.ar = (value >> 8) & 1;
882 s->timer.st = (value >> 7) & 1;
883 s->free = (value >> 1) & 1;
884 omap_timer_update(&s->timer);
885 break;
886
887 case 0x04: /* LOAD_TIMER */
888 s->timer.reset_val = value & 0xffff;
889 break;
890
891 case 0x08: /* TIMER_MODE */
892 if (!s->mode && ((value >> 15) & 1))
893 omap_clk_get(s->timer.clk);
894 s->mode |= (value >> 15) & 1;
895 if (s->last_wr == 0xf5) {
896 if ((value & 0xff) == 0xa0) {
d8f699cb
AZ		 897 if (s->mode) {
898 s->mode = 0;
899 omap_clk_put(s->timer.clk);
900 }
c3d2689d
AZ		 901 } else {
902 /* XXX: on T|E hardware somehow this has no effect,
903 * on Zire 71 it works as specified. */
904 s->reset = 1;
905 qemu_system_reset_request();
906 }
907 }
908 s->last_wr = value & 0xff;
909 break;
910
911 default:
912 OMAP_BAD_REG(addr);
913 }
914}
915
d60efc6b 916static CPUReadMemoryFunc * const omap_wd_timer_readfn[] = {
c3d2689d
AZ		 917 omap_badwidth_read16,
918 omap_wd_timer_read,
919 omap_badwidth_read16,
920};
921
d60efc6b 922static CPUWriteMemoryFunc * const omap_wd_timer_writefn[] = {
c3d2689d
AZ		 923 omap_badwidth_write16,
924 omap_wd_timer_write,
925 omap_badwidth_write16,
926};
927
928static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
929{
930 qemu_del_timer(s->timer.timer);
931 if (!s->mode)
932 omap_clk_get(s->timer.clk);
933 s->mode = 1;
934 s->free = 1;
935 s->reset = 0;
936 s->timer.enable = 1;
937 s->timer.it_ena = 1;
938 s->timer.reset_val = 0xffff;
939 s->timer.val = 0;
940 s->timer.st = 0;
941 s->timer.ptv = 0;
942 s->timer.ar = 0;
943 omap_timer_update(&s->timer);
944}
945
c227f099 946struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
c3d2689d
AZ		 947 qemu_irq irq, omap_clk clk)
948{
949 int iomemtype;
950 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
951 qemu_mallocz(sizeof(struct omap_watchdog_timer_s));
952
953 s->timer.irq = irq;
954 s->timer.clk = clk;
c3d2689d
AZ		 955 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
956 omap_wd_timer_reset(s);
957 omap_timer_clk_setup(&s->timer);
958
1eed09cb 959 iomemtype = cpu_register_io_memory(omap_wd_timer_readfn,
c3d2689d 960 omap_wd_timer_writefn, s);
8da3ff18 961 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 962
963 return s;
964}
965
966/* 32-kHz timer */
967struct omap_32khz_timer_s {
968 struct omap_mpu_timer_s timer;
969};
970
c227f099 971static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 972{
973 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
cf965d24 974 int offset = addr & OMAP_MPUI_REG_MASK;
c3d2689d
AZ		 975
976 switch (offset) {
977 case 0x00: /* TVR */
978 return s->timer.reset_val;
979
980 case 0x04: /* TCR */
981 return omap_timer_read(&s->timer);
982
983 case 0x08: /* CR */
984 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
985
986 default:
987 break;
988 }
989 OMAP_BAD_REG(addr);
990 return 0;
991}
992
c227f099 993static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 994 uint32_t value)
995{
996 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
cf965d24 997 int offset = addr & OMAP_MPUI_REG_MASK;
c3d2689d
AZ		 998
999 switch (offset) {
1000 case 0x00: /* TVR */
1001 s->timer.reset_val = value & 0x00ffffff;
1002 break;
1003
1004 case 0x04: /* TCR */
1005 OMAP_RO_REG(addr);
1006 break;
1007
1008 case 0x08: /* CR */
1009 s->timer.ar = (value >> 3) & 1;
1010 s->timer.it_ena = (value >> 2) & 1;
1011 if (s->timer.st != (value & 1) || (value & 2)) {
1012 omap_timer_sync(&s->timer);
1013 s->timer.enable = value & 1;
1014 s->timer.st = value & 1;
1015 omap_timer_update(&s->timer);
1016 }
1017 break;
1018
1019 default:
1020 OMAP_BAD_REG(addr);
1021 }
1022}
1023
d60efc6b 1024static CPUReadMemoryFunc * const omap_os_timer_readfn[] = {
c3d2689d
AZ		 1025 omap_badwidth_read32,
1026 omap_badwidth_read32,
1027 omap_os_timer_read,
1028};
1029
d60efc6b 1030static CPUWriteMemoryFunc * const omap_os_timer_writefn[] = {
c3d2689d
AZ		 1031 omap_badwidth_write32,
1032 omap_badwidth_write32,
1033 omap_os_timer_write,
1034};
1035
1036static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
1037{
1038 qemu_del_timer(s->timer.timer);
1039 s->timer.enable = 0;
1040 s->timer.it_ena = 0;
1041 s->timer.reset_val = 0x00ffffff;
1042 s->timer.val = 0;
1043 s->timer.st = 0;
1044 s->timer.ptv = 0;
1045 s->timer.ar = 1;
1046}
1047
c227f099 1048struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
c3d2689d
AZ		 1049 qemu_irq irq, omap_clk clk)
1050{
1051 int iomemtype;
1052 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
1053 qemu_mallocz(sizeof(struct omap_32khz_timer_s));
1054
1055 s->timer.irq = irq;
1056 s->timer.clk = clk;
c3d2689d
AZ		 1057 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
1058 omap_os_timer_reset(s);
1059 omap_timer_clk_setup(&s->timer);
1060
1eed09cb 1061 iomemtype = cpu_register_io_memory(omap_os_timer_readfn,
c3d2689d 1062 omap_os_timer_writefn, s);
8da3ff18 1063 cpu_register_physical_memory(base, 0x800, iomemtype);
c3d2689d
AZ		 1064
1065 return s;
1066}
1067
1068/* Ultra Low-Power Device Module */
c227f099 1069static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1070{
1071 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1072 uint16_t ret;
1073
8da3ff18 1074 switch (addr) {
c3d2689d 1075 case 0x14: /* IT_STATUS */
8da3ff18
PB		 1076 ret = s->ulpd_pm_regs[addr >> 2];
1077 s->ulpd_pm_regs[addr >> 2] = 0;
c3d2689d
AZ		 1078 qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
1079 return ret;
1080
1081 case 0x18: /* Reserved */
1082 case 0x1c: /* Reserved */
1083 case 0x20: /* Reserved */
1084 case 0x28: /* Reserved */
1085 case 0x2c: /* Reserved */
1086 OMAP_BAD_REG(addr);
1087 case 0x00: /* COUNTER_32_LSB */
1088 case 0x04: /* COUNTER_32_MSB */
1089 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1090 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1091 case 0x10: /* GAUGING_CTRL */
1092 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1093 case 0x30: /* CLOCK_CTRL */
1094 case 0x34: /* SOFT_REQ */
1095 case 0x38: /* COUNTER_32_FIQ */
1096 case 0x3c: /* DPLL_CTRL */
1097 case 0x40: /* STATUS_REQ */
1098 /* XXX: check clk::usecount state for every clock */
1099 case 0x48: /* LOCL_TIME */
1100 case 0x4c: /* APLL_CTRL */
1101 case 0x50: /* POWER_CTRL */
8da3ff18 1102 return s->ulpd_pm_regs[addr >> 2];
c3d2689d
AZ		 1103 }
1104
1105 OMAP_BAD_REG(addr);
1106 return 0;
1107}
1108
1109static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
1110 uint16_t diff, uint16_t value)
1111{
1112 if (diff & (1 << 4)) /* USB_MCLK_EN */
1113 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
1114 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
1115 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
1116}
1117
1118static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
1119 uint16_t diff, uint16_t value)
1120{
1121 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
1122 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
1123 if (diff & (1 << 1)) /* SOFT_COM_REQ */
1124 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
1125 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
1126 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
1127 if (diff & (1 << 3)) /* SOFT_USB_REQ */
1128 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
1129}
1130
c227f099 1131static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1132 uint32_t value)
1133{
1134 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1135 int64_t now, ticks;
1136 int div, mult;
1137 static const int bypass_div[4] = { 1, 2, 4, 4 };
1138 uint16_t diff;
1139
8da3ff18 1140 switch (addr) {
c3d2689d
AZ		 1141 case 0x00: /* COUNTER_32_LSB */
1142 case 0x04: /* COUNTER_32_MSB */
1143 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1144 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1145 case 0x14: /* IT_STATUS */
1146 case 0x40: /* STATUS_REQ */
1147 OMAP_RO_REG(addr);
1148 break;
1149
1150 case 0x10: /* GAUGING_CTRL */
1151 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
8da3ff18 1152 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
c3d2689d
AZ		 1153 now = qemu_get_clock(vm_clock);
1154
1155 if (value & 1)
1156 s->ulpd_gauge_start = now;
1157 else {
1158 now -= s->ulpd_gauge_start;
1159
1160 /* 32-kHz ticks */
6ee093c9 1161 ticks = muldiv64(now, 32768, get_ticks_per_sec());
c3d2689d
AZ		 1162 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
1163 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
1164 if (ticks >> 32) /* OVERFLOW_32K */
1165 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
1166
1167 /* High frequency ticks */
6ee093c9 1168 ticks = muldiv64(now, 12000000, get_ticks_per_sec());
c3d2689d
AZ		 1169 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
1170 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
1171 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
1172 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
1173
1174 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
1175 qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
1176 }
1177 }
8da3ff18 1178 s->ulpd_pm_regs[addr >> 2] = value;
c3d2689d
AZ		 1179 break;
1180
1181 case 0x18: /* Reserved */
1182 case 0x1c: /* Reserved */
1183 case 0x20: /* Reserved */
1184 case 0x28: /* Reserved */
1185 case 0x2c: /* Reserved */
1186 OMAP_BAD_REG(addr);
1187 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1188 case 0x38: /* COUNTER_32_FIQ */
1189 case 0x48: /* LOCL_TIME */
1190 case 0x50: /* POWER_CTRL */
8da3ff18 1191 s->ulpd_pm_regs[addr >> 2] = value;
c3d2689d
AZ		 1192 break;
1193
1194 case 0x30: /* CLOCK_CTRL */
8da3ff18
PB		 1195 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
1196 s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
c3d2689d
AZ		 1197 omap_ulpd_clk_update(s, diff, value);
1198 break;
1199
1200 case 0x34: /* SOFT_REQ */
8da3ff18
PB		 1201 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
1202 s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
c3d2689d
AZ		 1203 omap_ulpd_req_update(s, diff, value);
1204 break;
1205
1206 case 0x3c: /* DPLL_CTRL */
1207 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
1208 * omitted altogether, probably a typo. */
1209 /* This register has identical semantics with DPLL(1:3) control
1210 * registers, see omap_dpll_write() */
8da3ff18
PB		 1211 diff = s->ulpd_pm_regs[addr >> 2] & value;
1212 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
c3d2689d
AZ		 1213 if (diff & (0x3ff << 2)) {
1214 if (value & (1 << 4)) { /* PLL_ENABLE */
1215 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1216 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1217 } else {
1218 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1219 mult = 1;
1220 }
1221 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
1222 }
1223
1224 /* Enter the desired mode. */
8da3ff18
PB		 1225 s->ulpd_pm_regs[addr >> 2] =
1226 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
1227 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
c3d2689d
AZ		 1228
1229 /* Act as if the lock is restored. */
8da3ff18 1230 s->ulpd_pm_regs[addr >> 2] |= 2;
c3d2689d
AZ		 1231 break;
1232
1233 case 0x4c: /* APLL_CTRL */
8da3ff18
PB		 1234 diff = s->ulpd_pm_regs[addr >> 2] & value;
1235 s->ulpd_pm_regs[addr >> 2] = value & 0xf;
c3d2689d
AZ		 1236 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
1237 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
1238 (value & (1 << 0)) ? "apll" : "dpll4"));
1239 break;
1240
1241 default:
1242 OMAP_BAD_REG(addr);
1243 }
1244}
1245
d60efc6b 1246static CPUReadMemoryFunc * const omap_ulpd_pm_readfn[] = {
c3d2689d
AZ		 1247 omap_badwidth_read16,
1248 omap_ulpd_pm_read,
1249 omap_badwidth_read16,
1250};
1251
d60efc6b 1252static CPUWriteMemoryFunc * const omap_ulpd_pm_writefn[] = {
c3d2689d
AZ		 1253 omap_badwidth_write16,
1254 omap_ulpd_pm_write,
1255 omap_badwidth_write16,
1256};
1257
1258static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
1259{
1260 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
1261 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
1262 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
1263 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
1264 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
1265 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
1266 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
1267 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
1268 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
1269 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
1270 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
1271 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
1272 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
1273 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
1274 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
1275 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
1276 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
1277 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
1278 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
1279 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
1280 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
1281 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
1282 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
1283}
1284
c227f099 1285static void omap_ulpd_pm_init(target_phys_addr_t base,
c3d2689d
AZ		 1286 struct omap_mpu_state_s *mpu)
1287{
1eed09cb 1288 int iomemtype = cpu_register_io_memory(omap_ulpd_pm_readfn,
c3d2689d
AZ		 1289 omap_ulpd_pm_writefn, mpu);
1290
8da3ff18 1291 cpu_register_physical_memory(base, 0x800, iomemtype);
c3d2689d
AZ		 1292 omap_ulpd_pm_reset(mpu);
1293}
1294
1295/* OMAP Pin Configuration */
c227f099 1296static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1297{
1298 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1299
8da3ff18 1300 switch (addr) {
c3d2689d
AZ		 1301 case 0x00: /* FUNC_MUX_CTRL_0 */
1302 case 0x04: /* FUNC_MUX_CTRL_1 */
1303 case 0x08: /* FUNC_MUX_CTRL_2 */
8da3ff18 1304 return s->func_mux_ctrl[addr >> 2];
c3d2689d
AZ		 1305
1306 case 0x0c: /* COMP_MODE_CTRL_0 */
1307 return s->comp_mode_ctrl[0];
1308
1309 case 0x10: /* FUNC_MUX_CTRL_3 */
1310 case 0x14: /* FUNC_MUX_CTRL_4 */
1311 case 0x18: /* FUNC_MUX_CTRL_5 */
1312 case 0x1c: /* FUNC_MUX_CTRL_6 */
1313 case 0x20: /* FUNC_MUX_CTRL_7 */
1314 case 0x24: /* FUNC_MUX_CTRL_8 */
1315 case 0x28: /* FUNC_MUX_CTRL_9 */
1316 case 0x2c: /* FUNC_MUX_CTRL_A */
1317 case 0x30: /* FUNC_MUX_CTRL_B */
1318 case 0x34: /* FUNC_MUX_CTRL_C */
1319 case 0x38: /* FUNC_MUX_CTRL_D */
8da3ff18 1320 return s->func_mux_ctrl[(addr >> 2) - 1];
c3d2689d
AZ		 1321
1322 case 0x40: /* PULL_DWN_CTRL_0 */
1323 case 0x44: /* PULL_DWN_CTRL_1 */
1324 case 0x48: /* PULL_DWN_CTRL_2 */
1325 case 0x4c: /* PULL_DWN_CTRL_3 */
8da3ff18 1326 return s->pull_dwn_ctrl[(addr & 0xf) >> 2];
c3d2689d
AZ		 1327
1328 case 0x50: /* GATE_INH_CTRL_0 */
1329 return s->gate_inh_ctrl[0];
1330
1331 case 0x60: /* VOLTAGE_CTRL_0 */
1332 return s->voltage_ctrl[0];
1333
1334 case 0x70: /* TEST_DBG_CTRL_0 */
1335 return s->test_dbg_ctrl[0];
1336
1337 case 0x80: /* MOD_CONF_CTRL_0 */
1338 return s->mod_conf_ctrl[0];
1339 }
1340
1341 OMAP_BAD_REG(addr);
1342 return 0;
1343}
1344
1345static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
1346 uint32_t diff, uint32_t value)
1347{
1348 if (s->compat1509) {
1349 if (diff & (1 << 9)) /* BLUETOOTH */
1350 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
1351 (~value >> 9) & 1);
1352 if (diff & (1 << 7)) /* USB.CLKO */
1353 omap_clk_onoff(omap_findclk(s, "usb.clko"),
1354 (value >> 7) & 1);
1355 }
1356}
1357
1358static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
1359 uint32_t diff, uint32_t value)
1360{
1361 if (s->compat1509) {
1362 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
1363 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
1364 (value >> 31) & 1);
1365 if (diff & (1 << 1)) /* CLK32K */
1366 omap_clk_onoff(omap_findclk(s, "clk32k_out"),
1367 (~value >> 1) & 1);
1368 }
1369}
1370
1371static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
1372 uint32_t diff, uint32_t value)
1373{
1374 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
1375 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
1376 omap_findclk(s, ((value >> 31) & 1) ?
1377 "ck_48m" : "armper_ck"));
1378 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
1379 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
1380 omap_findclk(s, ((value >> 30) & 1) ?
1381 "ck_48m" : "armper_ck"));
1382 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
1383 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
1384 omap_findclk(s, ((value >> 29) & 1) ?
1385 "ck_48m" : "armper_ck"));
1386 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
1387 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
1388 omap_findclk(s, ((value >> 23) & 1) ?
1389 "ck_48m" : "armper_ck"));
1390 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
1391 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
1392 omap_findclk(s, ((value >> 12) & 1) ?
1393 "ck_48m" : "armper_ck"));
1394 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
1395 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
1396}
1397
c227f099 1398static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1399 uint32_t value)
1400{
1401 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1402 uint32_t diff;
1403
8da3ff18 1404 switch (addr) {
c3d2689d 1405 case 0x00: /* FUNC_MUX_CTRL_0 */
8da3ff18
PB		 1406 diff = s->func_mux_ctrl[addr >> 2] ^ value;
1407 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 1408 omap_pin_funcmux0_update(s, diff, value);
1409 return;
1410
1411 case 0x04: /* FUNC_MUX_CTRL_1 */
8da3ff18
PB		 1412 diff = s->func_mux_ctrl[addr >> 2] ^ value;
1413 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 1414 omap_pin_funcmux1_update(s, diff, value);
1415 return;
1416
1417 case 0x08: /* FUNC_MUX_CTRL_2 */
8da3ff18 1418 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 1419 return;
1420
1421 case 0x0c: /* COMP_MODE_CTRL_0 */
1422 s->comp_mode_ctrl[0] = value;
1423 s->compat1509 = (value != 0x0000eaef);
1424 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
1425 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
1426 return;
1427
1428 case 0x10: /* FUNC_MUX_CTRL_3 */
1429 case 0x14: /* FUNC_MUX_CTRL_4 */
1430 case 0x18: /* FUNC_MUX_CTRL_5 */
1431 case 0x1c: /* FUNC_MUX_CTRL_6 */
1432 case 0x20: /* FUNC_MUX_CTRL_7 */
1433 case 0x24: /* FUNC_MUX_CTRL_8 */
1434 case 0x28: /* FUNC_MUX_CTRL_9 */
1435 case 0x2c: /* FUNC_MUX_CTRL_A */
1436 case 0x30: /* FUNC_MUX_CTRL_B */
1437 case 0x34: /* FUNC_MUX_CTRL_C */
1438 case 0x38: /* FUNC_MUX_CTRL_D */
8da3ff18 1439 s->func_mux_ctrl[(addr >> 2) - 1] = value;
c3d2689d
AZ		 1440 return;
1441
1442 case 0x40: /* PULL_DWN_CTRL_0 */
1443 case 0x44: /* PULL_DWN_CTRL_1 */
1444 case 0x48: /* PULL_DWN_CTRL_2 */
1445 case 0x4c: /* PULL_DWN_CTRL_3 */
8da3ff18 1446 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value;
c3d2689d
AZ		 1447 return;
1448
1449 case 0x50: /* GATE_INH_CTRL_0 */
1450 s->gate_inh_ctrl[0] = value;
1451 return;
1452
1453 case 0x60: /* VOLTAGE_CTRL_0 */
1454 s->voltage_ctrl[0] = value;
1455 return;
1456
1457 case 0x70: /* TEST_DBG_CTRL_0 */
1458 s->test_dbg_ctrl[0] = value;
1459 return;
1460
1461 case 0x80: /* MOD_CONF_CTRL_0 */
1462 diff = s->mod_conf_ctrl[0] ^ value;
1463 s->mod_conf_ctrl[0] = value;
1464 omap_pin_modconf1_update(s, diff, value);
1465 return;
1466
1467 default:
1468 OMAP_BAD_REG(addr);
1469 }
1470}
1471
d60efc6b 1472static CPUReadMemoryFunc * const omap_pin_cfg_readfn[] = {
c3d2689d
AZ		 1473 omap_badwidth_read32,
1474 omap_badwidth_read32,
1475 omap_pin_cfg_read,
1476};
1477
d60efc6b 1478static CPUWriteMemoryFunc * const omap_pin_cfg_writefn[] = {
c3d2689d
AZ		 1479 omap_badwidth_write32,
1480 omap_badwidth_write32,
1481 omap_pin_cfg_write,
1482};
1483
1484static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
1485{
1486 /* Start in Compatibility Mode. */
1487 mpu->compat1509 = 1;
1488 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
1489 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
1490 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
1491 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
1492 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
1493 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
1494 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
1495 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
1496 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
1497 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
1498}
1499
c227f099 1500static void omap_pin_cfg_init(target_phys_addr_t base,
c3d2689d
AZ		 1501 struct omap_mpu_state_s *mpu)
1502{
1eed09cb 1503 int iomemtype = cpu_register_io_memory(omap_pin_cfg_readfn,
c3d2689d
AZ		 1504 omap_pin_cfg_writefn, mpu);
1505
8da3ff18 1506 cpu_register_physical_memory(base, 0x800, iomemtype);
c3d2689d
AZ		 1507 omap_pin_cfg_reset(mpu);
1508}
1509
1510/* Device Identification, Die Identification */
c227f099 1511static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1512{
1513 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1514
1515 switch (addr) {
1516 case 0xfffe1800: /* DIE_ID_LSB */
1517 return 0xc9581f0e;
1518 case 0xfffe1804: /* DIE_ID_MSB */
1519 return 0xa8858bfa;
1520
1521 case 0xfffe2000: /* PRODUCT_ID_LSB */
1522 return 0x00aaaafc;
1523 case 0xfffe2004: /* PRODUCT_ID_MSB */
1524 return 0xcafeb574;
1525
1526 case 0xfffed400: /* JTAG_ID_LSB */
1527 switch (s->mpu_model) {
1528 case omap310:
1529 return 0x03310315;
1530 case omap1510:
1531 return 0x03310115;
827df9f3 1532 default:
2ac71179 1533 hw_error("%s: bad mpu model\n", __FUNCTION__);
c3d2689d
AZ		 1534 }
1535 break;
1536
1537 case 0xfffed404: /* JTAG_ID_MSB */
1538 switch (s->mpu_model) {
1539 case omap310:
1540 return 0xfb57402f;
1541 case omap1510:
1542 return 0xfb47002f;
827df9f3 1543 default:
2ac71179 1544 hw_error("%s: bad mpu model\n", __FUNCTION__);
c3d2689d
AZ		 1545 }
1546 break;
1547 }
1548
1549 OMAP_BAD_REG(addr);
1550 return 0;
1551}
1552
c227f099 1553static void omap_id_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1554 uint32_t value)
1555{
1556 OMAP_BAD_REG(addr);
1557}
1558
d60efc6b 1559static CPUReadMemoryFunc * const omap_id_readfn[] = {
c3d2689d
AZ		 1560 omap_badwidth_read32,
1561 omap_badwidth_read32,
1562 omap_id_read,
1563};
1564
d60efc6b 1565static CPUWriteMemoryFunc * const omap_id_writefn[] = {
c3d2689d
AZ		 1566 omap_badwidth_write32,
1567 omap_badwidth_write32,
1568 omap_id_write,
1569};
1570
1571static void omap_id_init(struct omap_mpu_state_s *mpu)
1572{
1eed09cb 1573 int iomemtype = cpu_register_io_memory(omap_id_readfn,
c3d2689d 1574 omap_id_writefn, mpu);
8da3ff18
PB		 1575 cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800);
1576 cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400);
c3d2689d 1577 if (!cpu_is_omap15xx(mpu))
8da3ff18 1578 cpu_register_physical_memory_offset(0xfffe2000, 0x800, iomemtype, 0xfffe2000);
c3d2689d
AZ		 1579}
1580
1581/* MPUI Control (Dummy) */
c227f099 1582static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1583{
1584 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1585
8da3ff18 1586 switch (addr) {
c3d2689d
AZ		 1587 case 0x00: /* CTRL */
1588 return s->mpui_ctrl;
1589 case 0x04: /* DEBUG_ADDR */
1590 return 0x01ffffff;
1591 case 0x08: /* DEBUG_DATA */
1592 return 0xffffffff;
1593 case 0x0c: /* DEBUG_FLAG */
1594 return 0x00000800;
1595 case 0x10: /* STATUS */
1596 return 0x00000000;
1597
1598 /* Not in OMAP310 */
1599 case 0x14: /* DSP_STATUS */
1600 case 0x18: /* DSP_BOOT_CONFIG */
1601 return 0x00000000;
1602 case 0x1c: /* DSP_MPUI_CONFIG */
1603 return 0x0000ffff;
1604 }
1605
1606 OMAP_BAD_REG(addr);
1607 return 0;
1608}
1609
c227f099 1610static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1611 uint32_t value)
1612{
1613 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1614
8da3ff18 1615 switch (addr) {
c3d2689d
AZ		 1616 case 0x00: /* CTRL */
1617 s->mpui_ctrl = value & 0x007fffff;
1618 break;
1619
1620 case 0x04: /* DEBUG_ADDR */
1621 case 0x08: /* DEBUG_DATA */
1622 case 0x0c: /* DEBUG_FLAG */
1623 case 0x10: /* STATUS */
1624 /* Not in OMAP310 */
1625 case 0x14: /* DSP_STATUS */
1626 OMAP_RO_REG(addr);
1627 case 0x18: /* DSP_BOOT_CONFIG */
1628 case 0x1c: /* DSP_MPUI_CONFIG */
1629 break;
1630
1631 default:
1632 OMAP_BAD_REG(addr);
1633 }
1634}
1635
d60efc6b 1636static CPUReadMemoryFunc * const omap_mpui_readfn[] = {
c3d2689d
AZ		 1637 omap_badwidth_read32,
1638 omap_badwidth_read32,
1639 omap_mpui_read,
1640};
1641
d60efc6b 1642static CPUWriteMemoryFunc * const omap_mpui_writefn[] = {
c3d2689d
AZ		 1643 omap_badwidth_write32,
1644 omap_badwidth_write32,
1645 omap_mpui_write,
1646};
1647
1648static void omap_mpui_reset(struct omap_mpu_state_s *s)
1649{
1650 s->mpui_ctrl = 0x0003ff1b;
1651}
1652
c227f099 1653static void omap_mpui_init(target_phys_addr_t base,
c3d2689d
AZ		 1654 struct omap_mpu_state_s *mpu)
1655{
1eed09cb 1656 int iomemtype = cpu_register_io_memory(omap_mpui_readfn,
c3d2689d
AZ		 1657 omap_mpui_writefn, mpu);
1658
8da3ff18 1659 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 1660
1661 omap_mpui_reset(mpu);
1662}
1663
1664/* TIPB Bridges */
1665struct omap_tipb_bridge_s {
c3d2689d
AZ		 1666 qemu_irq abort;
1667
1668 int width_intr;
1669 uint16_t control;
1670 uint16_t alloc;
1671 uint16_t buffer;
1672 uint16_t enh_control;
1673};
1674
c227f099 1675static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1676{
1677 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
c3d2689d 1678
8da3ff18 1679 switch (addr) {
c3d2689d
AZ		 1680 case 0x00: /* TIPB_CNTL */
1681 return s->control;
1682 case 0x04: /* TIPB_BUS_ALLOC */
1683 return s->alloc;
1684 case 0x08: /* MPU_TIPB_CNTL */
1685 return s->buffer;
1686 case 0x0c: /* ENHANCED_TIPB_CNTL */
1687 return s->enh_control;
1688 case 0x10: /* ADDRESS_DBG */
1689 case 0x14: /* DATA_DEBUG_LOW */
1690 case 0x18: /* DATA_DEBUG_HIGH */
1691 return 0xffff;
1692 case 0x1c: /* DEBUG_CNTR_SIG */
1693 return 0x00f8;
1694 }
1695
1696 OMAP_BAD_REG(addr);
1697 return 0;
1698}
1699
c227f099 1700static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1701 uint32_t value)
1702{
1703 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
c3d2689d 1704
8da3ff18 1705 switch (addr) {
c3d2689d
AZ		 1706 case 0x00: /* TIPB_CNTL */
1707 s->control = value & 0xffff;
1708 break;
1709
1710 case 0x04: /* TIPB_BUS_ALLOC */
1711 s->alloc = value & 0x003f;
1712 break;
1713
1714 case 0x08: /* MPU_TIPB_CNTL */
1715 s->buffer = value & 0x0003;
1716 break;
1717
1718 case 0x0c: /* ENHANCED_TIPB_CNTL */
1719 s->width_intr = !(value & 2);
1720 s->enh_control = value & 0x000f;
1721 break;
1722
1723 case 0x10: /* ADDRESS_DBG */
1724 case 0x14: /* DATA_DEBUG_LOW */
1725 case 0x18: /* DATA_DEBUG_HIGH */
1726 case 0x1c: /* DEBUG_CNTR_SIG */
1727 OMAP_RO_REG(addr);
1728 break;
1729
1730 default:
1731 OMAP_BAD_REG(addr);
1732 }
1733}
1734
d60efc6b 1735static CPUReadMemoryFunc * const omap_tipb_bridge_readfn[] = {
c3d2689d
AZ		 1736 omap_badwidth_read16,
1737 omap_tipb_bridge_read,
1738 omap_tipb_bridge_read,
1739};
1740
d60efc6b 1741static CPUWriteMemoryFunc * const omap_tipb_bridge_writefn[] = {
c3d2689d
AZ		 1742 omap_badwidth_write16,
1743 omap_tipb_bridge_write,
1744 omap_tipb_bridge_write,
1745};
1746
1747static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1748{
1749 s->control = 0xffff;
1750 s->alloc = 0x0009;
1751 s->buffer = 0x0000;
1752 s->enh_control = 0x000f;
1753}
1754
c227f099 1755struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
c3d2689d
AZ		 1756 qemu_irq abort_irq, omap_clk clk)
1757{
1758 int iomemtype;
1759 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
1760 qemu_mallocz(sizeof(struct omap_tipb_bridge_s));
1761
1762 s->abort = abort_irq;
c3d2689d
AZ		 1763 omap_tipb_bridge_reset(s);
1764
1eed09cb 1765 iomemtype = cpu_register_io_memory(omap_tipb_bridge_readfn,
c3d2689d 1766 omap_tipb_bridge_writefn, s);
8da3ff18 1767 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 1768
1769 return s;
1770}
1771
1772/* Dummy Traffic Controller's Memory Interface */
c227f099 1773static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1774{
1775 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1776 uint32_t ret;
1777
8da3ff18 1778 switch (addr) {
d8f699cb
AZ		 1779 case 0x00: /* IMIF_PRIO */
1780 case 0x04: /* EMIFS_PRIO */
1781 case 0x08: /* EMIFF_PRIO */
1782 case 0x0c: /* EMIFS_CONFIG */
1783 case 0x10: /* EMIFS_CS0_CONFIG */
1784 case 0x14: /* EMIFS_CS1_CONFIG */
1785 case 0x18: /* EMIFS_CS2_CONFIG */
1786 case 0x1c: /* EMIFS_CS3_CONFIG */
1787 case 0x24: /* EMIFF_MRS */
1788 case 0x28: /* TIMEOUT1 */
1789 case 0x2c: /* TIMEOUT2 */
1790 case 0x30: /* TIMEOUT3 */
1791 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1792 case 0x40: /* EMIFS_CFG_DYN_WAIT */
8da3ff18 1793 return s->tcmi_regs[addr >> 2];
c3d2689d 1794
d8f699cb 1795 case 0x20: /* EMIFF_SDRAM_CONFIG */
8da3ff18
PB		 1796 ret = s->tcmi_regs[addr >> 2];
1797 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
c3d2689d
AZ		 1798 /* XXX: We can try using the VGA_DIRTY flag for this */
1799 return ret;
1800 }
1801
1802 OMAP_BAD_REG(addr);
1803 return 0;
1804}
1805
c227f099 1806static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1807 uint32_t value)
1808{
1809 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1810
8da3ff18 1811 switch (addr) {
d8f699cb
AZ		 1812 case 0x00: /* IMIF_PRIO */
1813 case 0x04: /* EMIFS_PRIO */
1814 case 0x08: /* EMIFF_PRIO */
1815 case 0x10: /* EMIFS_CS0_CONFIG */
1816 case 0x14: /* EMIFS_CS1_CONFIG */
1817 case 0x18: /* EMIFS_CS2_CONFIG */
1818 case 0x1c: /* EMIFS_CS3_CONFIG */
1819 case 0x20: /* EMIFF_SDRAM_CONFIG */
1820 case 0x24: /* EMIFF_MRS */
1821 case 0x28: /* TIMEOUT1 */
1822 case 0x2c: /* TIMEOUT2 */
1823 case 0x30: /* TIMEOUT3 */
1824 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1825 case 0x40: /* EMIFS_CFG_DYN_WAIT */
8da3ff18 1826 s->tcmi_regs[addr >> 2] = value;
c3d2689d 1827 break;
d8f699cb 1828 case 0x0c: /* EMIFS_CONFIG */
8da3ff18 1829 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4);
c3d2689d
AZ		 1830 break;
1831
1832 default:
1833 OMAP_BAD_REG(addr);
1834 }
1835}
1836
d60efc6b 1837static CPUReadMemoryFunc * const omap_tcmi_readfn[] = {
c3d2689d
AZ		 1838 omap_badwidth_read32,
1839 omap_badwidth_read32,
1840 omap_tcmi_read,
1841};
1842
d60efc6b 1843static CPUWriteMemoryFunc * const omap_tcmi_writefn[] = {
c3d2689d
AZ		 1844 omap_badwidth_write32,
1845 omap_badwidth_write32,
1846 omap_tcmi_write,
1847};
1848
1849static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1850{
1851 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1852 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1853 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1854 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1855 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1856 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1857 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1858 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1859 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1860 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1861 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1862 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1863 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1864 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1865 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1866}
1867
c227f099 1868static void omap_tcmi_init(target_phys_addr_t base,
c3d2689d
AZ		 1869 struct omap_mpu_state_s *mpu)
1870{
1eed09cb 1871 int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
c3d2689d
AZ		 1872 omap_tcmi_writefn, mpu);
1873
8da3ff18 1874 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 1875 omap_tcmi_reset(mpu);
1876}
1877
1878/* Digital phase-locked loops control */
c227f099 1879static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1880{
1881 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
c3d2689d 1882
8da3ff18 1883 if (addr == 0x00) /* CTL_REG */
c3d2689d
AZ		 1884 return s->mode;
1885
1886 OMAP_BAD_REG(addr);
1887 return 0;
1888}
1889
c227f099 1890static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1891 uint32_t value)
1892{
1893 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1894 uint16_t diff;
c3d2689d
AZ		 1895 static const int bypass_div[4] = { 1, 2, 4, 4 };
1896 int div, mult;
1897
8da3ff18 1898 if (addr == 0x00) { /* CTL_REG */
c3d2689d
AZ		 1899 /* See omap_ulpd_pm_write() too */
1900 diff = s->mode & value;
1901 s->mode = value & 0x2fff;
1902 if (diff & (0x3ff << 2)) {
1903 if (value & (1 << 4)) { /* PLL_ENABLE */
1904 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1905 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1906 } else {
1907 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1908 mult = 1;
1909 }
1910 omap_clk_setrate(s->dpll, div, mult);
1911 }
1912
1913 /* Enter the desired mode. */
1914 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1915
1916 /* Act as if the lock is restored. */
1917 s->mode |= 2;
1918 } else {
1919 OMAP_BAD_REG(addr);
1920 }
1921}
1922
d60efc6b 1923static CPUReadMemoryFunc * const omap_dpll_readfn[] = {
c3d2689d
AZ		 1924 omap_badwidth_read16,
1925 omap_dpll_read,
1926 omap_badwidth_read16,
1927};
1928
d60efc6b 1929static CPUWriteMemoryFunc * const omap_dpll_writefn[] = {
c3d2689d
AZ		 1930 omap_badwidth_write16,
1931 omap_dpll_write,
1932 omap_badwidth_write16,
1933};
1934
1935static void omap_dpll_reset(struct dpll_ctl_s *s)
1936{
1937 s->mode = 0x2002;
1938 omap_clk_setrate(s->dpll, 1, 1);
1939}
1940
c227f099 1941static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
c3d2689d
AZ		 1942 omap_clk clk)
1943{
1eed09cb 1944 int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
c3d2689d
AZ		 1945 omap_dpll_writefn, s);
1946
c3d2689d
AZ		 1947 s->dpll = clk;
1948 omap_dpll_reset(s);
1949
8da3ff18 1950 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 1951}
1952
1953/* UARTs */
1954struct omap_uart_s {
c227f099 1955 target_phys_addr_t base;
c3d2689d 1956 SerialState *serial; /* TODO */
827df9f3 1957 struct omap_target_agent_s *ta;
75554a3c
AZ		 1958 omap_clk fclk;
1959 qemu_irq irq;
827df9f3
AZ		 1960
1961 uint8_t eblr;
1962 uint8_t syscontrol;
1963 uint8_t wkup;
1964 uint8_t cfps;
54585ffe
AZ		 1965 uint8_t mdr[2];
1966 uint8_t scr;
c588de3d 1967 uint8_t clksel;
c3d2689d
AZ		 1968};
1969
827df9f3 1970void omap_uart_reset(struct omap_uart_s *s)
c3d2689d 1971{
827df9f3
AZ		 1972 s->eblr = 0x00;
1973 s->syscontrol = 0;
1974 s->wkup = 0x3f;
1975 s->cfps = 0x69;
c588de3d 1976 s->clksel = 0;
c3d2689d
AZ		 1977}
1978
c227f099 1979struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
827df9f3
AZ		 1980 qemu_irq irq, omap_clk fclk, omap_clk iclk,
1981 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
c3d2689d
AZ		 1982{
1983 struct omap_uart_s *s = (struct omap_uart_s *)
1984 qemu_mallocz(sizeof(struct omap_uart_s));
827df9f3 1985
75554a3c
AZ		 1986 s->base = base;
1987 s->fclk = fclk;
1988 s->irq = irq;
2d48377a 1989#ifdef TARGET_WORDS_BIGENDIAN
b6cd0ea1 1990 s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
2d48377a
BS		 1991 chr ?: qemu_chr_open("null", "null", NULL), 1,
1992 1);
1993#else
1994 s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
1995 chr ?: qemu_chr_open("null", "null", NULL), 1,
1996 0);
1997#endif
827df9f3
AZ		 1998 return s;
1999}
2000
c227f099 2001static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
827df9f3
AZ		 2002{
2003 struct omap_uart_s *s = (struct omap_uart_s *) opaque;
827df9f3 2004
8da3ff18
PB		 2005 addr &= 0xff;
2006 switch (addr) {
54585ffe
AZ		 2007 case 0x20: /* MDR1 */
2008 return s->mdr[0];
2009 case 0x24: /* MDR2 */
2010 return s->mdr[1];
2011 case 0x40: /* SCR */
2012 return s->scr;
2013 case 0x44: /* SSR */
2014 return 0x0;
c588de3d 2015 case 0x48: /* EBLR (OMAP2) */
827df9f3 2016 return s->eblr;
c588de3d
AZ		 2017 case 0x4C: /* OSC_12M_SEL (OMAP1) */
2018 return s->clksel;
827df9f3
AZ		 2019 case 0x50: /* MVR */
2020 return 0x30;
c588de3d 2021 case 0x54: /* SYSC (OMAP2) */
827df9f3 2022 return s->syscontrol;
c588de3d 2023 case 0x58: /* SYSS (OMAP2) */
827df9f3 2024 return 1;
c588de3d 2025 case 0x5c: /* WER (OMAP2) */
827df9f3 2026 return s->wkup;
c588de3d 2027 case 0x60: /* CFPS (OMAP2) */
827df9f3
AZ		 2028 return s->cfps;
2029 }
2030
2031 OMAP_BAD_REG(addr);
2032 return 0;
2033}
2034
c227f099 2035static void omap_uart_write(void *opaque, target_phys_addr_t addr,
827df9f3
AZ		 2036 uint32_t value)
2037{
2038 struct omap_uart_s *s = (struct omap_uart_s *) opaque;
827df9f3 2039
8da3ff18
PB		 2040 addr &= 0xff;
2041 switch (addr) {
54585ffe
AZ		 2042 case 0x20: /* MDR1 */
2043 s->mdr[0] = value & 0x7f;
2044 break;
2045 case 0x24: /* MDR2 */
2046 s->mdr[1] = value & 0xff;
2047 break;
2048 case 0x40: /* SCR */
2049 s->scr = value & 0xff;
2050 break;
c588de3d 2051 case 0x48: /* EBLR (OMAP2) */
827df9f3
AZ		 2052 s->eblr = value & 0xff;
2053 break;
c588de3d
AZ		 2054 case 0x4C: /* OSC_12M_SEL (OMAP1) */
2055 s->clksel = value & 1;
2056 break;
54585ffe 2057 case 0x44: /* SSR */
827df9f3 2058 case 0x50: /* MVR */
c588de3d 2059 case 0x58: /* SYSS (OMAP2) */
827df9f3
AZ		 2060 OMAP_RO_REG(addr);
2061 break;
c588de3d 2062 case 0x54: /* SYSC (OMAP2) */
827df9f3
AZ		 2063 s->syscontrol = value & 0x1d;
2064 if (value & 2)
2065 omap_uart_reset(s);
2066 break;
c588de3d 2067 case 0x5c: /* WER (OMAP2) */
827df9f3
AZ		 2068 s->wkup = value & 0x7f;
2069 break;
c588de3d 2070 case 0x60: /* CFPS (OMAP2) */
827df9f3
AZ		 2071 s->cfps = value & 0xff;
2072 break;
2073 default:
2074 OMAP_BAD_REG(addr);
2075 }
2076}
2077
d60efc6b 2078static CPUReadMemoryFunc * const omap_uart_readfn[] = {
827df9f3
AZ		 2079 omap_uart_read,
2080 omap_uart_read,
2081 omap_badwidth_read8,
2082};
2083
d60efc6b 2084static CPUWriteMemoryFunc * const omap_uart_writefn[] = {
827df9f3
AZ		 2085 omap_uart_write,
2086 omap_uart_write,
2087 omap_badwidth_write8,
2088};
2089
2090struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
2091 qemu_irq irq, omap_clk fclk, omap_clk iclk,
2092 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr)
2093{
c227f099 2094 target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
827df9f3
AZ		 2095 struct omap_uart_s *s = omap_uart_init(base, irq,
2096 fclk, iclk, txdma, rxdma, chr);
1eed09cb 2097 int iomemtype = cpu_register_io_memory(omap_uart_readfn,
827df9f3
AZ		 2098 omap_uart_writefn, s);
2099
2100 s->ta = ta;
827df9f3 2101
8da3ff18 2102 cpu_register_physical_memory(base + 0x20, 0x100, iomemtype);
827df9f3 2103
c3d2689d
AZ		 2104 return s;
2105}
2106
75554a3c
AZ		 2107void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
2108{
2109 /* TODO: Should reuse or destroy current s->serial */
2d48377a
BS		 2110#ifdef TARGET_WORDS_BIGENDIAN
2111 s->serial = serial_mm_init(s->base, 2, s->irq,
2112 omap_clk_getrate(s->fclk) / 16,
2113 chr ?: qemu_chr_open("null", "null", NULL), 1,
2114 1);
2115#else
75554a3c 2116 s->serial = serial_mm_init(s->base, 2, s->irq,
2d48377a
BS		 2117 omap_clk_getrate(s->fclk) / 16,
2118 chr ?: qemu_chr_open("null", "null", NULL), 1,
2119 0);
2120#endif
75554a3c
AZ		 2121}
2122
c3d2689d 2123/* MPU Clock/Reset/Power Mode Control */
c227f099 2124static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 2125{
2126 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 2127
8da3ff18 2128 switch (addr) {
c3d2689d
AZ		 2129 case 0x00: /* ARM_CKCTL */
2130 return s->clkm.arm_ckctl;
2131
2132 case 0x04: /* ARM_IDLECT1 */
2133 return s->clkm.arm_idlect1;
2134
2135 case 0x08: /* ARM_IDLECT2 */
2136 return s->clkm.arm_idlect2;
2137
2138 case 0x0c: /* ARM_EWUPCT */
2139 return s->clkm.arm_ewupct;
2140
2141 case 0x10: /* ARM_RSTCT1 */
2142 return s->clkm.arm_rstct1;
2143
2144 case 0x14: /* ARM_RSTCT2 */
2145 return s->clkm.arm_rstct2;
2146
2147 case 0x18: /* ARM_SYSST */
d8f699cb 2148 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
c3d2689d
AZ		 2149
2150 case 0x1c: /* ARM_CKOUT1 */
2151 return s->clkm.arm_ckout1;
2152
2153 case 0x20: /* ARM_CKOUT2 */
2154 break;
2155 }
2156
2157 OMAP_BAD_REG(addr);
2158 return 0;
2159}
2160
2161static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
2162 uint16_t diff, uint16_t value)
2163{
2164 omap_clk clk;
2165
2166 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
2167 if (value & (1 << 14))
2168 /* Reserved */;
2169 else {
2170 clk = omap_findclk(s, "arminth_ck");
2171 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2172 }
2173 }
2174 if (diff & (1 << 12)) { /* ARM_TIMXO */
2175 clk = omap_findclk(s, "armtim_ck");
2176 if (value & (1 << 12))
2177 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
2178 else
2179 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2180 }
2181 /* XXX: en_dspck */
2182 if (diff & (3 << 10)) { /* DSPMMUDIV */
2183 clk = omap_findclk(s, "dspmmu_ck");
2184 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
2185 }
2186 if (diff & (3 << 8)) { /* TCDIV */
2187 clk = omap_findclk(s, "tc_ck");
2188 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
2189 }
2190 if (diff & (3 << 6)) { /* DSPDIV */
2191 clk = omap_findclk(s, "dsp_ck");
2192 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
2193 }
2194 if (diff & (3 << 4)) { /* ARMDIV */
2195 clk = omap_findclk(s, "arm_ck");
2196 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
2197 }
2198 if (diff & (3 << 2)) { /* LCDDIV */
2199 clk = omap_findclk(s, "lcd_ck");
2200 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
2201 }
2202 if (diff & (3 << 0)) { /* PERDIV */
2203 clk = omap_findclk(s, "armper_ck");
2204 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
2205 }
2206}
2207
2208static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
2209 uint16_t diff, uint16_t value)
2210{
2211 omap_clk clk;
2212
2213 if (value & (1 << 11)) /* SETARM_IDLE */
2214 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
2215 if (!(value & (1 << 10))) /* WKUP_MODE */
2216 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
2217
2218#define SET_CANIDLE(clock, bit) \
2219 if (diff & (1 << bit)) { \
2220 clk = omap_findclk(s, clock); \
2221 omap_clk_canidle(clk, (value >> bit) & 1); \
2222 }
2223 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
2224 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
2225 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
2226 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
2227 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
2228 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
2229 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
2230 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
2231 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
2232 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
2233 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
2234 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
2235 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
2236 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
2237}
2238
2239static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
2240 uint16_t diff, uint16_t value)
2241{
2242 omap_clk clk;
2243
2244#define SET_ONOFF(clock, bit) \
2245 if (diff & (1 << bit)) { \
2246 clk = omap_findclk(s, clock); \
2247 omap_clk_onoff(clk, (value >> bit) & 1); \
2248 }
2249 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
2250 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
2251 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
2252 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
2253 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
2254 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
2255 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
2256 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
2257 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
2258 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
2259 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
2260}
2261
2262static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
2263 uint16_t diff, uint16_t value)
2264{
2265 omap_clk clk;
2266
2267 if (diff & (3 << 4)) { /* TCLKOUT */
2268 clk = omap_findclk(s, "tclk_out");
2269 switch ((value >> 4) & 3) {
2270 case 1:
2271 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
2272 omap_clk_onoff(clk, 1);
2273 break;
2274 case 2:
2275 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
2276 omap_clk_onoff(clk, 1);
2277 break;
2278 default:
2279 omap_clk_onoff(clk, 0);
2280 }
2281 }
2282 if (diff & (3 << 2)) { /* DCLKOUT */
2283 clk = omap_findclk(s, "dclk_out");
2284 switch ((value >> 2) & 3) {
2285 case 0:
2286 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
2287 break;
2288 case 1:
2289 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
2290 break;
2291 case 2:
2292 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
2293 break;
2294 case 3:
2295 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2296 break;
2297 }
2298 }
2299 if (diff & (3 << 0)) { /* ACLKOUT */
2300 clk = omap_findclk(s, "aclk_out");
2301 switch ((value >> 0) & 3) {
2302 case 1:
2303 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
2304 omap_clk_onoff(clk, 1);
2305 break;
2306 case 2:
2307 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
2308 omap_clk_onoff(clk, 1);
2309 break;
2310 case 3:
2311 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
2312 omap_clk_onoff(clk, 1);
2313 break;
2314 default:
2315 omap_clk_onoff(clk, 0);
2316 }
2317 }
2318}
2319
c227f099 2320static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 2321 uint32_t value)
2322{
2323 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 2324 uint16_t diff;
2325 omap_clk clk;
2326 static const char *clkschemename[8] = {
2327 "fully synchronous", "fully asynchronous", "synchronous scalable",
2328 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
2329 };
2330
8da3ff18 2331 switch (addr) {
c3d2689d
AZ		 2332 case 0x00: /* ARM_CKCTL */
2333 diff = s->clkm.arm_ckctl ^ value;
2334 s->clkm.arm_ckctl = value & 0x7fff;
2335 omap_clkm_ckctl_update(s, diff, value);
2336 return;
2337
2338 case 0x04: /* ARM_IDLECT1 */
2339 diff = s->clkm.arm_idlect1 ^ value;
2340 s->clkm.arm_idlect1 = value & 0x0fff;
2341 omap_clkm_idlect1_update(s, diff, value);
2342 return;
2343
2344 case 0x08: /* ARM_IDLECT2 */
2345 diff = s->clkm.arm_idlect2 ^ value;
2346 s->clkm.arm_idlect2 = value & 0x07ff;
2347 omap_clkm_idlect2_update(s, diff, value);
2348 return;
2349
2350 case 0x0c: /* ARM_EWUPCT */
c3d2689d
AZ		 2351 s->clkm.arm_ewupct = value & 0x003f;
2352 return;
2353
2354 case 0x10: /* ARM_RSTCT1 */
2355 diff = s->clkm.arm_rstct1 ^ value;
2356 s->clkm.arm_rstct1 = value & 0x0007;
2357 if (value & 9) {
2358 qemu_system_reset_request();
2359 s->clkm.cold_start = 0xa;
2360 }
2361 if (diff & ~value & 4) { /* DSP_RST */
2362 omap_mpui_reset(s);
2363 omap_tipb_bridge_reset(s->private_tipb);
2364 omap_tipb_bridge_reset(s->public_tipb);
2365 }
2366 if (diff & 2) { /* DSP_EN */
2367 clk = omap_findclk(s, "dsp_ck");
2368 omap_clk_canidle(clk, (~value >> 1) & 1);
2369 }
2370 return;
2371
2372 case 0x14: /* ARM_RSTCT2 */
2373 s->clkm.arm_rstct2 = value & 0x0001;
2374 return;
2375
2376 case 0x18: /* ARM_SYSST */
2377 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
2378 s->clkm.clocking_scheme = (value >> 11) & 7;
2379 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
2380 clkschemename[s->clkm.clocking_scheme]);
2381 }
2382 s->clkm.cold_start &= value & 0x3f;
2383 return;
2384
2385 case 0x1c: /* ARM_CKOUT1 */
2386 diff = s->clkm.arm_ckout1 ^ value;
2387 s->clkm.arm_ckout1 = value & 0x003f;
2388 omap_clkm_ckout1_update(s, diff, value);
2389 return;
2390
2391 case 0x20: /* ARM_CKOUT2 */
2392 default:
2393 OMAP_BAD_REG(addr);
2394 }
2395}
2396
d60efc6b 2397static CPUReadMemoryFunc * const omap_clkm_readfn[] = {
c3d2689d
AZ		 2398 omap_badwidth_read16,
2399 omap_clkm_read,
2400 omap_badwidth_read16,
2401};
2402
d60efc6b 2403static CPUWriteMemoryFunc * const omap_clkm_writefn[] = {
c3d2689d
AZ		 2404 omap_badwidth_write16,
2405 omap_clkm_write,
2406 omap_badwidth_write16,
2407};
2408
c227f099 2409static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 2410{
2411 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 2412
8da3ff18 2413 switch (addr) {
c3d2689d
AZ		 2414 case 0x04: /* DSP_IDLECT1 */
2415 return s->clkm.dsp_idlect1;
2416
2417 case 0x08: /* DSP_IDLECT2 */
2418 return s->clkm.dsp_idlect2;
2419
2420 case 0x14: /* DSP_RSTCT2 */
2421 return s->clkm.dsp_rstct2;
2422
2423 case 0x18: /* DSP_SYSST */
d8f699cb 2424 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
c3d2689d
AZ		 2425 (s->env->halted << 6); /* Quite useless... */
2426 }
2427
2428 OMAP_BAD_REG(addr);
2429 return 0;
2430}
2431
2432static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
2433 uint16_t diff, uint16_t value)
2434{
2435 omap_clk clk;
2436
2437 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
2438}
2439
2440static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
2441 uint16_t diff, uint16_t value)
2442{
2443 omap_clk clk;
2444
2445 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
2446}
2447
c227f099 2448static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 2449 uint32_t value)
2450{
2451 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 2452 uint16_t diff;
2453
8da3ff18 2454 switch (addr) {
c3d2689d
AZ		 2455 case 0x04: /* DSP_IDLECT1 */
2456 diff = s->clkm.dsp_idlect1 ^ value;
2457 s->clkm.dsp_idlect1 = value & 0x01f7;
2458 omap_clkdsp_idlect1_update(s, diff, value);
2459 break;
2460
2461 case 0x08: /* DSP_IDLECT2 */
2462 s->clkm.dsp_idlect2 = value & 0x0037;
2463 diff = s->clkm.dsp_idlect1 ^ value;
2464 omap_clkdsp_idlect2_update(s, diff, value);
2465 break;
2466
2467 case 0x14: /* DSP_RSTCT2 */
2468 s->clkm.dsp_rstct2 = value & 0x0001;
2469 break;
2470
2471 case 0x18: /* DSP_SYSST */
2472 s->clkm.cold_start &= value & 0x3f;
2473 break;
2474
2475 default:
2476 OMAP_BAD_REG(addr);
2477 }
2478}
2479
d60efc6b 2480static CPUReadMemoryFunc * const omap_clkdsp_readfn[] = {
c3d2689d
AZ		 2481 omap_badwidth_read16,
2482 omap_clkdsp_read,
2483 omap_badwidth_read16,
2484};
2485
d60efc6b 2486static CPUWriteMemoryFunc * const omap_clkdsp_writefn[] = {
c3d2689d
AZ		 2487 omap_badwidth_write16,
2488 omap_clkdsp_write,
2489 omap_badwidth_write16,
2490};
2491
2492static void omap_clkm_reset(struct omap_mpu_state_s *s)
2493{
2494 if (s->wdt && s->wdt->reset)
2495 s->clkm.cold_start = 0x6;
2496 s->clkm.clocking_scheme = 0;
2497 omap_clkm_ckctl_update(s, ~0, 0x3000);
2498 s->clkm.arm_ckctl = 0x3000;
d8f699cb 2499 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
c3d2689d 2500 s->clkm.arm_idlect1 = 0x0400;
d8f699cb 2501 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
c3d2689d
AZ		 2502 s->clkm.arm_idlect2 = 0x0100;
2503 s->clkm.arm_ewupct = 0x003f;
2504 s->clkm.arm_rstct1 = 0x0000;
2505 s->clkm.arm_rstct2 = 0x0000;
2506 s->clkm.arm_ckout1 = 0x0015;
2507 s->clkm.dpll1_mode = 0x2002;
2508 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
2509 s->clkm.dsp_idlect1 = 0x0040;
2510 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
2511 s->clkm.dsp_idlect2 = 0x0000;
2512 s->clkm.dsp_rstct2 = 0x0000;
2513}
2514
c227f099
AL		 2515static void omap_clkm_init(target_phys_addr_t mpu_base,
2516 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
c3d2689d
AZ		 2517{
2518 int iomemtype[2] = {
1eed09cb
AK		 2519 cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s),
2520 cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s),
c3d2689d
AZ		 2521 };
2522
d8f699cb
AZ		 2523 s->clkm.arm_idlect1 = 0x03ff;
2524 s->clkm.arm_idlect2 = 0x0100;
2525 s->clkm.dsp_idlect1 = 0x0002;
c3d2689d 2526 omap_clkm_reset(s);
d8f699cb 2527 s->clkm.cold_start = 0x3a;
c3d2689d 2528
8da3ff18
PB		 2529 cpu_register_physical_memory(mpu_base, 0x100, iomemtype[0]);
2530 cpu_register_physical_memory(dsp_base, 0x1000, iomemtype[1]);
c3d2689d
AZ		 2531}
2532
fe71e81a
AZ		 2533/* MPU I/O */
2534struct omap_mpuio_s {
fe71e81a
AZ		 2535 qemu_irq irq;
2536 qemu_irq kbd_irq;
2537 qemu_irq *in;
2538 qemu_irq handler[16];
2539 qemu_irq wakeup;
2540
2541 uint16_t inputs;
2542 uint16_t outputs;
2543 uint16_t dir;
2544 uint16_t edge;
2545 uint16_t mask;
2546 uint16_t ints;
2547
2548 uint16_t debounce;
2549 uint16_t latch;
2550 uint8_t event;
2551
2552 uint8_t buttons[5];
2553 uint8_t row_latch;
2554 uint8_t cols;
2555 int kbd_mask;
2556 int clk;
2557};
2558
2559static void omap_mpuio_set(void *opaque, int line, int level)
2560{
2561 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2562 uint16_t prev = s->inputs;
2563
2564 if (level)
2565 s->inputs |= 1 << line;
2566 else
2567 s->inputs &= ~(1 << line);
2568
2569 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
2570 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
2571 s->ints |= 1 << line;
2572 qemu_irq_raise(s->irq);
2573 /* TODO: wakeup */
2574 }
2575 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
2576 (s->event >> 1) == line) /* PIN_SELECT */
2577 s->latch = s->inputs;
2578 }
2579}
2580
2581static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
2582{
2583 int i;
2584 uint8_t *row, rows = 0, cols = ~s->cols;
2585
38a34e1d 2586 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
fe71e81a 2587 if (*row & cols)
38a34e1d 2588 rows |= i;
fe71e81a 2589
cf6d9118
AZ		 2590 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
2591 s->row_latch = ~rows;
fe71e81a
AZ		 2592}
2593
c227f099 2594static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
fe71e81a
AZ		 2595{
2596 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
cf965d24 2597 int offset = addr & OMAP_MPUI_REG_MASK;
fe71e81a
AZ		 2598 uint16_t ret;
2599
2600 switch (offset) {
2601 case 0x00: /* INPUT_LATCH */
2602 return s->inputs;
2603
2604 case 0x04: /* OUTPUT_REG */
2605 return s->outputs;
2606
2607 case 0x08: /* IO_CNTL */
2608 return s->dir;
2609
2610 case 0x10: /* KBR_LATCH */
2611 return s->row_latch;
2612
2613 case 0x14: /* KBC_REG */
2614 return s->cols;
2615
2616 case 0x18: /* GPIO_EVENT_MODE_REG */
2617 return s->event;
2618
2619 case 0x1c: /* GPIO_INT_EDGE_REG */
2620 return s->edge;
2621
2622 case 0x20: /* KBD_INT */
cf6d9118 2623 return (~s->row_latch & 0x1f) && !s->kbd_mask;
fe71e81a
AZ		 2624
2625 case 0x24: /* GPIO_INT */
2626 ret = s->ints;
8e129e07
AZ		 2627 s->ints &= s->mask;
2628 if (ret)
2629 qemu_irq_lower(s->irq);
fe71e81a
AZ		 2630 return ret;
2631
2632 case 0x28: /* KBD_MASKIT */
2633 return s->kbd_mask;
2634
2635 case 0x2c: /* GPIO_MASKIT */
2636 return s->mask;
2637
2638 case 0x30: /* GPIO_DEBOUNCING_REG */
2639 return s->debounce;
2640
2641 case 0x34: /* GPIO_LATCH_REG */
2642 return s->latch;
2643 }
2644
2645 OMAP_BAD_REG(addr);
2646 return 0;
2647}
2648
c227f099 2649static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
fe71e81a
AZ		 2650 uint32_t value)
2651{
2652 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
cf965d24 2653 int offset = addr & OMAP_MPUI_REG_MASK;
fe71e81a
AZ		 2654 uint16_t diff;
2655 int ln;
2656
2657 switch (offset) {
2658 case 0x04: /* OUTPUT_REG */
d8f699cb 2659 diff = (s->outputs ^ value) & ~s->dir;
fe71e81a 2660 s->outputs = value;
fe71e81a
AZ		 2661 while ((ln = ffs(diff))) {
2662 ln --;
2663 if (s->handler[ln])
2664 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2665 diff &= ~(1 << ln);
2666 }
2667 break;
2668
2669 case 0x08: /* IO_CNTL */
2670 diff = s->outputs & (s->dir ^ value);
2671 s->dir = value;
2672
2673 value = s->outputs & ~s->dir;
2674 while ((ln = ffs(diff))) {
2675 ln --;
2676 if (s->handler[ln])
2677 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
2678 diff &= ~(1 << ln);
2679 }
2680 break;
2681
2682 case 0x14: /* KBC_REG */
2683 s->cols = value;
2684 omap_mpuio_kbd_update(s);
2685 break;
2686
2687 case 0x18: /* GPIO_EVENT_MODE_REG */
2688 s->event = value & 0x1f;
2689 break;
2690
2691 case 0x1c: /* GPIO_INT_EDGE_REG */
2692 s->edge = value;
2693 break;
2694
2695 case 0x28: /* KBD_MASKIT */
2696 s->kbd_mask = value & 1;
2697 omap_mpuio_kbd_update(s);
2698 break;
2699
2700 case 0x2c: /* GPIO_MASKIT */
2701 s->mask = value;
2702 break;
2703
2704 case 0x30: /* GPIO_DEBOUNCING_REG */
2705 s->debounce = value & 0x1ff;
2706 break;
2707
2708 case 0x00: /* INPUT_LATCH */
2709 case 0x10: /* KBR_LATCH */
2710 case 0x20: /* KBD_INT */
2711 case 0x24: /* GPIO_INT */
2712 case 0x34: /* GPIO_LATCH_REG */
2713 OMAP_RO_REG(addr);
2714 return;
2715
2716 default:
2717 OMAP_BAD_REG(addr);
2718 return;
2719 }
2720}
2721
d60efc6b 2722static CPUReadMemoryFunc * const omap_mpuio_readfn[] = {
fe71e81a
AZ		 2723 omap_badwidth_read16,
2724 omap_mpuio_read,
2725 omap_badwidth_read16,
2726};
2727
d60efc6b 2728static CPUWriteMemoryFunc * const omap_mpuio_writefn[] = {
fe71e81a
AZ		 2729 omap_badwidth_write16,
2730 omap_mpuio_write,
2731 omap_badwidth_write16,
2732};
2733
9596ebb7 2734static void omap_mpuio_reset(struct omap_mpuio_s *s)
fe71e81a
AZ		 2735{
2736 s->inputs = 0;
2737 s->outputs = 0;
2738 s->dir = ~0;
2739 s->event = 0;
2740 s->edge = 0;
2741 s->kbd_mask = 0;
2742 s->mask = 0;
2743 s->debounce = 0;
2744 s->latch = 0;
2745 s->ints = 0;
2746 s->row_latch = 0x1f;
38a34e1d 2747 s->clk = 1;
fe71e81a
AZ		 2748}
2749
2750static void omap_mpuio_onoff(void *opaque, int line, int on)
2751{
2752 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2753
2754 s->clk = on;
2755 if (on)
2756 omap_mpuio_kbd_update(s);
2757}
2758
c227f099 2759struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
fe71e81a
AZ		 2760 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2761 omap_clk clk)
2762{
2763 int iomemtype;
2764 struct omap_mpuio_s *s = (struct omap_mpuio_s *)
2765 qemu_mallocz(sizeof(struct omap_mpuio_s));
2766
fe71e81a
AZ		 2767 s->irq = gpio_int;
2768 s->kbd_irq = kbd_int;
2769 s->wakeup = wakeup;
2770 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2771 omap_mpuio_reset(s);
2772
1eed09cb 2773 iomemtype = cpu_register_io_memory(omap_mpuio_readfn,
fe71e81a 2774 omap_mpuio_writefn, s);
8da3ff18 2775 cpu_register_physical_memory(base, 0x800, iomemtype);
fe71e81a
AZ		 2776
2777 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
2778
2779 return s;
2780}
2781
2782qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2783{
2784 return s->in;
2785}
2786
2787void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2788{
2789 if (line >= 16 || line < 0)
2ac71179 2790 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
fe71e81a
AZ		 2791 s->handler[line] = handler;
2792}
2793
2794void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2795{
2796 if (row >= 5 || row < 0)
2ac71179 2797 hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
fe71e81a
AZ		 2798
2799 if (down)
38a34e1d 2800 s->buttons[row] |= 1 << col;
fe71e81a 2801 else
38a34e1d 2802 s->buttons[row] &= ~(1 << col);
fe71e81a
AZ		 2803
2804 omap_mpuio_kbd_update(s);
2805}
2806
d951f6ff
AZ		 2807/* MicroWire Interface */
2808struct omap_uwire_s {
d951f6ff
AZ		 2809 qemu_irq txirq;
2810 qemu_irq rxirq;
2811 qemu_irq txdrq;
2812
2813 uint16_t txbuf;
2814 uint16_t rxbuf;
2815 uint16_t control;
2816 uint16_t setup[5];
2817
bc24a225 2818 uWireSlave *chip[4];
d951f6ff
AZ		 2819};
2820
2821static void omap_uwire_transfer_start(struct omap_uwire_s *s)
2822{
2823 int chipselect = (s->control >> 10) & 3; /* INDEX */
bc24a225 2824 uWireSlave *slave = s->chip[chipselect];
d951f6ff
AZ		 2825
2826 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
2827 if (s->control & (1 << 12)) /* CS_CMD */
2828 if (slave && slave->send)
2829 slave->send(slave->opaque,
2830 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
2831 s->control &= ~(1 << 14); /* CSRB */
2832 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2833 * a DRQ. When is the level IRQ supposed to be reset? */
2834 }
2835
2836 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
2837 if (s->control & (1 << 12)) /* CS_CMD */
2838 if (slave && slave->receive)
2839 s->rxbuf = slave->receive(slave->opaque);
2840 s->control |= 1 << 15; /* RDRB */
2841 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2842 * a DRQ. When is the level IRQ supposed to be reset? */
2843 }
2844}
2845
c227f099 2846static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
d951f6ff
AZ		 2847{
2848 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
cf965d24 2849 int offset = addr & OMAP_MPUI_REG_MASK;
d951f6ff
AZ		 2850
2851 switch (offset) {
2852 case 0x00: /* RDR */
2853 s->control &= ~(1 << 15); /* RDRB */
2854 return s->rxbuf;
2855
2856 case 0x04: /* CSR */
2857 return s->control;
2858
2859 case 0x08: /* SR1 */
2860 return s->setup[0];
2861 case 0x0c: /* SR2 */
2862 return s->setup[1];
2863 case 0x10: /* SR3 */
2864 return s->setup[2];
2865 case 0x14: /* SR4 */
2866 return s->setup[3];
2867 case 0x18: /* SR5 */
2868 return s->setup[4];
2869 }
2870
2871 OMAP_BAD_REG(addr);
2872 return 0;
2873}
2874
c227f099 2875static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
d951f6ff
AZ		 2876 uint32_t value)
2877{
2878 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
cf965d24 2879 int offset = addr & OMAP_MPUI_REG_MASK;
d951f6ff
AZ		 2880
2881 switch (offset) {
2882 case 0x00: /* TDR */
2883 s->txbuf = value; /* TD */
d951f6ff
AZ		 2884 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
2885 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
cf965d24
AZ		 2886 (s->control & (1 << 12)))) { /* CS_CMD */
2887 s->control |= 1 << 14; /* CSRB */
d951f6ff 2888 omap_uwire_transfer_start(s);
cf965d24 2889 }
d951f6ff
AZ		 2890 break;
2891
2892 case 0x04: /* CSR */
2893 s->control = value & 0x1fff;
2894 if (value & (1 << 13)) /* START */
2895 omap_uwire_transfer_start(s);
2896 break;
2897
2898 case 0x08: /* SR1 */
2899 s->setup[0] = value & 0x003f;
2900 break;
2901
2902 case 0x0c: /* SR2 */
2903 s->setup[1] = value & 0x0fc0;
2904 break;
2905
2906 case 0x10: /* SR3 */
2907 s->setup[2] = value & 0x0003;
2908 break;
2909
2910 case 0x14: /* SR4 */
2911 s->setup[3] = value & 0x0001;
2912 break;
2913
2914 case 0x18: /* SR5 */
2915 s->setup[4] = value & 0x000f;
2916 break;
2917
2918 default:
2919 OMAP_BAD_REG(addr);
2920 return;
2921 }
2922}
2923
d60efc6b 2924static CPUReadMemoryFunc * const omap_uwire_readfn[] = {
d951f6ff
AZ		 2925 omap_badwidth_read16,
2926 omap_uwire_read,
2927 omap_badwidth_read16,
2928};
2929
d60efc6b 2930static CPUWriteMemoryFunc * const omap_uwire_writefn[] = {
d951f6ff
AZ		 2931 omap_badwidth_write16,
2932 omap_uwire_write,
2933 omap_badwidth_write16,
2934};
2935
9596ebb7 2936static void omap_uwire_reset(struct omap_uwire_s *s)
d951f6ff 2937{
66450b15 2938 s->control = 0;
d951f6ff
AZ		 2939 s->setup[0] = 0;
2940 s->setup[1] = 0;
2941 s->setup[2] = 0;
2942 s->setup[3] = 0;
2943 s->setup[4] = 0;
2944}
2945
c227f099 2946struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
d951f6ff
AZ		 2947 qemu_irq *irq, qemu_irq dma, omap_clk clk)
2948{
2949 int iomemtype;
2950 struct omap_uwire_s *s = (struct omap_uwire_s *)
2951 qemu_mallocz(sizeof(struct omap_uwire_s));
2952
d951f6ff
AZ		 2953 s->txirq = irq[0];
2954 s->rxirq = irq[1];
2955 s->txdrq = dma;
2956 omap_uwire_reset(s);
2957
1eed09cb 2958 iomemtype = cpu_register_io_memory(omap_uwire_readfn,
d951f6ff 2959 omap_uwire_writefn, s);
8da3ff18 2960 cpu_register_physical_memory(base, 0x800, iomemtype);
d951f6ff
AZ		 2961
2962 return s;
2963}
2964
2965void omap_uwire_attach(struct omap_uwire_s *s,
bc24a225 2966 uWireSlave *slave, int chipselect)
d951f6ff 2967{
827df9f3
AZ		 2968 if (chipselect < 0 || chipselect > 3) {
2969 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
2970 exit(-1);
2971 }
d951f6ff
AZ		 2972
2973 s->chip[chipselect] = slave;
2974}
2975
66450b15 2976/* Pseudonoise Pulse-Width Light Modulator */
9596ebb7 2977static void omap_pwl_update(struct omap_mpu_state_s *s)
66450b15
AZ		 2978{
2979 int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
2980
2981 if (output != s->pwl.output) {
2982 s->pwl.output = output;
2983 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
2984 }
2985}
2986
c227f099 2987static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
66450b15
AZ		 2988{
2989 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 2990 int offset = addr & OMAP_MPUI_REG_MASK;
66450b15
AZ		 2991
2992 switch (offset) {
2993 case 0x00: /* PWL_LEVEL */
2994 return s->pwl.level;
2995 case 0x04: /* PWL_CTRL */
2996 return s->pwl.enable;
2997 }
2998 OMAP_BAD_REG(addr);
2999 return 0;
3000}
3001
c227f099 3002static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
66450b15
AZ		 3003 uint32_t value)
3004{
3005 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 3006 int offset = addr & OMAP_MPUI_REG_MASK;
66450b15
AZ		 3007
3008 switch (offset) {
3009 case 0x00: /* PWL_LEVEL */
3010 s->pwl.level = value;
3011 omap_pwl_update(s);
3012 break;
3013 case 0x04: /* PWL_CTRL */
3014 s->pwl.enable = value & 1;
3015 omap_pwl_update(s);
3016 break;
3017 default:
3018 OMAP_BAD_REG(addr);
3019 return;
3020 }
3021}
3022
d60efc6b 3023static CPUReadMemoryFunc * const omap_pwl_readfn[] = {
02645926 3024 omap_pwl_read,
66450b15
AZ		 3025 omap_badwidth_read8,
3026 omap_badwidth_read8,
66450b15
AZ		 3027};
3028
d60efc6b 3029static CPUWriteMemoryFunc * const omap_pwl_writefn[] = {
02645926 3030 omap_pwl_write,
66450b15
AZ		 3031 omap_badwidth_write8,
3032 omap_badwidth_write8,
66450b15
AZ		 3033};
3034
9596ebb7 3035static void omap_pwl_reset(struct omap_mpu_state_s *s)
66450b15
AZ		 3036{
3037 s->pwl.output = 0;
3038 s->pwl.level = 0;
3039 s->pwl.enable = 0;
3040 s->pwl.clk = 1;
3041 omap_pwl_update(s);
3042}
3043
3044static void omap_pwl_clk_update(void *opaque, int line, int on)
3045{
3046 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
3047
3048 s->pwl.clk = on;
3049 omap_pwl_update(s);
3050}
3051
c227f099 3052static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
66450b15
AZ		 3053 omap_clk clk)
3054{
3055 int iomemtype;
3056
66450b15
AZ		 3057 omap_pwl_reset(s);
3058
1eed09cb 3059 iomemtype = cpu_register_io_memory(omap_pwl_readfn,
66450b15 3060 omap_pwl_writefn, s);
b854bc19 3061 cpu_register_physical_memory(base, 0x800, iomemtype);
66450b15
AZ		 3062
3063 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
3064}
3065
f34c417b 3066/* Pulse-Width Tone module */
c227f099 3067static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
f34c417b
AZ		 3068{
3069 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 3070 int offset = addr & OMAP_MPUI_REG_MASK;
f34c417b
AZ		 3071
3072 switch (offset) {
3073 case 0x00: /* FRC */
3074 return s->pwt.frc;
3075 case 0x04: /* VCR */
3076 return s->pwt.vrc;
3077 case 0x08: /* GCR */
3078 return s->pwt.gcr;
3079 }
3080 OMAP_BAD_REG(addr);
3081 return 0;
3082}
3083
c227f099 3084static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
f34c417b
AZ		 3085 uint32_t value)
3086{
3087 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 3088 int offset = addr & OMAP_MPUI_REG_MASK;
f34c417b
AZ		 3089
3090 switch (offset) {
3091 case 0x00: /* FRC */
3092 s->pwt.frc = value & 0x3f;
3093 break;
3094 case 0x04: /* VRC */
3095 if ((value ^ s->pwt.vrc) & 1) {
3096 if (value & 1)
3097 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
3098 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
3099 ((omap_clk_getrate(s->pwt.clk) >> 3) /
3100 /* Pre-multiplexer divider */
3101 ((s->pwt.gcr & 2) ? 1 : 154) /
3102 /* Octave multiplexer */
3103 (2 << (value & 3)) *
3104 /* 101/107 divider */
3105 ((value & (1 << 2)) ? 101 : 107) *
3106 /* 49/55 divider */
3107 ((value & (1 << 3)) ? 49 : 55) *
3108 /* 50/63 divider */
3109 ((value & (1 << 4)) ? 50 : 63) *
3110 /* 80/127 divider */
3111 ((value & (1 << 5)) ? 80 : 127) /
3112 (107 * 55 * 63 * 127)));
3113 else
3114 printf("%s: silence!\n", __FUNCTION__);
3115 }
3116 s->pwt.vrc = value & 0x7f;
3117 break;
3118 case 0x08: /* GCR */
3119 s->pwt.gcr = value & 3;
3120 break;
3121 default:
3122 OMAP_BAD_REG(addr);
3123 return;
3124 }
3125}
3126
d60efc6b 3127static CPUReadMemoryFunc * const omap_pwt_readfn[] = {
02645926 3128 omap_pwt_read,
f34c417b
AZ		 3129 omap_badwidth_read8,
3130 omap_badwidth_read8,
f34c417b
AZ		 3131};
3132
d60efc6b 3133static CPUWriteMemoryFunc * const omap_pwt_writefn[] = {
02645926 3134 omap_pwt_write,
f34c417b
AZ		 3135 omap_badwidth_write8,
3136 omap_badwidth_write8,
f34c417b
AZ		 3137};
3138
9596ebb7 3139static void omap_pwt_reset(struct omap_mpu_state_s *s)
f34c417b
AZ		 3140{
3141 s->pwt.frc = 0;
3142 s->pwt.vrc = 0;
3143 s->pwt.gcr = 0;
3144}
3145
c227f099 3146static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
f34c417b
AZ		 3147 omap_clk clk)
3148{
3149 int iomemtype;
3150
f34c417b
AZ		 3151 s->pwt.clk = clk;
3152 omap_pwt_reset(s);
3153
1eed09cb 3154 iomemtype = cpu_register_io_memory(omap_pwt_readfn,
f34c417b 3155 omap_pwt_writefn, s);
b854bc19 3156 cpu_register_physical_memory(base, 0x800, iomemtype);
f34c417b
AZ		 3157}
3158
5c1c390f
AZ		 3159/* Real-time Clock module */
3160struct omap_rtc_s {
5c1c390f
AZ		 3161 qemu_irq irq;
3162 qemu_irq alarm;
3163 QEMUTimer *clk;
3164
3165 uint8_t interrupts;
3166 uint8_t status;
3167 int16_t comp_reg;
3168 int running;
3169 int pm_am;
3170 int auto_comp;
3171 int round;
5c1c390f
AZ		 3172 struct tm alarm_tm;
3173 time_t alarm_ti;
3174
3175 struct tm current_tm;
3176 time_t ti;
3177 uint64_t tick;
3178};
3179
3180static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
3181{
106627d0 3182 /* s->alarm is level-triggered */
5c1c390f
AZ		 3183 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
3184}
3185
3186static void omap_rtc_alarm_update(struct omap_rtc_s *s)
3187{
0cd2df75 3188 s->alarm_ti = mktimegm(&s->alarm_tm);
5c1c390f
AZ		 3189 if (s->alarm_ti == -1)
3190 printf("%s: conversion failed\n", __FUNCTION__);
3191}
3192
c227f099 3193static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
5c1c390f
AZ		 3194{
3195 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
cf965d24 3196 int offset = addr & OMAP_MPUI_REG_MASK;
5c1c390f
AZ		 3197 uint8_t i;
3198
3199 switch (offset) {
3200 case 0x00: /* SECONDS_REG */
abd0c6bd 3201 return to_bcd(s->current_tm.tm_sec);
5c1c390f
AZ		 3202
3203 case 0x04: /* MINUTES_REG */
abd0c6bd 3204 return to_bcd(s->current_tm.tm_min);
5c1c390f
AZ		 3205
3206 case 0x08: /* HOURS_REG */
3207 if (s->pm_am)
3208 return ((s->current_tm.tm_hour > 11) << 7) |
abd0c6bd 3209 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
5c1c390f 3210 else
abd0c6bd 3211 return to_bcd(s->current_tm.tm_hour);
5c1c390f
AZ		 3212
3213 case 0x0c: /* DAYS_REG */
abd0c6bd 3214 return to_bcd(s->current_tm.tm_mday);
5c1c390f
AZ		 3215
3216 case 0x10: /* MONTHS_REG */
abd0c6bd 3217 return to_bcd(s->current_tm.tm_mon + 1);
5c1c390f
AZ		 3218
3219 case 0x14: /* YEARS_REG */
abd0c6bd 3220 return to_bcd(s->current_tm.tm_year % 100);
5c1c390f
AZ		 3221
3222 case 0x18: /* WEEK_REG */
3223 return s->current_tm.tm_wday;
3224
3225 case 0x20: /* ALARM_SECONDS_REG */
abd0c6bd 3226 return to_bcd(s->alarm_tm.tm_sec);
5c1c390f
AZ		 3227
3228 case 0x24: /* ALARM_MINUTES_REG */
abd0c6bd 3229 return to_bcd(s->alarm_tm.tm_min);
5c1c390f
AZ		 3230
3231 case 0x28: /* ALARM_HOURS_REG */
3232 if (s->pm_am)
3233 return ((s->alarm_tm.tm_hour > 11) << 7) |
abd0c6bd 3234 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
5c1c390f 3235 else
abd0c6bd 3236 return to_bcd(s->alarm_tm.tm_hour);
5c1c390f
AZ		 3237
3238 case 0x2c: /* ALARM_DAYS_REG */
abd0c6bd 3239 return to_bcd(s->alarm_tm.tm_mday);
5c1c390f
AZ		 3240
3241 case 0x30: /* ALARM_MONTHS_REG */
abd0c6bd 3242 return to_bcd(s->alarm_tm.tm_mon + 1);
5c1c390f
AZ		 3243
3244 case 0x34: /* ALARM_YEARS_REG */
abd0c6bd 3245 return to_bcd(s->alarm_tm.tm_year % 100);
5c1c390f
AZ		 3246
3247 case 0x40: /* RTC_CTRL_REG */
3248 return (s->pm_am << 3) | (s->auto_comp << 2) |
3249 (s->round << 1) | s->running;
3250
3251 case 0x44: /* RTC_STATUS_REG */
3252 i = s->status;
3253 s->status &= ~0x3d;
3254 return i;
3255
3256 case 0x48: /* RTC_INTERRUPTS_REG */
3257 return s->interrupts;
3258
3259 case 0x4c: /* RTC_COMP_LSB_REG */
3260 return ((uint16_t) s->comp_reg) & 0xff;
3261
3262 case 0x50: /* RTC_COMP_MSB_REG */
3263 return ((uint16_t) s->comp_reg) >> 8;
3264 }
3265
3266 OMAP_BAD_REG(addr);
3267 return 0;
3268}
3269
c227f099 3270static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
5c1c390f
AZ		 3271 uint32_t value)
3272{
3273 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
cf965d24 3274 int offset = addr & OMAP_MPUI_REG_MASK;
5c1c390f
AZ		 3275 struct tm new_tm;
3276 time_t ti[2];
3277
3278 switch (offset) {
3279 case 0x00: /* SECONDS_REG */
eb38c52c 3280#ifdef ALMDEBUG
5c1c390f
AZ		 3281 printf("RTC SEC_REG <-- %02x\n", value);
3282#endif
3283 s->ti -= s->current_tm.tm_sec;
abd0c6bd 3284 s->ti += from_bcd(value);
5c1c390f
AZ		 3285 return;
3286
3287 case 0x04: /* MINUTES_REG */
eb38c52c 3288#ifdef ALMDEBUG
5c1c390f
AZ		 3289 printf("RTC MIN_REG <-- %02x\n", value);
3290#endif
3291 s->ti -= s->current_tm.tm_min * 60;
abd0c6bd 3292 s->ti += from_bcd(value) * 60;
5c1c390f
AZ		 3293 return;
3294
3295 case 0x08: /* HOURS_REG */
eb38c52c 3296#ifdef ALMDEBUG
5c1c390f
AZ		 3297 printf("RTC HRS_REG <-- %02x\n", value);
3298#endif
3299 s->ti -= s->current_tm.tm_hour * 3600;
3300 if (s->pm_am) {
abd0c6bd 3301 s->ti += (from_bcd(value & 0x3f) & 12) * 3600;
5c1c390f
AZ		 3302 s->ti += ((value >> 7) & 1) * 43200;
3303 } else
abd0c6bd 3304 s->ti += from_bcd(value & 0x3f) * 3600;
5c1c390f
AZ		 3305 return;
3306
3307 case 0x0c: /* DAYS_REG */
eb38c52c 3308#ifdef ALMDEBUG
5c1c390f
AZ		 3309 printf("RTC DAY_REG <-- %02x\n", value);
3310#endif
3311 s->ti -= s->current_tm.tm_mday * 86400;
abd0c6bd 3312 s->ti += from_bcd(value) * 86400;
5c1c390f
AZ		 3313 return;
3314
3315 case 0x10: /* MONTHS_REG */
eb38c52c 3316#ifdef ALMDEBUG
5c1c390f
AZ		 3317 printf("RTC MTH_REG <-- %02x\n", value);
3318#endif
3319 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
abd0c6bd 3320 new_tm.tm_mon = from_bcd(value);
0cd2df75
AJ		 3321 ti[0] = mktimegm(&s->current_tm);
3322 ti[1] = mktimegm(&new_tm);
5c1c390f
AZ		 3323
3324 if (ti[0] != -1 && ti[1] != -1) {
3325 s->ti -= ti[0];
3326 s->ti += ti[1];
3327 } else {
3328 /* A less accurate version */
3329 s->ti -= s->current_tm.tm_mon * 2592000;
abd0c6bd 3330 s->ti += from_bcd(value) * 2592000;
5c1c390f
AZ		 3331 }
3332 return;
3333
3334 case 0x14: /* YEARS_REG */
eb38c52c 3335#ifdef ALMDEBUG
5c1c390f
AZ		 3336 printf("RTC YRS_REG <-- %02x\n", value);
3337#endif
3338 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
abd0c6bd 3339 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100);
0cd2df75
AJ		 3340 ti[0] = mktimegm(&s->current_tm);
3341 ti[1] = mktimegm(&new_tm);
5c1c390f
AZ		 3342
3343 if (ti[0] != -1 && ti[1] != -1) {
3344 s->ti -= ti[0];
3345 s->ti += ti[1];
3346 } else {
3347 /* A less accurate version */
3348 s->ti -= (s->current_tm.tm_year % 100) * 31536000;
abd0c6bd 3349 s->ti += from_bcd(value) * 31536000;
5c1c390f
AZ		 3350 }
3351 return;
3352
3353 case 0x18: /* WEEK_REG */
3354 return; /* Ignored */
3355
3356 case 0x20: /* ALARM_SECONDS_REG */
eb38c52c 3357#ifdef ALMDEBUG
5c1c390f
AZ		 3358 printf("ALM SEC_REG <-- %02x\n", value);
3359#endif
abd0c6bd 3360 s->alarm_tm.tm_sec = from_bcd(value);
5c1c390f
AZ		 3361 omap_rtc_alarm_update(s);
3362 return;
3363
3364 case 0x24: /* ALARM_MINUTES_REG */
eb38c52c 3365#ifdef ALMDEBUG
5c1c390f
AZ		 3366 printf("ALM MIN_REG <-- %02x\n", value);
3367#endif
abd0c6bd 3368 s->alarm_tm.tm_min = from_bcd(value);
5c1c390f
AZ		 3369 omap_rtc_alarm_update(s);
3370 return;
3371
3372 case 0x28: /* ALARM_HOURS_REG */
eb38c52c 3373#ifdef ALMDEBUG
5c1c390f
AZ		 3374 printf("ALM HRS_REG <-- %02x\n", value);
3375#endif
3376 if (s->pm_am)
3377 s->alarm_tm.tm_hour =
abd0c6bd 3378 ((from_bcd(value & 0x3f)) % 12) +
5c1c390f
AZ		 3379 ((value >> 7) & 1) * 12;
3380 else
abd0c6bd 3381 s->alarm_tm.tm_hour = from_bcd(value);
5c1c390f
AZ		 3382 omap_rtc_alarm_update(s);
3383 return;
3384
3385 case 0x2c: /* ALARM_DAYS_REG */
eb38c52c 3386#ifdef ALMDEBUG
5c1c390f
AZ		 3387 printf("ALM DAY_REG <-- %02x\n", value);
3388#endif
abd0c6bd 3389 s->alarm_tm.tm_mday = from_bcd(value);
5c1c390f
AZ		 3390 omap_rtc_alarm_update(s);
3391 return;
3392
3393 case 0x30: /* ALARM_MONTHS_REG */
eb38c52c 3394#ifdef ALMDEBUG
5c1c390f
AZ		 3395 printf("ALM MON_REG <-- %02x\n", value);
3396#endif
abd0c6bd 3397 s->alarm_tm.tm_mon = from_bcd(value);
5c1c390f
AZ		 3398 omap_rtc_alarm_update(s);
3399 return;
3400
3401 case 0x34: /* ALARM_YEARS_REG */
eb38c52c 3402#ifdef ALMDEBUG
5c1c390f
AZ		 3403 printf("ALM YRS_REG <-- %02x\n", value);
3404#endif
abd0c6bd 3405 s->alarm_tm.tm_year = from_bcd(value);
5c1c390f
AZ		 3406 omap_rtc_alarm_update(s);
3407 return;
3408
3409 case 0x40: /* RTC_CTRL_REG */
eb38c52c 3410#ifdef ALMDEBUG
5c1c390f
AZ		 3411 printf("RTC CONTROL <-- %02x\n", value);
3412#endif
3413 s->pm_am = (value >> 3) & 1;
3414 s->auto_comp = (value >> 2) & 1;
3415 s->round = (value >> 1) & 1;
3416 s->running = value & 1;
3417 s->status &= 0xfd;
3418 s->status |= s->running << 1;
3419 return;
3420
3421 case 0x44: /* RTC_STATUS_REG */
eb38c52c 3422#ifdef ALMDEBUG
5c1c390f
AZ		 3423 printf("RTC STATUSL <-- %02x\n", value);
3424#endif
3425 s->status &= ~((value & 0xc0) ^ 0x80);
3426 omap_rtc_interrupts_update(s);
3427 return;
3428
3429 case 0x48: /* RTC_INTERRUPTS_REG */
eb38c52c 3430#ifdef ALMDEBUG
5c1c390f
AZ		 3431 printf("RTC INTRS <-- %02x\n", value);
3432#endif
3433 s->interrupts = value;
3434 return;
3435
3436 case 0x4c: /* RTC_COMP_LSB_REG */
eb38c52c 3437#ifdef ALMDEBUG
5c1c390f
AZ		 3438 printf("RTC COMPLSB <-- %02x\n", value);
3439#endif
3440 s->comp_reg &= 0xff00;
3441 s->comp_reg |= 0x00ff & value;
3442 return;
3443
3444 case 0x50: /* RTC_COMP_MSB_REG */
eb38c52c 3445#ifdef ALMDEBUG
5c1c390f
AZ		 3446 printf("RTC COMPMSB <-- %02x\n", value);
3447#endif
3448 s->comp_reg &= 0x00ff;
3449 s->comp_reg |= 0xff00 & (value << 8);
3450 return;
3451
3452 default:
3453 OMAP_BAD_REG(addr);
3454 return;
3455 }
3456}
3457
d60efc6b 3458static CPUReadMemoryFunc * const omap_rtc_readfn[] = {
5c1c390f
AZ		 3459 omap_rtc_read,
3460 omap_badwidth_read8,
3461 omap_badwidth_read8,
3462};
3463
d60efc6b 3464static CPUWriteMemoryFunc * const omap_rtc_writefn[] = {
5c1c390f
AZ		 3465 omap_rtc_write,
3466 omap_badwidth_write8,
3467 omap_badwidth_write8,
3468};
3469
3470static void omap_rtc_tick(void *opaque)
3471{
3472 struct omap_rtc_s *s = opaque;
3473
3474 if (s->round) {
3475 /* Round to nearest full minute. */
3476 if (s->current_tm.tm_sec < 30)
3477 s->ti -= s->current_tm.tm_sec;
3478 else
3479 s->ti += 60 - s->current_tm.tm_sec;
3480
3481 s->round = 0;
3482 }
3483
f6503059 3484 memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
5c1c390f
AZ		 3485
3486 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
3487 s->status |= 0x40;
3488 omap_rtc_interrupts_update(s);
3489 }
3490
3491 if (s->interrupts & 0x04)
3492 switch (s->interrupts & 3) {
3493 case 0:
3494 s->status |= 0x04;
106627d0 3495 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 3496 break;
3497 case 1:
3498 if (s->current_tm.tm_sec)
3499 break;
3500 s->status |= 0x08;
106627d0 3501 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 3502 break;
3503 case 2:
3504 if (s->current_tm.tm_sec || s->current_tm.tm_min)
3505 break;
3506 s->status |= 0x10;
106627d0 3507 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 3508 break;
3509 case 3:
3510 if (s->current_tm.tm_sec ||
3511 s->current_tm.tm_min || s->current_tm.tm_hour)
3512 break;
3513 s->status |= 0x20;
106627d0 3514 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 3515 break;
3516 }
3517
3518 /* Move on */
3519 if (s->running)
3520 s->ti ++;
3521 s->tick += 1000;
3522
3523 /*
3524 * Every full hour add a rough approximation of the compensation
3525 * register to the 32kHz Timer (which drives the RTC) value.
3526 */
3527 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
3528 s->tick += s->comp_reg * 1000 / 32768;
3529
3530 qemu_mod_timer(s->clk, s->tick);
3531}
3532
9596ebb7 3533static void omap_rtc_reset(struct omap_rtc_s *s)
5c1c390f 3534{
f6503059
AZ		 3535 struct tm tm;
3536
5c1c390f
AZ		 3537 s->interrupts = 0;
3538 s->comp_reg = 0;
3539 s->running = 0;
3540 s->pm_am = 0;
3541 s->auto_comp = 0;
3542 s->round = 0;
3543 s->tick = qemu_get_clock(rt_clock);
3544 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
3545 s->alarm_tm.tm_mday = 0x01;
3546 s->status = 1 << 7;
f6503059 3547 qemu_get_timedate(&tm, 0);
0cd2df75 3548 s->ti = mktimegm(&tm);
5c1c390f
AZ		 3549
3550 omap_rtc_alarm_update(s);
3551 omap_rtc_tick(s);
3552}
3553
c227f099 3554struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
5c1c390f
AZ		 3555 qemu_irq *irq, omap_clk clk)
3556{
3557 int iomemtype;
3558 struct omap_rtc_s *s = (struct omap_rtc_s *)
3559 qemu_mallocz(sizeof(struct omap_rtc_s));
3560
5c1c390f
AZ		 3561 s->irq = irq[0];
3562 s->alarm = irq[1];
3563 s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s);
5c1c390f
AZ		 3564
3565 omap_rtc_reset(s);
3566
1eed09cb 3567 iomemtype = cpu_register_io_memory(omap_rtc_readfn,
5c1c390f 3568 omap_rtc_writefn, s);
8da3ff18 3569 cpu_register_physical_memory(base, 0x800, iomemtype);
5c1c390f
AZ		 3570
3571 return s;
3572}
3573
d8f699cb
AZ		 3574/* Multi-channel Buffered Serial Port interfaces */
3575struct omap_mcbsp_s {
d8f699cb
AZ		 3576 qemu_irq txirq;
3577 qemu_irq rxirq;
3578 qemu_irq txdrq;
3579 qemu_irq rxdrq;
3580
3581 uint16_t spcr[2];
3582 uint16_t rcr[2];
3583 uint16_t xcr[2];
3584 uint16_t srgr[2];
3585 uint16_t mcr[2];
3586 uint16_t pcr;
3587 uint16_t rcer[8];
3588 uint16_t xcer[8];
3589 int tx_rate;
3590 int rx_rate;
3591 int tx_req;
73560bc8 3592 int rx_req;
d8f699cb 3593
bc24a225 3594 I2SCodec *codec;
73560bc8
AZ		 3595 QEMUTimer *source_timer;
3596 QEMUTimer *sink_timer;
d8f699cb
AZ		 3597};
3598
3599static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
3600{
3601 int irq;
3602
3603 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
3604 case 0:
3605 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
3606 break;
3607 case 3:
3608 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
3609 break;
3610 default:
3611 irq = 0;
3612 break;
3613 }
3614
106627d0
AZ		 3615 if (irq)
3616 qemu_irq_pulse(s->rxirq);
d8f699cb
AZ		 3617
3618 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
3619 case 0:
3620 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
3621 break;
3622 case 3:
3623 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
3624 break;
3625 default:
3626 irq = 0;
3627 break;
3628 }
3629
106627d0
AZ		 3630 if (irq)
3631 qemu_irq_pulse(s->txirq);
d8f699cb
AZ		 3632}
3633
73560bc8 3634static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
d8f699cb 3635{
73560bc8
AZ		 3636 if ((s->spcr[0] >> 1) & 1) /* RRDY */
3637 s->spcr[0] |= 1 << 2; /* RFULL */
3638 s->spcr[0] |= 1 << 1; /* RRDY */
3639 qemu_irq_raise(s->rxdrq);
3640 omap_mcbsp_intr_update(s);
d8f699cb
AZ		 3641}
3642
73560bc8 3643static void omap_mcbsp_source_tick(void *opaque)
d8f699cb 3644{
73560bc8
AZ		 3645 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3646 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3647
3648 if (!s->rx_rate)
d8f699cb 3649 return;
73560bc8
AZ		 3650 if (s->rx_req)
3651 printf("%s: Rx FIFO overrun\n", __FUNCTION__);
d8f699cb 3652
73560bc8 3653 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
d8f699cb 3654
73560bc8 3655 omap_mcbsp_rx_newdata(s);
6ee093c9
JQ		 3656 qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) +
3657 get_ticks_per_sec());
d8f699cb
AZ		 3658}
3659
3660static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
3661{
73560bc8
AZ		 3662 if (!s->codec || !s->codec->rts)
3663 omap_mcbsp_source_tick(s);
3664 else if (s->codec->in.len) {
3665 s->rx_req = s->codec->in.len;
3666 omap_mcbsp_rx_newdata(s);
d8f699cb 3667 }
d8f699cb
AZ		 3668}
3669
3670static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
73560bc8
AZ		 3671{
3672 qemu_del_timer(s->source_timer);
3673}
3674
3675static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
d8f699cb
AZ		 3676{
3677 s->spcr[0] &= ~(1 << 1); /* RRDY */
3678 qemu_irq_lower(s->rxdrq);
3679 omap_mcbsp_intr_update(s);
3680}
3681
73560bc8
AZ		 3682static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
3683{
3684 s->spcr[1] |= 1 << 1; /* XRDY */
3685 qemu_irq_raise(s->txdrq);
3686 omap_mcbsp_intr_update(s);
3687}
3688
3689static void omap_mcbsp_sink_tick(void *opaque)
d8f699cb 3690{
73560bc8
AZ		 3691 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3692 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3693
3694 if (!s->tx_rate)
d8f699cb 3695 return;
73560bc8
AZ		 3696 if (s->tx_req)
3697 printf("%s: Tx FIFO underrun\n", __FUNCTION__);
3698
3699 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
3700
3701 omap_mcbsp_tx_newdata(s);
6ee093c9
JQ		 3702 qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) +
3703 get_ticks_per_sec());
73560bc8
AZ		 3704}
3705
3706static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
3707{
3708 if (!s->codec || !s->codec->cts)
3709 omap_mcbsp_sink_tick(s);
3710 else if (s->codec->out.size) {
3711 s->tx_req = s->codec->out.size;
3712 omap_mcbsp_tx_newdata(s);
3713 }
3714}
3715
3716static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
3717{
3718 s->spcr[1] &= ~(1 << 1); /* XRDY */
3719 qemu_irq_lower(s->txdrq);
3720 omap_mcbsp_intr_update(s);
3721 if (s->codec && s->codec->cts)
3722 s->codec->tx_swallow(s->codec->opaque);
d8f699cb
AZ		 3723}
3724
3725static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
3726{
73560bc8
AZ		 3727 s->tx_req = 0;
3728 omap_mcbsp_tx_done(s);
3729 qemu_del_timer(s->sink_timer);
3730}
3731
3732static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
3733{
3734 int prev_rx_rate, prev_tx_rate;
3735 int rx_rate = 0, tx_rate = 0;
3736 int cpu_rate = 1500000; /* XXX */
3737
3738 /* TODO: check CLKSTP bit */
3739 if (s->spcr[1] & (1 << 6)) { /* GRST */
3740 if (s->spcr[0] & (1 << 0)) { /* RRST */
3741 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3742 (s->pcr & (1 << 8))) { /* CLKRM */
3743 if (~s->pcr & (1 << 7)) /* SCLKME */
3744 rx_rate = cpu_rate /
3745 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3746 } else
3747 if (s->codec)
3748 rx_rate = s->codec->rx_rate;
3749 }
3750
3751 if (s->spcr[1] & (1 << 0)) { /* XRST */
3752 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3753 (s->pcr & (1 << 9))) { /* CLKXM */
3754 if (~s->pcr & (1 << 7)) /* SCLKME */
3755 tx_rate = cpu_rate /
3756 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3757 } else
3758 if (s->codec)
3759 tx_rate = s->codec->tx_rate;
3760 }
3761 }
3762 prev_tx_rate = s->tx_rate;
3763 prev_rx_rate = s->rx_rate;
3764 s->tx_rate = tx_rate;
3765 s->rx_rate = rx_rate;
3766
3767 if (s->codec)
3768 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3769
3770 if (!prev_tx_rate && tx_rate)
3771 omap_mcbsp_tx_start(s);
3772 else if (s->tx_rate && !tx_rate)
3773 omap_mcbsp_tx_stop(s);
3774
3775 if (!prev_rx_rate && rx_rate)
3776 omap_mcbsp_rx_start(s);
3777 else if (prev_tx_rate && !tx_rate)
3778 omap_mcbsp_rx_stop(s);
d8f699cb
AZ		 3779}
3780
c227f099 3781static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
d8f699cb
AZ		 3782{
3783 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3784 int offset = addr & OMAP_MPUI_REG_MASK;
3785 uint16_t ret;
3786
3787 switch (offset) {
3788 case 0x00: /* DRR2 */
3789 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
3790 return 0x0000;
3791 /* Fall through. */
3792 case 0x02: /* DRR1 */
73560bc8 3793 if (s->rx_req < 2) {
d8f699cb 3794 printf("%s: Rx FIFO underrun\n", __FUNCTION__);
73560bc8 3795 omap_mcbsp_rx_done(s);
d8f699cb 3796 } else {
73560bc8
AZ		 3797 s->tx_req -= 2;
3798 if (s->codec && s->codec->in.len >= 2) {
3799 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
3800 ret |= s->codec->in.fifo[s->codec->in.start ++];
3801 s->codec->in.len -= 2;
3802 } else
3803 ret = 0x0000;
3804 if (!s->tx_req)
3805 omap_mcbsp_rx_done(s);
d8f699cb
AZ		 3806 return ret;
3807 }
3808 return 0x0000;
3809
3810 case 0x04: /* DXR2 */
3811 case 0x06: /* DXR1 */
3812 return 0x0000;
3813
3814 case 0x08: /* SPCR2 */
3815 return s->spcr[1];
3816 case 0x0a: /* SPCR1 */
3817 return s->spcr[0];
3818 case 0x0c: /* RCR2 */
3819 return s->rcr[1];
3820 case 0x0e: /* RCR1 */
3821 return s->rcr[0];
3822 case 0x10: /* XCR2 */
3823 return s->xcr[1];
3824 case 0x12: /* XCR1 */
3825 return s->xcr[0];
3826 case 0x14: /* SRGR2 */
3827 return s->srgr[1];
3828 case 0x16: /* SRGR1 */
3829 return s->srgr[0];
3830 case 0x18: /* MCR2 */
3831 return s->mcr[1];
3832 case 0x1a: /* MCR1 */
3833 return s->mcr[0];
3834 case 0x1c: /* RCERA */
3835 return s->rcer[0];
3836 case 0x1e: /* RCERB */
3837 return s->rcer[1];
3838 case 0x20: /* XCERA */
3839 return s->xcer[0];
3840 case 0x22: /* XCERB */
3841 return s->xcer[1];
3842 case 0x24: /* PCR0 */
3843 return s->pcr;
3844 case 0x26: /* RCERC */
3845 return s->rcer[2];
3846 case 0x28: /* RCERD */
3847 return s->rcer[3];
3848 case 0x2a: /* XCERC */
3849 return s->xcer[2];
3850 case 0x2c: /* XCERD */
3851 return s->xcer[3];
3852 case 0x2e: /* RCERE */
3853 return s->rcer[4];
3854 case 0x30: /* RCERF */
3855 return s->rcer[5];
3856 case 0x32: /* XCERE */
3857 return s->xcer[4];
3858 case 0x34: /* XCERF */
3859 return s->xcer[5];
3860 case 0x36: /* RCERG */
3861 return s->rcer[6];
3862 case 0x38: /* RCERH */
3863 return s->rcer[7];
3864 case 0x3a: /* XCERG */
3865 return s->xcer[6];
3866 case 0x3c: /* XCERH */
3867 return s->xcer[7];
3868 }
3869
3870 OMAP_BAD_REG(addr);
3871 return 0;
3872}
3873
c227f099 3874static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
d8f699cb
AZ		 3875 uint32_t value)
3876{
3877 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3878 int offset = addr & OMAP_MPUI_REG_MASK;
3879
3880 switch (offset) {
3881 case 0x00: /* DRR2 */
3882 case 0x02: /* DRR1 */
3883 OMAP_RO_REG(addr);
3884 return;
3885
3886 case 0x04: /* DXR2 */
3887 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3888 return;
3889 /* Fall through. */
3890 case 0x06: /* DXR1 */
73560bc8
AZ		 3891 if (s->tx_req > 1) {
3892 s->tx_req -= 2;
3893 if (s->codec && s->codec->cts) {
d8f699cb
AZ		 3894 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
3895 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
d8f699cb 3896 }
73560bc8
AZ		 3897 if (s->tx_req < 2)
3898 omap_mcbsp_tx_done(s);
d8f699cb
AZ		 3899 } else
3900 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
3901 return;
3902
3903 case 0x08: /* SPCR2 */
3904 s->spcr[1] &= 0x0002;
3905 s->spcr[1] |= 0x03f9 & value;
3906 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
73560bc8 3907 if (~value & 1) /* XRST */
d8f699cb 3908 s->spcr[1] &= ~6;
d8f699cb
AZ		 3909 omap_mcbsp_req_update(s);
3910 return;
3911 case 0x0a: /* SPCR1 */
3912 s->spcr[0] &= 0x0006;
3913 s->spcr[0] |= 0xf8f9 & value;
3914 if (value & (1 << 15)) /* DLB */
3915 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
3916 if (~value & 1) { /* RRST */
3917 s->spcr[0] &= ~6;
73560bc8
AZ		 3918 s->rx_req = 0;
3919 omap_mcbsp_rx_done(s);
d8f699cb 3920 }
d8f699cb
AZ		 3921 omap_mcbsp_req_update(s);
3922 return;
3923
3924 case 0x0c: /* RCR2 */
3925 s->rcr[1] = value & 0xffff;
3926 return;
3927 case 0x0e: /* RCR1 */
3928 s->rcr[0] = value & 0x7fe0;
3929 return;
3930 case 0x10: /* XCR2 */
3931 s->xcr[1] = value & 0xffff;
3932 return;
3933 case 0x12: /* XCR1 */
3934 s->xcr[0] = value & 0x7fe0;
3935 return;
3936 case 0x14: /* SRGR2 */
3937 s->srgr[1] = value & 0xffff;
73560bc8 3938 omap_mcbsp_req_update(s);
d8f699cb
AZ		 3939 return;
3940 case 0x16: /* SRGR1 */
3941 s->srgr[0] = value & 0xffff;
73560bc8 3942 omap_mcbsp_req_update(s);
d8f699cb
AZ		 3943 return;
3944 case 0x18: /* MCR2 */
3945 s->mcr[1] = value & 0x03e3;
3946 if (value & 3) /* XMCM */
3947 printf("%s: Tx channel selection mode enable attempt\n",
3948 __FUNCTION__);
3949 return;
3950 case 0x1a: /* MCR1 */
3951 s->mcr[0] = value & 0x03e1;
3952 if (value & 1) /* RMCM */
3953 printf("%s: Rx channel selection mode enable attempt\n",
3954 __FUNCTION__);
3955 return;
3956 case 0x1c: /* RCERA */
3957 s->rcer[0] = value & 0xffff;
3958 return;
3959 case 0x1e: /* RCERB */
3960 s->rcer[1] = value & 0xffff;
3961 return;
3962 case 0x20: /* XCERA */
3963 s->xcer[0] = value & 0xffff;
3964 return;
3965 case 0x22: /* XCERB */
3966 s->xcer[1] = value & 0xffff;
3967 return;
3968 case 0x24: /* PCR0 */
3969 s->pcr = value & 0x7faf;
3970 return;
3971 case 0x26: /* RCERC */
3972 s->rcer[2] = value & 0xffff;
3973 return;
3974 case 0x28: /* RCERD */
3975 s->rcer[3] = value & 0xffff;
3976 return;
3977 case 0x2a: /* XCERC */
3978 s->xcer[2] = value & 0xffff;
3979 return;
3980 case 0x2c: /* XCERD */
3981 s->xcer[3] = value & 0xffff;
3982 return;
3983 case 0x2e: /* RCERE */
3984 s->rcer[4] = value & 0xffff;
3985 return;
3986 case 0x30: /* RCERF */
3987 s->rcer[5] = value & 0xffff;
3988 return;
3989 case 0x32: /* XCERE */
3990 s->xcer[4] = value & 0xffff;
3991 return;
3992 case 0x34: /* XCERF */
3993 s->xcer[5] = value & 0xffff;
3994 return;
3995 case 0x36: /* RCERG */
3996 s->rcer[6] = value & 0xffff;
3997 return;
3998 case 0x38: /* RCERH */
3999 s->rcer[7] = value & 0xffff;
4000 return;
4001 case 0x3a: /* XCERG */
4002 s->xcer[6] = value & 0xffff;
4003 return;
4004 case 0x3c: /* XCERH */
4005 s->xcer[7] = value & 0xffff;
4006 return;
4007 }
4008
4009 OMAP_BAD_REG(addr);
4010}
4011
c227f099 4012static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
73560bc8
AZ		 4013 uint32_t value)
4014{
4015 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4016 int offset = addr & OMAP_MPUI_REG_MASK;
4017
4018 if (offset == 0x04) { /* DXR */
4019 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
4020 return;
4021 if (s->tx_req > 3) {
4022 s->tx_req -= 4;
4023 if (s->codec && s->codec->cts) {
4024 s->codec->out.fifo[s->codec->out.len ++] =
4025 (value >> 24) & 0xff;
4026 s->codec->out.fifo[s->codec->out.len ++] =
4027 (value >> 16) & 0xff;
4028 s->codec->out.fifo[s->codec->out.len ++] =
4029 (value >> 8) & 0xff;
4030 s->codec->out.fifo[s->codec->out.len ++] =
4031 (value >> 0) & 0xff;
4032 }
4033 if (s->tx_req < 4)
4034 omap_mcbsp_tx_done(s);
4035 } else
4036 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
4037 return;
4038 }
4039
4040 omap_badwidth_write16(opaque, addr, value);
4041}
4042
d60efc6b 4043static CPUReadMemoryFunc * const omap_mcbsp_readfn[] = {
d8f699cb
AZ		 4044 omap_badwidth_read16,
4045 omap_mcbsp_read,
4046 omap_badwidth_read16,
4047};
4048
d60efc6b 4049static CPUWriteMemoryFunc * const omap_mcbsp_writefn[] = {
d8f699cb 4050 omap_badwidth_write16,
73560bc8
AZ		 4051 omap_mcbsp_writeh,
4052 omap_mcbsp_writew,
d8f699cb
AZ		 4053};
4054
4055static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
4056{
4057 memset(&s->spcr, 0, sizeof(s->spcr));
4058 memset(&s->rcr, 0, sizeof(s->rcr));
4059 memset(&s->xcr, 0, sizeof(s->xcr));
4060 s->srgr[0] = 0x0001;
4061 s->srgr[1] = 0x2000;
4062 memset(&s->mcr, 0, sizeof(s->mcr));
4063 memset(&s->pcr, 0, sizeof(s->pcr));
4064 memset(&s->rcer, 0, sizeof(s->rcer));
4065 memset(&s->xcer, 0, sizeof(s->xcer));
4066 s->tx_req = 0;
73560bc8 4067 s->rx_req = 0;
d8f699cb
AZ		 4068 s->tx_rate = 0;
4069 s->rx_rate = 0;
73560bc8
AZ		 4070 qemu_del_timer(s->source_timer);
4071 qemu_del_timer(s->sink_timer);
d8f699cb
AZ		 4072}
4073
c227f099 4074struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
d8f699cb
AZ		 4075 qemu_irq *irq, qemu_irq *dma, omap_clk clk)
4076{
4077 int iomemtype;
4078 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
4079 qemu_mallocz(sizeof(struct omap_mcbsp_s));
4080
d8f699cb
AZ		 4081 s->txirq = irq[0];
4082 s->rxirq = irq[1];
4083 s->txdrq = dma[0];
4084 s->rxdrq = dma[1];
73560bc8
AZ		 4085 s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s);
4086 s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s);
d8f699cb
AZ		 4087 omap_mcbsp_reset(s);
4088
1eed09cb 4089 iomemtype = cpu_register_io_memory(omap_mcbsp_readfn,
d8f699cb 4090 omap_mcbsp_writefn, s);
8da3ff18 4091 cpu_register_physical_memory(base, 0x800, iomemtype);
d8f699cb
AZ		 4092
4093 return s;
4094}
4095
9596ebb7 4096static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
d8f699cb
AZ		 4097{
4098 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4099
73560bc8
AZ		 4100 if (s->rx_rate) {
4101 s->rx_req = s->codec->in.len;
4102 omap_mcbsp_rx_newdata(s);
4103 }
d8f699cb
AZ		 4104}
4105
9596ebb7 4106static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
d8f699cb
AZ		 4107{
4108 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
4109
73560bc8
AZ		 4110 if (s->tx_rate) {
4111 s->tx_req = s->codec->out.size;
4112 omap_mcbsp_tx_newdata(s);
4113 }
d8f699cb
AZ		 4114}
4115
bc24a225 4116void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
d8f699cb
AZ		 4117{
4118 s->codec = slave;
4119 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
4120 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
4121}
4122
f9d43072
AZ		 4123/* LED Pulse Generators */
4124struct omap_lpg_s {
f9d43072
AZ		 4125 QEMUTimer *tm;
4126
4127 uint8_t control;
4128 uint8_t power;
4129 int64_t on;
4130 int64_t period;
4131 int clk;
4132 int cycle;
4133};
4134
4135static void omap_lpg_tick(void *opaque)
4136{
4137 struct omap_lpg_s *s = opaque;
4138
4139 if (s->cycle)
4140 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on);
4141 else
4142 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on);
4143
4144 s->cycle = !s->cycle;
4145 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
4146}
4147
4148static void omap_lpg_update(struct omap_lpg_s *s)
4149{
4150 int64_t on, period = 1, ticks = 1000;
4151 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
4152
4153 if (~s->control & (1 << 6)) /* LPGRES */
4154 on = 0;
4155 else if (s->control & (1 << 7)) /* PERM_ON */
4156 on = period;
4157 else {
4158 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
4159 256 / 32);
4160 on = (s->clk && s->power) ? muldiv64(ticks,
4161 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
4162 }
4163
4164 qemu_del_timer(s->tm);
4165 if (on == period && s->on < s->period)
4166 printf("%s: LED is on\n", __FUNCTION__);
4167 else if (on == 0 && s->on)
4168 printf("%s: LED is off\n", __FUNCTION__);
4169 else if (on && (on != s->on || period != s->period)) {
4170 s->cycle = 0;
4171 s->on = on;
4172 s->period = period;
4173 omap_lpg_tick(s);
4174 return;
4175 }
4176
4177 s->on = on;
4178 s->period = period;
4179}
4180
4181static void omap_lpg_reset(struct omap_lpg_s *s)
4182{
4183 s->control = 0x00;
4184 s->power = 0x00;
4185 s->clk = 1;
4186 omap_lpg_update(s);
4187}
4188
c227f099 4189static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
f9d43072
AZ		 4190{
4191 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4192 int offset = addr & OMAP_MPUI_REG_MASK;
4193
4194 switch (offset) {
4195 case 0x00: /* LCR */
4196 return s->control;
4197
4198 case 0x04: /* PMR */
4199 return s->power;
4200 }
4201
4202 OMAP_BAD_REG(addr);
4203 return 0;
4204}
4205
c227f099 4206static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
f9d43072
AZ		 4207 uint32_t value)
4208{
4209 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4210 int offset = addr & OMAP_MPUI_REG_MASK;
4211
4212 switch (offset) {
4213 case 0x00: /* LCR */
4214 if (~value & (1 << 6)) /* LPGRES */
4215 omap_lpg_reset(s);
4216 s->control = value & 0xff;
4217 omap_lpg_update(s);
4218 return;
4219
4220 case 0x04: /* PMR */
4221 s->power = value & 0x01;
4222 omap_lpg_update(s);
4223 return;
4224
4225 default:
4226 OMAP_BAD_REG(addr);
4227 return;
4228 }
4229}
4230
d60efc6b 4231static CPUReadMemoryFunc * const omap_lpg_readfn[] = {
f9d43072
AZ		 4232 omap_lpg_read,
4233 omap_badwidth_read8,
4234 omap_badwidth_read8,
4235};
4236
d60efc6b 4237static CPUWriteMemoryFunc * const omap_lpg_writefn[] = {
f9d43072
AZ		 4238 omap_lpg_write,
4239 omap_badwidth_write8,
4240 omap_badwidth_write8,
4241};
4242
4243static void omap_lpg_clk_update(void *opaque, int line, int on)
4244{
4245 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
4246
4247 s->clk = on;
4248 omap_lpg_update(s);
4249}
4250
c227f099 4251struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
f9d43072
AZ		 4252{
4253 int iomemtype;
4254 struct omap_lpg_s *s = (struct omap_lpg_s *)
4255 qemu_mallocz(sizeof(struct omap_lpg_s));
4256
f9d43072
AZ		 4257 s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s);
4258
4259 omap_lpg_reset(s);
4260
1eed09cb 4261 iomemtype = cpu_register_io_memory(omap_lpg_readfn,
f9d43072 4262 omap_lpg_writefn, s);
8da3ff18 4263 cpu_register_physical_memory(base, 0x800, iomemtype);
f9d43072
AZ		 4264
4265 omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
4266
4267 return s;
4268}
4269
4270/* MPUI Peripheral Bridge configuration */
c227f099 4271static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
f9d43072
AZ		 4272{
4273 if (addr == OMAP_MPUI_BASE) /* CMR */
4274 return 0xfe4d;
4275
4276 OMAP_BAD_REG(addr);
4277 return 0;
4278}
4279
d60efc6b 4280static CPUReadMemoryFunc * const omap_mpui_io_readfn[] = {
f9d43072
AZ		 4281 omap_badwidth_read16,
4282 omap_mpui_io_read,
4283 omap_badwidth_read16,
4284};
4285
d60efc6b 4286static CPUWriteMemoryFunc * const omap_mpui_io_writefn[] = {
f9d43072
AZ		 4287 omap_badwidth_write16,
4288 omap_badwidth_write16,
4289 omap_badwidth_write16,
4290};
4291
4292static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
4293{
1eed09cb 4294 int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn,
f9d43072
AZ		 4295 omap_mpui_io_writefn, mpu);
4296 cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
4297}
4298
c3d2689d 4299/* General chip reset */
827df9f3 4300static void omap1_mpu_reset(void *opaque)
c3d2689d
AZ		 4301{
4302 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4303
c3d2689d
AZ		 4304 omap_inth_reset(mpu->ih[0]);
4305 omap_inth_reset(mpu->ih[1]);
4306 omap_dma_reset(mpu->dma);
4307 omap_mpu_timer_reset(mpu->timer[0]);
4308 omap_mpu_timer_reset(mpu->timer[1]);
4309 omap_mpu_timer_reset(mpu->timer[2]);
4310 omap_wd_timer_reset(mpu->wdt);
4311 omap_os_timer_reset(mpu->os_timer);
4312 omap_lcdc_reset(mpu->lcd);
4313 omap_ulpd_pm_reset(mpu);
4314 omap_pin_cfg_reset(mpu);
4315 omap_mpui_reset(mpu);
4316 omap_tipb_bridge_reset(mpu->private_tipb);
4317 omap_tipb_bridge_reset(mpu->public_tipb);
4318 omap_dpll_reset(&mpu->dpll[0]);
4319 omap_dpll_reset(&mpu->dpll[1]);
4320 omap_dpll_reset(&mpu->dpll[2]);
d951f6ff
AZ		 4321 omap_uart_reset(mpu->uart[0]);
4322 omap_uart_reset(mpu->uart[1]);
4323 omap_uart_reset(mpu->uart[2]);
b30bb3a2 4324 omap_mmc_reset(mpu->mmc);
fe71e81a 4325 omap_mpuio_reset(mpu->mpuio);
64330148 4326 omap_gpio_reset(mpu->gpio);
d951f6ff 4327 omap_uwire_reset(mpu->microwire);
66450b15 4328 omap_pwl_reset(mpu);
4a2c8ac2 4329 omap_pwt_reset(mpu);
827df9f3 4330 omap_i2c_reset(mpu->i2c[0]);
5c1c390f 4331 omap_rtc_reset(mpu->rtc);
d8f699cb
AZ		 4332 omap_mcbsp_reset(mpu->mcbsp1);
4333 omap_mcbsp_reset(mpu->mcbsp2);
4334 omap_mcbsp_reset(mpu->mcbsp3);
f9d43072
AZ		 4335 omap_lpg_reset(mpu->led[0]);
4336 omap_lpg_reset(mpu->led[1]);
8ef6367e 4337 omap_clkm_reset(mpu);
c3d2689d
AZ		 4338 cpu_reset(mpu->env);
4339}
4340
cf965d24 4341static const struct omap_map_s {
c227f099
AL		 4342 target_phys_addr_t phys_dsp;
4343 target_phys_addr_t phys_mpu;
cf965d24
AZ		 4344 uint32_t size;
4345 const char *name;
4346} omap15xx_dsp_mm[] = {
4347 /* Strobe 0 */
4348 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
4349 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
4350 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
4351 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
4352 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
4353 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
4354 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
4355 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
4356 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
4357 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
4358 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
4359 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
4360 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
4361 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
4362 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
4363 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
4364 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
4365 /* Strobe 1 */
4366 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
4367
4368 { 0 }
4369};
4370
4371static void omap_setup_dsp_mapping(const struct omap_map_s *map)
4372{
4373 int io;
4374
4375 for (; map->phys_dsp; map ++) {
4376 io = cpu_get_physical_page_desc(map->phys_mpu);
4377
4378 cpu_register_physical_memory(map->phys_dsp, map->size, io);
4379 }
4380}
4381
827df9f3 4382void omap_mpu_wakeup(void *opaque, int irq, int req)
c3d2689d
AZ		 4383{
4384 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4385
fe71e81a
AZ		 4386 if (mpu->env->halted)
4387 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
c3d2689d
AZ		 4388}
4389
827df9f3 4390static const struct dma_irq_map omap1_dma_irq_map[] = {
089b7c0a
AZ		 4391 { 0, OMAP_INT_DMA_CH0_6 },
4392 { 0, OMAP_INT_DMA_CH1_7 },
4393 { 0, OMAP_INT_DMA_CH2_8 },
4394 { 0, OMAP_INT_DMA_CH3 },
4395 { 0, OMAP_INT_DMA_CH4 },
4396 { 0, OMAP_INT_DMA_CH5 },
4397 { 1, OMAP_INT_1610_DMA_CH6 },
4398 { 1, OMAP_INT_1610_DMA_CH7 },
4399 { 1, OMAP_INT_1610_DMA_CH8 },
4400 { 1, OMAP_INT_1610_DMA_CH9 },
4401 { 1, OMAP_INT_1610_DMA_CH10 },
4402 { 1, OMAP_INT_1610_DMA_CH11 },
4403 { 1, OMAP_INT_1610_DMA_CH12 },
4404 { 1, OMAP_INT_1610_DMA_CH13 },
4405 { 1, OMAP_INT_1610_DMA_CH14 },
4406 { 1, OMAP_INT_1610_DMA_CH15 }
4407};
4408
b4e3104b
AZ		 4409/* DMA ports for OMAP1 */
4410static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
c227f099 4411 target_phys_addr_t addr)
b4e3104b
AZ		 4412{
4413 return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
4414}
4415
4416static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
c227f099 4417 target_phys_addr_t addr)
b4e3104b
AZ		 4418{
4419 return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
4420}
4421
4422static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
c227f099 4423 target_phys_addr_t addr)
b4e3104b
AZ		 4424{
4425 return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
4426}
4427
4428static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
c227f099 4429 target_phys_addr_t addr)
b4e3104b
AZ		 4430{
4431 return addr >= 0xfffb0000 && addr < 0xffff0000;
4432}
4433
4434static int omap_validate_local_addr(struct omap_mpu_state_s *s,
c227f099 4435 target_phys_addr_t addr)
b4e3104b
AZ		 4436{
4437 return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
4438}
4439
4440static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
c227f099 4441 target_phys_addr_t addr)
b4e3104b
AZ		 4442{
4443 return addr >= 0xe1010000 && addr < 0xe1020004;
4444}
4445
c3d2689d 4446struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
3023f332 4447 const char *core)
c3d2689d 4448{
089b7c0a 4449 int i;
c3d2689d
AZ		 4450 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4451 qemu_mallocz(sizeof(struct omap_mpu_state_s));
c227f099 4452 ram_addr_t imif_base, emiff_base;
106627d0 4453 qemu_irq *cpu_irq;
089b7c0a 4454 qemu_irq dma_irqs[6];
751c6a17 4455 DriveInfo *dinfo;
106627d0 4456
aaed909a
FB		 4457 if (!core)
4458 core = "ti925t";
c3d2689d
AZ		 4459
4460 /* Core */
4461 s->mpu_model = omap310;
aaed909a
FB		 4462 s->env = cpu_init(core);
4463 if (!s->env) {
4464 fprintf(stderr, "Unable to find CPU definition\n");
4465 exit(1);
4466 }
c3d2689d
AZ		 4467 s->sdram_size = sdram_size;
4468 s->sram_size = OMAP15XX_SRAM_SIZE;
4469
fe71e81a
AZ		 4470 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
4471
c3d2689d
AZ		 4472 /* Clocks */
4473 omap_clk_init(s);
4474
4475 /* Memory-mapped stuff */
4476 cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
4477 (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
4478 cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
4479 (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
4480
4481 omap_clkm_init(0xfffece00, 0xe1008000, s);
4482
106627d0 4483 cpu_irq = arm_pic_init_cpu(s->env);
827df9f3 4484 s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
106627d0 4485 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
c3d2689d 4486 omap_findclk(s, "arminth_ck"));
827df9f3 4487 s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1],
106627d0 4488 s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], NULL,
c3d2689d 4489 omap_findclk(s, "arminth_ck"));
c3d2689d 4490
089b7c0a 4491 for (i = 0; i < 6; i ++)
827df9f3
AZ		 4492 dma_irqs[i] =
4493 s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr];
089b7c0a
AZ		 4494 s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD],
4495 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
4496
c3d2689d
AZ		 4497 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
4498 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
4499 s->port[imif ].addr_valid = omap_validate_imif_addr;
4500 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
4501 s->port[local ].addr_valid = omap_validate_local_addr;
4502 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
4503
afbb5194
AZ		 4504 /* Register SDRAM and SRAM DMA ports for fast transfers. */
4505 soc_dma_port_add_mem_ram(s->dma,
4506 emiff_base, OMAP_EMIFF_BASE, s->sdram_size);
4507 soc_dma_port_add_mem_ram(s->dma,
4508 imif_base, OMAP_IMIF_BASE, s->sram_size);
4509
c3d2689d
AZ		 4510 s->timer[0] = omap_mpu_timer_init(0xfffec500,
4511 s->irq[0][OMAP_INT_TIMER1],
4512 omap_findclk(s, "mputim_ck"));
4513 s->timer[1] = omap_mpu_timer_init(0xfffec600,
4514 s->irq[0][OMAP_INT_TIMER2],
4515 omap_findclk(s, "mputim_ck"));
4516 s->timer[2] = omap_mpu_timer_init(0xfffec700,
4517 s->irq[0][OMAP_INT_TIMER3],
4518 omap_findclk(s, "mputim_ck"));
4519
4520 s->wdt = omap_wd_timer_init(0xfffec800,
4521 s->irq[0][OMAP_INT_WD_TIMER],
4522 omap_findclk(s, "armwdt_ck"));
4523
4524 s->os_timer = omap_os_timer_init(0xfffb9000,
4525 s->irq[1][OMAP_INT_OS_TIMER],
4526 omap_findclk(s, "clk32-kHz"));
4527
4528 s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
3023f332 4529 omap_dma_get_lcdch(s->dma), imif_base, emiff_base,
c3d2689d
AZ		 4530 omap_findclk(s, "lcd_ck"));
4531
4532 omap_ulpd_pm_init(0xfffe0800, s);
4533 omap_pin_cfg_init(0xfffe1000, s);
4534 omap_id_init(s);
4535
4536 omap_mpui_init(0xfffec900, s);
4537
4538 s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
4539 s->irq[0][OMAP_INT_BRIDGE_PRIV],
4540 omap_findclk(s, "tipb_ck"));
4541 s->public_tipb = omap_tipb_bridge_init(0xfffed300,
4542 s->irq[0][OMAP_INT_BRIDGE_PUB],
4543 omap_findclk(s, "tipb_ck"));
4544
4545 omap_tcmi_init(0xfffecc00, s);
4546
d951f6ff 4547 s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
c3d2689d 4548 omap_findclk(s, "uart1_ck"),
827df9f3
AZ		 4549 omap_findclk(s, "uart1_ck"),
4550 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
c3d2689d 4551 serial_hds[0]);
d951f6ff 4552 s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
c3d2689d 4553 omap_findclk(s, "uart2_ck"),
827df9f3
AZ		 4554 omap_findclk(s, "uart2_ck"),
4555 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
b9d38e95 4556 serial_hds[0] ? serial_hds[1] : NULL);
13643323 4557 s->uart[2] = omap_uart_init(0xfffb9800, s->irq[0][OMAP_INT_UART3],
c3d2689d 4558 omap_findclk(s, "uart3_ck"),
827df9f3
AZ		 4559 omap_findclk(s, "uart3_ck"),
4560 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
b9d38e95 4561 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
c3d2689d
AZ		 4562
4563 omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
4564 omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
4565 omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
4566
751c6a17
GH		 4567 dinfo = drive_get(IF_SD, 0, 0);
4568 if (!dinfo) {
e4bcb14c
TS		 4569 fprintf(stderr, "qemu: missing SecureDigital device\n");
4570 exit(1);
4571 }
751c6a17 4572 s->mmc = omap_mmc_init(0xfffb7800, dinfo->bdrv,
9d413d1d
AZ		 4573 s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
4574 omap_findclk(s, "mmc_ck"));
b30bb3a2 4575
fe71e81a
AZ		 4576 s->mpuio = omap_mpuio_init(0xfffb5000,
4577 s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
4578 s->wakeup, omap_findclk(s, "clk32-kHz"));
4579
3efda49d 4580 s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1],
66450b15 4581 omap_findclk(s, "arm_gpio_ck"));
64330148 4582
d951f6ff
AZ		 4583 s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
4584 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
4585
d8f699cb
AZ		 4586 omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck"));
4587 omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck"));
66450b15 4588
827df9f3 4589 s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
4a2c8ac2
AZ		 4590 &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
4591
5c1c390f
AZ		 4592 s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER],
4593 omap_findclk(s, "clk32-kHz"));
02645926 4594
d8f699cb
AZ		 4595 s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
4596 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
4597 s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
4598 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
4599 s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
4600 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
4601
f9d43072
AZ		 4602 s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
4603 s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
4604
02645926 4605 /* Register mappings not currenlty implemented:
02645926
AZ		 4606 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4607 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4608 * USB W2FC fffb4000 - fffb47ff
4609 * Camera Interface fffb6800 - fffb6fff
02645926
AZ		 4610 * USB Host fffba000 - fffba7ff
4611 * FAC fffba800 - fffbafff
4612 * HDQ/1-Wire fffbc000 - fffbc7ff
b854bc19 4613 * TIPB switches fffbc800 - fffbcfff
02645926
AZ		 4614 * Mailbox fffcf000 - fffcf7ff
4615 * Local bus IF fffec100 - fffec1ff
4616 * Local bus MMU fffec200 - fffec2ff
4617 * DSP MMU fffed200 - fffed2ff
4618 */
4619
cf965d24 4620 omap_setup_dsp_mapping(omap15xx_dsp_mm);
f9d43072 4621 omap_setup_mpui_io(s);
cf965d24 4622
a08d4367 4623 qemu_register_reset(omap1_mpu_reset, s);
c3d2689d
AZ		 4624
4625 return s;
4626}
Qemu copy for testing