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omap1: convert to memory API (part I)
[qemu.git] / hw / omap1.c
CommitLineData
c3d2689d
AZ		 1/*
2 * TI OMAP processors emulation.
3 *
b4e3104b 4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
c3d2689d
AZ		 5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
827df9f3
AZ		 8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
c3d2689d
AZ		 10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
fad6cb1a 16 * You should have received a copy of the GNU General Public License along
8167ee88 17 * with this program; if not, see <http://www.gnu.org/licenses/>.
c3d2689d 18 */
87ecb68b
PB		 19#include "hw.h"
20#include "arm-misc.h"
21#include "omap.h"
22#include "sysemu.h"
23#include "qemu-timer.h"
827df9f3 24#include "qemu-char.h"
afbb5194 25#include "soc_dma.h"
87ecb68b
PB		 26/* We use pc-style serial ports. */
27#include "pc.h"
2446333c 28#include "blockdev.h"
45416789 29#include "range.h"
77831c20 30#include "sysbus.h"
c3d2689d 31
827df9f3 32/* Should signal the TCMI/GPMC */
c227f099 33uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
66450b15 34{
02645926
AZ		 35 uint8_t ret;
36
66450b15 37 OMAP_8B_REG(addr);
b854bc19 38 cpu_physical_memory_read(addr, (void *) &ret, 1);
02645926 39 return ret;
66450b15
AZ		 40}
41
c227f099 42void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
66450b15
AZ		 43 uint32_t value)
44{
b854bc19
AZ		 45 uint8_t val8 = value;
46
66450b15 47 OMAP_8B_REG(addr);
b854bc19 48 cpu_physical_memory_write(addr, (void *) &val8, 1);
66450b15
AZ		 49}
50
c227f099 51uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
c3d2689d 52{
b854bc19
AZ		 53 uint16_t ret;
54
c3d2689d 55 OMAP_16B_REG(addr);
b854bc19
AZ		 56 cpu_physical_memory_read(addr, (void *) &ret, 2);
57 return ret;
c3d2689d
AZ		 58}
59
c227f099 60void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 61 uint32_t value)
62{
b854bc19
AZ		 63 uint16_t val16 = value;
64
c3d2689d 65 OMAP_16B_REG(addr);
b854bc19 66 cpu_physical_memory_write(addr, (void *) &val16, 2);
c3d2689d
AZ		 67}
68
c227f099 69uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
c3d2689d 70{
b854bc19
AZ		 71 uint32_t ret;
72
c3d2689d 73 OMAP_32B_REG(addr);
b854bc19
AZ		 74 cpu_physical_memory_read(addr, (void *) &ret, 4);
75 return ret;
c3d2689d
AZ		 76}
77
c227f099 78void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 79 uint32_t value)
80{
81 OMAP_32B_REG(addr);
b854bc19 82 cpu_physical_memory_write(addr, (void *) &value, 4);
c3d2689d
AZ		 83}
84
c3d2689d
AZ		 85/* MPU OS timers */
86struct omap_mpu_timer_s {
4b3fedf3 87 MemoryRegion iomem;
c3d2689d
AZ		 88 qemu_irq irq;
89 omap_clk clk;
c3d2689d
AZ		 90 uint32_t val;
91 int64_t time;
92 QEMUTimer *timer;
e856f2ad 93 QEMUBH *tick;
c3d2689d
AZ		 94 int64_t rate;
95 int it_ena;
96
97 int enable;
98 int ptv;
99 int ar;
100 int st;
101 uint32_t reset_val;
102};
103
104static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
105{
74475455 106 uint64_t distance = qemu_get_clock_ns(vm_clock) - timer->time;
c3d2689d
AZ		 107
108 if (timer->st && timer->enable && timer->rate)
109 return timer->val - muldiv64(distance >> (timer->ptv + 1),
6ee093c9 110 timer->rate, get_ticks_per_sec());
c3d2689d
AZ		 111 else
112 return timer->val;
113}
114
115static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
116{
117 timer->val = omap_timer_read(timer);
74475455 118 timer->time = qemu_get_clock_ns(vm_clock);
c3d2689d
AZ		 119}
120
121static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
122{
123 int64_t expires;
124
125 if (timer->enable && timer->st && timer->rate) {
126 timer->val = timer->reset_val; /* Should skip this on clk enable */
b8b137d6 127 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1),
6ee093c9 128 get_ticks_per_sec(), timer->rate);
b854bc19
AZ		 129
130 /* If timer expiry would be sooner than in about 1 ms and
131 * auto-reload isn't set, then fire immediately. This is a hack
132 * to make systems like PalmOS run in acceptable time. PalmOS
133 * sets the interval to a very low value and polls the status bit
134 * in a busy loop when it wants to sleep just a couple of CPU
135 * ticks. */
6ee093c9 136 if (expires > (get_ticks_per_sec() >> 10) || timer->ar)
b854bc19 137 qemu_mod_timer(timer->timer, timer->time + expires);
e856f2ad
AZ		 138 else
139 qemu_bh_schedule(timer->tick);
c3d2689d
AZ		 140 } else
141 qemu_del_timer(timer->timer);
142}
143
e856f2ad 144static void omap_timer_fire(void *opaque)
c3d2689d 145{
e856f2ad 146 struct omap_mpu_timer_s *timer = opaque;
c3d2689d
AZ		 147
148 if (!timer->ar) {
149 timer->val = 0;
150 timer->st = 0;
151 }
152
153 if (timer->it_ena)
106627d0
AZ		 154 /* Edge-triggered irq */
155 qemu_irq_pulse(timer->irq);
e856f2ad
AZ		 156}
157
158static void omap_timer_tick(void *opaque)
159{
160 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
161
162 omap_timer_sync(timer);
163 omap_timer_fire(timer);
c3d2689d
AZ		 164 omap_timer_update(timer);
165}
166
167static void omap_timer_clk_update(void *opaque, int line, int on)
168{
169 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
170
171 omap_timer_sync(timer);
172 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
173 omap_timer_update(timer);
174}
175
176static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
177{
178 omap_clk_adduser(timer->clk,
179 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
180 timer->rate = omap_clk_getrate(timer->clk);
181}
182
4b3fedf3
AK		 183static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr,
184 unsigned size)
c3d2689d
AZ		 185{
186 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
c3d2689d 187
4b3fedf3
AK		 188 if (size != 4) {
189 return omap_badwidth_read32(opaque, addr);
190 }
191
8da3ff18 192 switch (addr) {
c3d2689d
AZ		 193 case 0x00: /* CNTL_TIMER */
194 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
195
196 case 0x04: /* LOAD_TIM */
197 break;
198
199 case 0x08: /* READ_TIM */
200 return omap_timer_read(s);
201 }
202
203 OMAP_BAD_REG(addr);
204 return 0;
205}
206
c227f099 207static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 208 uint64_t value, unsigned size)
c3d2689d
AZ		 209{
210 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
c3d2689d 211
4b3fedf3
AK		 212 if (size != 4) {
213 return omap_badwidth_write32(opaque, addr, value);
214 }
215
8da3ff18 216 switch (addr) {
c3d2689d
AZ		 217 case 0x00: /* CNTL_TIMER */
218 omap_timer_sync(s);
219 s->enable = (value >> 5) & 1;
220 s->ptv = (value >> 2) & 7;
221 s->ar = (value >> 1) & 1;
222 s->st = value & 1;
223 omap_timer_update(s);
224 return;
225
226 case 0x04: /* LOAD_TIM */
227 s->reset_val = value;
228 return;
229
230 case 0x08: /* READ_TIM */
231 OMAP_RO_REG(addr);
232 break;
233
234 default:
235 OMAP_BAD_REG(addr);
236 }
237}
238
4b3fedf3
AK		 239static const MemoryRegionOps omap_mpu_timer_ops = {
240 .read = omap_mpu_timer_read,
241 .write = omap_mpu_timer_write,
242 .endianness = DEVICE_LITTLE_ENDIAN,
c3d2689d
AZ		 243};
244
245static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
246{
247 qemu_del_timer(s->timer);
248 s->enable = 0;
249 s->reset_val = 31337;
250 s->val = 0;
251 s->ptv = 0;
252 s->ar = 0;
253 s->st = 0;
254 s->it_ena = 1;
255}
256
4b3fedf3
AK		 257static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
258 target_phys_addr_t base,
c3d2689d
AZ		 259 qemu_irq irq, omap_clk clk)
260{
c3d2689d 261 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
7267c094 262 g_malloc0(sizeof(struct omap_mpu_timer_s));
c3d2689d
AZ		 263
264 s->irq = irq;
265 s->clk = clk;
74475455 266 s->timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, s);
e856f2ad 267 s->tick = qemu_bh_new(omap_timer_fire, s);
c3d2689d
AZ		 268 omap_mpu_timer_reset(s);
269 omap_timer_clk_setup(s);
270
4b3fedf3
AK		 271 memory_region_init_io(&s->iomem, &omap_mpu_timer_ops, s,
272 "omap-mpu-timer", 0x100);
273
274 memory_region_add_subregion(system_memory, base, &s->iomem);
c3d2689d
AZ		 275
276 return s;
277}
278
279/* Watchdog timer */
280struct omap_watchdog_timer_s {
281 struct omap_mpu_timer_s timer;
4b3fedf3 282 MemoryRegion iomem;
c3d2689d
AZ		 283 uint8_t last_wr;
284 int mode;
285 int free;
286 int reset;
287};
288
4b3fedf3
AK		 289static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr,
290 unsigned size)
c3d2689d
AZ		 291{
292 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
c3d2689d 293
4b3fedf3
AK		 294 if (size != 2) {
295 return omap_badwidth_read16(opaque, addr);
296 }
297
8da3ff18 298 switch (addr) {
c3d2689d
AZ		 299 case 0x00: /* CNTL_TIMER */
300 return (s->timer.ptv << 9) | (s->timer.ar << 8) |
301 (s->timer.st << 7) | (s->free << 1);
302
303 case 0x04: /* READ_TIMER */
304 return omap_timer_read(&s->timer);
305
306 case 0x08: /* TIMER_MODE */
307 return s->mode << 15;
308 }
309
310 OMAP_BAD_REG(addr);
311 return 0;
312}
313
c227f099 314static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 315 uint64_t value, unsigned size)
c3d2689d
AZ		 316{
317 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
c3d2689d 318
4b3fedf3
AK		 319 if (size != 2) {
320 return omap_badwidth_write16(opaque, addr, value);
321 }
322
8da3ff18 323 switch (addr) {
c3d2689d
AZ		 324 case 0x00: /* CNTL_TIMER */
325 omap_timer_sync(&s->timer);
326 s->timer.ptv = (value >> 9) & 7;
327 s->timer.ar = (value >> 8) & 1;
328 s->timer.st = (value >> 7) & 1;
329 s->free = (value >> 1) & 1;
330 omap_timer_update(&s->timer);
331 break;
332
333 case 0x04: /* LOAD_TIMER */
334 s->timer.reset_val = value & 0xffff;
335 break;
336
337 case 0x08: /* TIMER_MODE */
338 if (!s->mode && ((value >> 15) & 1))
339 omap_clk_get(s->timer.clk);
340 s->mode |= (value >> 15) & 1;
341 if (s->last_wr == 0xf5) {
342 if ((value & 0xff) == 0xa0) {
d8f699cb
AZ		 343 if (s->mode) {
344 s->mode = 0;
345 omap_clk_put(s->timer.clk);
346 }
c3d2689d
AZ		 347 } else {
348 /* XXX: on T|E hardware somehow this has no effect,
349 * on Zire 71 it works as specified. */
350 s->reset = 1;
351 qemu_system_reset_request();
352 }
353 }
354 s->last_wr = value & 0xff;
355 break;
356
357 default:
358 OMAP_BAD_REG(addr);
359 }
360}
361
4b3fedf3
AK		 362static const MemoryRegionOps omap_wd_timer_ops = {
363 .read = omap_wd_timer_read,
364 .write = omap_wd_timer_write,
365 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 366};
367
368static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
369{
370 qemu_del_timer(s->timer.timer);
371 if (!s->mode)
372 omap_clk_get(s->timer.clk);
373 s->mode = 1;
374 s->free = 1;
375 s->reset = 0;
376 s->timer.enable = 1;
377 s->timer.it_ena = 1;
378 s->timer.reset_val = 0xffff;
379 s->timer.val = 0;
380 s->timer.st = 0;
381 s->timer.ptv = 0;
382 s->timer.ar = 0;
383 omap_timer_update(&s->timer);
384}
385
4b3fedf3
AK		 386static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
387 target_phys_addr_t base,
c3d2689d
AZ		 388 qemu_irq irq, omap_clk clk)
389{
c3d2689d 390 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
7267c094 391 g_malloc0(sizeof(struct omap_watchdog_timer_s));
c3d2689d
AZ		 392
393 s->timer.irq = irq;
394 s->timer.clk = clk;
74475455 395 s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
c3d2689d
AZ		 396 omap_wd_timer_reset(s);
397 omap_timer_clk_setup(&s->timer);
398
4b3fedf3
AK		 399 memory_region_init_io(&s->iomem, &omap_wd_timer_ops, s,
400 "omap-wd-timer", 0x100);
401 memory_region_add_subregion(memory, base, &s->iomem);
c3d2689d
AZ		 402
403 return s;
404}
405
406/* 32-kHz timer */
407struct omap_32khz_timer_s {
408 struct omap_mpu_timer_s timer;
4b3fedf3 409 MemoryRegion iomem;
c3d2689d
AZ		 410};
411
4b3fedf3
AK		 412static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,
413 unsigned size)
c3d2689d
AZ		 414{
415 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
cf965d24 416 int offset = addr & OMAP_MPUI_REG_MASK;
c3d2689d 417
4b3fedf3
AK		 418 if (size != 4) {
419 return omap_badwidth_read32(opaque, addr);
420 }
421
c3d2689d
AZ		 422 switch (offset) {
423 case 0x00: /* TVR */
424 return s->timer.reset_val;
425
426 case 0x04: /* TCR */
427 return omap_timer_read(&s->timer);
428
429 case 0x08: /* CR */
430 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
431
432 default:
433 break;
434 }
435 OMAP_BAD_REG(addr);
436 return 0;
437}
438
c227f099 439static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 440 uint64_t value, unsigned size)
c3d2689d
AZ		 441{
442 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
cf965d24 443 int offset = addr & OMAP_MPUI_REG_MASK;
c3d2689d 444
4b3fedf3
AK		 445 if (size != 4) {
446 return omap_badwidth_write32(opaque, addr, value);
447 }
448
c3d2689d
AZ		 449 switch (offset) {
450 case 0x00: /* TVR */
451 s->timer.reset_val = value & 0x00ffffff;
452 break;
453
454 case 0x04: /* TCR */
455 OMAP_RO_REG(addr);
456 break;
457
458 case 0x08: /* CR */
459 s->timer.ar = (value >> 3) & 1;
460 s->timer.it_ena = (value >> 2) & 1;
461 if (s->timer.st != (value & 1) || (value & 2)) {
462 omap_timer_sync(&s->timer);
463 s->timer.enable = value & 1;
464 s->timer.st = value & 1;
465 omap_timer_update(&s->timer);
466 }
467 break;
468
469 default:
470 OMAP_BAD_REG(addr);
471 }
472}
473
4b3fedf3
AK		 474static const MemoryRegionOps omap_os_timer_ops = {
475 .read = omap_os_timer_read,
476 .write = omap_os_timer_write,
477 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 478};
479
480static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
481{
482 qemu_del_timer(s->timer.timer);
483 s->timer.enable = 0;
484 s->timer.it_ena = 0;
485 s->timer.reset_val = 0x00ffffff;
486 s->timer.val = 0;
487 s->timer.st = 0;
488 s->timer.ptv = 0;
489 s->timer.ar = 1;
490}
491
4b3fedf3
AK		 492static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
493 target_phys_addr_t base,
c3d2689d
AZ		 494 qemu_irq irq, omap_clk clk)
495{
c3d2689d 496 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
7267c094 497 g_malloc0(sizeof(struct omap_32khz_timer_s));
c3d2689d
AZ		 498
499 s->timer.irq = irq;
500 s->timer.clk = clk;
74475455 501 s->timer.timer = qemu_new_timer_ns(vm_clock, omap_timer_tick, &s->timer);
c3d2689d
AZ		 502 omap_os_timer_reset(s);
503 omap_timer_clk_setup(&s->timer);
504
4b3fedf3
AK		 505 memory_region_init_io(&s->iomem, &omap_os_timer_ops, s,
506 "omap-os-timer", 0x800);
507 memory_region_add_subregion(memory, base, &s->iomem);
c3d2689d
AZ		 508
509 return s;
510}
511
512/* Ultra Low-Power Device Module */
4b3fedf3
AK		 513static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
514 unsigned size)
c3d2689d
AZ		 515{
516 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 517 uint16_t ret;
518
4b3fedf3
AK		 519 if (size != 2) {
520 return omap_badwidth_read16(opaque, addr);
521 }
522
8da3ff18 523 switch (addr) {
c3d2689d 524 case 0x14: /* IT_STATUS */
8da3ff18
PB		 525 ret = s->ulpd_pm_regs[addr >> 2];
526 s->ulpd_pm_regs[addr >> 2] = 0;
c3d2689d
AZ		 527 qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
528 return ret;
529
530 case 0x18: /* Reserved */
531 case 0x1c: /* Reserved */
532 case 0x20: /* Reserved */
533 case 0x28: /* Reserved */
534 case 0x2c: /* Reserved */
535 OMAP_BAD_REG(addr);
536 case 0x00: /* COUNTER_32_LSB */
537 case 0x04: /* COUNTER_32_MSB */
538 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
539 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
540 case 0x10: /* GAUGING_CTRL */
541 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
542 case 0x30: /* CLOCK_CTRL */
543 case 0x34: /* SOFT_REQ */
544 case 0x38: /* COUNTER_32_FIQ */
545 case 0x3c: /* DPLL_CTRL */
546 case 0x40: /* STATUS_REQ */
547 /* XXX: check clk::usecount state for every clock */
548 case 0x48: /* LOCL_TIME */
549 case 0x4c: /* APLL_CTRL */
550 case 0x50: /* POWER_CTRL */
8da3ff18 551 return s->ulpd_pm_regs[addr >> 2];
c3d2689d
AZ		 552 }
553
554 OMAP_BAD_REG(addr);
555 return 0;
556}
557
558static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
559 uint16_t diff, uint16_t value)
560{
561 if (diff & (1 << 4)) /* USB_MCLK_EN */
562 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
563 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
564 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
565}
566
567static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
568 uint16_t diff, uint16_t value)
569{
570 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
571 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
572 if (diff & (1 << 1)) /* SOFT_COM_REQ */
573 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
574 if (diff & (1 << 2)) /* SOFT_SDW_REQ */
575 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
576 if (diff & (1 << 3)) /* SOFT_USB_REQ */
577 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
578}
579
c227f099 580static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 581 uint64_t value, unsigned size)
c3d2689d
AZ		 582{
583 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 584 int64_t now, ticks;
585 int div, mult;
586 static const int bypass_div[4] = { 1, 2, 4, 4 };
587 uint16_t diff;
588
4b3fedf3
AK		 589 if (size != 2) {
590 return omap_badwidth_write16(opaque, addr, value);
591 }
592
8da3ff18 593 switch (addr) {
c3d2689d
AZ		 594 case 0x00: /* COUNTER_32_LSB */
595 case 0x04: /* COUNTER_32_MSB */
596 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
597 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
598 case 0x14: /* IT_STATUS */
599 case 0x40: /* STATUS_REQ */
600 OMAP_RO_REG(addr);
601 break;
602
603 case 0x10: /* GAUGING_CTRL */
604 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
8da3ff18 605 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) {
74475455 606 now = qemu_get_clock_ns(vm_clock);
c3d2689d
AZ		 607
608 if (value & 1)
609 s->ulpd_gauge_start = now;
610 else {
611 now -= s->ulpd_gauge_start;
612
613 /* 32-kHz ticks */
6ee093c9 614 ticks = muldiv64(now, 32768, get_ticks_per_sec());
c3d2689d
AZ		 615 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
616 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
617 if (ticks >> 32) /* OVERFLOW_32K */
618 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
619
620 /* High frequency ticks */
6ee093c9 621 ticks = muldiv64(now, 12000000, get_ticks_per_sec());
c3d2689d
AZ		 622 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
623 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
624 if (ticks >> 32) /* OVERFLOW_HI_FREQ */
625 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
626
627 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
628 qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
629 }
630 }
8da3ff18 631 s->ulpd_pm_regs[addr >> 2] = value;
c3d2689d
AZ		 632 break;
633
634 case 0x18: /* Reserved */
635 case 0x1c: /* Reserved */
636 case 0x20: /* Reserved */
637 case 0x28: /* Reserved */
638 case 0x2c: /* Reserved */
639 OMAP_BAD_REG(addr);
640 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
641 case 0x38: /* COUNTER_32_FIQ */
642 case 0x48: /* LOCL_TIME */
643 case 0x50: /* POWER_CTRL */
8da3ff18 644 s->ulpd_pm_regs[addr >> 2] = value;
c3d2689d
AZ		 645 break;
646
647 case 0x30: /* CLOCK_CTRL */
8da3ff18
PB		 648 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
649 s->ulpd_pm_regs[addr >> 2] = value & 0x3f;
c3d2689d
AZ		 650 omap_ulpd_clk_update(s, diff, value);
651 break;
652
653 case 0x34: /* SOFT_REQ */
8da3ff18
PB		 654 diff = s->ulpd_pm_regs[addr >> 2] ^ value;
655 s->ulpd_pm_regs[addr >> 2] = value & 0x1f;
c3d2689d
AZ		 656 omap_ulpd_req_update(s, diff, value);
657 break;
658
659 case 0x3c: /* DPLL_CTRL */
660 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
661 * omitted altogether, probably a typo. */
662 /* This register has identical semantics with DPLL(1:3) control
663 * registers, see omap_dpll_write() */
8da3ff18
PB		 664 diff = s->ulpd_pm_regs[addr >> 2] & value;
665 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff;
c3d2689d
AZ		 666 if (diff & (0x3ff << 2)) {
667 if (value & (1 << 4)) { /* PLL_ENABLE */
668 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
669 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
670 } else {
671 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
672 mult = 1;
673 }
674 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
675 }
676
677 /* Enter the desired mode. */
8da3ff18
PB		 678 s->ulpd_pm_regs[addr >> 2] =
679 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) |
680 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1);
c3d2689d
AZ		 681
682 /* Act as if the lock is restored. */
8da3ff18 683 s->ulpd_pm_regs[addr >> 2] |= 2;
c3d2689d
AZ		 684 break;
685
686 case 0x4c: /* APLL_CTRL */
8da3ff18
PB		 687 diff = s->ulpd_pm_regs[addr >> 2] & value;
688 s->ulpd_pm_regs[addr >> 2] = value & 0xf;
c3d2689d
AZ		 689 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
690 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
691 (value & (1 << 0)) ? "apll" : "dpll4"));
692 break;
693
694 default:
695 OMAP_BAD_REG(addr);
696 }
697}
698
4b3fedf3
AK		 699static const MemoryRegionOps omap_ulpd_pm_ops = {
700 .read = omap_ulpd_pm_read,
701 .write = omap_ulpd_pm_write,
702 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 703};
704
705static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
706{
707 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
708 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
709 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
710 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
711 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
712 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
713 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
714 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
715 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
716 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
717 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
718 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
719 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
720 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
721 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
722 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
723 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
724 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
725 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
726 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
727 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
728 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
729 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
730}
731
4b3fedf3
AK		 732static void omap_ulpd_pm_init(MemoryRegion *system_memory,
733 target_phys_addr_t base,
c3d2689d
AZ		 734 struct omap_mpu_state_s *mpu)
735{
4b3fedf3
AK		 736 memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
737 "omap-ulpd-pm", 0x800);
738 memory_region_add_subregion(system_memory, base, &mpu->ulpd_pm_iomem);
c3d2689d
AZ		 739 omap_ulpd_pm_reset(mpu);
740}
741
742/* OMAP Pin Configuration */
4b3fedf3
AK		 743static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr,
744 unsigned size)
c3d2689d
AZ		 745{
746 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 747
4b3fedf3
AK		 748 if (size != 4) {
749 return omap_badwidth_read32(opaque, addr);
750 }
751
8da3ff18 752 switch (addr) {
c3d2689d
AZ		 753 case 0x00: /* FUNC_MUX_CTRL_0 */
754 case 0x04: /* FUNC_MUX_CTRL_1 */
755 case 0x08: /* FUNC_MUX_CTRL_2 */
8da3ff18 756 return s->func_mux_ctrl[addr >> 2];
c3d2689d
AZ		 757
758 case 0x0c: /* COMP_MODE_CTRL_0 */
759 return s->comp_mode_ctrl[0];
760
761 case 0x10: /* FUNC_MUX_CTRL_3 */
762 case 0x14: /* FUNC_MUX_CTRL_4 */
763 case 0x18: /* FUNC_MUX_CTRL_5 */
764 case 0x1c: /* FUNC_MUX_CTRL_6 */
765 case 0x20: /* FUNC_MUX_CTRL_7 */
766 case 0x24: /* FUNC_MUX_CTRL_8 */
767 case 0x28: /* FUNC_MUX_CTRL_9 */
768 case 0x2c: /* FUNC_MUX_CTRL_A */
769 case 0x30: /* FUNC_MUX_CTRL_B */
770 case 0x34: /* FUNC_MUX_CTRL_C */
771 case 0x38: /* FUNC_MUX_CTRL_D */
8da3ff18 772 return s->func_mux_ctrl[(addr >> 2) - 1];
c3d2689d
AZ		 773
774 case 0x40: /* PULL_DWN_CTRL_0 */
775 case 0x44: /* PULL_DWN_CTRL_1 */
776 case 0x48: /* PULL_DWN_CTRL_2 */
777 case 0x4c: /* PULL_DWN_CTRL_3 */
8da3ff18 778 return s->pull_dwn_ctrl[(addr & 0xf) >> 2];
c3d2689d
AZ		 779
780 case 0x50: /* GATE_INH_CTRL_0 */
781 return s->gate_inh_ctrl[0];
782
783 case 0x60: /* VOLTAGE_CTRL_0 */
784 return s->voltage_ctrl[0];
785
786 case 0x70: /* TEST_DBG_CTRL_0 */
787 return s->test_dbg_ctrl[0];
788
789 case 0x80: /* MOD_CONF_CTRL_0 */
790 return s->mod_conf_ctrl[0];
791 }
792
793 OMAP_BAD_REG(addr);
794 return 0;
795}
796
797static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
798 uint32_t diff, uint32_t value)
799{
800 if (s->compat1509) {
801 if (diff & (1 << 9)) /* BLUETOOTH */
802 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
803 (~value >> 9) & 1);
804 if (diff & (1 << 7)) /* USB.CLKO */
805 omap_clk_onoff(omap_findclk(s, "usb.clko"),
806 (value >> 7) & 1);
807 }
808}
809
810static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
811 uint32_t diff, uint32_t value)
812{
813 if (s->compat1509) {
814 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
815 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
816 (value >> 31) & 1);
817 if (diff & (1 << 1)) /* CLK32K */
818 omap_clk_onoff(omap_findclk(s, "clk32k_out"),
819 (~value >> 1) & 1);
820 }
821}
822
823static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
824 uint32_t diff, uint32_t value)
825{
826 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
827 omap_clk_reparent(omap_findclk(s, "uart3_ck"),
828 omap_findclk(s, ((value >> 31) & 1) ?
829 "ck_48m" : "armper_ck"));
830 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
831 omap_clk_reparent(omap_findclk(s, "uart2_ck"),
832 omap_findclk(s, ((value >> 30) & 1) ?
833 "ck_48m" : "armper_ck"));
834 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
835 omap_clk_reparent(omap_findclk(s, "uart1_ck"),
836 omap_findclk(s, ((value >> 29) & 1) ?
837 "ck_48m" : "armper_ck"));
838 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
839 omap_clk_reparent(omap_findclk(s, "mmc_ck"),
840 omap_findclk(s, ((value >> 23) & 1) ?
841 "ck_48m" : "armper_ck"));
842 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
843 omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
844 omap_findclk(s, ((value >> 12) & 1) ?
845 "ck_48m" : "armper_ck"));
846 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
847 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
848}
849
c227f099 850static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 851 uint64_t value, unsigned size)
c3d2689d
AZ		 852{
853 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 854 uint32_t diff;
855
4b3fedf3
AK		 856 if (size != 4) {
857 return omap_badwidth_write32(opaque, addr, value);
858 }
859
8da3ff18 860 switch (addr) {
c3d2689d 861 case 0x00: /* FUNC_MUX_CTRL_0 */
8da3ff18
PB		 862 diff = s->func_mux_ctrl[addr >> 2] ^ value;
863 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 864 omap_pin_funcmux0_update(s, diff, value);
865 return;
866
867 case 0x04: /* FUNC_MUX_CTRL_1 */
8da3ff18
PB		 868 diff = s->func_mux_ctrl[addr >> 2] ^ value;
869 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 870 omap_pin_funcmux1_update(s, diff, value);
871 return;
872
873 case 0x08: /* FUNC_MUX_CTRL_2 */
8da3ff18 874 s->func_mux_ctrl[addr >> 2] = value;
c3d2689d
AZ		 875 return;
876
877 case 0x0c: /* COMP_MODE_CTRL_0 */
878 s->comp_mode_ctrl[0] = value;
879 s->compat1509 = (value != 0x0000eaef);
880 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
881 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
882 return;
883
884 case 0x10: /* FUNC_MUX_CTRL_3 */
885 case 0x14: /* FUNC_MUX_CTRL_4 */
886 case 0x18: /* FUNC_MUX_CTRL_5 */
887 case 0x1c: /* FUNC_MUX_CTRL_6 */
888 case 0x20: /* FUNC_MUX_CTRL_7 */
889 case 0x24: /* FUNC_MUX_CTRL_8 */
890 case 0x28: /* FUNC_MUX_CTRL_9 */
891 case 0x2c: /* FUNC_MUX_CTRL_A */
892 case 0x30: /* FUNC_MUX_CTRL_B */
893 case 0x34: /* FUNC_MUX_CTRL_C */
894 case 0x38: /* FUNC_MUX_CTRL_D */
8da3ff18 895 s->func_mux_ctrl[(addr >> 2) - 1] = value;
c3d2689d
AZ		 896 return;
897
898 case 0x40: /* PULL_DWN_CTRL_0 */
899 case 0x44: /* PULL_DWN_CTRL_1 */
900 case 0x48: /* PULL_DWN_CTRL_2 */
901 case 0x4c: /* PULL_DWN_CTRL_3 */
8da3ff18 902 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value;
c3d2689d
AZ		 903 return;
904
905 case 0x50: /* GATE_INH_CTRL_0 */
906 s->gate_inh_ctrl[0] = value;
907 return;
908
909 case 0x60: /* VOLTAGE_CTRL_0 */
910 s->voltage_ctrl[0] = value;
911 return;
912
913 case 0x70: /* TEST_DBG_CTRL_0 */
914 s->test_dbg_ctrl[0] = value;
915 return;
916
917 case 0x80: /* MOD_CONF_CTRL_0 */
918 diff = s->mod_conf_ctrl[0] ^ value;
919 s->mod_conf_ctrl[0] = value;
920 omap_pin_modconf1_update(s, diff, value);
921 return;
922
923 default:
924 OMAP_BAD_REG(addr);
925 }
926}
927
4b3fedf3
AK		 928static const MemoryRegionOps omap_pin_cfg_ops = {
929 .read = omap_pin_cfg_read,
930 .write = omap_pin_cfg_write,
931 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 932};
933
934static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
935{
936 /* Start in Compatibility Mode. */
937 mpu->compat1509 = 1;
938 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
939 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
940 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
941 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
942 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
943 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
944 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
945 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
946 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
947 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
948}
949
4b3fedf3
AK		 950static void omap_pin_cfg_init(MemoryRegion *system_memory,
951 target_phys_addr_t base,
c3d2689d
AZ		 952 struct omap_mpu_state_s *mpu)
953{
4b3fedf3
AK		 954 memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
955 "omap-pin-cfg", 0x800);
956 memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem);
c3d2689d
AZ		 957 omap_pin_cfg_reset(mpu);
958}
959
960/* Device Identification, Die Identification */
4b3fedf3
AK		 961static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr,
962 unsigned size)
c3d2689d
AZ		 963{
964 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
965
4b3fedf3
AK		 966 if (size != 4) {
967 return omap_badwidth_read32(opaque, addr);
968 }
969
c3d2689d
AZ		 970 switch (addr) {
971 case 0xfffe1800: /* DIE_ID_LSB */
972 return 0xc9581f0e;
973 case 0xfffe1804: /* DIE_ID_MSB */
974 return 0xa8858bfa;
975
976 case 0xfffe2000: /* PRODUCT_ID_LSB */
977 return 0x00aaaafc;
978 case 0xfffe2004: /* PRODUCT_ID_MSB */
979 return 0xcafeb574;
980
981 case 0xfffed400: /* JTAG_ID_LSB */
982 switch (s->mpu_model) {
983 case omap310:
984 return 0x03310315;
985 case omap1510:
986 return 0x03310115;
827df9f3 987 default:
2ac71179 988 hw_error("%s: bad mpu model\n", __FUNCTION__);
c3d2689d
AZ		 989 }
990 break;
991
992 case 0xfffed404: /* JTAG_ID_MSB */
993 switch (s->mpu_model) {
994 case omap310:
995 return 0xfb57402f;
996 case omap1510:
997 return 0xfb47002f;
827df9f3 998 default:
2ac71179 999 hw_error("%s: bad mpu model\n", __FUNCTION__);
c3d2689d
AZ		 1000 }
1001 break;
1002 }
1003
1004 OMAP_BAD_REG(addr);
1005 return 0;
1006}
1007
c227f099 1008static void omap_id_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 1009 uint64_t value, unsigned size)
c3d2689d 1010{
4b3fedf3
AK		 1011 if (size != 4) {
1012 return omap_badwidth_write32(opaque, addr, value);
1013 }
1014
c3d2689d
AZ		 1015 OMAP_BAD_REG(addr);
1016}
1017
4b3fedf3
AK		 1018static const MemoryRegionOps omap_id_ops = {
1019 .read = omap_id_read,
1020 .write = omap_id_write,
1021 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1022};
1023
4b3fedf3 1024static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
c3d2689d 1025{
4b3fedf3
AK		 1026 memory_region_init_io(&mpu->id_iomem, &omap_id_ops, mpu,
1027 "omap-id", 0x100000000ULL);
1028 memory_region_init_alias(&mpu->id_iomem_e18, "omap-id-e18", &mpu->id_iomem,
1029 0xfffe1800, 0x800);
1030 memory_region_add_subregion(memory, 0xfffe1800, &mpu->id_iomem_e18);
1031 memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-ed4", &mpu->id_iomem,
1032 0xfffed400, 0x100);
1033 memory_region_add_subregion(memory, 0xfffed400, &mpu->id_iomem_ed4);
1034 if (!cpu_is_omap15xx(mpu)) {
1035 memory_region_init_alias(&mpu->id_iomem_ed4, "omap-id-e20",
1036 &mpu->id_iomem, 0xfffe2000, 0x800);
1037 memory_region_add_subregion(memory, 0xfffe2000, &mpu->id_iomem_e20);
1038 }
c3d2689d
AZ		 1039}
1040
1041/* MPUI Control (Dummy) */
4b3fedf3
AK		 1042static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr,
1043 unsigned size)
c3d2689d
AZ		 1044{
1045 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1046
4b3fedf3
AK		 1047 if (size != 4) {
1048 return omap_badwidth_read32(opaque, addr);
1049 }
1050
8da3ff18 1051 switch (addr) {
c3d2689d
AZ		 1052 case 0x00: /* CTRL */
1053 return s->mpui_ctrl;
1054 case 0x04: /* DEBUG_ADDR */
1055 return 0x01ffffff;
1056 case 0x08: /* DEBUG_DATA */
1057 return 0xffffffff;
1058 case 0x0c: /* DEBUG_FLAG */
1059 return 0x00000800;
1060 case 0x10: /* STATUS */
1061 return 0x00000000;
1062
1063 /* Not in OMAP310 */
1064 case 0x14: /* DSP_STATUS */
1065 case 0x18: /* DSP_BOOT_CONFIG */
1066 return 0x00000000;
1067 case 0x1c: /* DSP_MPUI_CONFIG */
1068 return 0x0000ffff;
1069 }
1070
1071 OMAP_BAD_REG(addr);
1072 return 0;
1073}
1074
c227f099 1075static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 1076 uint64_t value, unsigned size)
c3d2689d
AZ		 1077{
1078 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1079
4b3fedf3
AK		 1080 if (size != 4) {
1081 return omap_badwidth_write32(opaque, addr, value);
1082 }
1083
8da3ff18 1084 switch (addr) {
c3d2689d
AZ		 1085 case 0x00: /* CTRL */
1086 s->mpui_ctrl = value & 0x007fffff;
1087 break;
1088
1089 case 0x04: /* DEBUG_ADDR */
1090 case 0x08: /* DEBUG_DATA */
1091 case 0x0c: /* DEBUG_FLAG */
1092 case 0x10: /* STATUS */
1093 /* Not in OMAP310 */
1094 case 0x14: /* DSP_STATUS */
1095 OMAP_RO_REG(addr);
1096 case 0x18: /* DSP_BOOT_CONFIG */
1097 case 0x1c: /* DSP_MPUI_CONFIG */
1098 break;
1099
1100 default:
1101 OMAP_BAD_REG(addr);
1102 }
1103}
1104
4b3fedf3
AK		 1105static const MemoryRegionOps omap_mpui_ops = {
1106 .read = omap_mpui_read,
1107 .write = omap_mpui_write,
1108 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1109};
1110
1111static void omap_mpui_reset(struct omap_mpu_state_s *s)
1112{
1113 s->mpui_ctrl = 0x0003ff1b;
1114}
1115
4b3fedf3 1116static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base,
c3d2689d
AZ		 1117 struct omap_mpu_state_s *mpu)
1118{
4b3fedf3
AK		 1119 memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
1120 "omap-mpui", 0x100);
1121 memory_region_add_subregion(memory, base, &mpu->mpui_iomem);
c3d2689d
AZ		 1122
1123 omap_mpui_reset(mpu);
1124}
1125
1126/* TIPB Bridges */
1127struct omap_tipb_bridge_s {
c3d2689d 1128 qemu_irq abort;
4b3fedf3 1129 MemoryRegion iomem;
c3d2689d
AZ		 1130
1131 int width_intr;
1132 uint16_t control;
1133 uint16_t alloc;
1134 uint16_t buffer;
1135 uint16_t enh_control;
1136};
1137
4b3fedf3
AK		 1138static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr,
1139 unsigned size)
c3d2689d
AZ		 1140{
1141 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
c3d2689d 1142
4b3fedf3
AK		 1143 if (size < 2) {
1144 return omap_badwidth_read16(opaque, addr);
1145 }
1146
8da3ff18 1147 switch (addr) {
c3d2689d
AZ		 1148 case 0x00: /* TIPB_CNTL */
1149 return s->control;
1150 case 0x04: /* TIPB_BUS_ALLOC */
1151 return s->alloc;
1152 case 0x08: /* MPU_TIPB_CNTL */
1153 return s->buffer;
1154 case 0x0c: /* ENHANCED_TIPB_CNTL */
1155 return s->enh_control;
1156 case 0x10: /* ADDRESS_DBG */
1157 case 0x14: /* DATA_DEBUG_LOW */
1158 case 0x18: /* DATA_DEBUG_HIGH */
1159 return 0xffff;
1160 case 0x1c: /* DEBUG_CNTR_SIG */
1161 return 0x00f8;
1162 }
1163
1164 OMAP_BAD_REG(addr);
1165 return 0;
1166}
1167
c227f099 1168static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
4b3fedf3 1169 uint64_t value, unsigned size)
c3d2689d
AZ		 1170{
1171 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
c3d2689d 1172
4b3fedf3
AK		 1173 if (size < 2) {
1174 return omap_badwidth_write16(opaque, addr, value);
1175 }
1176
8da3ff18 1177 switch (addr) {
c3d2689d
AZ		 1178 case 0x00: /* TIPB_CNTL */
1179 s->control = value & 0xffff;
1180 break;
1181
1182 case 0x04: /* TIPB_BUS_ALLOC */
1183 s->alloc = value & 0x003f;
1184 break;
1185
1186 case 0x08: /* MPU_TIPB_CNTL */
1187 s->buffer = value & 0x0003;
1188 break;
1189
1190 case 0x0c: /* ENHANCED_TIPB_CNTL */
1191 s->width_intr = !(value & 2);
1192 s->enh_control = value & 0x000f;
1193 break;
1194
1195 case 0x10: /* ADDRESS_DBG */
1196 case 0x14: /* DATA_DEBUG_LOW */
1197 case 0x18: /* DATA_DEBUG_HIGH */
1198 case 0x1c: /* DEBUG_CNTR_SIG */
1199 OMAP_RO_REG(addr);
1200 break;
1201
1202 default:
1203 OMAP_BAD_REG(addr);
1204 }
1205}
1206
4b3fedf3
AK		 1207static const MemoryRegionOps omap_tipb_bridge_ops = {
1208 .read = omap_tipb_bridge_read,
1209 .write = omap_tipb_bridge_write,
1210 .endianness = DEVICE_NATIVE_ENDIAN,
c3d2689d
AZ		 1211};
1212
1213static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
1214{
1215 s->control = 0xffff;
1216 s->alloc = 0x0009;
1217 s->buffer = 0x0000;
1218 s->enh_control = 0x000f;
1219}
1220
4b3fedf3
AK		 1221static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
1222 MemoryRegion *memory, target_phys_addr_t base,
1223 qemu_irq abort_irq, omap_clk clk)
c3d2689d 1224{
c3d2689d 1225 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
7267c094 1226 g_malloc0(sizeof(struct omap_tipb_bridge_s));
c3d2689d
AZ		 1227
1228 s->abort = abort_irq;
c3d2689d
AZ		 1229 omap_tipb_bridge_reset(s);
1230
4b3fedf3
AK		 1231 memory_region_init_io(&s->iomem, &omap_tipb_bridge_ops, s,
1232 "omap-tipb-bridge", 0x100);
1233 memory_region_add_subregion(memory, base, &s->iomem);
c3d2689d
AZ		 1234
1235 return s;
1236}
1237
1238/* Dummy Traffic Controller's Memory Interface */
c227f099 1239static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1240{
1241 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1242 uint32_t ret;
1243
8da3ff18 1244 switch (addr) {
d8f699cb
AZ		 1245 case 0x00: /* IMIF_PRIO */
1246 case 0x04: /* EMIFS_PRIO */
1247 case 0x08: /* EMIFF_PRIO */
1248 case 0x0c: /* EMIFS_CONFIG */
1249 case 0x10: /* EMIFS_CS0_CONFIG */
1250 case 0x14: /* EMIFS_CS1_CONFIG */
1251 case 0x18: /* EMIFS_CS2_CONFIG */
1252 case 0x1c: /* EMIFS_CS3_CONFIG */
1253 case 0x24: /* EMIFF_MRS */
1254 case 0x28: /* TIMEOUT1 */
1255 case 0x2c: /* TIMEOUT2 */
1256 case 0x30: /* TIMEOUT3 */
1257 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1258 case 0x40: /* EMIFS_CFG_DYN_WAIT */
8da3ff18 1259 return s->tcmi_regs[addr >> 2];
c3d2689d 1260
d8f699cb 1261 case 0x20: /* EMIFF_SDRAM_CONFIG */
8da3ff18
PB		 1262 ret = s->tcmi_regs[addr >> 2];
1263 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
c3d2689d
AZ		 1264 /* XXX: We can try using the VGA_DIRTY flag for this */
1265 return ret;
1266 }
1267
1268 OMAP_BAD_REG(addr);
1269 return 0;
1270}
1271
c227f099 1272static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1273 uint32_t value)
1274{
1275 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1276
8da3ff18 1277 switch (addr) {
d8f699cb
AZ		 1278 case 0x00: /* IMIF_PRIO */
1279 case 0x04: /* EMIFS_PRIO */
1280 case 0x08: /* EMIFF_PRIO */
1281 case 0x10: /* EMIFS_CS0_CONFIG */
1282 case 0x14: /* EMIFS_CS1_CONFIG */
1283 case 0x18: /* EMIFS_CS2_CONFIG */
1284 case 0x1c: /* EMIFS_CS3_CONFIG */
1285 case 0x20: /* EMIFF_SDRAM_CONFIG */
1286 case 0x24: /* EMIFF_MRS */
1287 case 0x28: /* TIMEOUT1 */
1288 case 0x2c: /* TIMEOUT2 */
1289 case 0x30: /* TIMEOUT3 */
1290 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1291 case 0x40: /* EMIFS_CFG_DYN_WAIT */
8da3ff18 1292 s->tcmi_regs[addr >> 2] = value;
c3d2689d 1293 break;
d8f699cb 1294 case 0x0c: /* EMIFS_CONFIG */
8da3ff18 1295 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4);
c3d2689d
AZ		 1296 break;
1297
1298 default:
1299 OMAP_BAD_REG(addr);
1300 }
1301}
1302
d60efc6b 1303static CPUReadMemoryFunc * const omap_tcmi_readfn[] = {
c3d2689d
AZ		 1304 omap_badwidth_read32,
1305 omap_badwidth_read32,
1306 omap_tcmi_read,
1307};
1308
d60efc6b 1309static CPUWriteMemoryFunc * const omap_tcmi_writefn[] = {
c3d2689d
AZ		 1310 omap_badwidth_write32,
1311 omap_badwidth_write32,
1312 omap_tcmi_write,
1313};
1314
1315static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
1316{
1317 mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
1318 mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
1319 mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
1320 mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
1321 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
1322 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
1323 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
1324 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
1325 mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
1326 mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
1327 mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
1328 mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
1329 mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
1330 mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
1331 mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
1332}
1333
c227f099 1334static void omap_tcmi_init(target_phys_addr_t base,
c3d2689d
AZ		 1335 struct omap_mpu_state_s *mpu)
1336{
1eed09cb 1337 int iomemtype = cpu_register_io_memory(omap_tcmi_readfn,
2507c12a 1338 omap_tcmi_writefn, mpu, DEVICE_NATIVE_ENDIAN);
c3d2689d 1339
8da3ff18 1340 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 1341 omap_tcmi_reset(mpu);
1342}
1343
1344/* Digital phase-locked loops control */
c227f099 1345static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1346{
1347 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
c3d2689d 1348
8da3ff18 1349 if (addr == 0x00) /* CTL_REG */
c3d2689d
AZ		 1350 return s->mode;
1351
1352 OMAP_BAD_REG(addr);
1353 return 0;
1354}
1355
c227f099 1356static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1357 uint32_t value)
1358{
1359 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
1360 uint16_t diff;
c3d2689d
AZ		 1361 static const int bypass_div[4] = { 1, 2, 4, 4 };
1362 int div, mult;
1363
8da3ff18 1364 if (addr == 0x00) { /* CTL_REG */
c3d2689d
AZ		 1365 /* See omap_ulpd_pm_write() too */
1366 diff = s->mode & value;
1367 s->mode = value & 0x2fff;
1368 if (diff & (0x3ff << 2)) {
1369 if (value & (1 << 4)) { /* PLL_ENABLE */
1370 div = ((value >> 5) & 3) + 1; /* PLL_DIV */
1371 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
1372 } else {
1373 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
1374 mult = 1;
1375 }
1376 omap_clk_setrate(s->dpll, div, mult);
1377 }
1378
1379 /* Enter the desired mode. */
1380 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
1381
1382 /* Act as if the lock is restored. */
1383 s->mode |= 2;
1384 } else {
1385 OMAP_BAD_REG(addr);
1386 }
1387}
1388
d60efc6b 1389static CPUReadMemoryFunc * const omap_dpll_readfn[] = {
c3d2689d
AZ		 1390 omap_badwidth_read16,
1391 omap_dpll_read,
1392 omap_badwidth_read16,
1393};
1394
d60efc6b 1395static CPUWriteMemoryFunc * const omap_dpll_writefn[] = {
c3d2689d
AZ		 1396 omap_badwidth_write16,
1397 omap_dpll_write,
1398 omap_badwidth_write16,
1399};
1400
1401static void omap_dpll_reset(struct dpll_ctl_s *s)
1402{
1403 s->mode = 0x2002;
1404 omap_clk_setrate(s->dpll, 1, 1);
1405}
1406
c227f099 1407static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
c3d2689d
AZ		 1408 omap_clk clk)
1409{
1eed09cb 1410 int iomemtype = cpu_register_io_memory(omap_dpll_readfn,
2507c12a 1411 omap_dpll_writefn, s, DEVICE_NATIVE_ENDIAN);
c3d2689d 1412
c3d2689d
AZ		 1413 s->dpll = clk;
1414 omap_dpll_reset(s);
1415
8da3ff18 1416 cpu_register_physical_memory(base, 0x100, iomemtype);
c3d2689d
AZ		 1417}
1418
c3d2689d 1419/* MPU Clock/Reset/Power Mode Control */
c227f099 1420static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1421{
1422 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1423
8da3ff18 1424 switch (addr) {
c3d2689d
AZ		 1425 case 0x00: /* ARM_CKCTL */
1426 return s->clkm.arm_ckctl;
1427
1428 case 0x04: /* ARM_IDLECT1 */
1429 return s->clkm.arm_idlect1;
1430
1431 case 0x08: /* ARM_IDLECT2 */
1432 return s->clkm.arm_idlect2;
1433
1434 case 0x0c: /* ARM_EWUPCT */
1435 return s->clkm.arm_ewupct;
1436
1437 case 0x10: /* ARM_RSTCT1 */
1438 return s->clkm.arm_rstct1;
1439
1440 case 0x14: /* ARM_RSTCT2 */
1441 return s->clkm.arm_rstct2;
1442
1443 case 0x18: /* ARM_SYSST */
d8f699cb 1444 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start;
c3d2689d
AZ		 1445
1446 case 0x1c: /* ARM_CKOUT1 */
1447 return s->clkm.arm_ckout1;
1448
1449 case 0x20: /* ARM_CKOUT2 */
1450 break;
1451 }
1452
1453 OMAP_BAD_REG(addr);
1454 return 0;
1455}
1456
1457static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
1458 uint16_t diff, uint16_t value)
1459{
1460 omap_clk clk;
1461
1462 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
1463 if (value & (1 << 14))
1464 /* Reserved */;
1465 else {
1466 clk = omap_findclk(s, "arminth_ck");
1467 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1468 }
1469 }
1470 if (diff & (1 << 12)) { /* ARM_TIMXO */
1471 clk = omap_findclk(s, "armtim_ck");
1472 if (value & (1 << 12))
1473 omap_clk_reparent(clk, omap_findclk(s, "clkin"));
1474 else
1475 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1476 }
1477 /* XXX: en_dspck */
1478 if (diff & (3 << 10)) { /* DSPMMUDIV */
1479 clk = omap_findclk(s, "dspmmu_ck");
1480 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
1481 }
1482 if (diff & (3 << 8)) { /* TCDIV */
1483 clk = omap_findclk(s, "tc_ck");
1484 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
1485 }
1486 if (diff & (3 << 6)) { /* DSPDIV */
1487 clk = omap_findclk(s, "dsp_ck");
1488 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
1489 }
1490 if (diff & (3 << 4)) { /* ARMDIV */
1491 clk = omap_findclk(s, "arm_ck");
1492 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
1493 }
1494 if (diff & (3 << 2)) { /* LCDDIV */
1495 clk = omap_findclk(s, "lcd_ck");
1496 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
1497 }
1498 if (diff & (3 << 0)) { /* PERDIV */
1499 clk = omap_findclk(s, "armper_ck");
1500 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
1501 }
1502}
1503
1504static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
1505 uint16_t diff, uint16_t value)
1506{
1507 omap_clk clk;
1508
1509 if (value & (1 << 11)) /* SETARM_IDLE */
1510 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
1511 if (!(value & (1 << 10))) /* WKUP_MODE */
1512 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
1513
1514#define SET_CANIDLE(clock, bit) \
1515 if (diff & (1 << bit)) { \
1516 clk = omap_findclk(s, clock); \
1517 omap_clk_canidle(clk, (value >> bit) & 1); \
1518 }
1519 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
1520 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
1521 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
1522 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
1523 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
1524 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
1525 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
1526 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
1527 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
1528 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
1529 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
1530 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
1531 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
1532 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
1533}
1534
1535static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
1536 uint16_t diff, uint16_t value)
1537{
1538 omap_clk clk;
1539
1540#define SET_ONOFF(clock, bit) \
1541 if (diff & (1 << bit)) { \
1542 clk = omap_findclk(s, clock); \
1543 omap_clk_onoff(clk, (value >> bit) & 1); \
1544 }
1545 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
1546 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
1547 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
1548 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
1549 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
1550 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
1551 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
1552 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
1553 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
1554 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
1555 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
1556}
1557
1558static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
1559 uint16_t diff, uint16_t value)
1560{
1561 omap_clk clk;
1562
1563 if (diff & (3 << 4)) { /* TCLKOUT */
1564 clk = omap_findclk(s, "tclk_out");
1565 switch ((value >> 4) & 3) {
1566 case 1:
1567 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
1568 omap_clk_onoff(clk, 1);
1569 break;
1570 case 2:
1571 omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
1572 omap_clk_onoff(clk, 1);
1573 break;
1574 default:
1575 omap_clk_onoff(clk, 0);
1576 }
1577 }
1578 if (diff & (3 << 2)) { /* DCLKOUT */
1579 clk = omap_findclk(s, "dclk_out");
1580 switch ((value >> 2) & 3) {
1581 case 0:
1582 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
1583 break;
1584 case 1:
1585 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
1586 break;
1587 case 2:
1588 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
1589 break;
1590 case 3:
1591 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1592 break;
1593 }
1594 }
1595 if (diff & (3 << 0)) { /* ACLKOUT */
1596 clk = omap_findclk(s, "aclk_out");
1597 switch ((value >> 0) & 3) {
1598 case 1:
1599 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
1600 omap_clk_onoff(clk, 1);
1601 break;
1602 case 2:
1603 omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
1604 omap_clk_onoff(clk, 1);
1605 break;
1606 case 3:
1607 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
1608 omap_clk_onoff(clk, 1);
1609 break;
1610 default:
1611 omap_clk_onoff(clk, 0);
1612 }
1613 }
1614}
1615
c227f099 1616static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1617 uint32_t value)
1618{
1619 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1620 uint16_t diff;
1621 omap_clk clk;
1622 static const char *clkschemename[8] = {
1623 "fully synchronous", "fully asynchronous", "synchronous scalable",
1624 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
1625 };
1626
8da3ff18 1627 switch (addr) {
c3d2689d
AZ		 1628 case 0x00: /* ARM_CKCTL */
1629 diff = s->clkm.arm_ckctl ^ value;
1630 s->clkm.arm_ckctl = value & 0x7fff;
1631 omap_clkm_ckctl_update(s, diff, value);
1632 return;
1633
1634 case 0x04: /* ARM_IDLECT1 */
1635 diff = s->clkm.arm_idlect1 ^ value;
1636 s->clkm.arm_idlect1 = value & 0x0fff;
1637 omap_clkm_idlect1_update(s, diff, value);
1638 return;
1639
1640 case 0x08: /* ARM_IDLECT2 */
1641 diff = s->clkm.arm_idlect2 ^ value;
1642 s->clkm.arm_idlect2 = value & 0x07ff;
1643 omap_clkm_idlect2_update(s, diff, value);
1644 return;
1645
1646 case 0x0c: /* ARM_EWUPCT */
c3d2689d
AZ		 1647 s->clkm.arm_ewupct = value & 0x003f;
1648 return;
1649
1650 case 0x10: /* ARM_RSTCT1 */
1651 diff = s->clkm.arm_rstct1 ^ value;
1652 s->clkm.arm_rstct1 = value & 0x0007;
1653 if (value & 9) {
1654 qemu_system_reset_request();
1655 s->clkm.cold_start = 0xa;
1656 }
1657 if (diff & ~value & 4) { /* DSP_RST */
1658 omap_mpui_reset(s);
1659 omap_tipb_bridge_reset(s->private_tipb);
1660 omap_tipb_bridge_reset(s->public_tipb);
1661 }
1662 if (diff & 2) { /* DSP_EN */
1663 clk = omap_findclk(s, "dsp_ck");
1664 omap_clk_canidle(clk, (~value >> 1) & 1);
1665 }
1666 return;
1667
1668 case 0x14: /* ARM_RSTCT2 */
1669 s->clkm.arm_rstct2 = value & 0x0001;
1670 return;
1671
1672 case 0x18: /* ARM_SYSST */
1673 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
1674 s->clkm.clocking_scheme = (value >> 11) & 7;
1675 printf("%s: clocking scheme set to %s\n", __FUNCTION__,
1676 clkschemename[s->clkm.clocking_scheme]);
1677 }
1678 s->clkm.cold_start &= value & 0x3f;
1679 return;
1680
1681 case 0x1c: /* ARM_CKOUT1 */
1682 diff = s->clkm.arm_ckout1 ^ value;
1683 s->clkm.arm_ckout1 = value & 0x003f;
1684 omap_clkm_ckout1_update(s, diff, value);
1685 return;
1686
1687 case 0x20: /* ARM_CKOUT2 */
1688 default:
1689 OMAP_BAD_REG(addr);
1690 }
1691}
1692
d60efc6b 1693static CPUReadMemoryFunc * const omap_clkm_readfn[] = {
c3d2689d
AZ		 1694 omap_badwidth_read16,
1695 omap_clkm_read,
1696 omap_badwidth_read16,
1697};
1698
d60efc6b 1699static CPUWriteMemoryFunc * const omap_clkm_writefn[] = {
c3d2689d
AZ		 1700 omap_badwidth_write16,
1701 omap_clkm_write,
1702 omap_badwidth_write16,
1703};
1704
c227f099 1705static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
c3d2689d
AZ		 1706{
1707 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d 1708
8da3ff18 1709 switch (addr) {
c3d2689d
AZ		 1710 case 0x04: /* DSP_IDLECT1 */
1711 return s->clkm.dsp_idlect1;
1712
1713 case 0x08: /* DSP_IDLECT2 */
1714 return s->clkm.dsp_idlect2;
1715
1716 case 0x14: /* DSP_RSTCT2 */
1717 return s->clkm.dsp_rstct2;
1718
1719 case 0x18: /* DSP_SYSST */
d8f699cb 1720 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
c3d2689d
AZ		 1721 (s->env->halted << 6); /* Quite useless... */
1722 }
1723
1724 OMAP_BAD_REG(addr);
1725 return 0;
1726}
1727
1728static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
1729 uint16_t diff, uint16_t value)
1730{
1731 omap_clk clk;
1732
1733 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
1734}
1735
1736static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
1737 uint16_t diff, uint16_t value)
1738{
1739 omap_clk clk;
1740
1741 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
1742}
1743
c227f099 1744static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
c3d2689d
AZ		 1745 uint32_t value)
1746{
1747 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
c3d2689d
AZ		 1748 uint16_t diff;
1749
8da3ff18 1750 switch (addr) {
c3d2689d
AZ		 1751 case 0x04: /* DSP_IDLECT1 */
1752 diff = s->clkm.dsp_idlect1 ^ value;
1753 s->clkm.dsp_idlect1 = value & 0x01f7;
1754 omap_clkdsp_idlect1_update(s, diff, value);
1755 break;
1756
1757 case 0x08: /* DSP_IDLECT2 */
1758 s->clkm.dsp_idlect2 = value & 0x0037;
1759 diff = s->clkm.dsp_idlect1 ^ value;
1760 omap_clkdsp_idlect2_update(s, diff, value);
1761 break;
1762
1763 case 0x14: /* DSP_RSTCT2 */
1764 s->clkm.dsp_rstct2 = value & 0x0001;
1765 break;
1766
1767 case 0x18: /* DSP_SYSST */
1768 s->clkm.cold_start &= value & 0x3f;
1769 break;
1770
1771 default:
1772 OMAP_BAD_REG(addr);
1773 }
1774}
1775
d60efc6b 1776static CPUReadMemoryFunc * const omap_clkdsp_readfn[] = {
c3d2689d
AZ		 1777 omap_badwidth_read16,
1778 omap_clkdsp_read,
1779 omap_badwidth_read16,
1780};
1781
d60efc6b 1782static CPUWriteMemoryFunc * const omap_clkdsp_writefn[] = {
c3d2689d
AZ		 1783 omap_badwidth_write16,
1784 omap_clkdsp_write,
1785 omap_badwidth_write16,
1786};
1787
1788static void omap_clkm_reset(struct omap_mpu_state_s *s)
1789{
1790 if (s->wdt && s->wdt->reset)
1791 s->clkm.cold_start = 0x6;
1792 s->clkm.clocking_scheme = 0;
1793 omap_clkm_ckctl_update(s, ~0, 0x3000);
1794 s->clkm.arm_ckctl = 0x3000;
d8f699cb 1795 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400);
c3d2689d 1796 s->clkm.arm_idlect1 = 0x0400;
d8f699cb 1797 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100);
c3d2689d
AZ		 1798 s->clkm.arm_idlect2 = 0x0100;
1799 s->clkm.arm_ewupct = 0x003f;
1800 s->clkm.arm_rstct1 = 0x0000;
1801 s->clkm.arm_rstct2 = 0x0000;
1802 s->clkm.arm_ckout1 = 0x0015;
1803 s->clkm.dpll1_mode = 0x2002;
1804 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
1805 s->clkm.dsp_idlect1 = 0x0040;
1806 omap_clkdsp_idlect2_update(s, ~0, 0x0000);
1807 s->clkm.dsp_idlect2 = 0x0000;
1808 s->clkm.dsp_rstct2 = 0x0000;
1809}
1810
c227f099
AL		 1811static void omap_clkm_init(target_phys_addr_t mpu_base,
1812 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
c3d2689d
AZ		 1813{
1814 int iomemtype[2] = {
2507c12a
AG		 1815 cpu_register_io_memory(omap_clkm_readfn, omap_clkm_writefn, s,
1816 DEVICE_NATIVE_ENDIAN),
1817 cpu_register_io_memory(omap_clkdsp_readfn, omap_clkdsp_writefn, s,
1818 DEVICE_NATIVE_ENDIAN),
c3d2689d
AZ		 1819 };
1820
d8f699cb
AZ		 1821 s->clkm.arm_idlect1 = 0x03ff;
1822 s->clkm.arm_idlect2 = 0x0100;
1823 s->clkm.dsp_idlect1 = 0x0002;
c3d2689d 1824 omap_clkm_reset(s);
d8f699cb 1825 s->clkm.cold_start = 0x3a;
c3d2689d 1826
8da3ff18
PB		 1827 cpu_register_physical_memory(mpu_base, 0x100, iomemtype[0]);
1828 cpu_register_physical_memory(dsp_base, 0x1000, iomemtype[1]);
c3d2689d
AZ		 1829}
1830
fe71e81a
AZ		 1831/* MPU I/O */
1832struct omap_mpuio_s {
fe71e81a
AZ		 1833 qemu_irq irq;
1834 qemu_irq kbd_irq;
1835 qemu_irq *in;
1836 qemu_irq handler[16];
1837 qemu_irq wakeup;
1838
1839 uint16_t inputs;
1840 uint16_t outputs;
1841 uint16_t dir;
1842 uint16_t edge;
1843 uint16_t mask;
1844 uint16_t ints;
1845
1846 uint16_t debounce;
1847 uint16_t latch;
1848 uint8_t event;
1849
1850 uint8_t buttons[5];
1851 uint8_t row_latch;
1852 uint8_t cols;
1853 int kbd_mask;
1854 int clk;
1855};
1856
1857static void omap_mpuio_set(void *opaque, int line, int level)
1858{
1859 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
1860 uint16_t prev = s->inputs;
1861
1862 if (level)
1863 s->inputs |= 1 << line;
1864 else
1865 s->inputs &= ~(1 << line);
1866
1867 if (((1 << line) & s->dir & ~s->mask) && s->clk) {
1868 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) {
1869 s->ints |= 1 << line;
1870 qemu_irq_raise(s->irq);
1871 /* TODO: wakeup */
1872 }
1873 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */
1874 (s->event >> 1) == line) /* PIN_SELECT */
1875 s->latch = s->inputs;
1876 }
1877}
1878
1879static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
1880{
1881 int i;
1882 uint8_t *row, rows = 0, cols = ~s->cols;
1883
38a34e1d 1884 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1)
fe71e81a 1885 if (*row & cols)
38a34e1d 1886 rows |= i;
fe71e81a 1887
cf6d9118
AZ		 1888 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk);
1889 s->row_latch = ~rows;
fe71e81a
AZ		 1890}
1891
c227f099 1892static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
fe71e81a
AZ		 1893{
1894 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
cf965d24 1895 int offset = addr & OMAP_MPUI_REG_MASK;
fe71e81a
AZ		 1896 uint16_t ret;
1897
1898 switch (offset) {
1899 case 0x00: /* INPUT_LATCH */
1900 return s->inputs;
1901
1902 case 0x04: /* OUTPUT_REG */
1903 return s->outputs;
1904
1905 case 0x08: /* IO_CNTL */
1906 return s->dir;
1907
1908 case 0x10: /* KBR_LATCH */
1909 return s->row_latch;
1910
1911 case 0x14: /* KBC_REG */
1912 return s->cols;
1913
1914 case 0x18: /* GPIO_EVENT_MODE_REG */
1915 return s->event;
1916
1917 case 0x1c: /* GPIO_INT_EDGE_REG */
1918 return s->edge;
1919
1920 case 0x20: /* KBD_INT */
cf6d9118 1921 return (~s->row_latch & 0x1f) && !s->kbd_mask;
fe71e81a
AZ		 1922
1923 case 0x24: /* GPIO_INT */
1924 ret = s->ints;
8e129e07
AZ		 1925 s->ints &= s->mask;
1926 if (ret)
1927 qemu_irq_lower(s->irq);
fe71e81a
AZ		 1928 return ret;
1929
1930 case 0x28: /* KBD_MASKIT */
1931 return s->kbd_mask;
1932
1933 case 0x2c: /* GPIO_MASKIT */
1934 return s->mask;
1935
1936 case 0x30: /* GPIO_DEBOUNCING_REG */
1937 return s->debounce;
1938
1939 case 0x34: /* GPIO_LATCH_REG */
1940 return s->latch;
1941 }
1942
1943 OMAP_BAD_REG(addr);
1944 return 0;
1945}
1946
c227f099 1947static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
fe71e81a
AZ		 1948 uint32_t value)
1949{
1950 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
cf965d24 1951 int offset = addr & OMAP_MPUI_REG_MASK;
fe71e81a
AZ		 1952 uint16_t diff;
1953 int ln;
1954
1955 switch (offset) {
1956 case 0x04: /* OUTPUT_REG */
d8f699cb 1957 diff = (s->outputs ^ value) & ~s->dir;
fe71e81a 1958 s->outputs = value;
fe71e81a
AZ		 1959 while ((ln = ffs(diff))) {
1960 ln --;
1961 if (s->handler[ln])
1962 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
1963 diff &= ~(1 << ln);
1964 }
1965 break;
1966
1967 case 0x08: /* IO_CNTL */
1968 diff = s->outputs & (s->dir ^ value);
1969 s->dir = value;
1970
1971 value = s->outputs & ~s->dir;
1972 while ((ln = ffs(diff))) {
1973 ln --;
1974 if (s->handler[ln])
1975 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
1976 diff &= ~(1 << ln);
1977 }
1978 break;
1979
1980 case 0x14: /* KBC_REG */
1981 s->cols = value;
1982 omap_mpuio_kbd_update(s);
1983 break;
1984
1985 case 0x18: /* GPIO_EVENT_MODE_REG */
1986 s->event = value & 0x1f;
1987 break;
1988
1989 case 0x1c: /* GPIO_INT_EDGE_REG */
1990 s->edge = value;
1991 break;
1992
1993 case 0x28: /* KBD_MASKIT */
1994 s->kbd_mask = value & 1;
1995 omap_mpuio_kbd_update(s);
1996 break;
1997
1998 case 0x2c: /* GPIO_MASKIT */
1999 s->mask = value;
2000 break;
2001
2002 case 0x30: /* GPIO_DEBOUNCING_REG */
2003 s->debounce = value & 0x1ff;
2004 break;
2005
2006 case 0x00: /* INPUT_LATCH */
2007 case 0x10: /* KBR_LATCH */
2008 case 0x20: /* KBD_INT */
2009 case 0x24: /* GPIO_INT */
2010 case 0x34: /* GPIO_LATCH_REG */
2011 OMAP_RO_REG(addr);
2012 return;
2013
2014 default:
2015 OMAP_BAD_REG(addr);
2016 return;
2017 }
2018}
2019
d60efc6b 2020static CPUReadMemoryFunc * const omap_mpuio_readfn[] = {
fe71e81a
AZ		 2021 omap_badwidth_read16,
2022 omap_mpuio_read,
2023 omap_badwidth_read16,
2024};
2025
d60efc6b 2026static CPUWriteMemoryFunc * const omap_mpuio_writefn[] = {
fe71e81a
AZ		 2027 omap_badwidth_write16,
2028 omap_mpuio_write,
2029 omap_badwidth_write16,
2030};
2031
9596ebb7 2032static void omap_mpuio_reset(struct omap_mpuio_s *s)
fe71e81a
AZ		 2033{
2034 s->inputs = 0;
2035 s->outputs = 0;
2036 s->dir = ~0;
2037 s->event = 0;
2038 s->edge = 0;
2039 s->kbd_mask = 0;
2040 s->mask = 0;
2041 s->debounce = 0;
2042 s->latch = 0;
2043 s->ints = 0;
2044 s->row_latch = 0x1f;
38a34e1d 2045 s->clk = 1;
fe71e81a
AZ		 2046}
2047
2048static void omap_mpuio_onoff(void *opaque, int line, int on)
2049{
2050 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
2051
2052 s->clk = on;
2053 if (on)
2054 omap_mpuio_kbd_update(s);
2055}
2056
c227f099 2057struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
fe71e81a
AZ		 2058 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
2059 omap_clk clk)
2060{
2061 int iomemtype;
2062 struct omap_mpuio_s *s = (struct omap_mpuio_s *)
7267c094 2063 g_malloc0(sizeof(struct omap_mpuio_s));
fe71e81a 2064
fe71e81a
AZ		 2065 s->irq = gpio_int;
2066 s->kbd_irq = kbd_int;
2067 s->wakeup = wakeup;
2068 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16);
2069 omap_mpuio_reset(s);
2070
1eed09cb 2071 iomemtype = cpu_register_io_memory(omap_mpuio_readfn,
2507c12a 2072 omap_mpuio_writefn, s, DEVICE_NATIVE_ENDIAN);
8da3ff18 2073 cpu_register_physical_memory(base, 0x800, iomemtype);
fe71e81a
AZ		 2074
2075 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]);
2076
2077 return s;
2078}
2079
2080qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s)
2081{
2082 return s->in;
2083}
2084
2085void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler)
2086{
2087 if (line >= 16 || line < 0)
2ac71179 2088 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
fe71e81a
AZ		 2089 s->handler[line] = handler;
2090}
2091
2092void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down)
2093{
2094 if (row >= 5 || row < 0)
2ac71179 2095 hw_error("%s: No key %i-%i\n", __FUNCTION__, col, row);
fe71e81a
AZ		 2096
2097 if (down)
38a34e1d 2098 s->buttons[row] |= 1 << col;
fe71e81a 2099 else
38a34e1d 2100 s->buttons[row] &= ~(1 << col);
fe71e81a
AZ		 2101
2102 omap_mpuio_kbd_update(s);
2103}
2104
d951f6ff
AZ		 2105/* MicroWire Interface */
2106struct omap_uwire_s {
d951f6ff
AZ		 2107 qemu_irq txirq;
2108 qemu_irq rxirq;
2109 qemu_irq txdrq;
2110
2111 uint16_t txbuf;
2112 uint16_t rxbuf;
2113 uint16_t control;
2114 uint16_t setup[5];
2115
bc24a225 2116 uWireSlave *chip[4];
d951f6ff
AZ		 2117};
2118
2119static void omap_uwire_transfer_start(struct omap_uwire_s *s)
2120{
2121 int chipselect = (s->control >> 10) & 3; /* INDEX */
bc24a225 2122 uWireSlave *slave = s->chip[chipselect];
d951f6ff
AZ		 2123
2124 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */
2125 if (s->control & (1 << 12)) /* CS_CMD */
2126 if (slave && slave->send)
2127 slave->send(slave->opaque,
2128 s->txbuf >> (16 - ((s->control >> 5) & 0x1f)));
2129 s->control &= ~(1 << 14); /* CSRB */
2130 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2131 * a DRQ. When is the level IRQ supposed to be reset? */
2132 }
2133
2134 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */
2135 if (s->control & (1 << 12)) /* CS_CMD */
2136 if (slave && slave->receive)
2137 s->rxbuf = slave->receive(slave->opaque);
2138 s->control |= 1 << 15; /* RDRB */
2139 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2140 * a DRQ. When is the level IRQ supposed to be reset? */
2141 }
2142}
2143
c227f099 2144static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
d951f6ff
AZ		 2145{
2146 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
cf965d24 2147 int offset = addr & OMAP_MPUI_REG_MASK;
d951f6ff
AZ		 2148
2149 switch (offset) {
2150 case 0x00: /* RDR */
2151 s->control &= ~(1 << 15); /* RDRB */
2152 return s->rxbuf;
2153
2154 case 0x04: /* CSR */
2155 return s->control;
2156
2157 case 0x08: /* SR1 */
2158 return s->setup[0];
2159 case 0x0c: /* SR2 */
2160 return s->setup[1];
2161 case 0x10: /* SR3 */
2162 return s->setup[2];
2163 case 0x14: /* SR4 */
2164 return s->setup[3];
2165 case 0x18: /* SR5 */
2166 return s->setup[4];
2167 }
2168
2169 OMAP_BAD_REG(addr);
2170 return 0;
2171}
2172
c227f099 2173static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
d951f6ff
AZ		 2174 uint32_t value)
2175{
2176 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
cf965d24 2177 int offset = addr & OMAP_MPUI_REG_MASK;
d951f6ff
AZ		 2178
2179 switch (offset) {
2180 case 0x00: /* TDR */
2181 s->txbuf = value; /* TD */
d951f6ff
AZ		 2182 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */
2183 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
cf965d24
AZ		 2184 (s->control & (1 << 12)))) { /* CS_CMD */
2185 s->control |= 1 << 14; /* CSRB */
d951f6ff 2186 omap_uwire_transfer_start(s);
cf965d24 2187 }
d951f6ff
AZ		 2188 break;
2189
2190 case 0x04: /* CSR */
2191 s->control = value & 0x1fff;
2192 if (value & (1 << 13)) /* START */
2193 omap_uwire_transfer_start(s);
2194 break;
2195
2196 case 0x08: /* SR1 */
2197 s->setup[0] = value & 0x003f;
2198 break;
2199
2200 case 0x0c: /* SR2 */
2201 s->setup[1] = value & 0x0fc0;
2202 break;
2203
2204 case 0x10: /* SR3 */
2205 s->setup[2] = value & 0x0003;
2206 break;
2207
2208 case 0x14: /* SR4 */
2209 s->setup[3] = value & 0x0001;
2210 break;
2211
2212 case 0x18: /* SR5 */
2213 s->setup[4] = value & 0x000f;
2214 break;
2215
2216 default:
2217 OMAP_BAD_REG(addr);
2218 return;
2219 }
2220}
2221
d60efc6b 2222static CPUReadMemoryFunc * const omap_uwire_readfn[] = {
d951f6ff
AZ		 2223 omap_badwidth_read16,
2224 omap_uwire_read,
2225 omap_badwidth_read16,
2226};
2227
d60efc6b 2228static CPUWriteMemoryFunc * const omap_uwire_writefn[] = {
d951f6ff
AZ		 2229 omap_badwidth_write16,
2230 omap_uwire_write,
2231 omap_badwidth_write16,
2232};
2233
9596ebb7 2234static void omap_uwire_reset(struct omap_uwire_s *s)
d951f6ff 2235{
66450b15 2236 s->control = 0;
d951f6ff
AZ		 2237 s->setup[0] = 0;
2238 s->setup[1] = 0;
2239 s->setup[2] = 0;
2240 s->setup[3] = 0;
2241 s->setup[4] = 0;
2242}
2243
c227f099 2244struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
d951f6ff
AZ		 2245 qemu_irq *irq, qemu_irq dma, omap_clk clk)
2246{
2247 int iomemtype;
2248 struct omap_uwire_s *s = (struct omap_uwire_s *)
7267c094 2249 g_malloc0(sizeof(struct omap_uwire_s));
d951f6ff 2250
d951f6ff
AZ		 2251 s->txirq = irq[0];
2252 s->rxirq = irq[1];
2253 s->txdrq = dma;
2254 omap_uwire_reset(s);
2255
1eed09cb 2256 iomemtype = cpu_register_io_memory(omap_uwire_readfn,
2507c12a 2257 omap_uwire_writefn, s, DEVICE_NATIVE_ENDIAN);
8da3ff18 2258 cpu_register_physical_memory(base, 0x800, iomemtype);
d951f6ff
AZ		 2259
2260 return s;
2261}
2262
2263void omap_uwire_attach(struct omap_uwire_s *s,
bc24a225 2264 uWireSlave *slave, int chipselect)
d951f6ff 2265{
827df9f3
AZ		 2266 if (chipselect < 0 || chipselect > 3) {
2267 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
2268 exit(-1);
2269 }
d951f6ff
AZ		 2270
2271 s->chip[chipselect] = slave;
2272}
2273
66450b15 2274/* Pseudonoise Pulse-Width Light Modulator */
9596ebb7 2275static void omap_pwl_update(struct omap_mpu_state_s *s)
66450b15
AZ		 2276{
2277 int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
2278
2279 if (output != s->pwl.output) {
2280 s->pwl.output = output;
2281 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
2282 }
2283}
2284
c227f099 2285static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
66450b15
AZ		 2286{
2287 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 2288 int offset = addr & OMAP_MPUI_REG_MASK;
66450b15
AZ		 2289
2290 switch (offset) {
2291 case 0x00: /* PWL_LEVEL */
2292 return s->pwl.level;
2293 case 0x04: /* PWL_CTRL */
2294 return s->pwl.enable;
2295 }
2296 OMAP_BAD_REG(addr);
2297 return 0;
2298}
2299
c227f099 2300static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
66450b15
AZ		 2301 uint32_t value)
2302{
2303 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 2304 int offset = addr & OMAP_MPUI_REG_MASK;
66450b15
AZ		 2305
2306 switch (offset) {
2307 case 0x00: /* PWL_LEVEL */
2308 s->pwl.level = value;
2309 omap_pwl_update(s);
2310 break;
2311 case 0x04: /* PWL_CTRL */
2312 s->pwl.enable = value & 1;
2313 omap_pwl_update(s);
2314 break;
2315 default:
2316 OMAP_BAD_REG(addr);
2317 return;
2318 }
2319}
2320
d60efc6b 2321static CPUReadMemoryFunc * const omap_pwl_readfn[] = {
02645926 2322 omap_pwl_read,
66450b15
AZ		 2323 omap_badwidth_read8,
2324 omap_badwidth_read8,
66450b15
AZ		 2325};
2326
d60efc6b 2327static CPUWriteMemoryFunc * const omap_pwl_writefn[] = {
02645926 2328 omap_pwl_write,
66450b15
AZ		 2329 omap_badwidth_write8,
2330 omap_badwidth_write8,
66450b15
AZ		 2331};
2332
9596ebb7 2333static void omap_pwl_reset(struct omap_mpu_state_s *s)
66450b15
AZ		 2334{
2335 s->pwl.output = 0;
2336 s->pwl.level = 0;
2337 s->pwl.enable = 0;
2338 s->pwl.clk = 1;
2339 omap_pwl_update(s);
2340}
2341
2342static void omap_pwl_clk_update(void *opaque, int line, int on)
2343{
2344 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2345
2346 s->pwl.clk = on;
2347 omap_pwl_update(s);
2348}
2349
c227f099 2350static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
66450b15
AZ		 2351 omap_clk clk)
2352{
2353 int iomemtype;
2354
66450b15
AZ		 2355 omap_pwl_reset(s);
2356
1eed09cb 2357 iomemtype = cpu_register_io_memory(omap_pwl_readfn,
2507c12a 2358 omap_pwl_writefn, s, DEVICE_NATIVE_ENDIAN);
b854bc19 2359 cpu_register_physical_memory(base, 0x800, iomemtype);
66450b15
AZ		 2360
2361 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
2362}
2363
f34c417b 2364/* Pulse-Width Tone module */
c227f099 2365static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
f34c417b
AZ		 2366{
2367 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 2368 int offset = addr & OMAP_MPUI_REG_MASK;
f34c417b
AZ		 2369
2370 switch (offset) {
2371 case 0x00: /* FRC */
2372 return s->pwt.frc;
2373 case 0x04: /* VCR */
2374 return s->pwt.vrc;
2375 case 0x08: /* GCR */
2376 return s->pwt.gcr;
2377 }
2378 OMAP_BAD_REG(addr);
2379 return 0;
2380}
2381
c227f099 2382static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
f34c417b
AZ		 2383 uint32_t value)
2384{
2385 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
cf965d24 2386 int offset = addr & OMAP_MPUI_REG_MASK;
f34c417b
AZ		 2387
2388 switch (offset) {
2389 case 0x00: /* FRC */
2390 s->pwt.frc = value & 0x3f;
2391 break;
2392 case 0x04: /* VRC */
2393 if ((value ^ s->pwt.vrc) & 1) {
2394 if (value & 1)
2395 printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
2396 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
2397 ((omap_clk_getrate(s->pwt.clk) >> 3) /
2398 /* Pre-multiplexer divider */
2399 ((s->pwt.gcr & 2) ? 1 : 154) /
2400 /* Octave multiplexer */
2401 (2 << (value & 3)) *
2402 /* 101/107 divider */
2403 ((value & (1 << 2)) ? 101 : 107) *
2404 /* 49/55 divider */
2405 ((value & (1 << 3)) ? 49 : 55) *
2406 /* 50/63 divider */
2407 ((value & (1 << 4)) ? 50 : 63) *
2408 /* 80/127 divider */
2409 ((value & (1 << 5)) ? 80 : 127) /
2410 (107 * 55 * 63 * 127)));
2411 else
2412 printf("%s: silence!\n", __FUNCTION__);
2413 }
2414 s->pwt.vrc = value & 0x7f;
2415 break;
2416 case 0x08: /* GCR */
2417 s->pwt.gcr = value & 3;
2418 break;
2419 default:
2420 OMAP_BAD_REG(addr);
2421 return;
2422 }
2423}
2424
d60efc6b 2425static CPUReadMemoryFunc * const omap_pwt_readfn[] = {
02645926 2426 omap_pwt_read,
f34c417b
AZ		 2427 omap_badwidth_read8,
2428 omap_badwidth_read8,
f34c417b
AZ		 2429};
2430
d60efc6b 2431static CPUWriteMemoryFunc * const omap_pwt_writefn[] = {
02645926 2432 omap_pwt_write,
f34c417b
AZ		 2433 omap_badwidth_write8,
2434 omap_badwidth_write8,
f34c417b
AZ		 2435};
2436
9596ebb7 2437static void omap_pwt_reset(struct omap_mpu_state_s *s)
f34c417b
AZ		 2438{
2439 s->pwt.frc = 0;
2440 s->pwt.vrc = 0;
2441 s->pwt.gcr = 0;
2442}
2443
c227f099 2444static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s,
f34c417b
AZ		 2445 omap_clk clk)
2446{
2447 int iomemtype;
2448
f34c417b
AZ		 2449 s->pwt.clk = clk;
2450 omap_pwt_reset(s);
2451
1eed09cb 2452 iomemtype = cpu_register_io_memory(omap_pwt_readfn,
2507c12a 2453 omap_pwt_writefn, s, DEVICE_NATIVE_ENDIAN);
b854bc19 2454 cpu_register_physical_memory(base, 0x800, iomemtype);
f34c417b
AZ		 2455}
2456
5c1c390f
AZ		 2457/* Real-time Clock module */
2458struct omap_rtc_s {
5c1c390f
AZ		 2459 qemu_irq irq;
2460 qemu_irq alarm;
2461 QEMUTimer *clk;
2462
2463 uint8_t interrupts;
2464 uint8_t status;
2465 int16_t comp_reg;
2466 int running;
2467 int pm_am;
2468 int auto_comp;
2469 int round;
5c1c390f
AZ		 2470 struct tm alarm_tm;
2471 time_t alarm_ti;
2472
2473 struct tm current_tm;
2474 time_t ti;
2475 uint64_t tick;
2476};
2477
2478static void omap_rtc_interrupts_update(struct omap_rtc_s *s)
2479{
106627d0 2480 /* s->alarm is level-triggered */
5c1c390f
AZ		 2481 qemu_set_irq(s->alarm, (s->status >> 6) & 1);
2482}
2483
2484static void omap_rtc_alarm_update(struct omap_rtc_s *s)
2485{
0cd2df75 2486 s->alarm_ti = mktimegm(&s->alarm_tm);
5c1c390f
AZ		 2487 if (s->alarm_ti == -1)
2488 printf("%s: conversion failed\n", __FUNCTION__);
2489}
2490
c227f099 2491static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
5c1c390f
AZ		 2492{
2493 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
cf965d24 2494 int offset = addr & OMAP_MPUI_REG_MASK;
5c1c390f
AZ		 2495 uint8_t i;
2496
2497 switch (offset) {
2498 case 0x00: /* SECONDS_REG */
abd0c6bd 2499 return to_bcd(s->current_tm.tm_sec);
5c1c390f
AZ		 2500
2501 case 0x04: /* MINUTES_REG */
abd0c6bd 2502 return to_bcd(s->current_tm.tm_min);
5c1c390f
AZ		 2503
2504 case 0x08: /* HOURS_REG */
2505 if (s->pm_am)
2506 return ((s->current_tm.tm_hour > 11) << 7) |
abd0c6bd 2507 to_bcd(((s->current_tm.tm_hour - 1) % 12) + 1);
5c1c390f 2508 else
abd0c6bd 2509 return to_bcd(s->current_tm.tm_hour);
5c1c390f
AZ		 2510
2511 case 0x0c: /* DAYS_REG */
abd0c6bd 2512 return to_bcd(s->current_tm.tm_mday);
5c1c390f
AZ		 2513
2514 case 0x10: /* MONTHS_REG */
abd0c6bd 2515 return to_bcd(s->current_tm.tm_mon + 1);
5c1c390f
AZ		 2516
2517 case 0x14: /* YEARS_REG */
abd0c6bd 2518 return to_bcd(s->current_tm.tm_year % 100);
5c1c390f
AZ		 2519
2520 case 0x18: /* WEEK_REG */
2521 return s->current_tm.tm_wday;
2522
2523 case 0x20: /* ALARM_SECONDS_REG */
abd0c6bd 2524 return to_bcd(s->alarm_tm.tm_sec);
5c1c390f
AZ		 2525
2526 case 0x24: /* ALARM_MINUTES_REG */
abd0c6bd 2527 return to_bcd(s->alarm_tm.tm_min);
5c1c390f
AZ		 2528
2529 case 0x28: /* ALARM_HOURS_REG */
2530 if (s->pm_am)
2531 return ((s->alarm_tm.tm_hour > 11) << 7) |
abd0c6bd 2532 to_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1);
5c1c390f 2533 else
abd0c6bd 2534 return to_bcd(s->alarm_tm.tm_hour);
5c1c390f
AZ		 2535
2536 case 0x2c: /* ALARM_DAYS_REG */
abd0c6bd 2537 return to_bcd(s->alarm_tm.tm_mday);
5c1c390f
AZ		 2538
2539 case 0x30: /* ALARM_MONTHS_REG */
abd0c6bd 2540 return to_bcd(s->alarm_tm.tm_mon + 1);
5c1c390f
AZ		 2541
2542 case 0x34: /* ALARM_YEARS_REG */
abd0c6bd 2543 return to_bcd(s->alarm_tm.tm_year % 100);
5c1c390f
AZ		 2544
2545 case 0x40: /* RTC_CTRL_REG */
2546 return (s->pm_am << 3) | (s->auto_comp << 2) |
2547 (s->round << 1) | s->running;
2548
2549 case 0x44: /* RTC_STATUS_REG */
2550 i = s->status;
2551 s->status &= ~0x3d;
2552 return i;
2553
2554 case 0x48: /* RTC_INTERRUPTS_REG */
2555 return s->interrupts;
2556
2557 case 0x4c: /* RTC_COMP_LSB_REG */
2558 return ((uint16_t) s->comp_reg) & 0xff;
2559
2560 case 0x50: /* RTC_COMP_MSB_REG */
2561 return ((uint16_t) s->comp_reg) >> 8;
2562 }
2563
2564 OMAP_BAD_REG(addr);
2565 return 0;
2566}
2567
c227f099 2568static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
5c1c390f
AZ		 2569 uint32_t value)
2570{
2571 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
cf965d24 2572 int offset = addr & OMAP_MPUI_REG_MASK;
5c1c390f
AZ		 2573 struct tm new_tm;
2574 time_t ti[2];
2575
2576 switch (offset) {
2577 case 0x00: /* SECONDS_REG */
eb38c52c 2578#ifdef ALMDEBUG
5c1c390f
AZ		 2579 printf("RTC SEC_REG <-- %02x\n", value);
2580#endif
2581 s->ti -= s->current_tm.tm_sec;
abd0c6bd 2582 s->ti += from_bcd(value);
5c1c390f
AZ		 2583 return;
2584
2585 case 0x04: /* MINUTES_REG */
eb38c52c 2586#ifdef ALMDEBUG
5c1c390f
AZ		 2587 printf("RTC MIN_REG <-- %02x\n", value);
2588#endif
2589 s->ti -= s->current_tm.tm_min * 60;
abd0c6bd 2590 s->ti += from_bcd(value) * 60;
5c1c390f
AZ		 2591 return;
2592
2593 case 0x08: /* HOURS_REG */
eb38c52c 2594#ifdef ALMDEBUG
5c1c390f
AZ		 2595 printf("RTC HRS_REG <-- %02x\n", value);
2596#endif
2597 s->ti -= s->current_tm.tm_hour * 3600;
2598 if (s->pm_am) {
abd0c6bd 2599 s->ti += (from_bcd(value & 0x3f) & 12) * 3600;
5c1c390f
AZ		 2600 s->ti += ((value >> 7) & 1) * 43200;
2601 } else
abd0c6bd 2602 s->ti += from_bcd(value & 0x3f) * 3600;
5c1c390f
AZ		 2603 return;
2604
2605 case 0x0c: /* DAYS_REG */
eb38c52c 2606#ifdef ALMDEBUG
5c1c390f
AZ		 2607 printf("RTC DAY_REG <-- %02x\n", value);
2608#endif
2609 s->ti -= s->current_tm.tm_mday * 86400;
abd0c6bd 2610 s->ti += from_bcd(value) * 86400;
5c1c390f
AZ		 2611 return;
2612
2613 case 0x10: /* MONTHS_REG */
eb38c52c 2614#ifdef ALMDEBUG
5c1c390f
AZ		 2615 printf("RTC MTH_REG <-- %02x\n", value);
2616#endif
2617 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
abd0c6bd 2618 new_tm.tm_mon = from_bcd(value);
0cd2df75
AJ		 2619 ti[0] = mktimegm(&s->current_tm);
2620 ti[1] = mktimegm(&new_tm);
5c1c390f
AZ		 2621
2622 if (ti[0] != -1 && ti[1] != -1) {
2623 s->ti -= ti[0];
2624 s->ti += ti[1];
2625 } else {
2626 /* A less accurate version */
2627 s->ti -= s->current_tm.tm_mon * 2592000;
abd0c6bd 2628 s->ti += from_bcd(value) * 2592000;
5c1c390f
AZ		 2629 }
2630 return;
2631
2632 case 0x14: /* YEARS_REG */
eb38c52c 2633#ifdef ALMDEBUG
5c1c390f
AZ		 2634 printf("RTC YRS_REG <-- %02x\n", value);
2635#endif
2636 memcpy(&new_tm, &s->current_tm, sizeof(new_tm));
abd0c6bd 2637 new_tm.tm_year += from_bcd(value) - (new_tm.tm_year % 100);
0cd2df75
AJ		 2638 ti[0] = mktimegm(&s->current_tm);
2639 ti[1] = mktimegm(&new_tm);
5c1c390f
AZ		 2640
2641 if (ti[0] != -1 && ti[1] != -1) {
2642 s->ti -= ti[0];
2643 s->ti += ti[1];
2644 } else {
2645 /* A less accurate version */
2646 s->ti -= (s->current_tm.tm_year % 100) * 31536000;
abd0c6bd 2647 s->ti += from_bcd(value) * 31536000;
5c1c390f
AZ		 2648 }
2649 return;
2650
2651 case 0x18: /* WEEK_REG */
2652 return; /* Ignored */
2653
2654 case 0x20: /* ALARM_SECONDS_REG */
eb38c52c 2655#ifdef ALMDEBUG
5c1c390f
AZ		 2656 printf("ALM SEC_REG <-- %02x\n", value);
2657#endif
abd0c6bd 2658 s->alarm_tm.tm_sec = from_bcd(value);
5c1c390f
AZ		 2659 omap_rtc_alarm_update(s);
2660 return;
2661
2662 case 0x24: /* ALARM_MINUTES_REG */
eb38c52c 2663#ifdef ALMDEBUG
5c1c390f
AZ		 2664 printf("ALM MIN_REG <-- %02x\n", value);
2665#endif
abd0c6bd 2666 s->alarm_tm.tm_min = from_bcd(value);
5c1c390f
AZ		 2667 omap_rtc_alarm_update(s);
2668 return;
2669
2670 case 0x28: /* ALARM_HOURS_REG */
eb38c52c 2671#ifdef ALMDEBUG
5c1c390f
AZ		 2672 printf("ALM HRS_REG <-- %02x\n", value);
2673#endif
2674 if (s->pm_am)
2675 s->alarm_tm.tm_hour =
abd0c6bd 2676 ((from_bcd(value & 0x3f)) % 12) +
5c1c390f
AZ		 2677 ((value >> 7) & 1) * 12;
2678 else
abd0c6bd 2679 s->alarm_tm.tm_hour = from_bcd(value);
5c1c390f
AZ		 2680 omap_rtc_alarm_update(s);
2681 return;
2682
2683 case 0x2c: /* ALARM_DAYS_REG */
eb38c52c 2684#ifdef ALMDEBUG
5c1c390f
AZ		 2685 printf("ALM DAY_REG <-- %02x\n", value);
2686#endif
abd0c6bd 2687 s->alarm_tm.tm_mday = from_bcd(value);
5c1c390f
AZ		 2688 omap_rtc_alarm_update(s);
2689 return;
2690
2691 case 0x30: /* ALARM_MONTHS_REG */
eb38c52c 2692#ifdef ALMDEBUG
5c1c390f
AZ		 2693 printf("ALM MON_REG <-- %02x\n", value);
2694#endif
abd0c6bd 2695 s->alarm_tm.tm_mon = from_bcd(value);
5c1c390f
AZ		 2696 omap_rtc_alarm_update(s);
2697 return;
2698
2699 case 0x34: /* ALARM_YEARS_REG */
eb38c52c 2700#ifdef ALMDEBUG
5c1c390f
AZ		 2701 printf("ALM YRS_REG <-- %02x\n", value);
2702#endif
abd0c6bd 2703 s->alarm_tm.tm_year = from_bcd(value);
5c1c390f
AZ		 2704 omap_rtc_alarm_update(s);
2705 return;
2706
2707 case 0x40: /* RTC_CTRL_REG */
eb38c52c 2708#ifdef ALMDEBUG
5c1c390f
AZ		 2709 printf("RTC CONTROL <-- %02x\n", value);
2710#endif
2711 s->pm_am = (value >> 3) & 1;
2712 s->auto_comp = (value >> 2) & 1;
2713 s->round = (value >> 1) & 1;
2714 s->running = value & 1;
2715 s->status &= 0xfd;
2716 s->status |= s->running << 1;
2717 return;
2718
2719 case 0x44: /* RTC_STATUS_REG */
eb38c52c 2720#ifdef ALMDEBUG
5c1c390f
AZ		 2721 printf("RTC STATUSL <-- %02x\n", value);
2722#endif
2723 s->status &= ~((value & 0xc0) ^ 0x80);
2724 omap_rtc_interrupts_update(s);
2725 return;
2726
2727 case 0x48: /* RTC_INTERRUPTS_REG */
eb38c52c 2728#ifdef ALMDEBUG
5c1c390f
AZ		 2729 printf("RTC INTRS <-- %02x\n", value);
2730#endif
2731 s->interrupts = value;
2732 return;
2733
2734 case 0x4c: /* RTC_COMP_LSB_REG */
eb38c52c 2735#ifdef ALMDEBUG
5c1c390f
AZ		 2736 printf("RTC COMPLSB <-- %02x\n", value);
2737#endif
2738 s->comp_reg &= 0xff00;
2739 s->comp_reg |= 0x00ff & value;
2740 return;
2741
2742 case 0x50: /* RTC_COMP_MSB_REG */
eb38c52c 2743#ifdef ALMDEBUG
5c1c390f
AZ		 2744 printf("RTC COMPMSB <-- %02x\n", value);
2745#endif
2746 s->comp_reg &= 0x00ff;
2747 s->comp_reg |= 0xff00 & (value << 8);
2748 return;
2749
2750 default:
2751 OMAP_BAD_REG(addr);
2752 return;
2753 }
2754}
2755
d60efc6b 2756static CPUReadMemoryFunc * const omap_rtc_readfn[] = {
5c1c390f
AZ		 2757 omap_rtc_read,
2758 omap_badwidth_read8,
2759 omap_badwidth_read8,
2760};
2761
d60efc6b 2762static CPUWriteMemoryFunc * const omap_rtc_writefn[] = {
5c1c390f
AZ		 2763 omap_rtc_write,
2764 omap_badwidth_write8,
2765 omap_badwidth_write8,
2766};
2767
2768static void omap_rtc_tick(void *opaque)
2769{
2770 struct omap_rtc_s *s = opaque;
2771
2772 if (s->round) {
2773 /* Round to nearest full minute. */
2774 if (s->current_tm.tm_sec < 30)
2775 s->ti -= s->current_tm.tm_sec;
2776 else
2777 s->ti += 60 - s->current_tm.tm_sec;
2778
2779 s->round = 0;
2780 }
2781
f6503059 2782 memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm));
5c1c390f
AZ		 2783
2784 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) {
2785 s->status |= 0x40;
2786 omap_rtc_interrupts_update(s);
2787 }
2788
2789 if (s->interrupts & 0x04)
2790 switch (s->interrupts & 3) {
2791 case 0:
2792 s->status |= 0x04;
106627d0 2793 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 2794 break;
2795 case 1:
2796 if (s->current_tm.tm_sec)
2797 break;
2798 s->status |= 0x08;
106627d0 2799 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 2800 break;
2801 case 2:
2802 if (s->current_tm.tm_sec || s->current_tm.tm_min)
2803 break;
2804 s->status |= 0x10;
106627d0 2805 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 2806 break;
2807 case 3:
2808 if (s->current_tm.tm_sec ||
2809 s->current_tm.tm_min || s->current_tm.tm_hour)
2810 break;
2811 s->status |= 0x20;
106627d0 2812 qemu_irq_pulse(s->irq);
5c1c390f
AZ		 2813 break;
2814 }
2815
2816 /* Move on */
2817 if (s->running)
2818 s->ti ++;
2819 s->tick += 1000;
2820
2821 /*
2822 * Every full hour add a rough approximation of the compensation
2823 * register to the 32kHz Timer (which drives the RTC) value.
2824 */
2825 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min)
2826 s->tick += s->comp_reg * 1000 / 32768;
2827
2828 qemu_mod_timer(s->clk, s->tick);
2829}
2830
9596ebb7 2831static void omap_rtc_reset(struct omap_rtc_s *s)
5c1c390f 2832{
f6503059
AZ		 2833 struct tm tm;
2834
5c1c390f
AZ		 2835 s->interrupts = 0;
2836 s->comp_reg = 0;
2837 s->running = 0;
2838 s->pm_am = 0;
2839 s->auto_comp = 0;
2840 s->round = 0;
7bd427d8 2841 s->tick = qemu_get_clock_ms(rt_clock);
5c1c390f
AZ		 2842 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
2843 s->alarm_tm.tm_mday = 0x01;
2844 s->status = 1 << 7;
f6503059 2845 qemu_get_timedate(&tm, 0);
0cd2df75 2846 s->ti = mktimegm(&tm);
5c1c390f
AZ		 2847
2848 omap_rtc_alarm_update(s);
2849 omap_rtc_tick(s);
2850}
2851
c1ff227b 2852static struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
5c1c390f
AZ		 2853 qemu_irq *irq, omap_clk clk)
2854{
2855 int iomemtype;
2856 struct omap_rtc_s *s = (struct omap_rtc_s *)
7267c094 2857 g_malloc0(sizeof(struct omap_rtc_s));
5c1c390f 2858
5c1c390f
AZ		 2859 s->irq = irq[0];
2860 s->alarm = irq[1];
7bd427d8 2861 s->clk = qemu_new_timer_ms(rt_clock, omap_rtc_tick, s);
5c1c390f
AZ		 2862
2863 omap_rtc_reset(s);
2864
1eed09cb 2865 iomemtype = cpu_register_io_memory(omap_rtc_readfn,
2507c12a 2866 omap_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
8da3ff18 2867 cpu_register_physical_memory(base, 0x800, iomemtype);
5c1c390f
AZ		 2868
2869 return s;
2870}
2871
d8f699cb
AZ		 2872/* Multi-channel Buffered Serial Port interfaces */
2873struct omap_mcbsp_s {
d8f699cb
AZ		 2874 qemu_irq txirq;
2875 qemu_irq rxirq;
2876 qemu_irq txdrq;
2877 qemu_irq rxdrq;
2878
2879 uint16_t spcr[2];
2880 uint16_t rcr[2];
2881 uint16_t xcr[2];
2882 uint16_t srgr[2];
2883 uint16_t mcr[2];
2884 uint16_t pcr;
2885 uint16_t rcer[8];
2886 uint16_t xcer[8];
2887 int tx_rate;
2888 int rx_rate;
2889 int tx_req;
73560bc8 2890 int rx_req;
d8f699cb 2891
bc24a225 2892 I2SCodec *codec;
73560bc8
AZ		 2893 QEMUTimer *source_timer;
2894 QEMUTimer *sink_timer;
d8f699cb
AZ		 2895};
2896
2897static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s)
2898{
2899 int irq;
2900
2901 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */
2902 case 0:
2903 irq = (s->spcr[0] >> 1) & 1; /* RRDY */
2904 break;
2905 case 3:
2906 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */
2907 break;
2908 default:
2909 irq = 0;
2910 break;
2911 }
2912
106627d0
AZ		 2913 if (irq)
2914 qemu_irq_pulse(s->rxirq);
d8f699cb
AZ		 2915
2916 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */
2917 case 0:
2918 irq = (s->spcr[1] >> 1) & 1; /* XRDY */
2919 break;
2920 case 3:
2921 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */
2922 break;
2923 default:
2924 irq = 0;
2925 break;
2926 }
2927
106627d0
AZ		 2928 if (irq)
2929 qemu_irq_pulse(s->txirq);
d8f699cb
AZ		 2930}
2931
73560bc8 2932static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
d8f699cb 2933{
73560bc8
AZ		 2934 if ((s->spcr[0] >> 1) & 1) /* RRDY */
2935 s->spcr[0] |= 1 << 2; /* RFULL */
2936 s->spcr[0] |= 1 << 1; /* RRDY */
2937 qemu_irq_raise(s->rxdrq);
2938 omap_mcbsp_intr_update(s);
d8f699cb
AZ		 2939}
2940
73560bc8 2941static void omap_mcbsp_source_tick(void *opaque)
d8f699cb 2942{
73560bc8
AZ		 2943 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
2944 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
2945
2946 if (!s->rx_rate)
d8f699cb 2947 return;
73560bc8
AZ		 2948 if (s->rx_req)
2949 printf("%s: Rx FIFO overrun\n", __FUNCTION__);
d8f699cb 2950
73560bc8 2951 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7];
d8f699cb 2952
73560bc8 2953 omap_mcbsp_rx_newdata(s);
74475455 2954 qemu_mod_timer(s->source_timer, qemu_get_clock_ns(vm_clock) +
6ee093c9 2955 get_ticks_per_sec());
d8f699cb
AZ		 2956}
2957
2958static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s)
2959{
73560bc8
AZ		 2960 if (!s->codec || !s->codec->rts)
2961 omap_mcbsp_source_tick(s);
2962 else if (s->codec->in.len) {
2963 s->rx_req = s->codec->in.len;
2964 omap_mcbsp_rx_newdata(s);
d8f699cb 2965 }
d8f699cb
AZ		 2966}
2967
2968static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s)
73560bc8
AZ		 2969{
2970 qemu_del_timer(s->source_timer);
2971}
2972
2973static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s)
d8f699cb
AZ		 2974{
2975 s->spcr[0] &= ~(1 << 1); /* RRDY */
2976 qemu_irq_lower(s->rxdrq);
2977 omap_mcbsp_intr_update(s);
2978}
2979
73560bc8
AZ		 2980static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
2981{
2982 s->spcr[1] |= 1 << 1; /* XRDY */
2983 qemu_irq_raise(s->txdrq);
2984 omap_mcbsp_intr_update(s);
2985}
2986
2987static void omap_mcbsp_sink_tick(void *opaque)
d8f699cb 2988{
73560bc8
AZ		 2989 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
2990 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
2991
2992 if (!s->tx_rate)
d8f699cb 2993 return;
73560bc8
AZ		 2994 if (s->tx_req)
2995 printf("%s: Tx FIFO underrun\n", __FUNCTION__);
2996
2997 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7];
2998
2999 omap_mcbsp_tx_newdata(s);
74475455 3000 qemu_mod_timer(s->sink_timer, qemu_get_clock_ns(vm_clock) +
6ee093c9 3001 get_ticks_per_sec());
73560bc8
AZ		 3002}
3003
3004static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s)
3005{
3006 if (!s->codec || !s->codec->cts)
3007 omap_mcbsp_sink_tick(s);
3008 else if (s->codec->out.size) {
3009 s->tx_req = s->codec->out.size;
3010 omap_mcbsp_tx_newdata(s);
3011 }
3012}
3013
3014static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s)
3015{
3016 s->spcr[1] &= ~(1 << 1); /* XRDY */
3017 qemu_irq_lower(s->txdrq);
3018 omap_mcbsp_intr_update(s);
3019 if (s->codec && s->codec->cts)
3020 s->codec->tx_swallow(s->codec->opaque);
d8f699cb
AZ		 3021}
3022
3023static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s)
3024{
73560bc8
AZ		 3025 s->tx_req = 0;
3026 omap_mcbsp_tx_done(s);
3027 qemu_del_timer(s->sink_timer);
3028}
3029
3030static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
3031{
3032 int prev_rx_rate, prev_tx_rate;
3033 int rx_rate = 0, tx_rate = 0;
3034 int cpu_rate = 1500000; /* XXX */
3035
3036 /* TODO: check CLKSTP bit */
3037 if (s->spcr[1] & (1 << 6)) { /* GRST */
3038 if (s->spcr[0] & (1 << 0)) { /* RRST */
3039 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3040 (s->pcr & (1 << 8))) { /* CLKRM */
3041 if (~s->pcr & (1 << 7)) /* SCLKME */
3042 rx_rate = cpu_rate /
3043 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3044 } else
3045 if (s->codec)
3046 rx_rate = s->codec->rx_rate;
3047 }
3048
3049 if (s->spcr[1] & (1 << 0)) { /* XRST */
3050 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */
3051 (s->pcr & (1 << 9))) { /* CLKXM */
3052 if (~s->pcr & (1 << 7)) /* SCLKME */
3053 tx_rate = cpu_rate /
3054 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */
3055 } else
3056 if (s->codec)
3057 tx_rate = s->codec->tx_rate;
3058 }
3059 }
3060 prev_tx_rate = s->tx_rate;
3061 prev_rx_rate = s->rx_rate;
3062 s->tx_rate = tx_rate;
3063 s->rx_rate = rx_rate;
3064
3065 if (s->codec)
3066 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate);
3067
3068 if (!prev_tx_rate && tx_rate)
3069 omap_mcbsp_tx_start(s);
3070 else if (s->tx_rate && !tx_rate)
3071 omap_mcbsp_tx_stop(s);
3072
3073 if (!prev_rx_rate && rx_rate)
3074 omap_mcbsp_rx_start(s);
3075 else if (prev_tx_rate && !tx_rate)
3076 omap_mcbsp_rx_stop(s);
d8f699cb
AZ		 3077}
3078
c227f099 3079static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr)
d8f699cb
AZ		 3080{
3081 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3082 int offset = addr & OMAP_MPUI_REG_MASK;
3083 uint16_t ret;
3084
3085 switch (offset) {
3086 case 0x00: /* DRR2 */
3087 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */
3088 return 0x0000;
3089 /* Fall through. */
3090 case 0x02: /* DRR1 */
73560bc8 3091 if (s->rx_req < 2) {
d8f699cb 3092 printf("%s: Rx FIFO underrun\n", __FUNCTION__);
73560bc8 3093 omap_mcbsp_rx_done(s);
d8f699cb 3094 } else {
73560bc8
AZ		 3095 s->tx_req -= 2;
3096 if (s->codec && s->codec->in.len >= 2) {
3097 ret = s->codec->in.fifo[s->codec->in.start ++] << 8;
3098 ret |= s->codec->in.fifo[s->codec->in.start ++];
3099 s->codec->in.len -= 2;
3100 } else
3101 ret = 0x0000;
3102 if (!s->tx_req)
3103 omap_mcbsp_rx_done(s);
d8f699cb
AZ		 3104 return ret;
3105 }
3106 return 0x0000;
3107
3108 case 0x04: /* DXR2 */
3109 case 0x06: /* DXR1 */
3110 return 0x0000;
3111
3112 case 0x08: /* SPCR2 */
3113 return s->spcr[1];
3114 case 0x0a: /* SPCR1 */
3115 return s->spcr[0];
3116 case 0x0c: /* RCR2 */
3117 return s->rcr[1];
3118 case 0x0e: /* RCR1 */
3119 return s->rcr[0];
3120 case 0x10: /* XCR2 */
3121 return s->xcr[1];
3122 case 0x12: /* XCR1 */
3123 return s->xcr[0];
3124 case 0x14: /* SRGR2 */
3125 return s->srgr[1];
3126 case 0x16: /* SRGR1 */
3127 return s->srgr[0];
3128 case 0x18: /* MCR2 */
3129 return s->mcr[1];
3130 case 0x1a: /* MCR1 */
3131 return s->mcr[0];
3132 case 0x1c: /* RCERA */
3133 return s->rcer[0];
3134 case 0x1e: /* RCERB */
3135 return s->rcer[1];
3136 case 0x20: /* XCERA */
3137 return s->xcer[0];
3138 case 0x22: /* XCERB */
3139 return s->xcer[1];
3140 case 0x24: /* PCR0 */
3141 return s->pcr;
3142 case 0x26: /* RCERC */
3143 return s->rcer[2];
3144 case 0x28: /* RCERD */
3145 return s->rcer[3];
3146 case 0x2a: /* XCERC */
3147 return s->xcer[2];
3148 case 0x2c: /* XCERD */
3149 return s->xcer[3];
3150 case 0x2e: /* RCERE */
3151 return s->rcer[4];
3152 case 0x30: /* RCERF */
3153 return s->rcer[5];
3154 case 0x32: /* XCERE */
3155 return s->xcer[4];
3156 case 0x34: /* XCERF */
3157 return s->xcer[5];
3158 case 0x36: /* RCERG */
3159 return s->rcer[6];
3160 case 0x38: /* RCERH */
3161 return s->rcer[7];
3162 case 0x3a: /* XCERG */
3163 return s->xcer[6];
3164 case 0x3c: /* XCERH */
3165 return s->xcer[7];
3166 }
3167
3168 OMAP_BAD_REG(addr);
3169 return 0;
3170}
3171
c227f099 3172static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
d8f699cb
AZ		 3173 uint32_t value)
3174{
3175 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3176 int offset = addr & OMAP_MPUI_REG_MASK;
3177
3178 switch (offset) {
3179 case 0x00: /* DRR2 */
3180 case 0x02: /* DRR1 */
3181 OMAP_RO_REG(addr);
3182 return;
3183
3184 case 0x04: /* DXR2 */
3185 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3186 return;
3187 /* Fall through. */
3188 case 0x06: /* DXR1 */
73560bc8
AZ		 3189 if (s->tx_req > 1) {
3190 s->tx_req -= 2;
3191 if (s->codec && s->codec->cts) {
d8f699cb
AZ		 3192 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff;
3193 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff;
d8f699cb 3194 }
73560bc8
AZ		 3195 if (s->tx_req < 2)
3196 omap_mcbsp_tx_done(s);
d8f699cb
AZ		 3197 } else
3198 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
3199 return;
3200
3201 case 0x08: /* SPCR2 */
3202 s->spcr[1] &= 0x0002;
3203 s->spcr[1] |= 0x03f9 & value;
3204 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */
73560bc8 3205 if (~value & 1) /* XRST */
d8f699cb 3206 s->spcr[1] &= ~6;
d8f699cb
AZ		 3207 omap_mcbsp_req_update(s);
3208 return;
3209 case 0x0a: /* SPCR1 */
3210 s->spcr[0] &= 0x0006;
3211 s->spcr[0] |= 0xf8f9 & value;
3212 if (value & (1 << 15)) /* DLB */
3213 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__);
3214 if (~value & 1) { /* RRST */
3215 s->spcr[0] &= ~6;
73560bc8
AZ		 3216 s->rx_req = 0;
3217 omap_mcbsp_rx_done(s);
d8f699cb 3218 }
d8f699cb
AZ		 3219 omap_mcbsp_req_update(s);
3220 return;
3221
3222 case 0x0c: /* RCR2 */
3223 s->rcr[1] = value & 0xffff;
3224 return;
3225 case 0x0e: /* RCR1 */
3226 s->rcr[0] = value & 0x7fe0;
3227 return;
3228 case 0x10: /* XCR2 */
3229 s->xcr[1] = value & 0xffff;
3230 return;
3231 case 0x12: /* XCR1 */
3232 s->xcr[0] = value & 0x7fe0;
3233 return;
3234 case 0x14: /* SRGR2 */
3235 s->srgr[1] = value & 0xffff;
73560bc8 3236 omap_mcbsp_req_update(s);
d8f699cb
AZ		 3237 return;
3238 case 0x16: /* SRGR1 */
3239 s->srgr[0] = value & 0xffff;
73560bc8 3240 omap_mcbsp_req_update(s);
d8f699cb
AZ		 3241 return;
3242 case 0x18: /* MCR2 */
3243 s->mcr[1] = value & 0x03e3;
3244 if (value & 3) /* XMCM */
3245 printf("%s: Tx channel selection mode enable attempt\n",
3246 __FUNCTION__);
3247 return;
3248 case 0x1a: /* MCR1 */
3249 s->mcr[0] = value & 0x03e1;
3250 if (value & 1) /* RMCM */
3251 printf("%s: Rx channel selection mode enable attempt\n",
3252 __FUNCTION__);
3253 return;
3254 case 0x1c: /* RCERA */
3255 s->rcer[0] = value & 0xffff;
3256 return;
3257 case 0x1e: /* RCERB */
3258 s->rcer[1] = value & 0xffff;
3259 return;
3260 case 0x20: /* XCERA */
3261 s->xcer[0] = value & 0xffff;
3262 return;
3263 case 0x22: /* XCERB */
3264 s->xcer[1] = value & 0xffff;
3265 return;
3266 case 0x24: /* PCR0 */
3267 s->pcr = value & 0x7faf;
3268 return;
3269 case 0x26: /* RCERC */
3270 s->rcer[2] = value & 0xffff;
3271 return;
3272 case 0x28: /* RCERD */
3273 s->rcer[3] = value & 0xffff;
3274 return;
3275 case 0x2a: /* XCERC */
3276 s->xcer[2] = value & 0xffff;
3277 return;
3278 case 0x2c: /* XCERD */
3279 s->xcer[3] = value & 0xffff;
3280 return;
3281 case 0x2e: /* RCERE */
3282 s->rcer[4] = value & 0xffff;
3283 return;
3284 case 0x30: /* RCERF */
3285 s->rcer[5] = value & 0xffff;
3286 return;
3287 case 0x32: /* XCERE */
3288 s->xcer[4] = value & 0xffff;
3289 return;
3290 case 0x34: /* XCERF */
3291 s->xcer[5] = value & 0xffff;
3292 return;
3293 case 0x36: /* RCERG */
3294 s->rcer[6] = value & 0xffff;
3295 return;
3296 case 0x38: /* RCERH */
3297 s->rcer[7] = value & 0xffff;
3298 return;
3299 case 0x3a: /* XCERG */
3300 s->xcer[6] = value & 0xffff;
3301 return;
3302 case 0x3c: /* XCERH */
3303 s->xcer[7] = value & 0xffff;
3304 return;
3305 }
3306
3307 OMAP_BAD_REG(addr);
3308}
3309
c227f099 3310static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
73560bc8
AZ		 3311 uint32_t value)
3312{
3313 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3314 int offset = addr & OMAP_MPUI_REG_MASK;
3315
3316 if (offset == 0x04) { /* DXR */
3317 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */
3318 return;
3319 if (s->tx_req > 3) {
3320 s->tx_req -= 4;
3321 if (s->codec && s->codec->cts) {
3322 s->codec->out.fifo[s->codec->out.len ++] =
3323 (value >> 24) & 0xff;
3324 s->codec->out.fifo[s->codec->out.len ++] =
3325 (value >> 16) & 0xff;
3326 s->codec->out.fifo[s->codec->out.len ++] =
3327 (value >> 8) & 0xff;
3328 s->codec->out.fifo[s->codec->out.len ++] =
3329 (value >> 0) & 0xff;
3330 }
3331 if (s->tx_req < 4)
3332 omap_mcbsp_tx_done(s);
3333 } else
3334 printf("%s: Tx FIFO overrun\n", __FUNCTION__);
3335 return;
3336 }
3337
3338 omap_badwidth_write16(opaque, addr, value);
3339}
3340
d60efc6b 3341static CPUReadMemoryFunc * const omap_mcbsp_readfn[] = {
d8f699cb
AZ		 3342 omap_badwidth_read16,
3343 omap_mcbsp_read,
3344 omap_badwidth_read16,
3345};
3346
d60efc6b 3347static CPUWriteMemoryFunc * const omap_mcbsp_writefn[] = {
d8f699cb 3348 omap_badwidth_write16,
73560bc8
AZ		 3349 omap_mcbsp_writeh,
3350 omap_mcbsp_writew,
d8f699cb
AZ		 3351};
3352
3353static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
3354{
3355 memset(&s->spcr, 0, sizeof(s->spcr));
3356 memset(&s->rcr, 0, sizeof(s->rcr));
3357 memset(&s->xcr, 0, sizeof(s->xcr));
3358 s->srgr[0] = 0x0001;
3359 s->srgr[1] = 0x2000;
3360 memset(&s->mcr, 0, sizeof(s->mcr));
3361 memset(&s->pcr, 0, sizeof(s->pcr));
3362 memset(&s->rcer, 0, sizeof(s->rcer));
3363 memset(&s->xcer, 0, sizeof(s->xcer));
3364 s->tx_req = 0;
73560bc8 3365 s->rx_req = 0;
d8f699cb
AZ		 3366 s->tx_rate = 0;
3367 s->rx_rate = 0;
73560bc8
AZ		 3368 qemu_del_timer(s->source_timer);
3369 qemu_del_timer(s->sink_timer);
d8f699cb
AZ		 3370}
3371
c227f099 3372struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
d8f699cb
AZ		 3373 qemu_irq *irq, qemu_irq *dma, omap_clk clk)
3374{
3375 int iomemtype;
3376 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
7267c094 3377 g_malloc0(sizeof(struct omap_mcbsp_s));
d8f699cb 3378
d8f699cb
AZ		 3379 s->txirq = irq[0];
3380 s->rxirq = irq[1];
3381 s->txdrq = dma[0];
3382 s->rxdrq = dma[1];
74475455
PB		 3383 s->sink_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_sink_tick, s);
3384 s->source_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_source_tick, s);
d8f699cb
AZ		 3385 omap_mcbsp_reset(s);
3386
1eed09cb 3387 iomemtype = cpu_register_io_memory(omap_mcbsp_readfn,
2507c12a 3388 omap_mcbsp_writefn, s, DEVICE_NATIVE_ENDIAN);
8da3ff18 3389 cpu_register_physical_memory(base, 0x800, iomemtype);
d8f699cb
AZ		 3390
3391 return s;
3392}
3393
9596ebb7 3394static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
d8f699cb
AZ		 3395{
3396 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3397
73560bc8
AZ		 3398 if (s->rx_rate) {
3399 s->rx_req = s->codec->in.len;
3400 omap_mcbsp_rx_newdata(s);
3401 }
d8f699cb
AZ		 3402}
3403
9596ebb7 3404static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
d8f699cb
AZ		 3405{
3406 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
3407
73560bc8
AZ		 3408 if (s->tx_rate) {
3409 s->tx_req = s->codec->out.size;
3410 omap_mcbsp_tx_newdata(s);
3411 }
d8f699cb
AZ		 3412}
3413
bc24a225 3414void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave)
d8f699cb
AZ		 3415{
3416 s->codec = slave;
3417 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0];
3418 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0];
3419}
3420
f9d43072
AZ		 3421/* LED Pulse Generators */
3422struct omap_lpg_s {
f9d43072
AZ		 3423 QEMUTimer *tm;
3424
3425 uint8_t control;
3426 uint8_t power;
3427 int64_t on;
3428 int64_t period;
3429 int clk;
3430 int cycle;
3431};
3432
3433static void omap_lpg_tick(void *opaque)
3434{
3435 struct omap_lpg_s *s = opaque;
3436
3437 if (s->cycle)
7bd427d8 3438 qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->period - s->on);
f9d43072 3439 else
7bd427d8 3440 qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->on);
f9d43072
AZ		 3441
3442 s->cycle = !s->cycle;
3443 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
3444}
3445
3446static void omap_lpg_update(struct omap_lpg_s *s)
3447{
3448 int64_t on, period = 1, ticks = 1000;
3449 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
3450
3451 if (~s->control & (1 << 6)) /* LPGRES */
3452 on = 0;
3453 else if (s->control & (1 << 7)) /* PERM_ON */
3454 on = period;
3455 else {
3456 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */
3457 256 / 32);
3458 on = (s->clk && s->power) ? muldiv64(ticks,
3459 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */
3460 }
3461
3462 qemu_del_timer(s->tm);
3463 if (on == period && s->on < s->period)
3464 printf("%s: LED is on\n", __FUNCTION__);
3465 else if (on == 0 && s->on)
3466 printf("%s: LED is off\n", __FUNCTION__);
3467 else if (on && (on != s->on || period != s->period)) {
3468 s->cycle = 0;
3469 s->on = on;
3470 s->period = period;
3471 omap_lpg_tick(s);
3472 return;
3473 }
3474
3475 s->on = on;
3476 s->period = period;
3477}
3478
3479static void omap_lpg_reset(struct omap_lpg_s *s)
3480{
3481 s->control = 0x00;
3482 s->power = 0x00;
3483 s->clk = 1;
3484 omap_lpg_update(s);
3485}
3486
c227f099 3487static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr)
f9d43072
AZ		 3488{
3489 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3490 int offset = addr & OMAP_MPUI_REG_MASK;
3491
3492 switch (offset) {
3493 case 0x00: /* LCR */
3494 return s->control;
3495
3496 case 0x04: /* PMR */
3497 return s->power;
3498 }
3499
3500 OMAP_BAD_REG(addr);
3501 return 0;
3502}
3503
c227f099 3504static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
f9d43072
AZ		 3505 uint32_t value)
3506{
3507 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3508 int offset = addr & OMAP_MPUI_REG_MASK;
3509
3510 switch (offset) {
3511 case 0x00: /* LCR */
3512 if (~value & (1 << 6)) /* LPGRES */
3513 omap_lpg_reset(s);
3514 s->control = value & 0xff;
3515 omap_lpg_update(s);
3516 return;
3517
3518 case 0x04: /* PMR */
3519 s->power = value & 0x01;
3520 omap_lpg_update(s);
3521 return;
3522
3523 default:
3524 OMAP_BAD_REG(addr);
3525 return;
3526 }
3527}
3528
d60efc6b 3529static CPUReadMemoryFunc * const omap_lpg_readfn[] = {
f9d43072
AZ		 3530 omap_lpg_read,
3531 omap_badwidth_read8,
3532 omap_badwidth_read8,
3533};
3534
d60efc6b 3535static CPUWriteMemoryFunc * const omap_lpg_writefn[] = {
f9d43072
AZ		 3536 omap_lpg_write,
3537 omap_badwidth_write8,
3538 omap_badwidth_write8,
3539};
3540
3541static void omap_lpg_clk_update(void *opaque, int line, int on)
3542{
3543 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
3544
3545 s->clk = on;
3546 omap_lpg_update(s);
3547}
3548
c1ff227b 3549static struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk)
f9d43072
AZ		 3550{
3551 int iomemtype;
3552 struct omap_lpg_s *s = (struct omap_lpg_s *)
7267c094 3553 g_malloc0(sizeof(struct omap_lpg_s));
f9d43072 3554
7bd427d8 3555 s->tm = qemu_new_timer_ms(rt_clock, omap_lpg_tick, s);
f9d43072
AZ		 3556
3557 omap_lpg_reset(s);
3558
1eed09cb 3559 iomemtype = cpu_register_io_memory(omap_lpg_readfn,
2507c12a 3560 omap_lpg_writefn, s, DEVICE_NATIVE_ENDIAN);
8da3ff18 3561 cpu_register_physical_memory(base, 0x800, iomemtype);
f9d43072
AZ		 3562
3563 omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]);
3564
3565 return s;
3566}
3567
3568/* MPUI Peripheral Bridge configuration */
c227f099 3569static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr)
f9d43072
AZ		 3570{
3571 if (addr == OMAP_MPUI_BASE) /* CMR */
3572 return 0xfe4d;
3573
3574 OMAP_BAD_REG(addr);
3575 return 0;
3576}
3577
d60efc6b 3578static CPUReadMemoryFunc * const omap_mpui_io_readfn[] = {
f9d43072
AZ		 3579 omap_badwidth_read16,
3580 omap_mpui_io_read,
3581 omap_badwidth_read16,
3582};
3583
d60efc6b 3584static CPUWriteMemoryFunc * const omap_mpui_io_writefn[] = {
f9d43072
AZ		 3585 omap_badwidth_write16,
3586 omap_badwidth_write16,
3587 omap_badwidth_write16,
3588};
3589
3590static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu)
3591{
1eed09cb 3592 int iomemtype = cpu_register_io_memory(omap_mpui_io_readfn,
2507c12a 3593 omap_mpui_io_writefn, mpu, DEVICE_NATIVE_ENDIAN);
f9d43072
AZ		 3594 cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype);
3595}
3596
c3d2689d 3597/* General chip reset */
827df9f3 3598static void omap1_mpu_reset(void *opaque)
c3d2689d
AZ		 3599{
3600 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
3601
c3d2689d
AZ		 3602 omap_inth_reset(mpu->ih[0]);
3603 omap_inth_reset(mpu->ih[1]);
3604 omap_dma_reset(mpu->dma);
3605 omap_mpu_timer_reset(mpu->timer[0]);
3606 omap_mpu_timer_reset(mpu->timer[1]);
3607 omap_mpu_timer_reset(mpu->timer[2]);
3608 omap_wd_timer_reset(mpu->wdt);
3609 omap_os_timer_reset(mpu->os_timer);
3610 omap_lcdc_reset(mpu->lcd);
3611 omap_ulpd_pm_reset(mpu);
3612 omap_pin_cfg_reset(mpu);
3613 omap_mpui_reset(mpu);
3614 omap_tipb_bridge_reset(mpu->private_tipb);
3615 omap_tipb_bridge_reset(mpu->public_tipb);
3616 omap_dpll_reset(&mpu->dpll[0]);
3617 omap_dpll_reset(&mpu->dpll[1]);
3618 omap_dpll_reset(&mpu->dpll[2]);
d951f6ff
AZ		 3619 omap_uart_reset(mpu->uart[0]);
3620 omap_uart_reset(mpu->uart[1]);
3621 omap_uart_reset(mpu->uart[2]);
b30bb3a2 3622 omap_mmc_reset(mpu->mmc);
fe71e81a 3623 omap_mpuio_reset(mpu->mpuio);
d951f6ff 3624 omap_uwire_reset(mpu->microwire);
66450b15 3625 omap_pwl_reset(mpu);
4a2c8ac2 3626 omap_pwt_reset(mpu);
827df9f3 3627 omap_i2c_reset(mpu->i2c[0]);
5c1c390f 3628 omap_rtc_reset(mpu->rtc);
d8f699cb
AZ		 3629 omap_mcbsp_reset(mpu->mcbsp1);
3630 omap_mcbsp_reset(mpu->mcbsp2);
3631 omap_mcbsp_reset(mpu->mcbsp3);
f9d43072
AZ		 3632 omap_lpg_reset(mpu->led[0]);
3633 omap_lpg_reset(mpu->led[1]);
8ef6367e 3634 omap_clkm_reset(mpu);
c3d2689d
AZ		 3635 cpu_reset(mpu->env);
3636}
3637
cf965d24 3638static const struct omap_map_s {
c227f099
AL		 3639 target_phys_addr_t phys_dsp;
3640 target_phys_addr_t phys_mpu;
cf965d24
AZ		 3641 uint32_t size;
3642 const char *name;
3643} omap15xx_dsp_mm[] = {
3644 /* Strobe 0 */
3645 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
3646 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
3647 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
3648 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
3649 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
3650 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
3651 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
3652 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
3653 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
3654 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
3655 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
3656 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
3657 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
3658 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
3659 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
3660 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
3661 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
3662 /* Strobe 1 */
3663 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
3664
3665 { 0 }
3666};
3667
3668static void omap_setup_dsp_mapping(const struct omap_map_s *map)
3669{
3670 int io;
3671
3672 for (; map->phys_dsp; map ++) {
3673 io = cpu_get_physical_page_desc(map->phys_mpu);
3674
3675 cpu_register_physical_memory(map->phys_dsp, map->size, io);
3676 }
3677}
3678
827df9f3 3679void omap_mpu_wakeup(void *opaque, int irq, int req)
c3d2689d
AZ		 3680{
3681 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
3682
fe71e81a
AZ		 3683 if (mpu->env->halted)
3684 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
c3d2689d
AZ		 3685}
3686
827df9f3 3687static const struct dma_irq_map omap1_dma_irq_map[] = {
089b7c0a
AZ		 3688 { 0, OMAP_INT_DMA_CH0_6 },
3689 { 0, OMAP_INT_DMA_CH1_7 },
3690 { 0, OMAP_INT_DMA_CH2_8 },
3691 { 0, OMAP_INT_DMA_CH3 },
3692 { 0, OMAP_INT_DMA_CH4 },
3693 { 0, OMAP_INT_DMA_CH5 },
3694 { 1, OMAP_INT_1610_DMA_CH6 },
3695 { 1, OMAP_INT_1610_DMA_CH7 },
3696 { 1, OMAP_INT_1610_DMA_CH8 },
3697 { 1, OMAP_INT_1610_DMA_CH9 },
3698 { 1, OMAP_INT_1610_DMA_CH10 },
3699 { 1, OMAP_INT_1610_DMA_CH11 },
3700 { 1, OMAP_INT_1610_DMA_CH12 },
3701 { 1, OMAP_INT_1610_DMA_CH13 },
3702 { 1, OMAP_INT_1610_DMA_CH14 },
3703 { 1, OMAP_INT_1610_DMA_CH15 }
3704};
3705
b4e3104b
AZ		 3706/* DMA ports for OMAP1 */
3707static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
c227f099 3708 target_phys_addr_t addr)
b4e3104b 3709{
45416789 3710 return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
b4e3104b
AZ		 3711}
3712
3713static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
c227f099 3714 target_phys_addr_t addr)
b4e3104b 3715{
45416789
BS		 3716 return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
3717 addr);
b4e3104b
AZ		 3718}
3719
3720static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
c227f099 3721 target_phys_addr_t addr)
b4e3104b 3722{
45416789 3723 return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
b4e3104b
AZ		 3724}
3725
3726static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
c227f099 3727 target_phys_addr_t addr)
b4e3104b 3728{
45416789 3729 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
b4e3104b
AZ		 3730}
3731
3732static int omap_validate_local_addr(struct omap_mpu_state_s *s,
c227f099 3733 target_phys_addr_t addr)
b4e3104b 3734{
45416789 3735 return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
b4e3104b
AZ		 3736}
3737
3738static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
c227f099 3739 target_phys_addr_t addr)
b4e3104b 3740{
45416789 3741 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
b4e3104b
AZ		 3742}
3743
4b3fedf3
AK		 3744struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
3745 unsigned long sdram_size,
3023f332 3746 const char *core)
c3d2689d 3747{
089b7c0a 3748 int i;
c3d2689d 3749 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
7267c094 3750 g_malloc0(sizeof(struct omap_mpu_state_s));
c227f099 3751 ram_addr_t imif_base, emiff_base;
106627d0 3752 qemu_irq *cpu_irq;
089b7c0a 3753 qemu_irq dma_irqs[6];
751c6a17 3754 DriveInfo *dinfo;
106627d0 3755
aaed909a
FB		 3756 if (!core)
3757 core = "ti925t";
c3d2689d
AZ		 3758
3759 /* Core */
3760 s->mpu_model = omap310;
aaed909a
FB		 3761 s->env = cpu_init(core);
3762 if (!s->env) {
3763 fprintf(stderr, "Unable to find CPU definition\n");
3764 exit(1);
3765 }
c3d2689d
AZ		 3766 s->sdram_size = sdram_size;
3767 s->sram_size = OMAP15XX_SRAM_SIZE;
3768
fe71e81a
AZ		 3769 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
3770
c3d2689d
AZ		 3771 /* Clocks */
3772 omap_clk_init(s);
3773
3774 /* Memory-mapped stuff */
3775 cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
1724f049
AW		 3776 (emiff_base = qemu_ram_alloc(NULL, "omap1.dram",
3777 s->sdram_size)) | IO_MEM_RAM);
c3d2689d 3778 cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
1724f049
AW		 3779 (imif_base = qemu_ram_alloc(NULL, "omap1.sram",
3780 s->sram_size)) | IO_MEM_RAM);
c3d2689d
AZ		 3781
3782 omap_clkm_init(0xfffece00, 0xe1008000, s);
3783
106627d0 3784 cpu_irq = arm_pic_init_cpu(s->env);
827df9f3 3785 s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
106627d0 3786 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
c3d2689d 3787 omap_findclk(s, "arminth_ck"));
827df9f3 3788 s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1],
7f132a21 3789 omap_inth_get_pin(s->ih[0], OMAP_INT_15XX_IH2_IRQ),
3790 NULL, omap_findclk(s, "arminth_ck"));
c3d2689d 3791
089b7c0a 3792 for (i = 0; i < 6; i ++)
827df9f3
AZ		 3793 dma_irqs[i] =
3794 s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr];
089b7c0a
AZ		 3795 s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD],
3796 s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
3797
c3d2689d
AZ		 3798 s->port[emiff ].addr_valid = omap_validate_emiff_addr;
3799 s->port[emifs ].addr_valid = omap_validate_emifs_addr;
3800 s->port[imif ].addr_valid = omap_validate_imif_addr;
3801 s->port[tipb ].addr_valid = omap_validate_tipb_addr;
3802 s->port[local ].addr_valid = omap_validate_local_addr;
3803 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
3804
afbb5194
AZ		 3805 /* Register SDRAM and SRAM DMA ports for fast transfers. */
3806 soc_dma_port_add_mem_ram(s->dma,
3807 emiff_base, OMAP_EMIFF_BASE, s->sdram_size);
3808 soc_dma_port_add_mem_ram(s->dma,
3809 imif_base, OMAP_IMIF_BASE, s->sram_size);
3810
4b3fedf3 3811 s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500,
c3d2689d
AZ		 3812 s->irq[0][OMAP_INT_TIMER1],
3813 omap_findclk(s, "mputim_ck"));
4b3fedf3 3814 s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600,
c3d2689d
AZ		 3815 s->irq[0][OMAP_INT_TIMER2],
3816 omap_findclk(s, "mputim_ck"));
4b3fedf3 3817 s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700,
c3d2689d
AZ		 3818 s->irq[0][OMAP_INT_TIMER3],
3819 omap_findclk(s, "mputim_ck"));
3820
4b3fedf3 3821 s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
c3d2689d
AZ		 3822 s->irq[0][OMAP_INT_WD_TIMER],
3823 omap_findclk(s, "armwdt_ck"));
3824
4b3fedf3 3825 s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
c3d2689d
AZ		 3826 s->irq[1][OMAP_INT_OS_TIMER],
3827 omap_findclk(s, "clk32-kHz"));
3828
3829 s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
3023f332 3830 omap_dma_get_lcdch(s->dma), imif_base, emiff_base,
c3d2689d
AZ		 3831 omap_findclk(s, "lcd_ck"));
3832
4b3fedf3
AK		 3833 omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
3834 omap_pin_cfg_init(system_memory, 0xfffe1000, s);
3835 omap_id_init(system_memory, s);
c3d2689d 3836
4b3fedf3 3837 omap_mpui_init(system_memory, 0xfffec900, s);
c3d2689d 3838
4b3fedf3 3839 s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
c3d2689d
AZ		 3840 s->irq[0][OMAP_INT_BRIDGE_PRIV],
3841 omap_findclk(s, "tipb_ck"));
4b3fedf3 3842 s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
c3d2689d
AZ		 3843 s->irq[0][OMAP_INT_BRIDGE_PUB],
3844 omap_findclk(s, "tipb_ck"));
3845
3846 omap_tcmi_init(0xfffecc00, s);
3847
d951f6ff 3848 s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
c3d2689d 3849 omap_findclk(s, "uart1_ck"),
827df9f3
AZ		 3850 omap_findclk(s, "uart1_ck"),
3851 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
6a8aabd3 3852 "uart1",
c3d2689d 3853 serial_hds[0]);
d951f6ff 3854 s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
c3d2689d 3855 omap_findclk(s, "uart2_ck"),
827df9f3
AZ		 3856 omap_findclk(s, "uart2_ck"),
3857 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
6a8aabd3 3858 "uart2",
b9d38e95 3859 serial_hds[0] ? serial_hds[1] : NULL);
13643323 3860 s->uart[2] = omap_uart_init(0xfffb9800, s->irq[0][OMAP_INT_UART3],
c3d2689d 3861 omap_findclk(s, "uart3_ck"),
827df9f3
AZ		 3862 omap_findclk(s, "uart3_ck"),
3863 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
6a8aabd3 3864 "uart3",
b9d38e95 3865 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
c3d2689d
AZ		 3866
3867 omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
3868 omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
3869 omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
3870
751c6a17
GH		 3871 dinfo = drive_get(IF_SD, 0, 0);
3872 if (!dinfo) {
e4bcb14c
TS		 3873 fprintf(stderr, "qemu: missing SecureDigital device\n");
3874 exit(1);
3875 }
751c6a17 3876 s->mmc = omap_mmc_init(0xfffb7800, dinfo->bdrv,
9d413d1d
AZ		 3877 s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
3878 omap_findclk(s, "mmc_ck"));
b30bb3a2 3879
fe71e81a
AZ		 3880 s->mpuio = omap_mpuio_init(0xfffb5000,
3881 s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
3882 s->wakeup, omap_findclk(s, "clk32-kHz"));
3883
77831c20
JR		 3884 s->gpio = qdev_create(NULL, "omap-gpio");
3885 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
3886 qdev_init_nofail(s->gpio);
3887 sysbus_connect_irq(sysbus_from_qdev(s->gpio), 0,
3888 s->irq[0][OMAP_INT_GPIO_BANK1]);
3889 sysbus_mmio_map(sysbus_from_qdev(s->gpio), 0, 0xfffce000);
64330148 3890
d951f6ff
AZ		 3891 s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
3892 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
3893
d8f699cb
AZ		 3894 omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck"));
3895 omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck"));
66450b15 3896
827df9f3 3897 s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
4a2c8ac2
AZ		 3898 &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
3899
5c1c390f
AZ		 3900 s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER],
3901 omap_findclk(s, "clk32-kHz"));
02645926 3902
d8f699cb
AZ		 3903 s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
3904 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
3905 s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
3906 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
3907 s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
3908 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
3909
f9d43072
AZ		 3910 s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz"));
3911 s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz"));
3912
02645926 3913 /* Register mappings not currenlty implemented:
02645926
AZ		 3914 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
3915 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
3916 * USB W2FC fffb4000 - fffb47ff
3917 * Camera Interface fffb6800 - fffb6fff
02645926
AZ		 3918 * USB Host fffba000 - fffba7ff
3919 * FAC fffba800 - fffbafff
3920 * HDQ/1-Wire fffbc000 - fffbc7ff
b854bc19 3921 * TIPB switches fffbc800 - fffbcfff
02645926
AZ		 3922 * Mailbox fffcf000 - fffcf7ff
3923 * Local bus IF fffec100 - fffec1ff
3924 * Local bus MMU fffec200 - fffec2ff
3925 * DSP MMU fffed200 - fffed2ff
3926 */
3927
cf965d24 3928 omap_setup_dsp_mapping(omap15xx_dsp_mm);
f9d43072 3929 omap_setup_mpui_io(s);
cf965d24 3930
a08d4367 3931 qemu_register_reset(omap1_mpu_reset, s);
c3d2689d
AZ		 3932
3933 return s;
3934}
Qemu copy for testing