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827df9f3 AZ |
1 | /* |
2 | * TI OMAP processors emulation. | |
3 | * | |
4 | * Copyright (C) 2007-2008 Nokia Corporation | |
5 | * Written by Andrzej Zaborowski <andrew@openedhand.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 or | |
10 | * (at your option) version 3 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | #include "hw.h" | |
23 | #include "arm-misc.h" | |
24 | #include "omap.h" | |
25 | #include "sysemu.h" | |
26 | #include "qemu-timer.h" | |
27 | #include "qemu-char.h" | |
28 | #include "flash.h" | |
afbb5194 | 29 | #include "soc_dma.h" |
99570a40 | 30 | #include "audio/audio.h" |
827df9f3 AZ |
31 | |
32 | /* GP timers */ | |
33 | struct omap_gp_timer_s { | |
34 | qemu_irq irq; | |
35 | qemu_irq wkup; | |
36 | qemu_irq in; | |
37 | qemu_irq out; | |
38 | omap_clk clk; | |
39 | target_phys_addr_t base; | |
40 | QEMUTimer *timer; | |
41 | QEMUTimer *match; | |
42 | struct omap_target_agent_s *ta; | |
43 | ||
44 | int in_val; | |
45 | int out_val; | |
46 | int64_t time; | |
47 | int64_t rate; | |
48 | int64_t ticks_per_sec; | |
49 | ||
50 | int16_t config; | |
51 | int status; | |
52 | int it_ena; | |
53 | int wu_ena; | |
54 | int enable; | |
55 | int inout; | |
56 | int capt2; | |
57 | int pt; | |
58 | enum { | |
59 | gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both | |
60 | } trigger; | |
61 | enum { | |
62 | gpt_capture_none, gpt_capture_rising, | |
63 | gpt_capture_falling, gpt_capture_both | |
64 | } capture; | |
65 | int scpwm; | |
66 | int ce; | |
67 | int pre; | |
68 | int ptv; | |
69 | int ar; | |
70 | int st; | |
71 | int posted; | |
72 | uint32_t val; | |
73 | uint32_t load_val; | |
74 | uint32_t capture_val[2]; | |
75 | uint32_t match_val; | |
76 | int capt_num; | |
77 | ||
78 | uint16_t writeh; /* LSB */ | |
79 | uint16_t readh; /* MSB */ | |
80 | }; | |
81 | ||
82 | #define GPT_TCAR_IT (1 << 2) | |
83 | #define GPT_OVF_IT (1 << 1) | |
84 | #define GPT_MAT_IT (1 << 0) | |
85 | ||
86 | static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it) | |
87 | { | |
88 | if (timer->it_ena & it) { | |
89 | if (!timer->status) | |
90 | qemu_irq_raise(timer->irq); | |
91 | ||
92 | timer->status |= it; | |
93 | /* Or are the status bits set even when masked? | |
94 | * i.e. is masking applied before or after the status register? */ | |
95 | } | |
96 | ||
97 | if (timer->wu_ena & it) | |
98 | qemu_irq_pulse(timer->wkup); | |
99 | } | |
100 | ||
101 | static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level) | |
102 | { | |
103 | if (!timer->inout && timer->out_val != level) { | |
104 | timer->out_val = level; | |
105 | qemu_set_irq(timer->out, level); | |
106 | } | |
107 | } | |
108 | ||
109 | static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer) | |
110 | { | |
111 | uint64_t distance; | |
112 | ||
113 | if (timer->st && timer->rate) { | |
114 | distance = qemu_get_clock(vm_clock) - timer->time; | |
115 | distance = muldiv64(distance, timer->rate, timer->ticks_per_sec); | |
116 | ||
117 | if (distance >= 0xffffffff - timer->val) | |
118 | return 0xffffffff; | |
119 | else | |
120 | return timer->val + distance; | |
121 | } else | |
122 | return timer->val; | |
123 | } | |
124 | ||
125 | static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer) | |
126 | { | |
127 | if (timer->st) { | |
128 | timer->val = omap_gp_timer_read(timer); | |
129 | timer->time = qemu_get_clock(vm_clock); | |
130 | } | |
131 | } | |
132 | ||
133 | static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer) | |
134 | { | |
135 | int64_t expires, matches; | |
136 | ||
137 | if (timer->st && timer->rate) { | |
138 | expires = muldiv64(0x100000000ll - timer->val, | |
139 | timer->ticks_per_sec, timer->rate); | |
140 | qemu_mod_timer(timer->timer, timer->time + expires); | |
141 | ||
142 | if (timer->ce && timer->match_val >= timer->val) { | |
143 | matches = muldiv64(timer->match_val - timer->val, | |
144 | timer->ticks_per_sec, timer->rate); | |
145 | qemu_mod_timer(timer->match, timer->time + matches); | |
146 | } else | |
147 | qemu_del_timer(timer->match); | |
148 | } else { | |
149 | qemu_del_timer(timer->timer); | |
150 | qemu_del_timer(timer->match); | |
151 | omap_gp_timer_out(timer, timer->scpwm); | |
152 | } | |
153 | } | |
154 | ||
155 | static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer) | |
156 | { | |
157 | if (timer->pt) | |
158 | /* TODO in overflow-and-match mode if the first event to | |
159 | * occurs is the match, don't toggle. */ | |
160 | omap_gp_timer_out(timer, !timer->out_val); | |
161 | else | |
162 | /* TODO inverted pulse on timer->out_val == 1? */ | |
163 | qemu_irq_pulse(timer->out); | |
164 | } | |
165 | ||
166 | static void omap_gp_timer_tick(void *opaque) | |
167 | { | |
168 | struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; | |
169 | ||
170 | if (!timer->ar) { | |
171 | timer->st = 0; | |
172 | timer->val = 0; | |
173 | } else { | |
174 | timer->val = timer->load_val; | |
175 | timer->time = qemu_get_clock(vm_clock); | |
176 | } | |
177 | ||
178 | if (timer->trigger == gpt_trigger_overflow || | |
179 | timer->trigger == gpt_trigger_both) | |
180 | omap_gp_timer_trigger(timer); | |
181 | ||
182 | omap_gp_timer_intr(timer, GPT_OVF_IT); | |
183 | omap_gp_timer_update(timer); | |
184 | } | |
185 | ||
186 | static void omap_gp_timer_match(void *opaque) | |
187 | { | |
188 | struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; | |
189 | ||
190 | if (timer->trigger == gpt_trigger_both) | |
191 | omap_gp_timer_trigger(timer); | |
192 | ||
193 | omap_gp_timer_intr(timer, GPT_MAT_IT); | |
194 | } | |
195 | ||
196 | static void omap_gp_timer_input(void *opaque, int line, int on) | |
197 | { | |
198 | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; | |
199 | int trigger; | |
200 | ||
201 | switch (s->capture) { | |
202 | default: | |
203 | case gpt_capture_none: | |
204 | trigger = 0; | |
205 | break; | |
206 | case gpt_capture_rising: | |
207 | trigger = !s->in_val && on; | |
208 | break; | |
209 | case gpt_capture_falling: | |
210 | trigger = s->in_val && !on; | |
211 | break; | |
212 | case gpt_capture_both: | |
213 | trigger = (s->in_val == !on); | |
214 | break; | |
215 | } | |
216 | s->in_val = on; | |
217 | ||
218 | if (s->inout && trigger && s->capt_num < 2) { | |
219 | s->capture_val[s->capt_num] = omap_gp_timer_read(s); | |
220 | ||
221 | if (s->capt2 == s->capt_num ++) | |
222 | omap_gp_timer_intr(s, GPT_TCAR_IT); | |
223 | } | |
224 | } | |
225 | ||
226 | static void omap_gp_timer_clk_update(void *opaque, int line, int on) | |
227 | { | |
228 | struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; | |
229 | ||
230 | omap_gp_timer_sync(timer); | |
231 | timer->rate = on ? omap_clk_getrate(timer->clk) : 0; | |
232 | omap_gp_timer_update(timer); | |
233 | } | |
234 | ||
235 | static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer) | |
236 | { | |
237 | omap_clk_adduser(timer->clk, | |
238 | qemu_allocate_irqs(omap_gp_timer_clk_update, timer, 1)[0]); | |
239 | timer->rate = omap_clk_getrate(timer->clk); | |
240 | } | |
241 | ||
242 | static void omap_gp_timer_reset(struct omap_gp_timer_s *s) | |
243 | { | |
244 | s->config = 0x000; | |
245 | s->status = 0; | |
246 | s->it_ena = 0; | |
247 | s->wu_ena = 0; | |
248 | s->inout = 0; | |
249 | s->capt2 = 0; | |
250 | s->capt_num = 0; | |
251 | s->pt = 0; | |
252 | s->trigger = gpt_trigger_none; | |
253 | s->capture = gpt_capture_none; | |
254 | s->scpwm = 0; | |
255 | s->ce = 0; | |
256 | s->pre = 0; | |
257 | s->ptv = 0; | |
258 | s->ar = 0; | |
259 | s->st = 0; | |
260 | s->posted = 1; | |
261 | s->val = 0x00000000; | |
262 | s->load_val = 0x00000000; | |
263 | s->capture_val[0] = 0x00000000; | |
264 | s->capture_val[1] = 0x00000000; | |
265 | s->match_val = 0x00000000; | |
266 | omap_gp_timer_update(s); | |
267 | } | |
268 | ||
269 | static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr) | |
270 | { | |
271 | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; | |
272 | int offset = addr - s->base; | |
273 | ||
274 | switch (offset) { | |
275 | case 0x00: /* TIDR */ | |
276 | return 0x21; | |
277 | ||
278 | case 0x10: /* TIOCP_CFG */ | |
279 | return s->config; | |
280 | ||
281 | case 0x14: /* TISTAT */ | |
282 | /* ??? When's this bit reset? */ | |
283 | return 1; /* RESETDONE */ | |
284 | ||
285 | case 0x18: /* TISR */ | |
286 | return s->status; | |
287 | ||
288 | case 0x1c: /* TIER */ | |
289 | return s->it_ena; | |
290 | ||
291 | case 0x20: /* TWER */ | |
292 | return s->wu_ena; | |
293 | ||
294 | case 0x24: /* TCLR */ | |
295 | return (s->inout << 14) | | |
296 | (s->capt2 << 13) | | |
297 | (s->pt << 12) | | |
298 | (s->trigger << 10) | | |
299 | (s->capture << 8) | | |
300 | (s->scpwm << 7) | | |
301 | (s->ce << 6) | | |
302 | (s->pre << 5) | | |
303 | (s->ptv << 2) | | |
304 | (s->ar << 1) | | |
305 | (s->st << 0); | |
306 | ||
307 | case 0x28: /* TCRR */ | |
308 | return omap_gp_timer_read(s); | |
309 | ||
310 | case 0x2c: /* TLDR */ | |
311 | return s->load_val; | |
312 | ||
313 | case 0x30: /* TTGR */ | |
314 | return 0xffffffff; | |
315 | ||
316 | case 0x34: /* TWPS */ | |
317 | return 0x00000000; /* No posted writes pending. */ | |
318 | ||
319 | case 0x38: /* TMAR */ | |
320 | return s->match_val; | |
321 | ||
322 | case 0x3c: /* TCAR1 */ | |
323 | return s->capture_val[0]; | |
324 | ||
325 | case 0x40: /* TSICR */ | |
326 | return s->posted << 2; | |
327 | ||
328 | case 0x44: /* TCAR2 */ | |
329 | return s->capture_val[1]; | |
330 | } | |
331 | ||
332 | OMAP_BAD_REG(addr); | |
333 | return 0; | |
334 | } | |
335 | ||
336 | static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr) | |
337 | { | |
338 | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; | |
339 | uint32_t ret; | |
340 | ||
341 | if (addr & 2) | |
342 | return s->readh; | |
343 | else { | |
344 | ret = omap_gp_timer_readw(opaque, addr); | |
345 | s->readh = ret >> 16; | |
346 | return ret & 0xffff; | |
347 | } | |
348 | } | |
349 | ||
350 | static CPUReadMemoryFunc *omap_gp_timer_readfn[] = { | |
351 | omap_badwidth_read32, | |
352 | omap_gp_timer_readh, | |
353 | omap_gp_timer_readw, | |
354 | }; | |
355 | ||
356 | static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr, | |
357 | uint32_t value) | |
358 | { | |
359 | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; | |
360 | int offset = addr - s->base; | |
361 | ||
362 | switch (offset) { | |
363 | case 0x00: /* TIDR */ | |
364 | case 0x14: /* TISTAT */ | |
365 | case 0x34: /* TWPS */ | |
366 | case 0x3c: /* TCAR1 */ | |
367 | case 0x44: /* TCAR2 */ | |
368 | OMAP_RO_REG(addr); | |
369 | break; | |
370 | ||
371 | case 0x10: /* TIOCP_CFG */ | |
372 | s->config = value & 0x33d; | |
373 | if (((value >> 3) & 3) == 3) /* IDLEMODE */ | |
374 | fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n", | |
375 | __FUNCTION__); | |
376 | if (value & 2) /* SOFTRESET */ | |
377 | omap_gp_timer_reset(s); | |
378 | break; | |
379 | ||
380 | case 0x18: /* TISR */ | |
381 | if (value & GPT_TCAR_IT) | |
382 | s->capt_num = 0; | |
383 | if (s->status && !(s->status &= ~value)) | |
384 | qemu_irq_lower(s->irq); | |
385 | break; | |
386 | ||
387 | case 0x1c: /* TIER */ | |
388 | s->it_ena = value & 7; | |
389 | break; | |
390 | ||
391 | case 0x20: /* TWER */ | |
392 | s->wu_ena = value & 7; | |
393 | break; | |
394 | ||
395 | case 0x24: /* TCLR */ | |
396 | omap_gp_timer_sync(s); | |
397 | s->inout = (value >> 14) & 1; | |
398 | s->capt2 = (value >> 13) & 1; | |
399 | s->pt = (value >> 12) & 1; | |
400 | s->trigger = (value >> 10) & 3; | |
401 | if (s->capture == gpt_capture_none && | |
402 | ((value >> 8) & 3) != gpt_capture_none) | |
403 | s->capt_num = 0; | |
404 | s->capture = (value >> 8) & 3; | |
405 | s->scpwm = (value >> 7) & 1; | |
406 | s->ce = (value >> 6) & 1; | |
407 | s->pre = (value >> 5) & 1; | |
408 | s->ptv = (value >> 2) & 7; | |
409 | s->ar = (value >> 1) & 1; | |
410 | s->st = (value >> 0) & 1; | |
411 | if (s->inout && s->trigger != gpt_trigger_none) | |
412 | fprintf(stderr, "%s: GP timer pin must be an output " | |
413 | "for this trigger mode\n", __FUNCTION__); | |
414 | if (!s->inout && s->capture != gpt_capture_none) | |
415 | fprintf(stderr, "%s: GP timer pin must be an input " | |
416 | "for this capture mode\n", __FUNCTION__); | |
417 | if (s->trigger == gpt_trigger_none) | |
418 | omap_gp_timer_out(s, s->scpwm); | |
419 | /* TODO: make sure this doesn't overflow 32-bits */ | |
420 | s->ticks_per_sec = ticks_per_sec << (s->pre ? s->ptv + 1 : 0); | |
421 | omap_gp_timer_update(s); | |
422 | break; | |
423 | ||
424 | case 0x28: /* TCRR */ | |
425 | s->time = qemu_get_clock(vm_clock); | |
426 | s->val = value; | |
427 | omap_gp_timer_update(s); | |
428 | break; | |
429 | ||
430 | case 0x2c: /* TLDR */ | |
431 | s->load_val = value; | |
432 | break; | |
433 | ||
434 | case 0x30: /* TTGR */ | |
435 | s->time = qemu_get_clock(vm_clock); | |
436 | s->val = s->load_val; | |
437 | omap_gp_timer_update(s); | |
438 | break; | |
439 | ||
440 | case 0x38: /* TMAR */ | |
441 | omap_gp_timer_sync(s); | |
442 | s->match_val = value; | |
443 | omap_gp_timer_update(s); | |
444 | break; | |
445 | ||
446 | case 0x40: /* TSICR */ | |
447 | s->posted = (value >> 2) & 1; | |
448 | if (value & 2) /* How much exactly are we supposed to reset? */ | |
449 | omap_gp_timer_reset(s); | |
450 | break; | |
451 | ||
452 | default: | |
453 | OMAP_BAD_REG(addr); | |
454 | } | |
455 | } | |
456 | ||
457 | static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr, | |
458 | uint32_t value) | |
459 | { | |
460 | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; | |
461 | ||
462 | if (addr & 2) | |
463 | return omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh); | |
464 | else | |
465 | s->writeh = (uint16_t) value; | |
466 | } | |
467 | ||
468 | static CPUWriteMemoryFunc *omap_gp_timer_writefn[] = { | |
469 | omap_badwidth_write32, | |
470 | omap_gp_timer_writeh, | |
471 | omap_gp_timer_write, | |
472 | }; | |
473 | ||
474 | struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, | |
475 | qemu_irq irq, omap_clk fclk, omap_clk iclk) | |
476 | { | |
477 | int iomemtype; | |
478 | struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) | |
479 | qemu_mallocz(sizeof(struct omap_gp_timer_s)); | |
480 | ||
481 | s->ta = ta; | |
482 | s->irq = irq; | |
483 | s->clk = fclk; | |
484 | s->timer = qemu_new_timer(vm_clock, omap_gp_timer_tick, s); | |
485 | s->match = qemu_new_timer(vm_clock, omap_gp_timer_match, s); | |
486 | s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0]; | |
487 | omap_gp_timer_reset(s); | |
488 | omap_gp_timer_clk_setup(s); | |
489 | ||
c66fb5bc | 490 | iomemtype = l4_register_io_memory(0, omap_gp_timer_readfn, |
827df9f3 AZ |
491 | omap_gp_timer_writefn, s); |
492 | s->base = omap_l4_attach(ta, 0, iomemtype); | |
493 | ||
494 | return s; | |
495 | } | |
496 | ||
497 | /* 32-kHz Sync Timer of the OMAP2 */ | |
498 | static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) { | |
499 | return muldiv64(qemu_get_clock(vm_clock), 0x8000, ticks_per_sec); | |
500 | } | |
501 | ||
502 | static void omap_synctimer_reset(struct omap_synctimer_s *s) | |
503 | { | |
504 | s->val = omap_synctimer_read(s); | |
505 | } | |
506 | ||
507 | static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr) | |
508 | { | |
509 | struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; | |
510 | int offset = addr - s->base; | |
511 | ||
512 | switch (offset) { | |
513 | case 0x00: /* 32KSYNCNT_REV */ | |
514 | return 0x21; | |
515 | ||
516 | case 0x10: /* CR */ | |
517 | return omap_synctimer_read(s) - s->val; | |
518 | } | |
519 | ||
520 | OMAP_BAD_REG(addr); | |
521 | return 0; | |
522 | } | |
523 | ||
524 | static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr) | |
525 | { | |
526 | struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; | |
527 | uint32_t ret; | |
528 | ||
529 | if (addr & 2) | |
530 | return s->readh; | |
531 | else { | |
532 | ret = omap_synctimer_readw(opaque, addr); | |
533 | s->readh = ret >> 16; | |
534 | return ret & 0xffff; | |
535 | } | |
536 | } | |
537 | ||
538 | static CPUReadMemoryFunc *omap_synctimer_readfn[] = { | |
539 | omap_badwidth_read32, | |
540 | omap_synctimer_readh, | |
541 | omap_synctimer_readw, | |
542 | }; | |
543 | ||
544 | static void omap_synctimer_write(void *opaque, target_phys_addr_t addr, | |
545 | uint32_t value) | |
546 | { | |
547 | OMAP_BAD_REG(addr); | |
548 | } | |
549 | ||
550 | static CPUWriteMemoryFunc *omap_synctimer_writefn[] = { | |
551 | omap_badwidth_write32, | |
552 | omap_synctimer_write, | |
553 | omap_synctimer_write, | |
554 | }; | |
555 | ||
556 | void omap_synctimer_init(struct omap_target_agent_s *ta, | |
557 | struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk) | |
558 | { | |
559 | struct omap_synctimer_s *s = &mpu->synctimer; | |
560 | ||
561 | omap_synctimer_reset(s); | |
c66fb5bc | 562 | s->base = omap_l4_attach(ta, 0, l4_register_io_memory(0, |
827df9f3 AZ |
563 | omap_synctimer_readfn, omap_synctimer_writefn, s)); |
564 | } | |
565 | ||
566 | /* General-Purpose Interface of OMAP2 */ | |
567 | struct omap2_gpio_s { | |
568 | target_phys_addr_t base; | |
569 | qemu_irq irq[2]; | |
570 | qemu_irq wkup; | |
571 | qemu_irq *in; | |
572 | qemu_irq handler[32]; | |
573 | ||
574 | uint8_t config[2]; | |
575 | uint32_t inputs; | |
576 | uint32_t outputs; | |
577 | uint32_t dir; | |
578 | uint32_t level[2]; | |
579 | uint32_t edge[2]; | |
580 | uint32_t mask[2]; | |
581 | uint32_t wumask; | |
582 | uint32_t ints[2]; | |
583 | uint32_t debounce; | |
584 | uint8_t delay; | |
585 | }; | |
586 | ||
587 | static inline void omap_gpio_module_int_update(struct omap2_gpio_s *s, | |
588 | int line) | |
589 | { | |
590 | qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]); | |
591 | } | |
592 | ||
593 | static void omap_gpio_module_wake(struct omap2_gpio_s *s, int line) | |
594 | { | |
595 | if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */ | |
596 | return; | |
597 | if (!(s->config[0] & (3 << 3))) /* Force Idle */ | |
598 | return; | |
599 | if (!(s->wumask & (1 << line))) | |
600 | return; | |
601 | ||
602 | qemu_irq_raise(s->wkup); | |
603 | } | |
604 | ||
605 | static inline void omap_gpio_module_out_update(struct omap2_gpio_s *s, | |
606 | uint32_t diff) | |
607 | { | |
608 | int ln; | |
609 | ||
610 | s->outputs ^= diff; | |
611 | diff &= ~s->dir; | |
612 | while ((ln = ffs(diff))) { | |
613 | ln --; | |
614 | qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1); | |
615 | diff &= ~(1 << ln); | |
616 | } | |
617 | } | |
618 | ||
619 | static void omap_gpio_module_level_update(struct omap2_gpio_s *s, int line) | |
620 | { | |
621 | s->ints[line] |= s->dir & | |
622 | ((s->inputs & s->level[1]) | (~s->inputs & s->level[0])); | |
623 | omap_gpio_module_int_update(s, line); | |
624 | } | |
625 | ||
626 | static inline void omap_gpio_module_int(struct omap2_gpio_s *s, int line) | |
627 | { | |
628 | s->ints[0] |= 1 << line; | |
629 | omap_gpio_module_int_update(s, 0); | |
630 | s->ints[1] |= 1 << line; | |
631 | omap_gpio_module_int_update(s, 1); | |
632 | omap_gpio_module_wake(s, line); | |
633 | } | |
634 | ||
635 | static void omap_gpio_module_set(void *opaque, int line, int level) | |
636 | { | |
637 | struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; | |
638 | ||
639 | if (level) { | |
640 | if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1])) | |
641 | omap_gpio_module_int(s, line); | |
642 | s->inputs |= 1 << line; | |
643 | } else { | |
644 | if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0])) | |
645 | omap_gpio_module_int(s, line); | |
646 | s->inputs &= ~(1 << line); | |
647 | } | |
648 | } | |
649 | ||
650 | static void omap_gpio_module_reset(struct omap2_gpio_s *s) | |
651 | { | |
652 | s->config[0] = 0; | |
653 | s->config[1] = 2; | |
654 | s->ints[0] = 0; | |
655 | s->ints[1] = 0; | |
656 | s->mask[0] = 0; | |
657 | s->mask[1] = 0; | |
658 | s->wumask = 0; | |
659 | s->dir = ~0; | |
660 | s->level[0] = 0; | |
661 | s->level[1] = 0; | |
662 | s->edge[0] = 0; | |
663 | s->edge[1] = 0; | |
664 | s->debounce = 0; | |
665 | s->delay = 0; | |
666 | } | |
667 | ||
668 | static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr) | |
669 | { | |
670 | struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; | |
671 | int offset = addr - s->base; | |
672 | ||
673 | switch (offset) { | |
674 | case 0x00: /* GPIO_REVISION */ | |
675 | return 0x18; | |
676 | ||
677 | case 0x10: /* GPIO_SYSCONFIG */ | |
678 | return s->config[0]; | |
679 | ||
680 | case 0x14: /* GPIO_SYSSTATUS */ | |
681 | return 0x01; | |
682 | ||
683 | case 0x18: /* GPIO_IRQSTATUS1 */ | |
684 | return s->ints[0]; | |
685 | ||
686 | case 0x1c: /* GPIO_IRQENABLE1 */ | |
687 | case 0x60: /* GPIO_CLEARIRQENABLE1 */ | |
688 | case 0x64: /* GPIO_SETIRQENABLE1 */ | |
689 | return s->mask[0]; | |
690 | ||
691 | case 0x20: /* GPIO_WAKEUPENABLE */ | |
692 | case 0x80: /* GPIO_CLEARWKUENA */ | |
693 | case 0x84: /* GPIO_SETWKUENA */ | |
694 | return s->wumask; | |
695 | ||
696 | case 0x28: /* GPIO_IRQSTATUS2 */ | |
697 | return s->ints[1]; | |
698 | ||
699 | case 0x2c: /* GPIO_IRQENABLE2 */ | |
700 | case 0x70: /* GPIO_CLEARIRQENABLE2 */ | |
701 | case 0x74: /* GPIO_SETIREQNEABLE2 */ | |
702 | return s->mask[1]; | |
703 | ||
704 | case 0x30: /* GPIO_CTRL */ | |
705 | return s->config[1]; | |
706 | ||
707 | case 0x34: /* GPIO_OE */ | |
708 | return s->dir; | |
709 | ||
710 | case 0x38: /* GPIO_DATAIN */ | |
711 | return s->inputs; | |
712 | ||
713 | case 0x3c: /* GPIO_DATAOUT */ | |
714 | case 0x90: /* GPIO_CLEARDATAOUT */ | |
715 | case 0x94: /* GPIO_SETDATAOUT */ | |
716 | return s->outputs; | |
717 | ||
718 | case 0x40: /* GPIO_LEVELDETECT0 */ | |
719 | return s->level[0]; | |
720 | ||
721 | case 0x44: /* GPIO_LEVELDETECT1 */ | |
722 | return s->level[1]; | |
723 | ||
724 | case 0x48: /* GPIO_RISINGDETECT */ | |
725 | return s->edge[0]; | |
726 | ||
727 | case 0x4c: /* GPIO_FALLINGDETECT */ | |
728 | return s->edge[1]; | |
729 | ||
730 | case 0x50: /* GPIO_DEBOUNCENABLE */ | |
731 | return s->debounce; | |
732 | ||
733 | case 0x54: /* GPIO_DEBOUNCINGTIME */ | |
734 | return s->delay; | |
735 | } | |
736 | ||
737 | OMAP_BAD_REG(addr); | |
738 | return 0; | |
739 | } | |
740 | ||
741 | static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr, | |
742 | uint32_t value) | |
743 | { | |
744 | struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; | |
745 | int offset = addr - s->base; | |
746 | uint32_t diff; | |
747 | int ln; | |
748 | ||
749 | switch (offset) { | |
750 | case 0x00: /* GPIO_REVISION */ | |
751 | case 0x14: /* GPIO_SYSSTATUS */ | |
752 | case 0x38: /* GPIO_DATAIN */ | |
753 | OMAP_RO_REG(addr); | |
754 | break; | |
755 | ||
756 | case 0x10: /* GPIO_SYSCONFIG */ | |
757 | if (((value >> 3) & 3) == 3) | |
758 | fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__); | |
759 | if (value & 2) | |
760 | omap_gpio_module_reset(s); | |
761 | s->config[0] = value & 0x1d; | |
762 | break; | |
763 | ||
764 | case 0x18: /* GPIO_IRQSTATUS1 */ | |
765 | if (s->ints[0] & value) { | |
766 | s->ints[0] &= ~value; | |
767 | omap_gpio_module_level_update(s, 0); | |
768 | } | |
769 | break; | |
770 | ||
771 | case 0x1c: /* GPIO_IRQENABLE1 */ | |
772 | s->mask[0] = value; | |
773 | omap_gpio_module_int_update(s, 0); | |
774 | break; | |
775 | ||
776 | case 0x20: /* GPIO_WAKEUPENABLE */ | |
777 | s->wumask = value; | |
778 | break; | |
779 | ||
780 | case 0x28: /* GPIO_IRQSTATUS2 */ | |
781 | if (s->ints[1] & value) { | |
782 | s->ints[1] &= ~value; | |
783 | omap_gpio_module_level_update(s, 1); | |
784 | } | |
785 | break; | |
786 | ||
787 | case 0x2c: /* GPIO_IRQENABLE2 */ | |
788 | s->mask[1] = value; | |
789 | omap_gpio_module_int_update(s, 1); | |
790 | break; | |
791 | ||
792 | case 0x30: /* GPIO_CTRL */ | |
793 | s->config[1] = value & 7; | |
794 | break; | |
795 | ||
796 | case 0x34: /* GPIO_OE */ | |
797 | diff = s->outputs & (s->dir ^ value); | |
798 | s->dir = value; | |
799 | ||
800 | value = s->outputs & ~s->dir; | |
801 | while ((ln = ffs(diff))) { | |
802 | diff &= ~(1 <<-- ln); | |
803 | qemu_set_irq(s->handler[ln], (value >> ln) & 1); | |
804 | } | |
805 | ||
806 | omap_gpio_module_level_update(s, 0); | |
807 | omap_gpio_module_level_update(s, 1); | |
808 | break; | |
809 | ||
810 | case 0x3c: /* GPIO_DATAOUT */ | |
811 | omap_gpio_module_out_update(s, s->outputs ^ value); | |
812 | break; | |
813 | ||
814 | case 0x40: /* GPIO_LEVELDETECT0 */ | |
815 | s->level[0] = value; | |
816 | omap_gpio_module_level_update(s, 0); | |
817 | omap_gpio_module_level_update(s, 1); | |
818 | break; | |
819 | ||
820 | case 0x44: /* GPIO_LEVELDETECT1 */ | |
821 | s->level[1] = value; | |
822 | omap_gpio_module_level_update(s, 0); | |
823 | omap_gpio_module_level_update(s, 1); | |
824 | break; | |
825 | ||
826 | case 0x48: /* GPIO_RISINGDETECT */ | |
827 | s->edge[0] = value; | |
828 | break; | |
829 | ||
830 | case 0x4c: /* GPIO_FALLINGDETECT */ | |
831 | s->edge[1] = value; | |
832 | break; | |
833 | ||
834 | case 0x50: /* GPIO_DEBOUNCENABLE */ | |
835 | s->debounce = value; | |
836 | break; | |
837 | ||
838 | case 0x54: /* GPIO_DEBOUNCINGTIME */ | |
839 | s->delay = value; | |
840 | break; | |
841 | ||
842 | case 0x60: /* GPIO_CLEARIRQENABLE1 */ | |
843 | s->mask[0] &= ~value; | |
844 | omap_gpio_module_int_update(s, 0); | |
845 | break; | |
846 | ||
847 | case 0x64: /* GPIO_SETIRQENABLE1 */ | |
848 | s->mask[0] |= value; | |
849 | omap_gpio_module_int_update(s, 0); | |
850 | break; | |
851 | ||
852 | case 0x70: /* GPIO_CLEARIRQENABLE2 */ | |
853 | s->mask[1] &= ~value; | |
854 | omap_gpio_module_int_update(s, 1); | |
855 | break; | |
856 | ||
857 | case 0x74: /* GPIO_SETIREQNEABLE2 */ | |
858 | s->mask[1] |= value; | |
859 | omap_gpio_module_int_update(s, 1); | |
860 | break; | |
861 | ||
862 | case 0x80: /* GPIO_CLEARWKUENA */ | |
863 | s->wumask &= ~value; | |
864 | break; | |
865 | ||
866 | case 0x84: /* GPIO_SETWKUENA */ | |
867 | s->wumask |= value; | |
868 | break; | |
869 | ||
870 | case 0x90: /* GPIO_CLEARDATAOUT */ | |
871 | omap_gpio_module_out_update(s, s->outputs & value); | |
872 | break; | |
873 | ||
874 | case 0x94: /* GPIO_SETDATAOUT */ | |
875 | omap_gpio_module_out_update(s, ~s->outputs & value); | |
876 | break; | |
877 | ||
878 | default: | |
879 | OMAP_BAD_REG(addr); | |
880 | return; | |
881 | } | |
882 | } | |
883 | ||
884 | static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr) | |
885 | { | |
886 | return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3); | |
887 | } | |
888 | ||
889 | static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr, | |
890 | uint32_t value) | |
891 | { | |
892 | struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; | |
893 | int offset = addr - s->base; | |
894 | uint32_t cur = 0; | |
895 | uint32_t mask = 0xffff; | |
896 | ||
897 | switch (offset & ~3) { | |
898 | case 0x00: /* GPIO_REVISION */ | |
899 | case 0x14: /* GPIO_SYSSTATUS */ | |
900 | case 0x38: /* GPIO_DATAIN */ | |
901 | OMAP_RO_REG(addr); | |
902 | break; | |
903 | ||
904 | case 0x10: /* GPIO_SYSCONFIG */ | |
905 | case 0x1c: /* GPIO_IRQENABLE1 */ | |
906 | case 0x20: /* GPIO_WAKEUPENABLE */ | |
907 | case 0x2c: /* GPIO_IRQENABLE2 */ | |
908 | case 0x30: /* GPIO_CTRL */ | |
909 | case 0x34: /* GPIO_OE */ | |
910 | case 0x3c: /* GPIO_DATAOUT */ | |
911 | case 0x40: /* GPIO_LEVELDETECT0 */ | |
912 | case 0x44: /* GPIO_LEVELDETECT1 */ | |
913 | case 0x48: /* GPIO_RISINGDETECT */ | |
914 | case 0x4c: /* GPIO_FALLINGDETECT */ | |
915 | case 0x50: /* GPIO_DEBOUNCENABLE */ | |
916 | case 0x54: /* GPIO_DEBOUNCINGTIME */ | |
917 | cur = omap_gpio_module_read(opaque, addr & ~3) & | |
918 | ~(mask << ((addr & 3) << 3)); | |
919 | ||
920 | /* Fall through. */ | |
921 | case 0x18: /* GPIO_IRQSTATUS1 */ | |
922 | case 0x28: /* GPIO_IRQSTATUS2 */ | |
923 | case 0x60: /* GPIO_CLEARIRQENABLE1 */ | |
924 | case 0x64: /* GPIO_SETIRQENABLE1 */ | |
925 | case 0x70: /* GPIO_CLEARIRQENABLE2 */ | |
926 | case 0x74: /* GPIO_SETIREQNEABLE2 */ | |
927 | case 0x80: /* GPIO_CLEARWKUENA */ | |
928 | case 0x84: /* GPIO_SETWKUENA */ | |
929 | case 0x90: /* GPIO_CLEARDATAOUT */ | |
930 | case 0x94: /* GPIO_SETDATAOUT */ | |
931 | value <<= (addr & 3) << 3; | |
932 | omap_gpio_module_write(opaque, addr, cur | value); | |
933 | break; | |
934 | ||
935 | default: | |
936 | OMAP_BAD_REG(addr); | |
937 | return; | |
938 | } | |
939 | } | |
940 | ||
941 | static CPUReadMemoryFunc *omap_gpio_module_readfn[] = { | |
942 | omap_gpio_module_readp, | |
943 | omap_gpio_module_readp, | |
944 | omap_gpio_module_read, | |
945 | }; | |
946 | ||
947 | static CPUWriteMemoryFunc *omap_gpio_module_writefn[] = { | |
948 | omap_gpio_module_writep, | |
949 | omap_gpio_module_writep, | |
950 | omap_gpio_module_write, | |
951 | }; | |
952 | ||
953 | static void omap_gpio_module_init(struct omap2_gpio_s *s, | |
954 | struct omap_target_agent_s *ta, int region, | |
955 | qemu_irq mpu, qemu_irq dsp, qemu_irq wkup, | |
956 | omap_clk fclk, omap_clk iclk) | |
957 | { | |
958 | int iomemtype; | |
959 | ||
960 | s->irq[0] = mpu; | |
961 | s->irq[1] = dsp; | |
962 | s->wkup = wkup; | |
963 | s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32); | |
964 | ||
c66fb5bc | 965 | iomemtype = l4_register_io_memory(0, omap_gpio_module_readfn, |
827df9f3 AZ |
966 | omap_gpio_module_writefn, s); |
967 | s->base = omap_l4_attach(ta, region, iomemtype); | |
968 | } | |
969 | ||
970 | struct omap_gpif_s { | |
971 | struct omap2_gpio_s module[5]; | |
972 | int modules; | |
973 | ||
974 | target_phys_addr_t topbase; | |
975 | int autoidle; | |
976 | int gpo; | |
977 | }; | |
978 | ||
979 | static void omap_gpif_reset(struct omap_gpif_s *s) | |
980 | { | |
981 | int i; | |
982 | ||
983 | for (i = 0; i < s->modules; i ++) | |
984 | omap_gpio_module_reset(s->module + i); | |
985 | ||
986 | s->autoidle = 0; | |
987 | s->gpo = 0; | |
988 | } | |
989 | ||
990 | static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr) | |
991 | { | |
992 | struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; | |
993 | int offset = addr - s->topbase; | |
994 | ||
995 | switch (offset) { | |
996 | case 0x00: /* IPGENERICOCPSPL_REVISION */ | |
997 | return 0x18; | |
998 | ||
999 | case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ | |
1000 | return s->autoidle; | |
1001 | ||
1002 | case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ | |
1003 | return 0x01; | |
1004 | ||
1005 | case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ | |
1006 | return 0x00; | |
1007 | ||
1008 | case 0x40: /* IPGENERICOCPSPL_GPO */ | |
1009 | return s->gpo; | |
1010 | ||
1011 | case 0x50: /* IPGENERICOCPSPL_GPI */ | |
1012 | return 0x00; | |
1013 | } | |
1014 | ||
1015 | OMAP_BAD_REG(addr); | |
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr, | |
1020 | uint32_t value) | |
1021 | { | |
1022 | struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; | |
1023 | int offset = addr - s->topbase; | |
1024 | ||
1025 | switch (offset) { | |
1026 | case 0x00: /* IPGENERICOCPSPL_REVISION */ | |
1027 | case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ | |
1028 | case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ | |
1029 | case 0x50: /* IPGENERICOCPSPL_GPI */ | |
1030 | OMAP_RO_REG(addr); | |
1031 | break; | |
1032 | ||
1033 | case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ | |
1034 | if (value & (1 << 1)) /* SOFTRESET */ | |
1035 | omap_gpif_reset(s); | |
1036 | s->autoidle = value & 1; | |
1037 | break; | |
1038 | ||
1039 | case 0x40: /* IPGENERICOCPSPL_GPO */ | |
1040 | s->gpo = value & 1; | |
1041 | break; | |
1042 | ||
1043 | default: | |
1044 | OMAP_BAD_REG(addr); | |
1045 | return; | |
1046 | } | |
1047 | } | |
1048 | ||
1049 | static CPUReadMemoryFunc *omap_gpif_top_readfn[] = { | |
1050 | omap_gpif_top_read, | |
1051 | omap_gpif_top_read, | |
1052 | omap_gpif_top_read, | |
1053 | }; | |
1054 | ||
1055 | static CPUWriteMemoryFunc *omap_gpif_top_writefn[] = { | |
1056 | omap_gpif_top_write, | |
1057 | omap_gpif_top_write, | |
1058 | omap_gpif_top_write, | |
1059 | }; | |
1060 | ||
1061 | struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta, | |
1062 | qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules) | |
1063 | { | |
1064 | int iomemtype, i; | |
1065 | struct omap_gpif_s *s = (struct omap_gpif_s *) | |
1066 | qemu_mallocz(sizeof(struct omap_gpif_s)); | |
1067 | int region[4] = { 0, 2, 4, 5 }; | |
1068 | ||
1069 | s->modules = modules; | |
1070 | for (i = 0; i < modules; i ++) | |
1071 | omap_gpio_module_init(s->module + i, ta, region[i], | |
1072 | irq[i], 0, 0, fclk[i], iclk); | |
1073 | ||
1074 | omap_gpif_reset(s); | |
1075 | ||
c66fb5bc | 1076 | iomemtype = l4_register_io_memory(0, omap_gpif_top_readfn, |
827df9f3 AZ |
1077 | omap_gpif_top_writefn, s); |
1078 | s->topbase = omap_l4_attach(ta, 1, iomemtype); | |
1079 | ||
1080 | return s; | |
1081 | } | |
1082 | ||
1083 | qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start) | |
1084 | { | |
1085 | if (start >= s->modules * 32 || start < 0) | |
1086 | cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", | |
1087 | __FUNCTION__, start); | |
1088 | return s->module[start >> 5].in + (start & 31); | |
1089 | } | |
1090 | ||
1091 | void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler) | |
1092 | { | |
1093 | if (line >= s->modules * 32 || line < 0) | |
1094 | cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line); | |
1095 | s->module[line >> 5].handler[line & 31] = handler; | |
1096 | } | |
1097 | ||
1098 | /* Multichannel SPI */ | |
1099 | struct omap_mcspi_s { | |
1100 | target_phys_addr_t base; | |
1101 | qemu_irq irq; | |
1102 | int chnum; | |
1103 | ||
1104 | uint32_t sysconfig; | |
1105 | uint32_t systest; | |
1106 | uint32_t irqst; | |
1107 | uint32_t irqen; | |
1108 | uint32_t wken; | |
1109 | uint32_t control; | |
1110 | ||
1111 | struct omap_mcspi_ch_s { | |
1112 | qemu_irq txdrq; | |
1113 | qemu_irq rxdrq; | |
e927bb00 | 1114 | uint32_t (*txrx)(void *opaque, uint32_t, int); |
827df9f3 AZ |
1115 | void *opaque; |
1116 | ||
1117 | uint32_t tx; | |
1118 | uint32_t rx; | |
1119 | ||
1120 | uint32_t config; | |
1121 | uint32_t status; | |
1122 | uint32_t control; | |
1123 | } ch[4]; | |
1124 | }; | |
1125 | ||
1126 | static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s) | |
1127 | { | |
1128 | qemu_set_irq(s->irq, s->irqst & s->irqen); | |
1129 | } | |
1130 | ||
1131 | static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch) | |
1132 | { | |
1133 | qemu_set_irq(ch->txdrq, | |
1134 | (ch->control & 1) && /* EN */ | |
1135 | (ch->config & (1 << 14)) && /* DMAW */ | |
1136 | (ch->status & (1 << 1)) && /* TXS */ | |
1137 | ((ch->config >> 12) & 3) != 1); /* TRM */ | |
1138 | qemu_set_irq(ch->rxdrq, | |
1139 | (ch->control & 1) && /* EN */ | |
1140 | (ch->config & (1 << 15)) && /* DMAW */ | |
1141 | (ch->status & (1 << 0)) && /* RXS */ | |
1142 | ((ch->config >> 12) & 3) != 2); /* TRM */ | |
1143 | } | |
1144 | ||
1145 | static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum) | |
1146 | { | |
1147 | struct omap_mcspi_ch_s *ch = s->ch + chnum; | |
1148 | ||
1149 | if (!(ch->control & 1)) /* EN */ | |
1150 | return; | |
1151 | if ((ch->status & (1 << 0)) && /* RXS */ | |
1152 | ((ch->config >> 12) & 3) != 2 && /* TRM */ | |
1153 | !(ch->config & (1 << 19))) /* TURBO */ | |
1154 | goto intr_update; | |
1155 | if ((ch->status & (1 << 1)) && /* TXS */ | |
1156 | ((ch->config >> 12) & 3) != 1) /* TRM */ | |
1157 | goto intr_update; | |
1158 | ||
1159 | if (!(s->control & 1) || /* SINGLE */ | |
1160 | (ch->config & (1 << 20))) { /* FORCE */ | |
1161 | if (ch->txrx) | |
e927bb00 AZ |
1162 | ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */ |
1163 | 1 + (0x1f & (ch->config >> 7))); | |
827df9f3 AZ |
1164 | } |
1165 | ||
1166 | ch->tx = 0; | |
1167 | ch->status |= 1 << 2; /* EOT */ | |
1168 | ch->status |= 1 << 1; /* TXS */ | |
1169 | if (((ch->config >> 12) & 3) != 2) /* TRM */ | |
1170 | ch->status |= 1 << 0; /* RXS */ | |
1171 | ||
1172 | intr_update: | |
1173 | if ((ch->status & (1 << 0)) && /* RXS */ | |
1174 | ((ch->config >> 12) & 3) != 2 && /* TRM */ | |
1175 | !(ch->config & (1 << 19))) /* TURBO */ | |
1176 | s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */ | |
1177 | if ((ch->status & (1 << 1)) && /* TXS */ | |
1178 | ((ch->config >> 12) & 3) != 1) /* TRM */ | |
1179 | s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */ | |
1180 | omap_mcspi_interrupt_update(s); | |
1181 | omap_mcspi_dmarequest_update(ch); | |
1182 | } | |
1183 | ||
1184 | static void omap_mcspi_reset(struct omap_mcspi_s *s) | |
1185 | { | |
1186 | int ch; | |
1187 | ||
1188 | s->sysconfig = 0; | |
1189 | s->systest = 0; | |
1190 | s->irqst = 0; | |
1191 | s->irqen = 0; | |
1192 | s->wken = 0; | |
1193 | s->control = 4; | |
1194 | ||
1195 | for (ch = 0; ch < 4; ch ++) { | |
1196 | s->ch[ch].config = 0x060000; | |
1197 | s->ch[ch].status = 2; /* TXS */ | |
1198 | s->ch[ch].control = 0; | |
1199 | ||
1200 | omap_mcspi_dmarequest_update(s->ch + ch); | |
1201 | } | |
1202 | ||
1203 | omap_mcspi_interrupt_update(s); | |
1204 | } | |
1205 | ||
1206 | static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr) | |
1207 | { | |
1208 | struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; | |
1209 | int offset = addr - s->base; | |
1210 | int ch = 0; | |
1211 | uint32_t ret; | |
1212 | ||
1213 | switch (offset) { | |
1214 | case 0x00: /* MCSPI_REVISION */ | |
1215 | return 0x91; | |
1216 | ||
1217 | case 0x10: /* MCSPI_SYSCONFIG */ | |
1218 | return s->sysconfig; | |
1219 | ||
1220 | case 0x14: /* MCSPI_SYSSTATUS */ | |
1221 | return 1; /* RESETDONE */ | |
1222 | ||
1223 | case 0x18: /* MCSPI_IRQSTATUS */ | |
1224 | return s->irqst; | |
1225 | ||
1226 | case 0x1c: /* MCSPI_IRQENABLE */ | |
1227 | return s->irqen; | |
1228 | ||
1229 | case 0x20: /* MCSPI_WAKEUPENABLE */ | |
1230 | return s->wken; | |
1231 | ||
1232 | case 0x24: /* MCSPI_SYST */ | |
1233 | return s->systest; | |
1234 | ||
1235 | case 0x28: /* MCSPI_MODULCTRL */ | |
1236 | return s->control; | |
1237 | ||
1238 | case 0x68: ch ++; | |
1239 | case 0x54: ch ++; | |
1240 | case 0x40: ch ++; | |
1241 | case 0x2c: /* MCSPI_CHCONF */ | |
1242 | return s->ch[ch].config; | |
1243 | ||
1244 | case 0x6c: ch ++; | |
1245 | case 0x58: ch ++; | |
1246 | case 0x44: ch ++; | |
1247 | case 0x30: /* MCSPI_CHSTAT */ | |
1248 | return s->ch[ch].status; | |
1249 | ||
1250 | case 0x70: ch ++; | |
1251 | case 0x5c: ch ++; | |
1252 | case 0x48: ch ++; | |
1253 | case 0x34: /* MCSPI_CHCTRL */ | |
1254 | return s->ch[ch].control; | |
1255 | ||
1256 | case 0x74: ch ++; | |
1257 | case 0x60: ch ++; | |
1258 | case 0x4c: ch ++; | |
1259 | case 0x38: /* MCSPI_TX */ | |
1260 | return s->ch[ch].tx; | |
1261 | ||
1262 | case 0x78: ch ++; | |
1263 | case 0x64: ch ++; | |
1264 | case 0x50: ch ++; | |
1265 | case 0x3c: /* MCSPI_RX */ | |
1266 | s->ch[ch].status &= ~(1 << 0); /* RXS */ | |
1267 | ret = s->ch[ch].rx; | |
1268 | omap_mcspi_transfer_run(s, ch); | |
1269 | return ret; | |
1270 | } | |
1271 | ||
1272 | OMAP_BAD_REG(addr); | |
1273 | return 0; | |
1274 | } | |
1275 | ||
1276 | static void omap_mcspi_write(void *opaque, target_phys_addr_t addr, | |
1277 | uint32_t value) | |
1278 | { | |
1279 | struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; | |
1280 | int offset = addr - s->base; | |
1281 | int ch = 0; | |
1282 | ||
1283 | switch (offset) { | |
1284 | case 0x00: /* MCSPI_REVISION */ | |
1285 | case 0x14: /* MCSPI_SYSSTATUS */ | |
1286 | case 0x30: /* MCSPI_CHSTAT0 */ | |
1287 | case 0x3c: /* MCSPI_RX0 */ | |
1288 | case 0x44: /* MCSPI_CHSTAT1 */ | |
1289 | case 0x50: /* MCSPI_RX1 */ | |
1290 | case 0x58: /* MCSPI_CHSTAT2 */ | |
1291 | case 0x64: /* MCSPI_RX2 */ | |
1292 | case 0x6c: /* MCSPI_CHSTAT3 */ | |
1293 | case 0x78: /* MCSPI_RX3 */ | |
1294 | OMAP_RO_REG(addr); | |
1295 | return; | |
1296 | ||
1297 | case 0x10: /* MCSPI_SYSCONFIG */ | |
1298 | if (value & (1 << 1)) /* SOFTRESET */ | |
1299 | omap_mcspi_reset(s); | |
1300 | s->sysconfig = value & 0x31d; | |
1301 | break; | |
1302 | ||
1303 | case 0x18: /* MCSPI_IRQSTATUS */ | |
1304 | if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) { | |
1305 | s->irqst &= ~value; | |
1306 | omap_mcspi_interrupt_update(s); | |
1307 | } | |
1308 | break; | |
1309 | ||
1310 | case 0x1c: /* MCSPI_IRQENABLE */ | |
1311 | s->irqen = value & 0x1777f; | |
1312 | omap_mcspi_interrupt_update(s); | |
1313 | break; | |
1314 | ||
1315 | case 0x20: /* MCSPI_WAKEUPENABLE */ | |
1316 | s->wken = value & 1; | |
1317 | break; | |
1318 | ||
1319 | case 0x24: /* MCSPI_SYST */ | |
1320 | if (s->control & (1 << 3)) /* SYSTEM_TEST */ | |
1321 | if (value & (1 << 11)) { /* SSB */ | |
1322 | s->irqst |= 0x1777f; | |
1323 | omap_mcspi_interrupt_update(s); | |
1324 | } | |
1325 | s->systest = value & 0xfff; | |
1326 | break; | |
1327 | ||
1328 | case 0x28: /* MCSPI_MODULCTRL */ | |
1329 | if (value & (1 << 3)) /* SYSTEM_TEST */ | |
1330 | if (s->systest & (1 << 11)) { /* SSB */ | |
1331 | s->irqst |= 0x1777f; | |
1332 | omap_mcspi_interrupt_update(s); | |
1333 | } | |
1334 | s->control = value & 0xf; | |
1335 | break; | |
1336 | ||
1337 | case 0x68: ch ++; | |
1338 | case 0x54: ch ++; | |
1339 | case 0x40: ch ++; | |
1340 | case 0x2c: /* MCSPI_CHCONF */ | |
1341 | if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */ | |
1342 | omap_mcspi_dmarequest_update(s->ch + ch); | |
1343 | if (((value >> 12) & 3) == 3) /* TRM */ | |
1344 | fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__); | |
1345 | if (((value >> 7) & 0x1f) < 3) /* WL */ | |
1346 | fprintf(stderr, "%s: invalid WL value (%i)\n", | |
1347 | __FUNCTION__, (value >> 7) & 0x1f); | |
1348 | s->ch[ch].config = value & 0x7fffff; | |
1349 | break; | |
1350 | ||
1351 | case 0x70: ch ++; | |
1352 | case 0x5c: ch ++; | |
1353 | case 0x48: ch ++; | |
1354 | case 0x34: /* MCSPI_CHCTRL */ | |
1355 | if (value & ~s->ch[ch].control & 1) { /* EN */ | |
1356 | s->ch[ch].control |= 1; | |
1357 | omap_mcspi_transfer_run(s, ch); | |
1358 | } else | |
1359 | s->ch[ch].control = value & 1; | |
1360 | break; | |
1361 | ||
1362 | case 0x74: ch ++; | |
1363 | case 0x60: ch ++; | |
1364 | case 0x4c: ch ++; | |
1365 | case 0x38: /* MCSPI_TX */ | |
1366 | s->ch[ch].tx = value; | |
1367 | s->ch[ch].status &= ~(1 << 1); /* TXS */ | |
1368 | omap_mcspi_transfer_run(s, ch); | |
1369 | break; | |
1370 | ||
1371 | default: | |
1372 | OMAP_BAD_REG(addr); | |
1373 | return; | |
1374 | } | |
1375 | } | |
1376 | ||
1377 | static CPUReadMemoryFunc *omap_mcspi_readfn[] = { | |
1378 | omap_badwidth_read32, | |
1379 | omap_badwidth_read32, | |
1380 | omap_mcspi_read, | |
1381 | }; | |
1382 | ||
1383 | static CPUWriteMemoryFunc *omap_mcspi_writefn[] = { | |
1384 | omap_badwidth_write32, | |
1385 | omap_badwidth_write32, | |
1386 | omap_mcspi_write, | |
1387 | }; | |
1388 | ||
1389 | struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, | |
1390 | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) | |
1391 | { | |
1392 | int iomemtype; | |
1393 | struct omap_mcspi_s *s = (struct omap_mcspi_s *) | |
1394 | qemu_mallocz(sizeof(struct omap_mcspi_s)); | |
1395 | struct omap_mcspi_ch_s *ch = s->ch; | |
1396 | ||
1397 | s->irq = irq; | |
1398 | s->chnum = chnum; | |
1399 | while (chnum --) { | |
1400 | ch->txdrq = *drq ++; | |
1401 | ch->rxdrq = *drq ++; | |
1402 | ch ++; | |
1403 | } | |
1404 | omap_mcspi_reset(s); | |
1405 | ||
c66fb5bc | 1406 | iomemtype = l4_register_io_memory(0, omap_mcspi_readfn, |
827df9f3 AZ |
1407 | omap_mcspi_writefn, s); |
1408 | s->base = omap_l4_attach(ta, 0, iomemtype); | |
1409 | ||
1410 | return s; | |
1411 | } | |
1412 | ||
1413 | void omap_mcspi_attach(struct omap_mcspi_s *s, | |
e927bb00 | 1414 | uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, |
827df9f3 AZ |
1415 | int chipselect) |
1416 | { | |
1417 | if (chipselect < 0 || chipselect >= s->chnum) | |
1418 | cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n", | |
1419 | __FUNCTION__, chipselect); | |
1420 | ||
1421 | s->ch[chipselect].txrx = txrx; | |
1422 | s->ch[chipselect].opaque = opaque; | |
1423 | } | |
1424 | ||
99570a40 AZ |
1425 | /* Enhanced Audio Controller (CODEC only) */ |
1426 | struct omap_eac_s { | |
1427 | target_phys_addr_t base; | |
1428 | qemu_irq irq; | |
1429 | ||
1430 | uint16_t sysconfig; | |
1431 | uint8_t config[4]; | |
1432 | uint8_t control; | |
1433 | uint8_t address; | |
1434 | uint16_t data; | |
1435 | uint8_t vtol; | |
1436 | uint8_t vtsl; | |
1437 | uint16_t mixer; | |
1438 | uint16_t gain[4]; | |
1439 | uint8_t att; | |
1440 | uint16_t max[7]; | |
1441 | ||
1442 | struct { | |
1443 | qemu_irq txdrq; | |
1444 | qemu_irq rxdrq; | |
1445 | uint32_t (*txrx)(void *opaque, uint32_t, int); | |
1446 | void *opaque; | |
1447 | ||
1448 | #define EAC_BUF_LEN 1024 | |
1449 | uint32_t rxbuf[EAC_BUF_LEN]; | |
1450 | int rxlen; | |
1451 | int rxavail; | |
1452 | uint32_t txbuf[EAC_BUF_LEN]; | |
1453 | int txlen; | |
1454 | int txavail; | |
1455 | ||
1456 | int enable; | |
1457 | int rate; | |
1458 | ||
1459 | uint16_t config[4]; | |
1460 | ||
1461 | /* These need to be moved to the actual codec */ | |
1462 | QEMUSoundCard card; | |
1463 | SWVoiceIn *in_voice; | |
1464 | SWVoiceOut *out_voice; | |
1465 | int hw_enable; | |
1466 | } codec; | |
1467 | ||
1468 | struct { | |
1469 | uint8_t control; | |
1470 | uint16_t config; | |
1471 | } modem, bt; | |
1472 | }; | |
1473 | ||
1474 | static inline void omap_eac_interrupt_update(struct omap_eac_s *s) | |
1475 | { | |
1476 | qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */ | |
1477 | } | |
1478 | ||
1479 | static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s) | |
1480 | { | |
1481 | qemu_set_irq(s->codec.rxdrq, s->codec.rxavail + s->codec.rxlen && | |
1482 | ((s->codec.config[1] >> 12) & 1)); /* DMAREN */ | |
1483 | } | |
1484 | ||
1485 | static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s) | |
1486 | { | |
1487 | qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail && | |
1488 | ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */ | |
1489 | } | |
1490 | ||
1491 | static inline void omap_eac_in_refill(struct omap_eac_s *s) | |
1492 | { | |
1493 | int left, start = 0; | |
1494 | ||
1495 | s->codec.rxlen = MIN(s->codec.rxavail, EAC_BUF_LEN); | |
1496 | s->codec.rxavail -= s->codec.rxlen; | |
1497 | ||
1498 | for (left = s->codec.rxlen << 2; left; start = (EAC_BUF_LEN << 2) - left) | |
1499 | left -= AUD_read(s->codec.in_voice, | |
1500 | (uint8_t *) s->codec.rxbuf + start, left); | |
1501 | } | |
1502 | ||
1503 | static inline void omap_eac_out_empty(struct omap_eac_s *s) | |
1504 | { | |
1505 | int left, start = 0; | |
1506 | ||
1507 | for (left = s->codec.txlen << 2; left; start = (s->codec.txlen << 2) - left) | |
1508 | left -= AUD_write(s->codec.out_voice, | |
1509 | (uint8_t *) s->codec.txbuf + start, left); | |
1510 | ||
1511 | s->codec.txavail -= s->codec.txlen; | |
1512 | s->codec.txlen = 0; | |
1513 | } | |
1514 | ||
1515 | static void omap_eac_in_cb(void *opaque, int avail_b) | |
1516 | { | |
1517 | struct omap_eac_s *s = (struct omap_eac_s *) opaque; | |
1518 | ||
1519 | s->codec.rxavail = avail_b >> 2; | |
1520 | omap_eac_in_dmarequest_update(s); | |
1521 | /* TODO: possibly discard current buffer if overrun */ | |
1522 | } | |
1523 | ||
1524 | static void omap_eac_out_cb(void *opaque, int free_b) | |
1525 | { | |
1526 | struct omap_eac_s *s = (struct omap_eac_s *) opaque; | |
1527 | ||
1528 | s->codec.txavail = free_b >> 2; | |
1529 | if (s->codec.txlen > s->codec.txavail) | |
1530 | s->codec.txlen = s->codec.txavail; | |
1531 | omap_eac_out_empty(s); | |
1532 | omap_eac_out_dmarequest_update(s); | |
1533 | } | |
1534 | ||
1535 | static void omap_eac_enable_update(struct omap_eac_s *s) | |
1536 | { | |
1537 | s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */ | |
1538 | (s->codec.config[1] & 2) && /* AUDEN */ | |
1539 | s->codec.hw_enable; | |
1540 | } | |
1541 | ||
1542 | static const int omap_eac_fsint[4] = { | |
1543 | 8000, | |
1544 | 11025, | |
1545 | 22050, | |
1546 | 44100, | |
1547 | }; | |
1548 | ||
1549 | static const int omap_eac_fsint2[8] = { | |
1550 | 8000, | |
1551 | 11025, | |
1552 | 22050, | |
1553 | 44100, | |
1554 | 48000, | |
1555 | 0, 0, 0, | |
1556 | }; | |
1557 | ||
1558 | static const int omap_eac_fsint3[16] = { | |
1559 | 8000, | |
1560 | 11025, | |
1561 | 16000, | |
1562 | 22050, | |
1563 | 24000, | |
1564 | 32000, | |
1565 | 44100, | |
1566 | 48000, | |
1567 | 0, 0, 0, 0, 0, 0, 0, 0, | |
1568 | }; | |
1569 | ||
1570 | static void omap_eac_rate_update(struct omap_eac_s *s) | |
1571 | { | |
1572 | int fsint[3]; | |
1573 | ||
1574 | fsint[2] = (s->codec.config[3] >> 9) & 0xf; | |
1575 | fsint[1] = (s->codec.config[2] >> 0) & 0x7; | |
1576 | fsint[0] = (s->codec.config[0] >> 6) & 0x3; | |
1577 | if (fsint[2] < 0xf) | |
1578 | s->codec.rate = omap_eac_fsint3[fsint[2]]; | |
1579 | else if (fsint[1] < 0x7) | |
1580 | s->codec.rate = omap_eac_fsint2[fsint[1]]; | |
1581 | else | |
1582 | s->codec.rate = omap_eac_fsint[fsint[0]]; | |
1583 | } | |
1584 | ||
1585 | static void omap_eac_volume_update(struct omap_eac_s *s) | |
1586 | { | |
1587 | /* TODO */ | |
1588 | } | |
1589 | ||
1590 | static void omap_eac_format_update(struct omap_eac_s *s) | |
1591 | { | |
1592 | audsettings_t fmt; | |
1593 | ||
1594 | omap_eac_out_empty(s); | |
1595 | ||
1596 | if (s->codec.in_voice) { | |
1597 | AUD_set_active_in(s->codec.in_voice, 0); | |
1598 | AUD_close_in(&s->codec.card, s->codec.in_voice); | |
1599 | s->codec.in_voice = 0; | |
1600 | } | |
1601 | if (s->codec.out_voice) { | |
1602 | AUD_set_active_out(s->codec.out_voice, 0); | |
1603 | AUD_close_out(&s->codec.card, s->codec.out_voice); | |
1604 | s->codec.out_voice = 0; | |
1605 | } | |
1606 | ||
1607 | omap_eac_enable_update(s); | |
1608 | if (!s->codec.enable) | |
1609 | return; | |
1610 | ||
1611 | omap_eac_rate_update(s); | |
1612 | fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */ | |
1613 | fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */ | |
1614 | fmt.freq = s->codec.rate; | |
1615 | /* TODO: signedness possibly depends on the CODEC hardware - or | |
1616 | * does I2S specify it? */ | |
1617 | /* All register writes are 16 bits so we we store 16-bit samples | |
1618 | * in the buffers regardless of AGCFR[B8_16] value. */ | |
1619 | fmt.fmt = AUD_FMT_U16; | |
1620 | ||
1621 | s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice, | |
1622 | "eac.codec.in", s, omap_eac_in_cb, &fmt); | |
1623 | s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice, | |
1624 | "eac.codec.out", s, omap_eac_out_cb, &fmt); | |
1625 | ||
1626 | omap_eac_volume_update(s); | |
1627 | ||
1628 | AUD_set_active_in(s->codec.in_voice, 1); | |
1629 | AUD_set_active_out(s->codec.out_voice, 1); | |
1630 | } | |
1631 | ||
1632 | static void omap_eac_reset(struct omap_eac_s *s) | |
1633 | { | |
1634 | s->sysconfig = 0; | |
1635 | s->config[0] = 0x0c; | |
1636 | s->config[1] = 0x09; | |
1637 | s->config[2] = 0xab; | |
1638 | s->config[3] = 0x03; | |
1639 | s->control = 0x00; | |
1640 | s->address = 0x00; | |
1641 | s->data = 0x0000; | |
1642 | s->vtol = 0x00; | |
1643 | s->vtsl = 0x00; | |
1644 | s->mixer = 0x0000; | |
1645 | s->gain[0] = 0xe7e7; | |
1646 | s->gain[1] = 0x6767; | |
1647 | s->gain[2] = 0x6767; | |
1648 | s->gain[3] = 0x6767; | |
1649 | s->att = 0xce; | |
1650 | s->max[0] = 0; | |
1651 | s->max[1] = 0; | |
1652 | s->max[2] = 0; | |
1653 | s->max[3] = 0; | |
1654 | s->max[4] = 0; | |
1655 | s->max[5] = 0; | |
1656 | s->max[6] = 0; | |
1657 | ||
1658 | s->modem.control = 0x00; | |
1659 | s->modem.config = 0x0000; | |
1660 | s->bt.control = 0x00; | |
1661 | s->bt.config = 0x0000; | |
1662 | s->codec.config[0] = 0x0649; | |
1663 | s->codec.config[1] = 0x0000; | |
1664 | s->codec.config[2] = 0x0007; | |
1665 | s->codec.config[3] = 0x1ffc; | |
1666 | s->codec.rxlen = 0; | |
1667 | s->codec.txlen = 0; | |
1668 | s->codec.rxavail = 0; | |
1669 | s->codec.txavail = 0; | |
1670 | ||
1671 | omap_eac_format_update(s); | |
1672 | omap_eac_interrupt_update(s); | |
1673 | } | |
1674 | ||
1675 | static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr) | |
1676 | { | |
1677 | struct omap_eac_s *s = (struct omap_eac_s *) opaque; | |
1678 | int offset = addr - s->base; | |
1679 | ||
1680 | switch (offset) { | |
1681 | case 0x000: /* CPCFR1 */ | |
1682 | return s->config[0]; | |
1683 | case 0x004: /* CPCFR2 */ | |
1684 | return s->config[1]; | |
1685 | case 0x008: /* CPCFR3 */ | |
1686 | return s->config[2]; | |
1687 | case 0x00c: /* CPCFR4 */ | |
1688 | return s->config[3]; | |
1689 | ||
1690 | case 0x010: /* CPTCTL */ | |
1691 | return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) | | |
1692 | ((s->codec.txlen < s->codec.txavail) << 5); | |
1693 | ||
1694 | case 0x014: /* CPTTADR */ | |
1695 | return s->address; | |
1696 | case 0x018: /* CPTDATL */ | |
1697 | return s->data & 0xff; | |
1698 | case 0x01c: /* CPTDATH */ | |
1699 | return s->data >> 8; | |
1700 | case 0x020: /* CPTVSLL */ | |
1701 | return s->vtol; | |
1702 | case 0x024: /* CPTVSLH */ | |
1703 | return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */ | |
1704 | case 0x040: /* MPCTR */ | |
1705 | return s->modem.control; | |
1706 | case 0x044: /* MPMCCFR */ | |
1707 | return s->modem.config; | |
1708 | case 0x060: /* BPCTR */ | |
1709 | return s->bt.control; | |
1710 | case 0x064: /* BPMCCFR */ | |
1711 | return s->bt.config; | |
1712 | case 0x080: /* AMSCFR */ | |
1713 | return s->mixer; | |
1714 | case 0x084: /* AMVCTR */ | |
1715 | return s->gain[0]; | |
1716 | case 0x088: /* AM1VCTR */ | |
1717 | return s->gain[1]; | |
1718 | case 0x08c: /* AM2VCTR */ | |
1719 | return s->gain[2]; | |
1720 | case 0x090: /* AM3VCTR */ | |
1721 | return s->gain[3]; | |
1722 | case 0x094: /* ASTCTR */ | |
1723 | return s->att; | |
1724 | case 0x098: /* APD1LCR */ | |
1725 | return s->max[0]; | |
1726 | case 0x09c: /* APD1RCR */ | |
1727 | return s->max[1]; | |
1728 | case 0x0a0: /* APD2LCR */ | |
1729 | return s->max[2]; | |
1730 | case 0x0a4: /* APD2RCR */ | |
1731 | return s->max[3]; | |
1732 | case 0x0a8: /* APD3LCR */ | |
1733 | return s->max[4]; | |
1734 | case 0x0ac: /* APD3RCR */ | |
1735 | return s->max[5]; | |
1736 | case 0x0b0: /* APD4R */ | |
1737 | return s->max[6]; | |
1738 | case 0x0b4: /* ADWR */ | |
1739 | /* This should be write-only? Docs list it as read-only. */ | |
1740 | return 0x0000; | |
1741 | case 0x0b8: /* ADRDR */ | |
1742 | if (likely(s->codec.rxlen > 1)) | |
1743 | return s->codec.rxbuf[EAC_BUF_LEN - s->codec.rxlen --]; | |
1744 | else if (s->codec.rxlen) { | |
1745 | if (s->codec.rxavail) | |
1746 | omap_eac_in_refill(s); | |
1747 | else { | |
1748 | s->codec.rxlen = 0; | |
1749 | omap_eac_in_dmarequest_update(s); | |
1750 | } | |
1751 | return s->codec.rxbuf[EAC_BUF_LEN - 1]; | |
1752 | } | |
1753 | return 0x0000; | |
1754 | case 0x0bc: /* AGCFR */ | |
1755 | return s->codec.config[0]; | |
1756 | case 0x0c0: /* AGCTR */ | |
1757 | return s->codec.config[1] | ((s->codec.config[1] & 2) << 14); | |
1758 | case 0x0c4: /* AGCFR2 */ | |
1759 | return s->codec.config[2]; | |
1760 | case 0x0c8: /* AGCFR3 */ | |
1761 | return s->codec.config[3]; | |
1762 | case 0x0cc: /* MBPDMACTR */ | |
1763 | case 0x0d0: /* MPDDMARR */ | |
1764 | case 0x0d8: /* MPUDMARR */ | |
1765 | case 0x0e4: /* BPDDMARR */ | |
1766 | case 0x0ec: /* BPUDMARR */ | |
1767 | return 0x0000; | |
1768 | ||
1769 | case 0x100: /* VERSION_NUMBER */ | |
1770 | return 0x0010; | |
1771 | ||
1772 | case 0x104: /* SYSCONFIG */ | |
1773 | return s->sysconfig; | |
1774 | ||
1775 | case 0x108: /* SYSSTATUS */ | |
1776 | return 1 | 0xe; /* RESETDONE | stuff */ | |
1777 | } | |
1778 | ||
1779 | OMAP_BAD_REG(addr); | |
1780 | return 0; | |
1781 | } | |
1782 | ||
1783 | static void omap_eac_write(void *opaque, target_phys_addr_t addr, | |
1784 | uint32_t value) | |
1785 | { | |
1786 | struct omap_eac_s *s = (struct omap_eac_s *) opaque; | |
1787 | int offset = addr - s->base; | |
1788 | ||
1789 | switch (offset) { | |
1790 | case 0x098: /* APD1LCR */ | |
1791 | case 0x09c: /* APD1RCR */ | |
1792 | case 0x0a0: /* APD2LCR */ | |
1793 | case 0x0a4: /* APD2RCR */ | |
1794 | case 0x0a8: /* APD3LCR */ | |
1795 | case 0x0ac: /* APD3RCR */ | |
1796 | case 0x0b0: /* APD4R */ | |
1797 | case 0x0b8: /* ADRDR */ | |
1798 | case 0x0d0: /* MPDDMARR */ | |
1799 | case 0x0d8: /* MPUDMARR */ | |
1800 | case 0x0e4: /* BPDDMARR */ | |
1801 | case 0x0ec: /* BPUDMARR */ | |
1802 | case 0x100: /* VERSION_NUMBER */ | |
1803 | case 0x108: /* SYSSTATUS */ | |
1804 | OMAP_RO_REG(addr); | |
1805 | return; | |
1806 | ||
1807 | case 0x000: /* CPCFR1 */ | |
1808 | s->config[0] = value & 0xff; | |
1809 | omap_eac_format_update(s); | |
1810 | break; | |
1811 | case 0x004: /* CPCFR2 */ | |
1812 | s->config[1] = value & 0xff; | |
1813 | omap_eac_format_update(s); | |
1814 | break; | |
1815 | case 0x008: /* CPCFR3 */ | |
1816 | s->config[2] = value & 0xff; | |
1817 | omap_eac_format_update(s); | |
1818 | break; | |
1819 | case 0x00c: /* CPCFR4 */ | |
1820 | s->config[3] = value & 0xff; | |
1821 | omap_eac_format_update(s); | |
1822 | break; | |
1823 | ||
1824 | case 0x010: /* CPTCTL */ | |
1825 | /* Assuming TXF and TXE bits are read-only... */ | |
1826 | s->control = value & 0x5f; | |
1827 | omap_eac_interrupt_update(s); | |
1828 | break; | |
1829 | ||
1830 | case 0x014: /* CPTTADR */ | |
1831 | s->address = value & 0xff; | |
1832 | break; | |
1833 | case 0x018: /* CPTDATL */ | |
1834 | s->data &= 0xff00; | |
1835 | s->data |= value & 0xff; | |
1836 | break; | |
1837 | case 0x01c: /* CPTDATH */ | |
1838 | s->data &= 0x00ff; | |
1839 | s->data |= value << 8; | |
1840 | break; | |
1841 | case 0x020: /* CPTVSLL */ | |
1842 | s->vtol = value & 0xf8; | |
1843 | break; | |
1844 | case 0x024: /* CPTVSLH */ | |
1845 | s->vtsl = value & 0x9f; | |
1846 | break; | |
1847 | case 0x040: /* MPCTR */ | |
1848 | s->modem.control = value & 0x8f; | |
1849 | break; | |
1850 | case 0x044: /* MPMCCFR */ | |
1851 | s->modem.config = value & 0x7fff; | |
1852 | break; | |
1853 | case 0x060: /* BPCTR */ | |
1854 | s->bt.control = value & 0x8f; | |
1855 | break; | |
1856 | case 0x064: /* BPMCCFR */ | |
1857 | s->bt.config = value & 0x7fff; | |
1858 | break; | |
1859 | case 0x080: /* AMSCFR */ | |
1860 | s->mixer = value & 0x0fff; | |
1861 | break; | |
1862 | case 0x084: /* AMVCTR */ | |
1863 | s->gain[0] = value & 0xffff; | |
1864 | break; | |
1865 | case 0x088: /* AM1VCTR */ | |
1866 | s->gain[1] = value & 0xff7f; | |
1867 | break; | |
1868 | case 0x08c: /* AM2VCTR */ | |
1869 | s->gain[2] = value & 0xff7f; | |
1870 | break; | |
1871 | case 0x090: /* AM3VCTR */ | |
1872 | s->gain[3] = value & 0xff7f; | |
1873 | break; | |
1874 | case 0x094: /* ASTCTR */ | |
1875 | s->att = value & 0xff; | |
1876 | break; | |
1877 | ||
1878 | case 0x0b4: /* ADWR */ | |
1879 | s->codec.txbuf[s->codec.txlen ++] = value; | |
1880 | if (unlikely(s->codec.txlen == EAC_BUF_LEN || | |
1881 | s->codec.txlen == s->codec.txavail)) { | |
1882 | if (s->codec.txavail) | |
1883 | omap_eac_out_empty(s); | |
1884 | else | |
1885 | s->codec.txlen = 0; | |
1886 | } | |
1887 | break; | |
1888 | ||
1889 | case 0x0bc: /* AGCFR */ | |
1890 | s->codec.config[0] = value & 0x07ff; | |
1891 | omap_eac_format_update(s); | |
1892 | break; | |
1893 | case 0x0c0: /* AGCTR */ | |
1894 | s->codec.config[1] = value & 0x780f; | |
1895 | omap_eac_format_update(s); | |
1896 | break; | |
1897 | case 0x0c4: /* AGCFR2 */ | |
1898 | s->codec.config[2] = value & 0x003f; | |
1899 | omap_eac_format_update(s); | |
1900 | break; | |
1901 | case 0x0c8: /* AGCFR3 */ | |
1902 | s->codec.config[3] = value & 0xffff; | |
1903 | omap_eac_format_update(s); | |
1904 | break; | |
1905 | case 0x0cc: /* MBPDMACTR */ | |
1906 | case 0x0d4: /* MPDDMAWR */ | |
1907 | case 0x0e0: /* MPUDMAWR */ | |
1908 | case 0x0e8: /* BPDDMAWR */ | |
1909 | case 0x0f0: /* BPUDMAWR */ | |
1910 | break; | |
1911 | ||
1912 | case 0x104: /* SYSCONFIG */ | |
1913 | if (value & (1 << 1)) /* SOFTRESET */ | |
1914 | omap_eac_reset(s); | |
1915 | s->sysconfig = value & 0x31d; | |
1916 | break; | |
1917 | ||
1918 | default: | |
1919 | OMAP_BAD_REG(addr); | |
1920 | return; | |
1921 | } | |
1922 | } | |
1923 | ||
1924 | static CPUReadMemoryFunc *omap_eac_readfn[] = { | |
1925 | omap_badwidth_read16, | |
1926 | omap_eac_read, | |
1927 | omap_badwidth_read16, | |
1928 | }; | |
1929 | ||
1930 | static CPUWriteMemoryFunc *omap_eac_writefn[] = { | |
1931 | omap_badwidth_write16, | |
1932 | omap_eac_write, | |
1933 | omap_badwidth_write16, | |
1934 | }; | |
1935 | ||
1936 | struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, | |
1937 | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) | |
1938 | { | |
1939 | int iomemtype; | |
1940 | struct omap_eac_s *s = (struct omap_eac_s *) | |
1941 | qemu_mallocz(sizeof(struct omap_eac_s)); | |
1942 | ||
1943 | s->irq = irq; | |
1944 | s->codec.rxdrq = *drq ++; | |
1945 | s->codec.txdrq = *drq ++; | |
1946 | omap_eac_reset(s); | |
1947 | ||
1948 | #ifdef HAS_AUDIO | |
1949 | /* TODO: do AUD_init globally for machine */ | |
1950 | AUD_register_card(AUD_init(), "OMAP EAC", &s->codec.card); | |
1951 | ||
1952 | iomemtype = cpu_register_io_memory(0, omap_eac_readfn, | |
1953 | omap_eac_writefn, s); | |
1954 | s->base = omap_l4_attach(ta, 0, iomemtype); | |
1955 | #endif | |
1956 | ||
1957 | return s; | |
1958 | } | |
1959 | ||
54585ffe AZ |
1960 | /* STI/XTI (emulation interface) console - reverse engineered only */ |
1961 | struct omap_sti_s { | |
1962 | target_phys_addr_t base; | |
1963 | target_phys_addr_t channel_base; | |
1964 | qemu_irq irq; | |
1965 | CharDriverState *chr; | |
1966 | ||
1967 | uint32_t sysconfig; | |
1968 | uint32_t systest; | |
1969 | uint32_t irqst; | |
1970 | uint32_t irqen; | |
1971 | uint32_t clkcontrol; | |
1972 | uint32_t serial_config; | |
1973 | }; | |
1974 | ||
1975 | #define STI_TRACE_CONSOLE_CHANNEL 239 | |
1976 | #define STI_TRACE_CONTROL_CHANNEL 253 | |
1977 | ||
1978 | static inline void omap_sti_interrupt_update(struct omap_sti_s *s) | |
1979 | { | |
1980 | qemu_set_irq(s->irq, s->irqst & s->irqen); | |
1981 | } | |
1982 | ||
1983 | static void omap_sti_reset(struct omap_sti_s *s) | |
1984 | { | |
1985 | s->sysconfig = 0; | |
1986 | s->irqst = 0; | |
1987 | s->irqen = 0; | |
1988 | s->clkcontrol = 0; | |
1989 | s->serial_config = 0; | |
1990 | ||
1991 | omap_sti_interrupt_update(s); | |
1992 | } | |
1993 | ||
1994 | static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr) | |
1995 | { | |
1996 | struct omap_sti_s *s = (struct omap_sti_s *) opaque; | |
1997 | int offset = addr - s->base; | |
1998 | ||
1999 | switch (offset) { | |
2000 | case 0x00: /* STI_REVISION */ | |
2001 | return 0x10; | |
2002 | ||
2003 | case 0x10: /* STI_SYSCONFIG */ | |
2004 | return s->sysconfig; | |
2005 | ||
2006 | case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ | |
2007 | return 0x00; | |
2008 | ||
2009 | case 0x18: /* STI_IRQSTATUS */ | |
2010 | return s->irqst; | |
2011 | ||
2012 | case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ | |
2013 | return s->irqen; | |
2014 | ||
2015 | case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ | |
2016 | case 0x28: /* STI_RX_DR / XTI_RXDATA */ | |
e927bb00 AZ |
2017 | /* TODO */ |
2018 | return 0; | |
54585ffe AZ |
2019 | |
2020 | case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ | |
2021 | return s->clkcontrol; | |
2022 | ||
2023 | case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ | |
2024 | return s->serial_config; | |
2025 | } | |
2026 | ||
2027 | OMAP_BAD_REG(addr); | |
2028 | return 0; | |
2029 | } | |
2030 | ||
2031 | static void omap_sti_write(void *opaque, target_phys_addr_t addr, | |
2032 | uint32_t value) | |
2033 | { | |
2034 | struct omap_sti_s *s = (struct omap_sti_s *) opaque; | |
2035 | int offset = addr - s->base; | |
2036 | ||
2037 | switch (offset) { | |
2038 | case 0x00: /* STI_REVISION */ | |
2039 | case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ | |
2040 | OMAP_RO_REG(addr); | |
2041 | return; | |
2042 | ||
2043 | case 0x10: /* STI_SYSCONFIG */ | |
2044 | if (value & (1 << 1)) /* SOFTRESET */ | |
2045 | omap_sti_reset(s); | |
2046 | s->sysconfig = value & 0xfe; | |
2047 | break; | |
2048 | ||
2049 | case 0x18: /* STI_IRQSTATUS */ | |
2050 | s->irqst &= ~value; | |
2051 | omap_sti_interrupt_update(s); | |
2052 | break; | |
2053 | ||
2054 | case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */ | |
2055 | s->irqen = value & 0xffff; | |
2056 | omap_sti_interrupt_update(s); | |
2057 | break; | |
2058 | ||
2059 | case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */ | |
2060 | s->clkcontrol = value & 0xff; | |
2061 | break; | |
2062 | ||
2063 | case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */ | |
2064 | s->serial_config = value & 0xff; | |
2065 | break; | |
2066 | ||
2067 | case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */ | |
2068 | case 0x28: /* STI_RX_DR / XTI_RXDATA */ | |
e927bb00 AZ |
2069 | /* TODO */ |
2070 | return; | |
2071 | ||
54585ffe AZ |
2072 | default: |
2073 | OMAP_BAD_REG(addr); | |
2074 | return; | |
2075 | } | |
2076 | } | |
2077 | ||
2078 | static CPUReadMemoryFunc *omap_sti_readfn[] = { | |
2079 | omap_badwidth_read32, | |
2080 | omap_badwidth_read32, | |
2081 | omap_sti_read, | |
2082 | }; | |
2083 | ||
2084 | static CPUWriteMemoryFunc *omap_sti_writefn[] = { | |
2085 | omap_badwidth_write32, | |
2086 | omap_badwidth_write32, | |
2087 | omap_sti_write, | |
2088 | }; | |
2089 | ||
2090 | static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr) | |
2091 | { | |
2092 | OMAP_BAD_REG(addr); | |
2093 | return 0; | |
2094 | } | |
2095 | ||
2096 | static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr, | |
2097 | uint32_t value) | |
2098 | { | |
2099 | struct omap_sti_s *s = (struct omap_sti_s *) opaque; | |
2100 | int offset = addr - s->channel_base; | |
2101 | int ch = offset >> 6; | |
2102 | uint8_t byte = value; | |
2103 | ||
2104 | if (ch == STI_TRACE_CONTROL_CHANNEL) { | |
2105 | /* Flush channel <i>value</i>. */ | |
2106 | qemu_chr_write(s->chr, "\r", 1); | |
2107 | } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) { | |
2108 | if (value == 0xc0 || value == 0xc3) { | |
2109 | /* Open channel <i>ch</i>. */ | |
2110 | } else if (value == 0x00) | |
2111 | qemu_chr_write(s->chr, "\n", 1); | |
2112 | else | |
2113 | qemu_chr_write(s->chr, &byte, 1); | |
2114 | } | |
2115 | } | |
2116 | ||
2117 | static CPUReadMemoryFunc *omap_sti_fifo_readfn[] = { | |
2118 | omap_sti_fifo_read, | |
2119 | omap_badwidth_read8, | |
2120 | omap_badwidth_read8, | |
2121 | }; | |
2122 | ||
2123 | static CPUWriteMemoryFunc *omap_sti_fifo_writefn[] = { | |
2124 | omap_sti_fifo_write, | |
2125 | omap_badwidth_write8, | |
2126 | omap_badwidth_write8, | |
2127 | }; | |
2128 | ||
2129 | struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, | |
2130 | target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk, | |
2131 | CharDriverState *chr) | |
2132 | { | |
2133 | int iomemtype; | |
2134 | struct omap_sti_s *s = (struct omap_sti_s *) | |
2135 | qemu_mallocz(sizeof(struct omap_sti_s)); | |
2136 | ||
2137 | s->irq = irq; | |
2138 | omap_sti_reset(s); | |
2139 | ||
2140 | s->chr = chr ?: qemu_chr_open("null"); | |
2141 | ||
c66fb5bc | 2142 | iomemtype = l4_register_io_memory(0, omap_sti_readfn, |
54585ffe AZ |
2143 | omap_sti_writefn, s); |
2144 | s->base = omap_l4_attach(ta, 0, iomemtype); | |
2145 | ||
2146 | iomemtype = cpu_register_io_memory(0, omap_sti_fifo_readfn, | |
2147 | omap_sti_fifo_writefn, s); | |
2148 | s->channel_base = channel_base; | |
2149 | cpu_register_physical_memory(s->channel_base, 0x10000, iomemtype); | |
2150 | ||
2151 | return s; | |
2152 | } | |
2153 | ||
827df9f3 AZ |
2154 | /* L4 Interconnect */ |
2155 | struct omap_target_agent_s { | |
2156 | struct omap_l4_s *bus; | |
2157 | int regions; | |
2158 | struct omap_l4_region_s *start; | |
2159 | target_phys_addr_t base; | |
2160 | uint32_t component; | |
2161 | uint32_t control; | |
2162 | uint32_t status; | |
2163 | }; | |
2164 | ||
2165 | struct omap_l4_s { | |
2166 | target_phys_addr_t base; | |
2167 | int ta_num; | |
2168 | struct omap_target_agent_s ta[0]; | |
2169 | }; | |
2170 | ||
c66fb5bc AZ |
2171 | #ifdef L4_MUX_HACK |
2172 | static int omap_l4_io_entries; | |
2173 | static int omap_cpu_io_entry; | |
2174 | static struct omap_l4_entry { | |
2175 | CPUReadMemoryFunc **mem_read; | |
2176 | CPUWriteMemoryFunc **mem_write; | |
2177 | void *opaque; | |
2178 | } *omap_l4_io_entry; | |
2179 | static CPUReadMemoryFunc **omap_l4_io_readb_fn; | |
2180 | static CPUReadMemoryFunc **omap_l4_io_readh_fn; | |
2181 | static CPUReadMemoryFunc **omap_l4_io_readw_fn; | |
2182 | static CPUWriteMemoryFunc **omap_l4_io_writeb_fn; | |
2183 | static CPUWriteMemoryFunc **omap_l4_io_writeh_fn; | |
2184 | static CPUWriteMemoryFunc **omap_l4_io_writew_fn; | |
2185 | static void **omap_l4_io_opaque; | |
2186 | ||
2187 | int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read, | |
2188 | CPUWriteMemoryFunc **mem_write, void *opaque) | |
2189 | { | |
2190 | omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read; | |
2191 | omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write; | |
2192 | omap_l4_io_entry[omap_l4_io_entries].opaque = opaque; | |
2193 | ||
2194 | return omap_l4_io_entries ++; | |
2195 | } | |
2196 | ||
2197 | static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr) | |
2198 | { | |
2199 | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; | |
2200 | ||
2201 | return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr); | |
2202 | } | |
2203 | ||
2204 | static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr) | |
2205 | { | |
2206 | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; | |
2207 | ||
2208 | return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr); | |
2209 | } | |
2210 | ||
2211 | static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr) | |
2212 | { | |
2213 | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; | |
2214 | ||
2215 | return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr); | |
2216 | } | |
2217 | ||
2218 | static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr, | |
2219 | uint32_t value) | |
2220 | { | |
2221 | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; | |
2222 | ||
2223 | return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value); | |
2224 | } | |
2225 | ||
2226 | static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr, | |
2227 | uint32_t value) | |
2228 | { | |
2229 | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; | |
2230 | ||
2231 | return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value); | |
2232 | } | |
2233 | ||
2234 | static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr, | |
2235 | uint32_t value) | |
2236 | { | |
2237 | unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS; | |
2238 | ||
2239 | return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value); | |
2240 | } | |
2241 | ||
2242 | static CPUReadMemoryFunc *omap_l4_io_readfn[] = { | |
2243 | omap_l4_io_readb, | |
2244 | omap_l4_io_readh, | |
2245 | omap_l4_io_readw, | |
2246 | }; | |
2247 | ||
2248 | static CPUWriteMemoryFunc *omap_l4_io_writefn[] = { | |
2249 | omap_l4_io_writeb, | |
2250 | omap_l4_io_writeh, | |
2251 | omap_l4_io_writew, | |
2252 | }; | |
2253 | #endif | |
2254 | ||
827df9f3 AZ |
2255 | struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num) |
2256 | { | |
2257 | struct omap_l4_s *bus = qemu_mallocz( | |
2258 | sizeof(*bus) + ta_num * sizeof(*bus->ta)); | |
2259 | ||
2260 | bus->ta_num = ta_num; | |
2261 | bus->base = base; | |
2262 | ||
c66fb5bc AZ |
2263 | #ifdef L4_MUX_HACK |
2264 | omap_l4_io_entries = 1; | |
2265 | omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry)); | |
2266 | ||
2267 | omap_cpu_io_entry = | |
2268 | cpu_register_io_memory(0, omap_l4_io_readfn, | |
2269 | omap_l4_io_writefn, bus); | |
2270 | # define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE) | |
2271 | omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); | |
2272 | omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); | |
2273 | omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); | |
2274 | omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); | |
2275 | omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); | |
2276 | omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES); | |
2277 | omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES); | |
2278 | #endif | |
2279 | ||
827df9f3 AZ |
2280 | return bus; |
2281 | } | |
2282 | ||
2283 | static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr) | |
2284 | { | |
2285 | struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; | |
2286 | target_phys_addr_t reg = addr - s->base; | |
2287 | ||
2288 | switch (reg) { | |
2289 | case 0x00: /* COMPONENT */ | |
2290 | return s->component; | |
2291 | ||
2292 | case 0x20: /* AGENT_CONTROL */ | |
2293 | return s->control; | |
2294 | ||
2295 | case 0x28: /* AGENT_STATUS */ | |
2296 | return s->status; | |
2297 | } | |
2298 | ||
2299 | OMAP_BAD_REG(addr); | |
2300 | return 0; | |
2301 | } | |
2302 | ||
2303 | static void omap_l4ta_write(void *opaque, target_phys_addr_t addr, | |
2304 | uint32_t value) | |
2305 | { | |
2306 | struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; | |
2307 | target_phys_addr_t reg = addr - s->base; | |
2308 | ||
2309 | switch (reg) { | |
2310 | case 0x00: /* COMPONENT */ | |
2311 | case 0x28: /* AGENT_STATUS */ | |
2312 | OMAP_RO_REG(addr); | |
2313 | break; | |
2314 | ||
2315 | case 0x20: /* AGENT_CONTROL */ | |
2316 | s->control = value & 0x01000700; | |
2317 | if (value & 1) /* OCP_RESET */ | |
2318 | s->status &= ~1; /* REQ_TIMEOUT */ | |
2319 | break; | |
2320 | ||
2321 | default: | |
2322 | OMAP_BAD_REG(addr); | |
2323 | } | |
2324 | } | |
2325 | ||
2326 | static CPUReadMemoryFunc *omap_l4ta_readfn[] = { | |
2327 | omap_badwidth_read16, | |
2328 | omap_l4ta_read, | |
2329 | omap_badwidth_read16, | |
2330 | }; | |
2331 | ||
2332 | static CPUWriteMemoryFunc *omap_l4ta_writefn[] = { | |
2333 | omap_badwidth_write32, | |
2334 | omap_badwidth_write32, | |
2335 | omap_l4ta_write, | |
2336 | }; | |
2337 | ||
2338 | #define L4TA(n) (n) | |
2339 | #define L4TAO(n) ((n) + 39) | |
2340 | ||
2341 | static struct omap_l4_region_s { | |
2342 | target_phys_addr_t offset; | |
2343 | size_t size; | |
2344 | int access; | |
2345 | } omap_l4_region[125] = { | |
2346 | [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */ | |
2347 | [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */ | |
2348 | [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */ | |
2349 | [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */ | |
2350 | [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */ | |
2351 | [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */ | |
2352 | [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */ | |
2353 | [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */ | |
2354 | [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */ | |
2355 | [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */ | |
2356 | [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */ | |
2357 | [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */ | |
2358 | [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */ | |
2359 | [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */ | |
2360 | [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */ | |
2361 | [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */ | |
2362 | [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */ | |
2363 | [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */ | |
2364 | [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */ | |
2365 | [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */ | |
2366 | [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */ | |
2367 | [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */ | |
2368 | [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */ | |
2369 | [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */ | |
2370 | [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */ | |
2371 | [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */ | |
2372 | [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */ | |
2373 | [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */ | |
2374 | [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */ | |
2375 | [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */ | |
2376 | [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */ | |
2377 | [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */ | |
2378 | [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */ | |
2379 | [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */ | |
2380 | [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */ | |
2381 | [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */ | |
2382 | [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */ | |
2383 | [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */ | |
2384 | [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */ | |
2385 | [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */ | |
2386 | [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */ | |
2387 | [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */ | |
2388 | [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */ | |
2389 | [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */ | |
2390 | [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */ | |
2391 | [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */ | |
2392 | [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */ | |
2393 | [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */ | |
2394 | [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */ | |
2395 | [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */ | |
2396 | [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */ | |
2397 | [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */ | |
2398 | [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */ | |
2399 | [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */ | |
2400 | [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */ | |
2401 | [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */ | |
2402 | [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */ | |
2403 | [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */ | |
2404 | [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */ | |
2405 | [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */ | |
2406 | [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */ | |
2407 | [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */ | |
2408 | [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */ | |
2409 | [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */ | |
2410 | [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */ | |
2411 | [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */ | |
2412 | [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */ | |
2413 | [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */ | |
2414 | [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */ | |
2415 | [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */ | |
2416 | [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */ | |
2417 | [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */ | |
2418 | [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */ | |
2419 | [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */ | |
2420 | [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */ | |
2421 | [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */ | |
2422 | [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */ | |
2423 | [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */ | |
2424 | [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */ | |
2425 | [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */ | |
2426 | [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */ | |
2427 | [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */ | |
2428 | [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */ | |
2429 | [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */ | |
2430 | [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */ | |
2431 | [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */ | |
2432 | [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */ | |
2433 | [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */ | |
2434 | [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */ | |
2435 | [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */ | |
2436 | [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */ | |
2437 | [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */ | |
2438 | [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */ | |
2439 | [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */ | |
2440 | [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */ | |
2441 | [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */ | |
2442 | [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */ | |
2443 | [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */ | |
2444 | [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */ | |
2445 | [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */ | |
2446 | [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */ | |
2447 | [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */ | |
2448 | [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */ | |
2449 | [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */ | |
2450 | [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */ | |
2451 | [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */ | |
2452 | [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */ | |
2453 | [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */ | |
2454 | [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */ | |
2455 | [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */ | |
2456 | [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */ | |
2457 | [111] = { 0xa0000, 0x1000, 32 }, /* RNG */ | |
2458 | [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */ | |
2459 | [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */ | |
2460 | [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */ | |
2461 | [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */ | |
2462 | [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */ | |
2463 | [117] = { 0xa6000, 0x1000, 32 }, /* AES */ | |
2464 | [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */ | |
2465 | [119] = { 0xa8000, 0x2000, 32 }, /* PKA */ | |
2466 | [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */ | |
2467 | [121] = { 0xb0000, 0x1000, 32 }, /* MG */ | |
2468 | [122] = { 0xb1000, 0x1000, 32 | 16 | 8 }, | |
2469 | [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */ | |
2470 | [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */ | |
2471 | }; | |
2472 | ||
2473 | static struct omap_l4_agent_info_s { | |
2474 | int ta; | |
2475 | int region; | |
2476 | int regions; | |
2477 | int ta_region; | |
2478 | } omap_l4_agent_info[54] = { | |
2479 | { 0, 0, 3, 2 }, /* L4IA initiatior agent */ | |
2480 | { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */ | |
2481 | { L4TAO(2), 5, 2, 1 }, /* 32K timer */ | |
2482 | { L4TAO(3), 7, 3, 2 }, /* PRCM */ | |
2483 | { L4TA(1), 10, 2, 1 }, /* BCM */ | |
2484 | { L4TA(2), 12, 2, 1 }, /* Test JTAG */ | |
2485 | { L4TA(3), 14, 6, 3 }, /* Quad GPIO */ | |
2486 | { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */ | |
2487 | { L4TA(7), 24, 2, 1 }, /* GP timer 1 */ | |
2488 | { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */ | |
2489 | { L4TA(10), 28, 5, 4 }, /* Display subsystem */ | |
2490 | { L4TA(11), 33, 5, 4 }, /* Camera subsystem */ | |
2491 | { L4TA(12), 38, 2, 1 }, /* sDMA */ | |
2492 | { L4TA(13), 40, 5, 4 }, /* SSI */ | |
2493 | { L4TAO(4), 45, 2, 1 }, /* USB */ | |
2494 | { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */ | |
2495 | { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */ | |
2496 | { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */ | |
2497 | { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */ | |
2498 | { L4TA(18), 55, 2, 1 }, /* XTI */ | |
2499 | { L4TA(19), 57, 2, 1 }, /* UART1 */ | |
2500 | { L4TA(20), 59, 2, 1 }, /* UART2 */ | |
2501 | { L4TA(21), 61, 2, 1 }, /* UART3 */ | |
2502 | { L4TAO(5), 63, 2, 1 }, /* I2C1 */ | |
2503 | { L4TAO(6), 65, 2, 1 }, /* I2C2 */ | |
2504 | { L4TAO(7), 67, 2, 1 }, /* McBSP1 */ | |
2505 | { L4TAO(8), 69, 2, 1 }, /* McBSP2 */ | |
2506 | { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */ | |
2507 | { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */ | |
2508 | { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */ | |
2509 | { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */ | |
2510 | { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */ | |
2511 | { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */ | |
2512 | { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */ | |
2513 | { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */ | |
2514 | { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */ | |
2515 | { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */ | |
2516 | { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */ | |
2517 | { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */ | |
2518 | { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */ | |
2519 | { L4TA(32), 97, 2, 1 }, /* EAC */ | |
2520 | { L4TA(33), 99, 2, 1 }, /* FAC */ | |
2521 | { L4TA(34), 101, 2, 1 }, /* IPC */ | |
2522 | { L4TA(35), 103, 2, 1 }, /* SPI1 */ | |
2523 | { L4TA(36), 105, 2, 1 }, /* SPI2 */ | |
2524 | { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */ | |
2525 | { L4TAO(10), 109, 2, 1 }, | |
2526 | { L4TAO(11), 111, 2, 1 }, /* RNG */ | |
2527 | { L4TAO(12), 113, 2, 1 }, /* DES3DES */ | |
2528 | { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */ | |
2529 | { L4TA(37), 117, 2, 1 }, /* AES */ | |
2530 | { L4TA(38), 119, 2, 1 }, /* PKA */ | |
2531 | { -1, 121, 2, 1 }, | |
2532 | { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */ | |
2533 | }; | |
2534 | ||
2535 | #define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs)) | |
2536 | #define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs)) | |
2537 | ||
2538 | struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs) | |
2539 | { | |
2540 | int i, iomemtype; | |
2541 | struct omap_target_agent_s *ta = 0; | |
2542 | struct omap_l4_agent_info_s *info = 0; | |
2543 | ||
2544 | for (i = 0; i < bus->ta_num; i ++) | |
2545 | if (omap_l4_agent_info[i].ta == cs) { | |
2546 | ta = &bus->ta[i]; | |
2547 | info = &omap_l4_agent_info[i]; | |
2548 | break; | |
2549 | } | |
2550 | if (!ta) { | |
2551 | fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs); | |
2552 | exit(-1); | |
2553 | } | |
2554 | ||
2555 | ta->bus = bus; | |
2556 | ta->start = &omap_l4_region[info->region]; | |
2557 | ta->regions = info->regions; | |
827df9f3 AZ |
2558 | |
2559 | ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); | |
2560 | ta->status = 0x00000000; | |
2561 | ta->control = 0x00000200; /* XXX 01000200 for L4TAO */ | |
2562 | ||
c66fb5bc | 2563 | iomemtype = l4_register_io_memory(0, omap_l4ta_readfn, |
827df9f3 | 2564 | omap_l4ta_writefn, ta); |
c66fb5bc | 2565 | ta->base = omap_l4_attach(ta, info->ta_region, iomemtype); |
827df9f3 AZ |
2566 | |
2567 | return ta; | |
2568 | } | |
2569 | ||
2570 | target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, | |
2571 | int iotype) | |
2572 | { | |
2573 | target_phys_addr_t base; | |
c66fb5bc AZ |
2574 | ssize_t size; |
2575 | #ifdef L4_MUX_HACK | |
2576 | int i; | |
2577 | #endif | |
827df9f3 AZ |
2578 | |
2579 | if (region < 0 || region >= ta->regions) { | |
2580 | fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region); | |
2581 | exit(-1); | |
2582 | } | |
2583 | ||
2584 | base = ta->bus->base + ta->start[region].offset; | |
2585 | size = ta->start[region].size; | |
c66fb5bc AZ |
2586 | if (iotype) { |
2587 | #ifndef L4_MUX_HACK | |
827df9f3 | 2588 | cpu_register_physical_memory(base, size, iotype); |
c66fb5bc AZ |
2589 | #else |
2590 | cpu_register_physical_memory(base, size, omap_cpu_io_entry); | |
2591 | i = (base - ta->bus->base) / TARGET_PAGE_SIZE; | |
2592 | for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) { | |
2593 | omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0]; | |
2594 | omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1]; | |
2595 | omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2]; | |
2596 | omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0]; | |
2597 | omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1]; | |
2598 | omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2]; | |
2599 | omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque; | |
2600 | } | |
2601 | #endif | |
2602 | } | |
827df9f3 AZ |
2603 | |
2604 | return base; | |
2605 | } | |
2606 | ||
2607 | /* TEST-Chip-level TAP */ | |
2608 | static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr) | |
2609 | { | |
2610 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | |
2611 | target_phys_addr_t reg = addr - s->tap_base; | |
2612 | ||
2613 | switch (reg) { | |
2614 | case 0x204: /* IDCODE_reg */ | |
2615 | switch (s->mpu_model) { | |
2616 | case omap2420: | |
2617 | case omap2422: | |
2618 | case omap2423: | |
2619 | return 0x5b5d902f; /* ES 2.2 */ | |
2620 | case omap2430: | |
2621 | return 0x5b68a02f; /* ES 2.2 */ | |
2622 | case omap3430: | |
2623 | return 0x1b7ae02f; /* ES 2 */ | |
2624 | default: | |
2625 | cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__); | |
2626 | } | |
2627 | ||
2628 | case 0x208: /* PRODUCTION_ID_reg for OMAP2 */ | |
2629 | case 0x210: /* PRODUCTION_ID_reg for OMAP3 */ | |
2630 | switch (s->mpu_model) { | |
2631 | case omap2420: | |
2632 | return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */ | |
2633 | case omap2422: | |
2634 | return 0x000400f0; | |
2635 | case omap2423: | |
2636 | return 0x000800f0; | |
2637 | case omap2430: | |
2638 | return 0x000000f0; | |
2639 | case omap3430: | |
2640 | return 0x000000f0; | |
2641 | default: | |
2642 | cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__); | |
2643 | } | |
2644 | ||
2645 | case 0x20c: | |
2646 | switch (s->mpu_model) { | |
2647 | case omap2420: | |
2648 | case omap2422: | |
2649 | case omap2423: | |
2650 | return 0xcafeb5d9; /* ES 2.2 */ | |
2651 | case omap2430: | |
2652 | return 0xcafeb68a; /* ES 2.2 */ | |
2653 | case omap3430: | |
2654 | return 0xcafeb7ae; /* ES 2 */ | |
2655 | default: | |
2656 | cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__); | |
2657 | } | |
2658 | ||
2659 | case 0x218: /* DIE_ID_reg */ | |
2660 | return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); | |
2661 | case 0x21c: /* DIE_ID_reg */ | |
2662 | return 0x54 << 24; | |
2663 | case 0x220: /* DIE_ID_reg */ | |
2664 | return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); | |
2665 | case 0x224: /* DIE_ID_reg */ | |
2666 | return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); | |
2667 | } | |
2668 | ||
2669 | OMAP_BAD_REG(addr); | |
2670 | return 0; | |
2671 | } | |
2672 | ||
2673 | static void omap_tap_write(void *opaque, target_phys_addr_t addr, | |
2674 | uint32_t value) | |
2675 | { | |
2676 | OMAP_BAD_REG(addr); | |
2677 | } | |
2678 | ||
2679 | static CPUReadMemoryFunc *omap_tap_readfn[] = { | |
2680 | omap_badwidth_read32, | |
2681 | omap_badwidth_read32, | |
2682 | omap_tap_read, | |
2683 | }; | |
2684 | ||
2685 | static CPUWriteMemoryFunc *omap_tap_writefn[] = { | |
2686 | omap_badwidth_write32, | |
2687 | omap_badwidth_write32, | |
2688 | omap_tap_write, | |
2689 | }; | |
2690 | ||
2691 | void omap_tap_init(struct omap_target_agent_s *ta, | |
2692 | struct omap_mpu_state_s *mpu) | |
2693 | { | |
c66fb5bc | 2694 | mpu->tap_base = omap_l4_attach(ta, 0, l4_register_io_memory(0, |
827df9f3 AZ |
2695 | omap_tap_readfn, omap_tap_writefn, mpu)); |
2696 | } | |
2697 | ||
2698 | /* Power, Reset, and Clock Management */ | |
2699 | struct omap_prcm_s { | |
2700 | target_phys_addr_t base; | |
2701 | qemu_irq irq[3]; | |
2702 | struct omap_mpu_state_s *mpu; | |
2703 | ||
2704 | uint32_t irqst[3]; | |
2705 | uint32_t irqen[3]; | |
2706 | ||
2707 | uint32_t sysconfig; | |
2708 | uint32_t voltctrl; | |
2709 | uint32_t scratch[20]; | |
2710 | ||
2711 | uint32_t clksrc[1]; | |
2712 | uint32_t clkout[1]; | |
2713 | uint32_t clkemul[1]; | |
2714 | uint32_t clkpol[1]; | |
2715 | uint32_t clksel[8]; | |
2716 | uint32_t clken[12]; | |
2717 | uint32_t clkctrl[4]; | |
2718 | uint32_t clkidle[7]; | |
2719 | uint32_t setuptime[2]; | |
2720 | ||
2721 | uint32_t wkup[3]; | |
2722 | uint32_t wken[3]; | |
2723 | uint32_t wkst[3]; | |
2724 | uint32_t rst[4]; | |
2725 | uint32_t rstctrl[1]; | |
2726 | uint32_t power[4]; | |
2727 | uint32_t rsttime_wkup; | |
2728 | ||
2729 | uint32_t ev; | |
2730 | uint32_t evtime[2]; | |
51fec3cc AZ |
2731 | |
2732 | int dpll_lock, apll_lock[2]; | |
827df9f3 AZ |
2733 | }; |
2734 | ||
2735 | static void omap_prcm_int_update(struct omap_prcm_s *s, int dom) | |
2736 | { | |
2737 | qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]); | |
2738 | /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */ | |
2739 | } | |
2740 | ||
2741 | static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr) | |
2742 | { | |
2743 | struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; | |
2744 | int offset = addr - s->base; | |
51fec3cc | 2745 | uint32_t ret; |
827df9f3 AZ |
2746 | |
2747 | switch (offset) { | |
2748 | case 0x000: /* PRCM_REVISION */ | |
2749 | return 0x10; | |
2750 | ||
2751 | case 0x010: /* PRCM_SYSCONFIG */ | |
2752 | return s->sysconfig; | |
2753 | ||
2754 | case 0x018: /* PRCM_IRQSTATUS_MPU */ | |
2755 | return s->irqst[0]; | |
2756 | ||
2757 | case 0x01c: /* PRCM_IRQENABLE_MPU */ | |
2758 | return s->irqen[0]; | |
2759 | ||
2760 | case 0x050: /* PRCM_VOLTCTRL */ | |
2761 | return s->voltctrl; | |
2762 | case 0x054: /* PRCM_VOLTST */ | |
2763 | return s->voltctrl & 3; | |
2764 | ||
2765 | case 0x060: /* PRCM_CLKSRC_CTRL */ | |
2766 | return s->clksrc[0]; | |
2767 | case 0x070: /* PRCM_CLKOUT_CTRL */ | |
2768 | return s->clkout[0]; | |
2769 | case 0x078: /* PRCM_CLKEMUL_CTRL */ | |
2770 | return s->clkemul[0]; | |
2771 | case 0x080: /* PRCM_CLKCFG_CTRL */ | |
2772 | case 0x084: /* PRCM_CLKCFG_STATUS */ | |
2773 | return 0; | |
2774 | ||
2775 | case 0x090: /* PRCM_VOLTSETUP */ | |
2776 | return s->setuptime[0]; | |
2777 | ||
2778 | case 0x094: /* PRCM_CLKSSETUP */ | |
2779 | return s->setuptime[1]; | |
2780 | ||
2781 | case 0x098: /* PRCM_POLCTRL */ | |
2782 | return s->clkpol[0]; | |
2783 | ||
2784 | case 0x0b0: /* GENERAL_PURPOSE1 */ | |
2785 | case 0x0b4: /* GENERAL_PURPOSE2 */ | |
2786 | case 0x0b8: /* GENERAL_PURPOSE3 */ | |
2787 | case 0x0bc: /* GENERAL_PURPOSE4 */ | |
2788 | case 0x0c0: /* GENERAL_PURPOSE5 */ | |
2789 | case 0x0c4: /* GENERAL_PURPOSE6 */ | |
2790 | case 0x0c8: /* GENERAL_PURPOSE7 */ | |
2791 | case 0x0cc: /* GENERAL_PURPOSE8 */ | |
2792 | case 0x0d0: /* GENERAL_PURPOSE9 */ | |
2793 | case 0x0d4: /* GENERAL_PURPOSE10 */ | |
2794 | case 0x0d8: /* GENERAL_PURPOSE11 */ | |
2795 | case 0x0dc: /* GENERAL_PURPOSE12 */ | |
2796 | case 0x0e0: /* GENERAL_PURPOSE13 */ | |
2797 | case 0x0e4: /* GENERAL_PURPOSE14 */ | |
2798 | case 0x0e8: /* GENERAL_PURPOSE15 */ | |
2799 | case 0x0ec: /* GENERAL_PURPOSE16 */ | |
2800 | case 0x0f0: /* GENERAL_PURPOSE17 */ | |
2801 | case 0x0f4: /* GENERAL_PURPOSE18 */ | |
2802 | case 0x0f8: /* GENERAL_PURPOSE19 */ | |
2803 | case 0x0fc: /* GENERAL_PURPOSE20 */ | |
2804 | return s->scratch[(offset - 0xb0) >> 2]; | |
2805 | ||
2806 | case 0x140: /* CM_CLKSEL_MPU */ | |
2807 | return s->clksel[0]; | |
2808 | case 0x148: /* CM_CLKSTCTRL_MPU */ | |
2809 | return s->clkctrl[0]; | |
2810 | ||
2811 | case 0x158: /* RM_RSTST_MPU */ | |
2812 | return s->rst[0]; | |
2813 | case 0x1c8: /* PM_WKDEP_MPU */ | |
2814 | return s->wkup[0]; | |
2815 | case 0x1d4: /* PM_EVGENCTRL_MPU */ | |
2816 | return s->ev; | |
2817 | case 0x1d8: /* PM_EVEGENONTIM_MPU */ | |
2818 | return s->evtime[0]; | |
2819 | case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ | |
2820 | return s->evtime[1]; | |
2821 | case 0x1e0: /* PM_PWSTCTRL_MPU */ | |
2822 | return s->power[0]; | |
2823 | case 0x1e4: /* PM_PWSTST_MPU */ | |
2824 | return 0; | |
2825 | ||
2826 | case 0x200: /* CM_FCLKEN1_CORE */ | |
2827 | return s->clken[0]; | |
2828 | case 0x204: /* CM_FCLKEN2_CORE */ | |
2829 | return s->clken[1]; | |
2830 | case 0x210: /* CM_ICLKEN1_CORE */ | |
2831 | return s->clken[2]; | |
2832 | case 0x214: /* CM_ICLKEN2_CORE */ | |
2833 | return s->clken[3]; | |
2834 | case 0x21c: /* CM_ICLKEN4_CORE */ | |
2835 | return s->clken[4]; | |
2836 | ||
2837 | case 0x220: /* CM_IDLEST1_CORE */ | |
2838 | /* TODO: check the actual iclk status */ | |
2839 | return 0x7ffffff9; | |
2840 | case 0x224: /* CM_IDLEST2_CORE */ | |
2841 | /* TODO: check the actual iclk status */ | |
2842 | return 0x00000007; | |
2843 | case 0x22c: /* CM_IDLEST4_CORE */ | |
2844 | /* TODO: check the actual iclk status */ | |
2845 | return 0x0000001f; | |
2846 | ||
2847 | case 0x230: /* CM_AUTOIDLE1_CORE */ | |
2848 | return s->clkidle[0]; | |
2849 | case 0x234: /* CM_AUTOIDLE2_CORE */ | |
2850 | return s->clkidle[1]; | |
2851 | case 0x238: /* CM_AUTOIDLE3_CORE */ | |
2852 | return s->clkidle[2]; | |
2853 | case 0x23c: /* CM_AUTOIDLE4_CORE */ | |
2854 | return s->clkidle[3]; | |
2855 | ||
2856 | case 0x240: /* CM_CLKSEL1_CORE */ | |
2857 | return s->clksel[1]; | |
2858 | case 0x244: /* CM_CLKSEL2_CORE */ | |
2859 | return s->clksel[2]; | |
2860 | ||
2861 | case 0x248: /* CM_CLKSTCTRL_CORE */ | |
2862 | return s->clkctrl[1]; | |
2863 | ||
2864 | case 0x2a0: /* PM_WKEN1_CORE */ | |
2865 | return s->wken[0]; | |
2866 | case 0x2a4: /* PM_WKEN2_CORE */ | |
2867 | return s->wken[1]; | |
2868 | ||
2869 | case 0x2b0: /* PM_WKST1_CORE */ | |
2870 | return s->wkst[0]; | |
2871 | case 0x2b4: /* PM_WKST2_CORE */ | |
2872 | return s->wkst[1]; | |
2873 | case 0x2c8: /* PM_WKDEP_CORE */ | |
2874 | return 0x1e; | |
2875 | ||
2876 | case 0x2e0: /* PM_PWSTCTRL_CORE */ | |
2877 | return s->power[1]; | |
2878 | case 0x2e4: /* PM_PWSTST_CORE */ | |
2879 | return 0x000030 | (s->power[1] & 0xfc00); | |
2880 | ||
2881 | case 0x300: /* CM_FCLKEN_GFX */ | |
2882 | return s->clken[5]; | |
2883 | case 0x310: /* CM_ICLKEN_GFX */ | |
2884 | return s->clken[6]; | |
2885 | case 0x320: /* CM_IDLEST_GFX */ | |
2886 | /* TODO: check the actual iclk status */ | |
2887 | return 0x00000001; | |
2888 | case 0x340: /* CM_CLKSEL_GFX */ | |
2889 | return s->clksel[3]; | |
2890 | case 0x348: /* CM_CLKSTCTRL_GFX */ | |
2891 | return s->clkctrl[2]; | |
2892 | case 0x350: /* RM_RSTCTRL_GFX */ | |
2893 | return s->rstctrl[0]; | |
2894 | case 0x358: /* RM_RSTST_GFX */ | |
2895 | return s->rst[1]; | |
2896 | case 0x3c8: /* PM_WKDEP_GFX */ | |
2897 | return s->wkup[1]; | |
2898 | ||
2899 | case 0x3e0: /* PM_PWSTCTRL_GFX */ | |
2900 | return s->power[2]; | |
2901 | case 0x3e4: /* PM_PWSTST_GFX */ | |
2902 | return s->power[2] & 3; | |
2903 | ||
2904 | case 0x400: /* CM_FCLKEN_WKUP */ | |
2905 | return s->clken[7]; | |
2906 | case 0x410: /* CM_ICLKEN_WKUP */ | |
2907 | return s->clken[8]; | |
2908 | case 0x420: /* CM_IDLEST_WKUP */ | |
2909 | /* TODO: check the actual iclk status */ | |
2910 | return 0x0000003f; | |
2911 | case 0x430: /* CM_AUTOIDLE_WKUP */ | |
2912 | return s->clkidle[4]; | |
2913 | case 0x440: /* CM_CLKSEL_WKUP */ | |
2914 | return s->clksel[4]; | |
2915 | case 0x450: /* RM_RSTCTRL_WKUP */ | |
2916 | return 0; | |
2917 | case 0x454: /* RM_RSTTIME_WKUP */ | |
2918 | return s->rsttime_wkup; | |
2919 | case 0x458: /* RM_RSTST_WKUP */ | |
2920 | return s->rst[2]; | |
2921 | case 0x4a0: /* PM_WKEN_WKUP */ | |
2922 | return s->wken[2]; | |
2923 | case 0x4b0: /* PM_WKST_WKUP */ | |
2924 | return s->wkst[2]; | |
2925 | ||
2926 | case 0x500: /* CM_CLKEN_PLL */ | |
2927 | return s->clken[9]; | |
2928 | case 0x520: /* CM_IDLEST_CKGEN */ | |
51fec3cc | 2929 | ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8); |
827df9f3 | 2930 | if (!(s->clksel[6] & 3)) |
51fec3cc AZ |
2931 | /* Core uses 32-kHz clock */ |
2932 | ret |= 3 << 0; | |
2933 | else if (!s->dpll_lock) | |
2934 | /* DPLL not locked, core uses ref_clk */ | |
2935 | ret |= 1 << 0; | |
2936 | else | |
2937 | /* Core uses DPLL */ | |
2938 | ret |= 2 << 0; | |
2939 | return ret; | |
827df9f3 AZ |
2940 | case 0x530: /* CM_AUTOIDLE_PLL */ |
2941 | return s->clkidle[5]; | |
2942 | case 0x540: /* CM_CLKSEL1_PLL */ | |
2943 | return s->clksel[5]; | |
2944 | case 0x544: /* CM_CLKSEL2_PLL */ | |
2945 | return s->clksel[6]; | |
2946 | ||
2947 | case 0x800: /* CM_FCLKEN_DSP */ | |
2948 | return s->clken[10]; | |
2949 | case 0x810: /* CM_ICLKEN_DSP */ | |
2950 | return s->clken[11]; | |
2951 | case 0x820: /* CM_IDLEST_DSP */ | |
2952 | /* TODO: check the actual iclk status */ | |
2953 | return 0x00000103; | |
2954 | case 0x830: /* CM_AUTOIDLE_DSP */ | |
2955 | return s->clkidle[6]; | |
2956 | case 0x840: /* CM_CLKSEL_DSP */ | |
2957 | return s->clksel[7]; | |
2958 | case 0x848: /* CM_CLKSTCTRL_DSP */ | |
2959 | return s->clkctrl[3]; | |
2960 | case 0x850: /* RM_RSTCTRL_DSP */ | |
2961 | return 0; | |
2962 | case 0x858: /* RM_RSTST_DSP */ | |
2963 | return s->rst[3]; | |
2964 | case 0x8c8: /* PM_WKDEP_DSP */ | |
2965 | return s->wkup[2]; | |
2966 | case 0x8e0: /* PM_PWSTCTRL_DSP */ | |
2967 | return s->power[3]; | |
2968 | case 0x8e4: /* PM_PWSTST_DSP */ | |
2969 | return 0x008030 | (s->power[3] & 0x3003); | |
2970 | ||
2971 | case 0x8f0: /* PRCM_IRQSTATUS_DSP */ | |
2972 | return s->irqst[1]; | |
2973 | case 0x8f4: /* PRCM_IRQENABLE_DSP */ | |
2974 | return s->irqen[1]; | |
2975 | ||
2976 | case 0x8f8: /* PRCM_IRQSTATUS_IVA */ | |
2977 | return s->irqst[2]; | |
2978 | case 0x8fc: /* PRCM_IRQENABLE_IVA */ | |
2979 | return s->irqen[2]; | |
2980 | } | |
2981 | ||
2982 | OMAP_BAD_REG(addr); | |
2983 | return 0; | |
2984 | } | |
2985 | ||
51fec3cc AZ |
2986 | static void omap_prcm_apll_update(struct omap_prcm_s *s) |
2987 | { | |
2988 | int mode[2]; | |
2989 | ||
2990 | mode[0] = (s->clken[9] >> 6) & 3; | |
2991 | s->apll_lock[0] = (mode[0] == 3); | |
2992 | mode[1] = (s->clken[9] >> 2) & 3; | |
2993 | s->apll_lock[1] = (mode[1] == 3); | |
2994 | /* TODO: update clocks */ | |
2995 | ||
2996 | if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[2] == 2) | |
2997 | fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n", | |
2998 | __FUNCTION__); | |
2999 | } | |
3000 | ||
3001 | static void omap_prcm_dpll_update(struct omap_prcm_s *s) | |
3002 | { | |
3003 | omap_clk dpll = omap_findclk(s->mpu, "dpll"); | |
3004 | omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll"); | |
3005 | omap_clk core = omap_findclk(s->mpu, "core_clk"); | |
3006 | int mode = (s->clken[9] >> 0) & 3; | |
3007 | int mult, div; | |
3008 | ||
3009 | mult = (s->clksel[5] >> 12) & 0x3ff; | |
3010 | div = (s->clksel[5] >> 8) & 0xf; | |
3011 | if (mult == 0 || mult == 1) | |
3012 | mode = 1; /* Bypass */ | |
3013 | ||
3014 | s->dpll_lock = 0; | |
3015 | switch (mode) { | |
3016 | case 0: | |
3017 | fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__); | |
3018 | break; | |
3019 | case 1: /* Low-power bypass mode (Default) */ | |
3020 | case 2: /* Fast-relock bypass mode */ | |
3021 | omap_clk_setrate(dpll, 1, 1); | |
3022 | omap_clk_setrate(dpll_x2, 1, 1); | |
3023 | break; | |
3024 | case 3: /* Lock mode */ | |
3025 | s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */ | |
3026 | ||
3027 | omap_clk_setrate(dpll, div + 1, mult); | |
3028 | omap_clk_setrate(dpll_x2, div + 1, mult * 2); | |
3029 | break; | |
3030 | } | |
3031 | ||
3032 | switch ((s->clksel[6] >> 0) & 3) { | |
3033 | case 0: | |
3034 | omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz")); | |
3035 | break; | |
3036 | case 1: | |
3037 | omap_clk_reparent(core, dpll); | |
3038 | break; | |
3039 | case 2: | |
3040 | /* Default */ | |
3041 | omap_clk_reparent(core, dpll_x2); | |
3042 | break; | |
3043 | case 3: | |
3044 | fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__); | |
3045 | break; | |
3046 | } | |
3047 | } | |
3048 | ||
827df9f3 AZ |
3049 | static void omap_prcm_write(void *opaque, target_phys_addr_t addr, |
3050 | uint32_t value) | |
3051 | { | |
3052 | struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; | |
3053 | int offset = addr - s->base; | |
3054 | ||
3055 | switch (offset) { | |
3056 | case 0x000: /* PRCM_REVISION */ | |
3057 | case 0x054: /* PRCM_VOLTST */ | |
3058 | case 0x084: /* PRCM_CLKCFG_STATUS */ | |
3059 | case 0x1e4: /* PM_PWSTST_MPU */ | |
3060 | case 0x220: /* CM_IDLEST1_CORE */ | |
3061 | case 0x224: /* CM_IDLEST2_CORE */ | |
3062 | case 0x22c: /* CM_IDLEST4_CORE */ | |
3063 | case 0x2c8: /* PM_WKDEP_CORE */ | |
3064 | case 0x2e4: /* PM_PWSTST_CORE */ | |
3065 | case 0x320: /* CM_IDLEST_GFX */ | |
3066 | case 0x3e4: /* PM_PWSTST_GFX */ | |
3067 | case 0x420: /* CM_IDLEST_WKUP */ | |
3068 | case 0x520: /* CM_IDLEST_CKGEN */ | |
3069 | case 0x820: /* CM_IDLEST_DSP */ | |
3070 | case 0x8e4: /* PM_PWSTST_DSP */ | |
3071 | OMAP_RO_REG(addr); | |
3072 | return; | |
3073 | ||
3074 | case 0x010: /* PRCM_SYSCONFIG */ | |
3075 | s->sysconfig = value & 1; | |
3076 | break; | |
3077 | ||
3078 | case 0x018: /* PRCM_IRQSTATUS_MPU */ | |
3079 | s->irqst[0] &= ~value; | |
3080 | omap_prcm_int_update(s, 0); | |
3081 | break; | |
3082 | case 0x01c: /* PRCM_IRQENABLE_MPU */ | |
3083 | s->irqen[0] = value & 0x3f; | |
3084 | omap_prcm_int_update(s, 0); | |
3085 | break; | |
3086 | ||
3087 | case 0x050: /* PRCM_VOLTCTRL */ | |
3088 | s->voltctrl = value & 0xf1c3; | |
3089 | break; | |
3090 | ||
3091 | case 0x060: /* PRCM_CLKSRC_CTRL */ | |
3092 | s->clksrc[0] = value & 0xdb; | |
3093 | /* TODO update clocks */ | |
3094 | break; | |
3095 | ||
3096 | case 0x070: /* PRCM_CLKOUT_CTRL */ | |
3097 | s->clkout[0] = value & 0xbbbb; | |
3098 | /* TODO update clocks */ | |
3099 | break; | |
3100 | ||
3101 | case 0x078: /* PRCM_CLKEMUL_CTRL */ | |
3102 | s->clkemul[0] = value & 1; | |
3103 | /* TODO update clocks */ | |
3104 | break; | |
3105 | ||
3106 | case 0x080: /* PRCM_CLKCFG_CTRL */ | |
3107 | break; | |
3108 | ||
3109 | case 0x090: /* PRCM_VOLTSETUP */ | |
3110 | s->setuptime[0] = value & 0xffff; | |
3111 | break; | |
3112 | case 0x094: /* PRCM_CLKSSETUP */ | |
3113 | s->setuptime[1] = value & 0xffff; | |
3114 | break; | |
3115 | ||
3116 | case 0x098: /* PRCM_POLCTRL */ | |
3117 | s->clkpol[0] = value & 0x701; | |
3118 | break; | |
3119 | ||
3120 | case 0x0b0: /* GENERAL_PURPOSE1 */ | |
3121 | case 0x0b4: /* GENERAL_PURPOSE2 */ | |
3122 | case 0x0b8: /* GENERAL_PURPOSE3 */ | |
3123 | case 0x0bc: /* GENERAL_PURPOSE4 */ | |
3124 | case 0x0c0: /* GENERAL_PURPOSE5 */ | |
3125 | case 0x0c4: /* GENERAL_PURPOSE6 */ | |
3126 | case 0x0c8: /* GENERAL_PURPOSE7 */ | |
3127 | case 0x0cc: /* GENERAL_PURPOSE8 */ | |
3128 | case 0x0d0: /* GENERAL_PURPOSE9 */ | |
3129 | case 0x0d4: /* GENERAL_PURPOSE10 */ | |
3130 | case 0x0d8: /* GENERAL_PURPOSE11 */ | |
3131 | case 0x0dc: /* GENERAL_PURPOSE12 */ | |
3132 | case 0x0e0: /* GENERAL_PURPOSE13 */ | |
3133 | case 0x0e4: /* GENERAL_PURPOSE14 */ | |
3134 | case 0x0e8: /* GENERAL_PURPOSE15 */ | |
3135 | case 0x0ec: /* GENERAL_PURPOSE16 */ | |
3136 | case 0x0f0: /* GENERAL_PURPOSE17 */ | |
3137 | case 0x0f4: /* GENERAL_PURPOSE18 */ | |
3138 | case 0x0f8: /* GENERAL_PURPOSE19 */ | |
3139 | case 0x0fc: /* GENERAL_PURPOSE20 */ | |
3140 | s->scratch[(offset - 0xb0) >> 2] = value; | |
3141 | break; | |
3142 | ||
3143 | case 0x140: /* CM_CLKSEL_MPU */ | |
3144 | s->clksel[0] = value & 0x1f; | |
3145 | /* TODO update clocks */ | |
3146 | break; | |
3147 | case 0x148: /* CM_CLKSTCTRL_MPU */ | |
3148 | s->clkctrl[0] = value & 0x1f; | |
3149 | break; | |
3150 | ||
3151 | case 0x158: /* RM_RSTST_MPU */ | |
3152 | s->rst[0] &= ~value; | |
3153 | break; | |
3154 | case 0x1c8: /* PM_WKDEP_MPU */ | |
3155 | s->wkup[0] = value & 0x15; | |
3156 | break; | |
3157 | ||
3158 | case 0x1d4: /* PM_EVGENCTRL_MPU */ | |
3159 | s->ev = value & 0x1f; | |
3160 | break; | |
3161 | case 0x1d8: /* PM_EVEGENONTIM_MPU */ | |
3162 | s->evtime[0] = value; | |
3163 | break; | |
3164 | case 0x1dc: /* PM_EVEGENOFFTIM_MPU */ | |
3165 | s->evtime[1] = value; | |
3166 | break; | |
3167 | ||
3168 | case 0x1e0: /* PM_PWSTCTRL_MPU */ | |
3169 | s->power[0] = value & 0xc0f; | |
3170 | break; | |
3171 | ||
3172 | case 0x200: /* CM_FCLKEN1_CORE */ | |
3173 | s->clken[0] = value & 0xbfffffff; | |
3174 | /* TODO update clocks */ | |
99570a40 | 3175 | /* The EN_EAC bit only gets/puts func_96m_clk. */ |
827df9f3 AZ |
3176 | break; |
3177 | case 0x204: /* CM_FCLKEN2_CORE */ | |
3178 | s->clken[1] = value & 0x00000007; | |
3179 | /* TODO update clocks */ | |
3180 | break; | |
3181 | case 0x210: /* CM_ICLKEN1_CORE */ | |
3182 | s->clken[2] = value & 0xfffffff9; | |
3183 | /* TODO update clocks */ | |
99570a40 | 3184 | /* The EN_EAC bit only gets/puts core_l4_iclk. */ |
827df9f3 AZ |
3185 | break; |
3186 | case 0x214: /* CM_ICLKEN2_CORE */ | |
3187 | s->clken[3] = value & 0x00000007; | |
3188 | /* TODO update clocks */ | |
3189 | break; | |
3190 | case 0x21c: /* CM_ICLKEN4_CORE */ | |
3191 | s->clken[4] = value & 0x0000001f; | |
3192 | /* TODO update clocks */ | |
3193 | break; | |
3194 | ||
3195 | case 0x230: /* CM_AUTOIDLE1_CORE */ | |
3196 | s->clkidle[0] = value & 0xfffffff9; | |
3197 | /* TODO update clocks */ | |
3198 | break; | |
3199 | case 0x234: /* CM_AUTOIDLE2_CORE */ | |
3200 | s->clkidle[1] = value & 0x00000007; | |
3201 | /* TODO update clocks */ | |
3202 | break; | |
3203 | case 0x238: /* CM_AUTOIDLE3_CORE */ | |
3204 | s->clkidle[2] = value & 0x00000007; | |
3205 | /* TODO update clocks */ | |
3206 | break; | |
3207 | case 0x23c: /* CM_AUTOIDLE4_CORE */ | |
3208 | s->clkidle[3] = value & 0x0000001f; | |
3209 | /* TODO update clocks */ | |
3210 | break; | |
3211 | ||
3212 | case 0x240: /* CM_CLKSEL1_CORE */ | |
3213 | s->clksel[1] = value & 0x0fffbf7f; | |
3214 | /* TODO update clocks */ | |
3215 | break; | |
3216 | ||
3217 | case 0x244: /* CM_CLKSEL2_CORE */ | |
3218 | s->clksel[2] = value & 0x00fffffc; | |
3219 | /* TODO update clocks */ | |
3220 | break; | |
3221 | ||
3222 | case 0x248: /* CM_CLKSTCTRL_CORE */ | |
3223 | s->clkctrl[1] = value & 0x7; | |
3224 | break; | |
3225 | ||
3226 | case 0x2a0: /* PM_WKEN1_CORE */ | |
3227 | s->wken[0] = value & 0x04667ff8; | |
3228 | break; | |
3229 | case 0x2a4: /* PM_WKEN2_CORE */ | |
3230 | s->wken[1] = value & 0x00000005; | |
3231 | break; | |
3232 | ||
3233 | case 0x2b0: /* PM_WKST1_CORE */ | |
3234 | s->wkst[0] &= ~value; | |
3235 | break; | |
3236 | case 0x2b4: /* PM_WKST2_CORE */ | |
3237 | s->wkst[1] &= ~value; | |
3238 | break; | |
3239 | ||
3240 | case 0x2e0: /* PM_PWSTCTRL_CORE */ | |
3241 | s->power[1] = (value & 0x00fc3f) | (1 << 2); | |
3242 | break; | |
3243 | ||
3244 | case 0x300: /* CM_FCLKEN_GFX */ | |
3245 | s->clken[5] = value & 6; | |
3246 | /* TODO update clocks */ | |
3247 | break; | |
3248 | case 0x310: /* CM_ICLKEN_GFX */ | |
3249 | s->clken[6] = value & 1; | |
3250 | /* TODO update clocks */ | |
3251 | break; | |
3252 | case 0x340: /* CM_CLKSEL_GFX */ | |
3253 | s->clksel[3] = value & 7; | |
3254 | /* TODO update clocks */ | |
3255 | break; | |
3256 | case 0x348: /* CM_CLKSTCTRL_GFX */ | |
3257 | s->clkctrl[2] = value & 1; | |
3258 | break; | |
3259 | case 0x350: /* RM_RSTCTRL_GFX */ | |
3260 | s->rstctrl[0] = value & 1; | |
3261 | /* TODO: reset */ | |
3262 | break; | |
3263 | case 0x358: /* RM_RSTST_GFX */ | |
3264 | s->rst[1] &= ~value; | |
3265 | break; | |
3266 | case 0x3c8: /* PM_WKDEP_GFX */ | |
3267 | s->wkup[1] = value & 0x13; | |
3268 | break; | |
3269 | case 0x3e0: /* PM_PWSTCTRL_GFX */ | |
3270 | s->power[2] = (value & 0x00c0f) | (3 << 2); | |
3271 | break; | |
3272 | ||
3273 | case 0x400: /* CM_FCLKEN_WKUP */ | |
3274 | s->clken[7] = value & 0xd; | |
3275 | /* TODO update clocks */ | |
3276 | break; | |
3277 | case 0x410: /* CM_ICLKEN_WKUP */ | |
3278 | s->clken[8] = value & 0x3f; | |
3279 | /* TODO update clocks */ | |
3280 | break; | |
3281 | case 0x430: /* CM_AUTOIDLE_WKUP */ | |
3282 | s->clkidle[4] = value & 0x0000003f; | |
3283 | /* TODO update clocks */ | |
3284 | break; | |
3285 | case 0x440: /* CM_CLKSEL_WKUP */ | |
3286 | s->clksel[4] = value & 3; | |
3287 | /* TODO update clocks */ | |
3288 | break; | |
3289 | case 0x450: /* RM_RSTCTRL_WKUP */ | |
3290 | /* TODO: reset */ | |
3291 | if (value & 2) | |
3292 | qemu_system_reset_request(); | |
3293 | break; | |
3294 | case 0x454: /* RM_RSTTIME_WKUP */ | |
3295 | s->rsttime_wkup = value & 0x1fff; | |
3296 | break; | |
3297 | case 0x458: /* RM_RSTST_WKUP */ | |
3298 | s->rst[2] &= ~value; | |
3299 | break; | |
3300 | case 0x4a0: /* PM_WKEN_WKUP */ | |
3301 | s->wken[2] = value & 0x00000005; | |
3302 | break; | |
3303 | case 0x4b0: /* PM_WKST_WKUP */ | |
3304 | s->wkst[2] &= ~value; | |
3305 | break; | |
3306 | ||
3307 | case 0x500: /* CM_CLKEN_PLL */ | |
51fec3cc AZ |
3308 | if (value & 0xffffff30) |
3309 | fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for " | |
3310 | "future compatiblity\n", __FUNCTION__); | |
3311 | if ((s->clken[9] ^ value) & 0xcc) { | |
3312 | s->clken[9] &= ~0xcc; | |
3313 | s->clken[9] |= value & 0xcc; | |
3314 | omap_prcm_apll_update(s); | |
3315 | } | |
3316 | if ((s->clken[9] ^ value) & 3) { | |
3317 | s->clken[9] &= ~3; | |
3318 | s->clken[9] |= value & 3; | |
3319 | omap_prcm_dpll_update(s); | |
3320 | } | |
827df9f3 AZ |
3321 | break; |
3322 | case 0x530: /* CM_AUTOIDLE_PLL */ | |
3323 | s->clkidle[5] = value & 0x000000cf; | |
3324 | /* TODO update clocks */ | |
3325 | break; | |
3326 | case 0x540: /* CM_CLKSEL1_PLL */ | |
51fec3cc AZ |
3327 | if (value & 0xfc4000d7) |
3328 | fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for " | |
3329 | "future compatiblity\n", __FUNCTION__); | |
3330 | if ((s->clksel[5] ^ value) & 0x003fff00) { | |
3331 | s->clksel[5] = value & 0x03bfff28; | |
3332 | omap_prcm_dpll_update(s); | |
3333 | } | |
3334 | /* TODO update the other clocks */ | |
3335 | ||
827df9f3 | 3336 | s->clksel[5] = value & 0x03bfff28; |
827df9f3 AZ |
3337 | break; |
3338 | case 0x544: /* CM_CLKSEL2_PLL */ | |
51fec3cc AZ |
3339 | if (value & ~3) |
3340 | fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for " | |
3341 | "future compatiblity\n", __FUNCTION__); | |
3342 | if (s->clksel[6] != (value & 3)) { | |
3343 | s->clksel[6] = value & 3; | |
3344 | omap_prcm_dpll_update(s); | |
3345 | } | |
827df9f3 AZ |
3346 | break; |
3347 | ||
3348 | case 0x800: /* CM_FCLKEN_DSP */ | |
3349 | s->clken[10] = value & 0x501; | |
3350 | /* TODO update clocks */ | |
3351 | break; | |
3352 | case 0x810: /* CM_ICLKEN_DSP */ | |
3353 | s->clken[11] = value & 0x2; | |
3354 | /* TODO update clocks */ | |
3355 | break; | |
3356 | case 0x830: /* CM_AUTOIDLE_DSP */ | |
3357 | s->clkidle[6] = value & 0x2; | |
3358 | /* TODO update clocks */ | |
3359 | break; | |
3360 | case 0x840: /* CM_CLKSEL_DSP */ | |
3361 | s->clksel[7] = value & 0x3fff; | |
3362 | /* TODO update clocks */ | |
3363 | break; | |
3364 | case 0x848: /* CM_CLKSTCTRL_DSP */ | |
3365 | s->clkctrl[3] = value & 0x101; | |
3366 | break; | |
3367 | case 0x850: /* RM_RSTCTRL_DSP */ | |
3368 | /* TODO: reset */ | |
3369 | break; | |
3370 | case 0x858: /* RM_RSTST_DSP */ | |
3371 | s->rst[3] &= ~value; | |
3372 | break; | |
3373 | case 0x8c8: /* PM_WKDEP_DSP */ | |
3374 | s->wkup[2] = value & 0x13; | |
3375 | break; | |
3376 | case 0x8e0: /* PM_PWSTCTRL_DSP */ | |
3377 | s->power[3] = (value & 0x03017) | (3 << 2); | |
3378 | break; | |
3379 | ||
3380 | case 0x8f0: /* PRCM_IRQSTATUS_DSP */ | |
3381 | s->irqst[1] &= ~value; | |
3382 | omap_prcm_int_update(s, 1); | |
3383 | break; | |
3384 | case 0x8f4: /* PRCM_IRQENABLE_DSP */ | |
3385 | s->irqen[1] = value & 0x7; | |
3386 | omap_prcm_int_update(s, 1); | |
3387 | break; | |
3388 | ||
3389 | case 0x8f8: /* PRCM_IRQSTATUS_IVA */ | |
3390 | s->irqst[2] &= ~value; | |
3391 | omap_prcm_int_update(s, 2); | |
3392 | break; | |
3393 | case 0x8fc: /* PRCM_IRQENABLE_IVA */ | |
3394 | s->irqen[2] = value & 0x7; | |
3395 | omap_prcm_int_update(s, 2); | |
3396 | break; | |
3397 | ||
3398 | default: | |
3399 | OMAP_BAD_REG(addr); | |
3400 | return; | |
3401 | } | |
3402 | } | |
3403 | ||
3404 | static CPUReadMemoryFunc *omap_prcm_readfn[] = { | |
3405 | omap_badwidth_read32, | |
3406 | omap_badwidth_read32, | |
3407 | omap_prcm_read, | |
3408 | }; | |
3409 | ||
3410 | static CPUWriteMemoryFunc *omap_prcm_writefn[] = { | |
3411 | omap_badwidth_write32, | |
3412 | omap_badwidth_write32, | |
3413 | omap_prcm_write, | |
3414 | }; | |
3415 | ||
3416 | static void omap_prcm_reset(struct omap_prcm_s *s) | |
3417 | { | |
3418 | s->sysconfig = 0; | |
3419 | s->irqst[0] = 0; | |
3420 | s->irqst[1] = 0; | |
3421 | s->irqst[2] = 0; | |
3422 | s->irqen[0] = 0; | |
3423 | s->irqen[1] = 0; | |
3424 | s->irqen[2] = 0; | |
3425 | s->voltctrl = 0x1040; | |
3426 | s->ev = 0x14; | |
3427 | s->evtime[0] = 0; | |
3428 | s->evtime[1] = 0; | |
3429 | s->clkctrl[0] = 0; | |
3430 | s->clkctrl[1] = 0; | |
3431 | s->clkctrl[2] = 0; | |
3432 | s->clkctrl[3] = 0; | |
3433 | s->clken[1] = 7; | |
3434 | s->clken[3] = 7; | |
3435 | s->clken[4] = 0; | |
3436 | s->clken[5] = 0; | |
3437 | s->clken[6] = 0; | |
3438 | s->clken[7] = 0xc; | |
3439 | s->clken[8] = 0x3e; | |
3440 | s->clken[9] = 0x0d; | |
3441 | s->clken[10] = 0; | |
3442 | s->clken[11] = 0; | |
3443 | s->clkidle[0] = 0; | |
3444 | s->clkidle[2] = 7; | |
3445 | s->clkidle[3] = 0; | |
3446 | s->clkidle[4] = 0; | |
3447 | s->clkidle[5] = 0x0c; | |
3448 | s->clkidle[6] = 0; | |
3449 | s->clksel[0] = 0x01; | |
3450 | s->clksel[1] = 0x02100121; | |
3451 | s->clksel[2] = 0x00000000; | |
3452 | s->clksel[3] = 0x01; | |
3453 | s->clksel[4] = 0; | |
3454 | s->clksel[7] = 0x0121; | |
3455 | s->wkup[0] = 0x15; | |
3456 | s->wkup[1] = 0x13; | |
3457 | s->wkup[2] = 0x13; | |
3458 | s->wken[0] = 0x04667ff8; | |
3459 | s->wken[1] = 0x00000005; | |
3460 | s->wken[2] = 5; | |
3461 | s->wkst[0] = 0; | |
3462 | s->wkst[1] = 0; | |
3463 | s->wkst[2] = 0; | |
3464 | s->power[0] = 0x00c; | |
3465 | s->power[1] = 4; | |
3466 | s->power[2] = 0x0000c; | |
3467 | s->power[3] = 0x14; | |
3468 | s->rstctrl[0] = 1; | |
3469 | s->rst[3] = 1; | |
51fec3cc AZ |
3470 | omap_prcm_apll_update(s); |
3471 | omap_prcm_dpll_update(s); | |
827df9f3 AZ |
3472 | } |
3473 | ||
3474 | static void omap_prcm_coldreset(struct omap_prcm_s *s) | |
3475 | { | |
3476 | s->setuptime[0] = 0; | |
3477 | s->setuptime[1] = 0; | |
3478 | memset(&s->scratch, 0, sizeof(s->scratch)); | |
3479 | s->rst[0] = 0x01; | |
3480 | s->rst[1] = 0x00; | |
3481 | s->rst[2] = 0x01; | |
3482 | s->clken[0] = 0; | |
3483 | s->clken[2] = 0; | |
3484 | s->clkidle[1] = 0; | |
3485 | s->clksel[5] = 0; | |
3486 | s->clksel[6] = 2; | |
3487 | s->clksrc[0] = 0x43; | |
3488 | s->clkout[0] = 0x0303; | |
3489 | s->clkemul[0] = 0; | |
3490 | s->clkpol[0] = 0x100; | |
3491 | s->rsttime_wkup = 0x1002; | |
3492 | ||
3493 | omap_prcm_reset(s); | |
3494 | } | |
3495 | ||
3496 | struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, | |
3497 | qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, | |
3498 | struct omap_mpu_state_s *mpu) | |
3499 | { | |
3500 | int iomemtype; | |
3501 | struct omap_prcm_s *s = (struct omap_prcm_s *) | |
3502 | qemu_mallocz(sizeof(struct omap_prcm_s)); | |
3503 | ||
3504 | s->irq[0] = mpu_int; | |
3505 | s->irq[1] = dsp_int; | |
3506 | s->irq[2] = iva_int; | |
3507 | s->mpu = mpu; | |
3508 | omap_prcm_coldreset(s); | |
3509 | ||
c66fb5bc | 3510 | iomemtype = l4_register_io_memory(0, omap_prcm_readfn, |
827df9f3 AZ |
3511 | omap_prcm_writefn, s); |
3512 | s->base = omap_l4_attach(ta, 0, iomemtype); | |
3513 | omap_l4_attach(ta, 1, iomemtype); | |
3514 | ||
3515 | return s; | |
3516 | } | |
3517 | ||
3518 | /* System and Pinout control */ | |
3519 | struct omap_sysctl_s { | |
3520 | target_phys_addr_t base; | |
3521 | struct omap_mpu_state_s *mpu; | |
3522 | ||
3523 | uint32_t sysconfig; | |
3524 | uint32_t devconfig; | |
3525 | uint32_t psaconfig; | |
3526 | uint32_t padconf[0x45]; | |
3527 | uint8_t obs; | |
3528 | uint32_t msuspendmux[5]; | |
3529 | }; | |
3530 | ||
3531 | static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr) | |
3532 | { | |
3533 | struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; | |
3534 | int offset = addr - s->base; | |
3535 | ||
3536 | switch (offset) { | |
3537 | case 0x000: /* CONTROL_REVISION */ | |
3538 | return 0x20; | |
3539 | ||
3540 | case 0x010: /* CONTROL_SYSCONFIG */ | |
3541 | return s->sysconfig; | |
3542 | ||
3543 | case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ | |
3544 | return s->padconf[(offset - 0x30) >> 2]; | |
3545 | ||
3546 | case 0x270: /* CONTROL_DEBOBS */ | |
3547 | return s->obs; | |
3548 | ||
3549 | case 0x274: /* CONTROL_DEVCONF */ | |
3550 | return s->devconfig; | |
3551 | ||
3552 | case 0x28c: /* CONTROL_EMU_SUPPORT */ | |
3553 | return 0; | |
3554 | ||
3555 | case 0x290: /* CONTROL_MSUSPENDMUX_0 */ | |
3556 | return s->msuspendmux[0]; | |
3557 | case 0x294: /* CONTROL_MSUSPENDMUX_1 */ | |
3558 | return s->msuspendmux[1]; | |
3559 | case 0x298: /* CONTROL_MSUSPENDMUX_2 */ | |
3560 | return s->msuspendmux[2]; | |
3561 | case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ | |
3562 | return s->msuspendmux[3]; | |
3563 | case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ | |
3564 | return s->msuspendmux[4]; | |
3565 | case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ | |
3566 | return 0; | |
3567 | ||
3568 | case 0x2b8: /* CONTROL_PSA_CTRL */ | |
3569 | return s->psaconfig; | |
3570 | case 0x2bc: /* CONTROL_PSA_CMD */ | |
3571 | case 0x2c0: /* CONTROL_PSA_VALUE */ | |
3572 | return 0; | |
3573 | ||
3574 | case 0x2b0: /* CONTROL_SEC_CTRL */ | |
3575 | return 0x800000f1; | |
3576 | case 0x2d0: /* CONTROL_SEC_EMU */ | |
3577 | return 0x80000015; | |
3578 | case 0x2d4: /* CONTROL_SEC_TAP */ | |
3579 | return 0x8000007f; | |
3580 | case 0x2b4: /* CONTROL_SEC_TEST */ | |
3581 | case 0x2f0: /* CONTROL_SEC_STATUS */ | |
3582 | case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ | |
3583 | /* Secure mode is not present on general-pusrpose device. Outside | |
3584 | * secure mode these values cannot be read or written. */ | |
3585 | return 0; | |
3586 | ||
3587 | case 0x2d8: /* CONTROL_OCM_RAM_PERM */ | |
3588 | return 0xff; | |
3589 | case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ | |
3590 | case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ | |
3591 | case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ | |
3592 | /* No secure mode so no Extended Secure RAM present. */ | |
3593 | return 0; | |
3594 | ||
3595 | case 0x2f8: /* CONTROL_STATUS */ | |
3596 | /* Device Type => General-purpose */ | |
3597 | return 0x0300; | |
3598 | case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ | |
3599 | ||
3600 | case 0x300: /* CONTROL_RPUB_KEY_H_0 */ | |
3601 | case 0x304: /* CONTROL_RPUB_KEY_H_1 */ | |
3602 | case 0x308: /* CONTROL_RPUB_KEY_H_2 */ | |
3603 | case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ | |
3604 | return 0xdecafbad; | |
3605 | ||
3606 | case 0x310: /* CONTROL_RAND_KEY_0 */ | |
3607 | case 0x314: /* CONTROL_RAND_KEY_1 */ | |
3608 | case 0x318: /* CONTROL_RAND_KEY_2 */ | |
3609 | case 0x31c: /* CONTROL_RAND_KEY_3 */ | |
3610 | case 0x320: /* CONTROL_CUST_KEY_0 */ | |
3611 | case 0x324: /* CONTROL_CUST_KEY_1 */ | |
3612 | case 0x330: /* CONTROL_TEST_KEY_0 */ | |
3613 | case 0x334: /* CONTROL_TEST_KEY_1 */ | |
3614 | case 0x338: /* CONTROL_TEST_KEY_2 */ | |
3615 | case 0x33c: /* CONTROL_TEST_KEY_3 */ | |
3616 | case 0x340: /* CONTROL_TEST_KEY_4 */ | |
3617 | case 0x344: /* CONTROL_TEST_KEY_5 */ | |
3618 | case 0x348: /* CONTROL_TEST_KEY_6 */ | |
3619 | case 0x34c: /* CONTROL_TEST_KEY_7 */ | |
3620 | case 0x350: /* CONTROL_TEST_KEY_8 */ | |
3621 | case 0x354: /* CONTROL_TEST_KEY_9 */ | |
3622 | /* Can only be accessed in secure mode and when C_FieldAccEnable | |
3623 | * bit is set in CONTROL_SEC_CTRL. | |
3624 | * TODO: otherwise an interconnect access error is generated. */ | |
3625 | return 0; | |
3626 | } | |
3627 | ||
3628 | OMAP_BAD_REG(addr); | |
3629 | return 0; | |
3630 | } | |
3631 | ||
3632 | static void omap_sysctl_write(void *opaque, target_phys_addr_t addr, | |
3633 | uint32_t value) | |
3634 | { | |
3635 | struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; | |
3636 | int offset = addr - s->base; | |
3637 | ||
3638 | switch (offset) { | |
3639 | case 0x000: /* CONTROL_REVISION */ | |
3640 | case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */ | |
3641 | case 0x2c0: /* CONTROL_PSA_VALUE */ | |
3642 | case 0x2f8: /* CONTROL_STATUS */ | |
3643 | case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */ | |
3644 | case 0x300: /* CONTROL_RPUB_KEY_H_0 */ | |
3645 | case 0x304: /* CONTROL_RPUB_KEY_H_1 */ | |
3646 | case 0x308: /* CONTROL_RPUB_KEY_H_2 */ | |
3647 | case 0x30c: /* CONTROL_RPUB_KEY_H_3 */ | |
3648 | case 0x310: /* CONTROL_RAND_KEY_0 */ | |
3649 | case 0x314: /* CONTROL_RAND_KEY_1 */ | |
3650 | case 0x318: /* CONTROL_RAND_KEY_2 */ | |
3651 | case 0x31c: /* CONTROL_RAND_KEY_3 */ | |
3652 | case 0x320: /* CONTROL_CUST_KEY_0 */ | |
3653 | case 0x324: /* CONTROL_CUST_KEY_1 */ | |
3654 | case 0x330: /* CONTROL_TEST_KEY_0 */ | |
3655 | case 0x334: /* CONTROL_TEST_KEY_1 */ | |
3656 | case 0x338: /* CONTROL_TEST_KEY_2 */ | |
3657 | case 0x33c: /* CONTROL_TEST_KEY_3 */ | |
3658 | case 0x340: /* CONTROL_TEST_KEY_4 */ | |
3659 | case 0x344: /* CONTROL_TEST_KEY_5 */ | |
3660 | case 0x348: /* CONTROL_TEST_KEY_6 */ | |
3661 | case 0x34c: /* CONTROL_TEST_KEY_7 */ | |
3662 | case 0x350: /* CONTROL_TEST_KEY_8 */ | |
3663 | case 0x354: /* CONTROL_TEST_KEY_9 */ | |
3664 | OMAP_RO_REG(addr); | |
3665 | return; | |
3666 | ||
3667 | case 0x010: /* CONTROL_SYSCONFIG */ | |
3668 | s->sysconfig = value & 0x1e; | |
3669 | break; | |
3670 | ||
3671 | case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */ | |
3672 | /* XXX: should check constant bits */ | |
3673 | s->padconf[(offset - 0x30) >> 2] = value & 0x1f1f1f1f; | |
3674 | break; | |
3675 | ||
3676 | case 0x270: /* CONTROL_DEBOBS */ | |
3677 | s->obs = value & 0xff; | |
3678 | break; | |
3679 | ||
3680 | case 0x274: /* CONTROL_DEVCONF */ | |
3681 | s->devconfig = value & 0xffffc7ff; | |
3682 | break; | |
3683 | ||
3684 | case 0x28c: /* CONTROL_EMU_SUPPORT */ | |
3685 | break; | |
3686 | ||
3687 | case 0x290: /* CONTROL_MSUSPENDMUX_0 */ | |
3688 | s->msuspendmux[0] = value & 0x3fffffff; | |
3689 | break; | |
3690 | case 0x294: /* CONTROL_MSUSPENDMUX_1 */ | |
3691 | s->msuspendmux[1] = value & 0x3fffffff; | |
3692 | break; | |
3693 | case 0x298: /* CONTROL_MSUSPENDMUX_2 */ | |
3694 | s->msuspendmux[2] = value & 0x3fffffff; | |
3695 | break; | |
3696 | case 0x29c: /* CONTROL_MSUSPENDMUX_3 */ | |
3697 | s->msuspendmux[3] = value & 0x3fffffff; | |
3698 | break; | |
3699 | case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */ | |
3700 | s->msuspendmux[4] = value & 0x3fffffff; | |
3701 | break; | |
3702 | ||
3703 | case 0x2b8: /* CONTROL_PSA_CTRL */ | |
3704 | s->psaconfig = value & 0x1c; | |
3705 | s->psaconfig |= (value & 0x20) ? 2 : 1; | |
3706 | break; | |
3707 | case 0x2bc: /* CONTROL_PSA_CMD */ | |
3708 | break; | |
3709 | ||
3710 | case 0x2b0: /* CONTROL_SEC_CTRL */ | |
3711 | case 0x2b4: /* CONTROL_SEC_TEST */ | |
3712 | case 0x2d0: /* CONTROL_SEC_EMU */ | |
3713 | case 0x2d4: /* CONTROL_SEC_TAP */ | |
3714 | case 0x2d8: /* CONTROL_OCM_RAM_PERM */ | |
3715 | case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */ | |
3716 | case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */ | |
3717 | case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */ | |
3718 | case 0x2f0: /* CONTROL_SEC_STATUS */ | |
3719 | case 0x2f4: /* CONTROL_SEC_ERR_STATUS */ | |
3720 | break; | |
3721 | ||
3722 | default: | |
3723 | OMAP_BAD_REG(addr); | |
3724 | return; | |
3725 | } | |
3726 | } | |
3727 | ||
3728 | static CPUReadMemoryFunc *omap_sysctl_readfn[] = { | |
3729 | omap_badwidth_read32, /* TODO */ | |
3730 | omap_badwidth_read32, /* TODO */ | |
3731 | omap_sysctl_read, | |
3732 | }; | |
3733 | ||
3734 | static CPUWriteMemoryFunc *omap_sysctl_writefn[] = { | |
3735 | omap_badwidth_write32, /* TODO */ | |
3736 | omap_badwidth_write32, /* TODO */ | |
3737 | omap_sysctl_write, | |
3738 | }; | |
3739 | ||
3740 | static void omap_sysctl_reset(struct omap_sysctl_s *s) | |
3741 | { | |
3742 | /* (power-on reset) */ | |
3743 | s->sysconfig = 0; | |
3744 | s->obs = 0; | |
3745 | s->devconfig = 0x0c000000; | |
3746 | s->msuspendmux[0] = 0x00000000; | |
3747 | s->msuspendmux[1] = 0x00000000; | |
3748 | s->msuspendmux[2] = 0x00000000; | |
3749 | s->msuspendmux[3] = 0x00000000; | |
3750 | s->msuspendmux[4] = 0x00000000; | |
3751 | s->psaconfig = 1; | |
3752 | ||
3753 | s->padconf[0x00] = 0x000f0f0f; | |
3754 | s->padconf[0x01] = 0x00000000; | |
3755 | s->padconf[0x02] = 0x00000000; | |
3756 | s->padconf[0x03] = 0x00000000; | |
3757 | s->padconf[0x04] = 0x00000000; | |
3758 | s->padconf[0x05] = 0x00000000; | |
3759 | s->padconf[0x06] = 0x00000000; | |
3760 | s->padconf[0x07] = 0x00000000; | |
3761 | s->padconf[0x08] = 0x08080800; | |
3762 | s->padconf[0x09] = 0x08080808; | |
3763 | s->padconf[0x0a] = 0x08080808; | |
3764 | s->padconf[0x0b] = 0x08080808; | |
3765 | s->padconf[0x0c] = 0x08080808; | |
3766 | s->padconf[0x0d] = 0x08080800; | |
3767 | s->padconf[0x0e] = 0x08080808; | |
3768 | s->padconf[0x0f] = 0x08080808; | |
3769 | s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */ | |
3770 | s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */ | |
3771 | s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */ | |
3772 | s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */ | |
3773 | s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */ | |
3774 | s->padconf[0x15] = 0x18181818; | |
3775 | s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */ | |
3776 | s->padconf[0x17] = 0x1f001f00; | |
3777 | s->padconf[0x18] = 0x1f1f1f1f; | |
3778 | s->padconf[0x19] = 0x00000000; | |
3779 | s->padconf[0x1a] = 0x1f180000; | |
3780 | s->padconf[0x1b] = 0x00001f1f; | |
3781 | s->padconf[0x1c] = 0x1f001f00; | |
3782 | s->padconf[0x1d] = 0x00000000; | |
3783 | s->padconf[0x1e] = 0x00000000; | |
3784 | s->padconf[0x1f] = 0x08000000; | |
3785 | s->padconf[0x20] = 0x08080808; | |
3786 | s->padconf[0x21] = 0x08080808; | |
3787 | s->padconf[0x22] = 0x0f080808; | |
3788 | s->padconf[0x23] = 0x0f0f0f0f; | |
3789 | s->padconf[0x24] = 0x000f0f0f; | |
3790 | s->padconf[0x25] = 0x1f1f1f0f; | |
3791 | s->padconf[0x26] = 0x080f0f1f; | |
3792 | s->padconf[0x27] = 0x070f1808; | |
3793 | s->padconf[0x28] = 0x0f070707; | |
3794 | s->padconf[0x29] = 0x000f0f1f; | |
3795 | s->padconf[0x2a] = 0x0f0f0f1f; | |
3796 | s->padconf[0x2b] = 0x08000000; | |
3797 | s->padconf[0x2c] = 0x0000001f; | |
3798 | s->padconf[0x2d] = 0x0f0f1f00; | |
3799 | s->padconf[0x2e] = 0x1f1f0f0f; | |
3800 | s->padconf[0x2f] = 0x0f1f1f1f; | |
3801 | s->padconf[0x30] = 0x0f0f0f0f; | |
3802 | s->padconf[0x31] = 0x0f1f0f1f; | |
3803 | s->padconf[0x32] = 0x0f0f0f0f; | |
3804 | s->padconf[0x33] = 0x0f1f0f1f; | |
3805 | s->padconf[0x34] = 0x1f1f0f0f; | |
3806 | s->padconf[0x35] = 0x0f0f1f1f; | |
3807 | s->padconf[0x36] = 0x0f0f1f0f; | |
3808 | s->padconf[0x37] = 0x0f0f0f0f; | |
3809 | s->padconf[0x38] = 0x1f18180f; | |
3810 | s->padconf[0x39] = 0x1f1f1f1f; | |
3811 | s->padconf[0x3a] = 0x00001f1f; | |
3812 | s->padconf[0x3b] = 0x00000000; | |
3813 | s->padconf[0x3c] = 0x00000000; | |
3814 | s->padconf[0x3d] = 0x0f0f0f0f; | |
3815 | s->padconf[0x3e] = 0x18000f0f; | |
3816 | s->padconf[0x3f] = 0x00070000; | |
3817 | s->padconf[0x40] = 0x00000707; | |
3818 | s->padconf[0x41] = 0x0f1f0700; | |
3819 | s->padconf[0x42] = 0x1f1f070f; | |
3820 | s->padconf[0x43] = 0x0008081f; | |
3821 | s->padconf[0x44] = 0x00000800; | |
3822 | } | |
3823 | ||
3824 | struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, | |
3825 | omap_clk iclk, struct omap_mpu_state_s *mpu) | |
3826 | { | |
3827 | int iomemtype; | |
3828 | struct omap_sysctl_s *s = (struct omap_sysctl_s *) | |
3829 | qemu_mallocz(sizeof(struct omap_sysctl_s)); | |
3830 | ||
3831 | s->mpu = mpu; | |
3832 | omap_sysctl_reset(s); | |
3833 | ||
c66fb5bc | 3834 | iomemtype = l4_register_io_memory(0, omap_sysctl_readfn, |
827df9f3 AZ |
3835 | omap_sysctl_writefn, s); |
3836 | s->base = omap_l4_attach(ta, 0, iomemtype); | |
3837 | omap_l4_attach(ta, 0, iomemtype); | |
3838 | ||
3839 | return s; | |
3840 | } | |
3841 | ||
3842 | /* SDRAM Controller Subsystem */ | |
3843 | struct omap_sdrc_s { | |
3844 | target_phys_addr_t base; | |
3845 | ||
3846 | uint8_t config; | |
3847 | }; | |
3848 | ||
3849 | static void omap_sdrc_reset(struct omap_sdrc_s *s) | |
3850 | { | |
3851 | s->config = 0x10; | |
3852 | } | |
3853 | ||
3854 | static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr) | |
3855 | { | |
3856 | struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; | |
3857 | int offset = addr - s->base; | |
3858 | ||
3859 | switch (offset) { | |
3860 | case 0x00: /* SDRC_REVISION */ | |
3861 | return 0x20; | |
3862 | ||
3863 | case 0x10: /* SDRC_SYSCONFIG */ | |
3864 | return s->config; | |
3865 | ||
3866 | case 0x14: /* SDRC_SYSSTATUS */ | |
3867 | return 1; /* RESETDONE */ | |
3868 | ||
3869 | case 0x40: /* SDRC_CS_CFG */ | |
3870 | case 0x44: /* SDRC_SHARING */ | |
3871 | case 0x48: /* SDRC_ERR_ADDR */ | |
3872 | case 0x4c: /* SDRC_ERR_TYPE */ | |
3873 | case 0x60: /* SDRC_DLLA_SCTRL */ | |
3874 | case 0x64: /* SDRC_DLLA_STATUS */ | |
3875 | case 0x68: /* SDRC_DLLB_CTRL */ | |
3876 | case 0x6c: /* SDRC_DLLB_STATUS */ | |
3877 | case 0x70: /* SDRC_POWER */ | |
3878 | case 0x80: /* SDRC_MCFG_0 */ | |
3879 | case 0x84: /* SDRC_MR_0 */ | |
3880 | case 0x88: /* SDRC_EMR1_0 */ | |
3881 | case 0x8c: /* SDRC_EMR2_0 */ | |
3882 | case 0x90: /* SDRC_EMR3_0 */ | |
3883 | case 0x94: /* SDRC_DCDL1_CTRL */ | |
3884 | case 0x98: /* SDRC_DCDL2_CTRL */ | |
3885 | case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ | |
3886 | case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ | |
3887 | case 0xa4: /* SDRC_RFR_CTRL_0 */ | |
3888 | case 0xa8: /* SDRC_MANUAL_0 */ | |
3889 | case 0xb0: /* SDRC_MCFG_1 */ | |
3890 | case 0xb4: /* SDRC_MR_1 */ | |
3891 | case 0xb8: /* SDRC_EMR1_1 */ | |
3892 | case 0xbc: /* SDRC_EMR2_1 */ | |
3893 | case 0xc0: /* SDRC_EMR3_1 */ | |
3894 | case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ | |
3895 | case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ | |
3896 | case 0xd4: /* SDRC_RFR_CTRL_1 */ | |
3897 | case 0xd8: /* SDRC_MANUAL_1 */ | |
3898 | return 0x00; | |
3899 | } | |
3900 | ||
3901 | OMAP_BAD_REG(addr); | |
3902 | return 0; | |
3903 | } | |
3904 | ||
3905 | static void omap_sdrc_write(void *opaque, target_phys_addr_t addr, | |
3906 | uint32_t value) | |
3907 | { | |
3908 | struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; | |
3909 | int offset = addr - s->base; | |
3910 | ||
3911 | switch (offset) { | |
3912 | case 0x00: /* SDRC_REVISION */ | |
3913 | case 0x14: /* SDRC_SYSSTATUS */ | |
3914 | case 0x48: /* SDRC_ERR_ADDR */ | |
3915 | case 0x64: /* SDRC_DLLA_STATUS */ | |
3916 | case 0x6c: /* SDRC_DLLB_STATUS */ | |
3917 | OMAP_RO_REG(addr); | |
3918 | return; | |
3919 | ||
3920 | case 0x10: /* SDRC_SYSCONFIG */ | |
3921 | if ((value >> 3) != 0x2) | |
3922 | fprintf(stderr, "%s: bad SDRAM idle mode %i\n", | |
3923 | __FUNCTION__, value >> 3); | |
3924 | if (value & 2) | |
3925 | omap_sdrc_reset(s); | |
3926 | s->config = value & 0x18; | |
3927 | break; | |
3928 | ||
3929 | case 0x40: /* SDRC_CS_CFG */ | |
3930 | case 0x44: /* SDRC_SHARING */ | |
3931 | case 0x4c: /* SDRC_ERR_TYPE */ | |
3932 | case 0x60: /* SDRC_DLLA_SCTRL */ | |
3933 | case 0x68: /* SDRC_DLLB_CTRL */ | |
3934 | case 0x70: /* SDRC_POWER */ | |
3935 | case 0x80: /* SDRC_MCFG_0 */ | |
3936 | case 0x84: /* SDRC_MR_0 */ | |
3937 | case 0x88: /* SDRC_EMR1_0 */ | |
3938 | case 0x8c: /* SDRC_EMR2_0 */ | |
3939 | case 0x90: /* SDRC_EMR3_0 */ | |
3940 | case 0x94: /* SDRC_DCDL1_CTRL */ | |
3941 | case 0x98: /* SDRC_DCDL2_CTRL */ | |
3942 | case 0x9c: /* SDRC_ACTIM_CTRLA_0 */ | |
3943 | case 0xa0: /* SDRC_ACTIM_CTRLB_0 */ | |
3944 | case 0xa4: /* SDRC_RFR_CTRL_0 */ | |
3945 | case 0xa8: /* SDRC_MANUAL_0 */ | |
3946 | case 0xb0: /* SDRC_MCFG_1 */ | |
3947 | case 0xb4: /* SDRC_MR_1 */ | |
3948 | case 0xb8: /* SDRC_EMR1_1 */ | |
3949 | case 0xbc: /* SDRC_EMR2_1 */ | |
3950 | case 0xc0: /* SDRC_EMR3_1 */ | |
3951 | case 0xc4: /* SDRC_ACTIM_CTRLA_1 */ | |
3952 | case 0xc8: /* SDRC_ACTIM_CTRLB_1 */ | |
3953 | case 0xd4: /* SDRC_RFR_CTRL_1 */ | |
3954 | case 0xd8: /* SDRC_MANUAL_1 */ | |
3955 | break; | |
3956 | ||
3957 | default: | |
3958 | OMAP_BAD_REG(addr); | |
3959 | return; | |
3960 | } | |
3961 | } | |
3962 | ||
3963 | static CPUReadMemoryFunc *omap_sdrc_readfn[] = { | |
3964 | omap_badwidth_read32, | |
3965 | omap_badwidth_read32, | |
3966 | omap_sdrc_read, | |
3967 | }; | |
3968 | ||
3969 | static CPUWriteMemoryFunc *omap_sdrc_writefn[] = { | |
3970 | omap_badwidth_write32, | |
3971 | omap_badwidth_write32, | |
3972 | omap_sdrc_write, | |
3973 | }; | |
3974 | ||
3975 | struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base) | |
3976 | { | |
3977 | int iomemtype; | |
3978 | struct omap_sdrc_s *s = (struct omap_sdrc_s *) | |
3979 | qemu_mallocz(sizeof(struct omap_sdrc_s)); | |
3980 | ||
3981 | s->base = base; | |
3982 | omap_sdrc_reset(s); | |
3983 | ||
3984 | iomemtype = cpu_register_io_memory(0, omap_sdrc_readfn, | |
3985 | omap_sdrc_writefn, s); | |
3986 | cpu_register_physical_memory(s->base, 0x1000, iomemtype); | |
3987 | ||
3988 | return s; | |
3989 | } | |
3990 | ||
3991 | /* General-Purpose Memory Controller */ | |
3992 | struct omap_gpmc_s { | |
3993 | target_phys_addr_t base; | |
3994 | qemu_irq irq; | |
3995 | ||
3996 | uint8_t sysconfig; | |
3997 | uint16_t irqst; | |
3998 | uint16_t irqen; | |
3999 | uint16_t timeout; | |
4000 | uint16_t config; | |
4001 | uint32_t prefconfig[2]; | |
4002 | int prefcontrol; | |
4003 | int preffifo; | |
4004 | int prefcount; | |
4005 | struct omap_gpmc_cs_file_s { | |
4006 | uint32_t config[7]; | |
4007 | target_phys_addr_t base; | |
4008 | size_t size; | |
4009 | int iomemtype; | |
4010 | void (*base_update)(void *opaque, target_phys_addr_t new); | |
4011 | void (*unmap)(void *opaque); | |
4012 | void *opaque; | |
4013 | } cs_file[8]; | |
4014 | int ecc_cs; | |
4015 | int ecc_ptr; | |
4016 | uint32_t ecc_cfg; | |
4017 | struct ecc_state_s ecc[9]; | |
4018 | }; | |
4019 | ||
4020 | static void omap_gpmc_int_update(struct omap_gpmc_s *s) | |
4021 | { | |
4022 | qemu_set_irq(s->irq, s->irqen & s->irqst); | |
4023 | } | |
4024 | ||
4025 | static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask) | |
4026 | { | |
4027 | /* TODO: check for overlapping regions and report access errors */ | |
4028 | if ((mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf) || | |
4029 | (base < 0 || base >= 0x40) || | |
4030 | (base & 0x0f & ~mask)) { | |
4031 | fprintf(stderr, "%s: wrong cs address mapping/decoding!\n", | |
4032 | __FUNCTION__); | |
4033 | return; | |
4034 | } | |
4035 | ||
4036 | if (!f->opaque) | |
4037 | return; | |
4038 | ||
4039 | f->base = base << 24; | |
4040 | f->size = (0x0fffffff & ~(mask << 24)) + 1; | |
4041 | /* TODO: rather than setting the size of the mapping (which should be | |
4042 | * constant), the mask should cause wrapping of the address space, so | |
4043 | * that the same memory becomes accessible at every <i>size</i> bytes | |
4044 | * starting from <i>base</i>. */ | |
4045 | if (f->iomemtype) | |
4046 | cpu_register_physical_memory(f->base, f->size, f->iomemtype); | |
4047 | ||
4048 | if (f->base_update) | |
4049 | f->base_update(f->opaque, f->base); | |
4050 | } | |
4051 | ||
4052 | static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f) | |
4053 | { | |
4054 | if (f->size) { | |
4055 | if (f->unmap) | |
4056 | f->unmap(f->opaque); | |
4057 | if (f->iomemtype) | |
4058 | cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED); | |
4059 | f->base = 0; | |
4060 | f->size = 0; | |
4061 | } | |
4062 | } | |
4063 | ||
4064 | static void omap_gpmc_reset(struct omap_gpmc_s *s) | |
4065 | { | |
4066 | int i; | |
4067 | ||
4068 | s->sysconfig = 0; | |
4069 | s->irqst = 0; | |
4070 | s->irqen = 0; | |
4071 | omap_gpmc_int_update(s); | |
4072 | s->timeout = 0; | |
4073 | s->config = 0xa00; | |
4074 | s->prefconfig[0] = 0x00004000; | |
4075 | s->prefconfig[1] = 0x00000000; | |
4076 | s->prefcontrol = 0; | |
4077 | s->preffifo = 0; | |
4078 | s->prefcount = 0; | |
4079 | for (i = 0; i < 8; i ++) { | |
4080 | if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */ | |
4081 | omap_gpmc_cs_unmap(s->cs_file + i); | |
4082 | s->cs_file[i].config[0] = i ? 1 << 12 : 0; | |
4083 | s->cs_file[i].config[1] = 0x101001; | |
4084 | s->cs_file[i].config[2] = 0x020201; | |
4085 | s->cs_file[i].config[3] = 0x10031003; | |
4086 | s->cs_file[i].config[4] = 0x10f1111; | |
4087 | s->cs_file[i].config[5] = 0; | |
4088 | s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6); | |
4089 | if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */ | |
4090 | omap_gpmc_cs_map(&s->cs_file[i], | |
4091 | s->cs_file[i].config[6] & 0x1f, /* MASKADDR */ | |
4092 | (s->cs_file[i].config[6] >> 8 & 0xf)); /* BASEADDR */ | |
4093 | } | |
4094 | omap_gpmc_cs_map(s->cs_file, 0, 0xf); | |
4095 | s->ecc_cs = 0; | |
4096 | s->ecc_ptr = 0; | |
4097 | s->ecc_cfg = 0x3fcff000; | |
4098 | for (i = 0; i < 9; i ++) | |
4099 | ecc_reset(&s->ecc[i]); | |
4100 | } | |
4101 | ||
4102 | static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr) | |
4103 | { | |
4104 | struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; | |
4105 | int offset = addr - s->base; | |
4106 | int cs; | |
4107 | struct omap_gpmc_cs_file_s *f; | |
4108 | ||
4109 | switch (offset) { | |
4110 | case 0x000: /* GPMC_REVISION */ | |
4111 | return 0x20; | |
4112 | ||
4113 | case 0x010: /* GPMC_SYSCONFIG */ | |
4114 | return s->sysconfig; | |
4115 | ||
4116 | case 0x014: /* GPMC_SYSSTATUS */ | |
4117 | return 1; /* RESETDONE */ | |
4118 | ||
4119 | case 0x018: /* GPMC_IRQSTATUS */ | |
4120 | return s->irqst; | |
4121 | ||
4122 | case 0x01c: /* GPMC_IRQENABLE */ | |
4123 | return s->irqen; | |
4124 | ||
4125 | case 0x040: /* GPMC_TIMEOUT_CONTROL */ | |
4126 | return s->timeout; | |
4127 | ||
4128 | case 0x044: /* GPMC_ERR_ADDRESS */ | |
4129 | case 0x048: /* GPMC_ERR_TYPE */ | |
4130 | return 0; | |
4131 | ||
4132 | case 0x050: /* GPMC_CONFIG */ | |
4133 | return s->config; | |
4134 | ||
4135 | case 0x054: /* GPMC_STATUS */ | |
4136 | return 0x001; | |
4137 | ||
4138 | case 0x060 ... 0x1d4: | |
4139 | cs = (offset - 0x060) / 0x30; | |
4140 | offset -= cs * 0x30; | |
4141 | f = s->cs_file + cs; | |
4142 | switch (offset - cs * 0x30) { | |
4143 | case 0x60: /* GPMC_CONFIG1 */ | |
4144 | return f->config[0]; | |
4145 | case 0x64: /* GPMC_CONFIG2 */ | |
4146 | return f->config[1]; | |
4147 | case 0x68: /* GPMC_CONFIG3 */ | |
4148 | return f->config[2]; | |
4149 | case 0x6c: /* GPMC_CONFIG4 */ | |
4150 | return f->config[3]; | |
4151 | case 0x70: /* GPMC_CONFIG5 */ | |
4152 | return f->config[4]; | |
4153 | case 0x74: /* GPMC_CONFIG6 */ | |
4154 | return f->config[5]; | |
4155 | case 0x78: /* GPMC_CONFIG7 */ | |
4156 | return f->config[6]; | |
4157 | case 0x84: /* GPMC_NAND_DATA */ | |
4158 | return 0; | |
4159 | } | |
4160 | break; | |
4161 | ||
4162 | case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */ | |
4163 | return s->prefconfig[0]; | |
4164 | case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */ | |
4165 | return s->prefconfig[1]; | |
4166 | case 0x1ec: /* GPMC_PREFETCH_CONTROL */ | |
4167 | return s->prefcontrol; | |
4168 | case 0x1f0: /* GPMC_PREFETCH_STATUS */ | |
4169 | return (s->preffifo << 24) | | |
4170 | ((s->preffifo > | |
4171 | ((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) | | |
4172 | s->prefcount; | |
4173 | ||
4174 | case 0x1f4: /* GPMC_ECC_CONFIG */ | |
4175 | return s->ecc_cs; | |
4176 | case 0x1f8: /* GPMC_ECC_CONTROL */ | |
4177 | return s->ecc_ptr; | |
4178 | case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */ | |
4179 | return s->ecc_cfg; | |
4180 | case 0x200 ... 0x220: /* GPMC_ECC_RESULT */ | |
4181 | cs = (offset & 0x1f) >> 2; | |
4182 | /* TODO: check correctness */ | |
4183 | return | |
4184 | ((s->ecc[cs].cp & 0x07) << 0) | | |
4185 | ((s->ecc[cs].cp & 0x38) << 13) | | |
4186 | ((s->ecc[cs].lp[0] & 0x1ff) << 3) | | |
4187 | ((s->ecc[cs].lp[1] & 0x1ff) << 19); | |
4188 | ||
4189 | case 0x230: /* GPMC_TESTMODE_CTRL */ | |
4190 | return 0; | |
4191 | case 0x234: /* GPMC_PSA_LSB */ | |
4192 | case 0x238: /* GPMC_PSA_MSB */ | |
4193 | return 0x00000000; | |
4194 | } | |
4195 | ||
4196 | OMAP_BAD_REG(addr); | |
4197 | return 0; | |
4198 | } | |
4199 | ||
4200 | static void omap_gpmc_write(void *opaque, target_phys_addr_t addr, | |
4201 | uint32_t value) | |
4202 | { | |
4203 | struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; | |
4204 | int offset = addr - s->base; | |
4205 | int cs; | |
4206 | struct omap_gpmc_cs_file_s *f; | |
4207 | ||
4208 | switch (offset) { | |
4209 | case 0x000: /* GPMC_REVISION */ | |
4210 | case 0x014: /* GPMC_SYSSTATUS */ | |
4211 | case 0x054: /* GPMC_STATUS */ | |
4212 | case 0x1f0: /* GPMC_PREFETCH_STATUS */ | |
4213 | case 0x200 ... 0x220: /* GPMC_ECC_RESULT */ | |
4214 | case 0x234: /* GPMC_PSA_LSB */ | |
4215 | case 0x238: /* GPMC_PSA_MSB */ | |
4216 | OMAP_RO_REG(addr); | |
4217 | break; | |
4218 | ||
4219 | case 0x010: /* GPMC_SYSCONFIG */ | |
4220 | if ((value >> 3) == 0x3) | |
4221 | fprintf(stderr, "%s: bad SDRAM idle mode %i\n", | |
4222 | __FUNCTION__, value >> 3); | |
4223 | if (value & 2) | |
4224 | omap_gpmc_reset(s); | |
4225 | s->sysconfig = value & 0x19; | |
4226 | break; | |
4227 | ||
4228 | case 0x018: /* GPMC_IRQSTATUS */ | |
4229 | s->irqen = ~value; | |
4230 | omap_gpmc_int_update(s); | |
4231 | break; | |
4232 | ||
4233 | case 0x01c: /* GPMC_IRQENABLE */ | |
4234 | s->irqen = value & 0xf03; | |
4235 | omap_gpmc_int_update(s); | |
4236 | break; | |
4237 | ||
4238 | case 0x040: /* GPMC_TIMEOUT_CONTROL */ | |
4239 | s->timeout = value & 0x1ff1; | |
4240 | break; | |
4241 | ||
4242 | case 0x044: /* GPMC_ERR_ADDRESS */ | |
4243 | case 0x048: /* GPMC_ERR_TYPE */ | |
4244 | break; | |
4245 | ||
4246 | case 0x050: /* GPMC_CONFIG */ | |
4247 | s->config = value & 0xf13; | |
4248 | break; | |
4249 | ||
4250 | case 0x060 ... 0x1d4: | |
4251 | cs = (offset - 0x060) / 0x30; | |
4252 | offset -= cs * 0x30; | |
4253 | f = s->cs_file + cs; | |
4254 | switch (offset) { | |
4255 | case 0x60: /* GPMC_CONFIG1 */ | |
4256 | f->config[0] = value & 0xffef3e13; | |
4257 | break; | |
4258 | case 0x64: /* GPMC_CONFIG2 */ | |
4259 | f->config[1] = value & 0x001f1f8f; | |
4260 | break; | |
4261 | case 0x68: /* GPMC_CONFIG3 */ | |
4262 | f->config[2] = value & 0x001f1f8f; | |
4263 | break; | |
4264 | case 0x6c: /* GPMC_CONFIG4 */ | |
4265 | f->config[3] = value & 0x1f8f1f8f; | |
4266 | break; | |
4267 | case 0x70: /* GPMC_CONFIG5 */ | |
4268 | f->config[4] = value & 0x0f1f1f1f; | |
4269 | break; | |
4270 | case 0x74: /* GPMC_CONFIG6 */ | |
4271 | f->config[5] = value & 0x00000fcf; | |
4272 | break; | |
4273 | case 0x78: /* GPMC_CONFIG7 */ | |
4274 | if ((f->config[6] ^ value) & 0xf7f) { | |
4275 | if (f->config[6] & (1 << 6)) /* CSVALID */ | |
4276 | omap_gpmc_cs_unmap(f); | |
4277 | if (value & (1 << 6)) /* CSVALID */ | |
4278 | omap_gpmc_cs_map(f, value & 0x1f, /* MASKADDR */ | |
4279 | (value >> 8 & 0xf)); /* BASEADDR */ | |
4280 | } | |
4281 | f->config[6] = value & 0x00000f7f; | |
4282 | break; | |
4283 | case 0x7c: /* GPMC_NAND_COMMAND */ | |
4284 | case 0x80: /* GPMC_NAND_ADDRESS */ | |
4285 | case 0x84: /* GPMC_NAND_DATA */ | |
4286 | break; | |
4287 | ||
4288 | default: | |
4289 | goto bad_reg; | |
4290 | } | |
4291 | break; | |
4292 | ||
4293 | case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */ | |
4294 | s->prefconfig[0] = value & 0x7f8f7fbf; | |
4295 | /* TODO: update interrupts, fifos, dmas */ | |
4296 | break; | |
4297 | ||
4298 | case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */ | |
4299 | s->prefconfig[1] = value & 0x3fff; | |
4300 | break; | |
4301 | ||
4302 | case 0x1ec: /* GPMC_PREFETCH_CONTROL */ | |
4303 | s->prefcontrol = value & 1; | |
4304 | if (s->prefcontrol) { | |
4305 | if (s->prefconfig[0] & 1) | |
4306 | s->preffifo = 0x40; | |
4307 | else | |
4308 | s->preffifo = 0x00; | |
4309 | } | |
4310 | /* TODO: start */ | |
4311 | break; | |
4312 | ||
4313 | case 0x1f4: /* GPMC_ECC_CONFIG */ | |
4314 | s->ecc_cs = 0x8f; | |
4315 | break; | |
4316 | case 0x1f8: /* GPMC_ECC_CONTROL */ | |
4317 | if (value & (1 << 8)) | |
4318 | for (cs = 0; cs < 9; cs ++) | |
4319 | ecc_reset(&s->ecc[cs]); | |
4320 | s->ecc_ptr = value & 0xf; | |
4321 | if (s->ecc_ptr == 0 || s->ecc_ptr > 9) { | |
4322 | s->ecc_ptr = 0; | |
4323 | s->ecc_cs &= ~1; | |
4324 | } | |
4325 | break; | |
4326 | case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */ | |
4327 | s->ecc_cfg = value & 0x3fcff1ff; | |
4328 | break; | |
4329 | case 0x230: /* GPMC_TESTMODE_CTRL */ | |
4330 | if (value & 7) | |
4331 | fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__); | |
4332 | break; | |
4333 | ||
4334 | default: | |
4335 | bad_reg: | |
4336 | OMAP_BAD_REG(addr); | |
4337 | return; | |
4338 | } | |
4339 | } | |
4340 | ||
4341 | static CPUReadMemoryFunc *omap_gpmc_readfn[] = { | |
4342 | omap_badwidth_read32, /* TODO */ | |
4343 | omap_badwidth_read32, /* TODO */ | |
4344 | omap_gpmc_read, | |
4345 | }; | |
4346 | ||
4347 | static CPUWriteMemoryFunc *omap_gpmc_writefn[] = { | |
4348 | omap_badwidth_write32, /* TODO */ | |
4349 | omap_badwidth_write32, /* TODO */ | |
4350 | omap_gpmc_write, | |
4351 | }; | |
4352 | ||
4353 | struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq) | |
4354 | { | |
4355 | int iomemtype; | |
4356 | struct omap_gpmc_s *s = (struct omap_gpmc_s *) | |
4357 | qemu_mallocz(sizeof(struct omap_gpmc_s)); | |
4358 | ||
4359 | s->base = base; | |
4360 | omap_gpmc_reset(s); | |
4361 | ||
4362 | iomemtype = cpu_register_io_memory(0, omap_gpmc_readfn, | |
4363 | omap_gpmc_writefn, s); | |
4364 | cpu_register_physical_memory(s->base, 0x1000, iomemtype); | |
4365 | ||
4366 | return s; | |
4367 | } | |
4368 | ||
4369 | void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, | |
4370 | void (*base_upd)(void *opaque, target_phys_addr_t new), | |
4371 | void (*unmap)(void *opaque), void *opaque) | |
4372 | { | |
4373 | struct omap_gpmc_cs_file_s *f; | |
4374 | ||
4375 | if (cs < 0 || cs >= 8) { | |
4376 | fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs); | |
4377 | exit(-1); | |
4378 | } | |
4379 | f = &s->cs_file[cs]; | |
4380 | ||
4381 | f->iomemtype = iomemtype; | |
4382 | f->base_update = base_upd; | |
4383 | f->unmap = unmap; | |
4384 | f->opaque = opaque; | |
4385 | ||
4386 | if (f->config[6] & (1 << 6)) /* CSVALID */ | |
4387 | omap_gpmc_cs_map(f, f->config[6] & 0x1f, /* MASKADDR */ | |
4388 | (f->config[6] >> 8 & 0xf)); /* BASEADDR */ | |
4389 | } | |
4390 | ||
4391 | /* General chip reset */ | |
4392 | static void omap2_mpu_reset(void *opaque) | |
4393 | { | |
4394 | struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; | |
4395 | ||
4396 | omap_inth_reset(mpu->ih[0]); | |
4397 | omap_dma_reset(mpu->dma); | |
4398 | omap_prcm_reset(mpu->prcm); | |
4399 | omap_sysctl_reset(mpu->sysc); | |
4400 | omap_gp_timer_reset(mpu->gptimer[0]); | |
4401 | omap_gp_timer_reset(mpu->gptimer[1]); | |
4402 | omap_gp_timer_reset(mpu->gptimer[2]); | |
4403 | omap_gp_timer_reset(mpu->gptimer[3]); | |
4404 | omap_gp_timer_reset(mpu->gptimer[4]); | |
4405 | omap_gp_timer_reset(mpu->gptimer[5]); | |
4406 | omap_gp_timer_reset(mpu->gptimer[6]); | |
4407 | omap_gp_timer_reset(mpu->gptimer[7]); | |
4408 | omap_gp_timer_reset(mpu->gptimer[8]); | |
4409 | omap_gp_timer_reset(mpu->gptimer[9]); | |
4410 | omap_gp_timer_reset(mpu->gptimer[10]); | |
4411 | omap_gp_timer_reset(mpu->gptimer[11]); | |
4412 | omap_synctimer_reset(&mpu->synctimer); | |
4413 | omap_sdrc_reset(mpu->sdrc); | |
4414 | omap_gpmc_reset(mpu->gpmc); | |
4415 | omap_dss_reset(mpu->dss); | |
4416 | omap_uart_reset(mpu->uart[0]); | |
4417 | omap_uart_reset(mpu->uart[1]); | |
4418 | omap_uart_reset(mpu->uart[2]); | |
4419 | omap_mmc_reset(mpu->mmc); | |
4420 | omap_gpif_reset(mpu->gpif); | |
4421 | omap_mcspi_reset(mpu->mcspi[0]); | |
4422 | omap_mcspi_reset(mpu->mcspi[1]); | |
4423 | omap_i2c_reset(mpu->i2c[0]); | |
4424 | omap_i2c_reset(mpu->i2c[1]); | |
4425 | cpu_reset(mpu->env); | |
4426 | } | |
4427 | ||
4428 | static int omap2_validate_addr(struct omap_mpu_state_s *s, | |
4429 | target_phys_addr_t addr) | |
4430 | { | |
4431 | return 1; | |
4432 | } | |
4433 | ||
4434 | static const struct dma_irq_map omap2_dma_irq_map[] = { | |
4435 | { 0, OMAP_INT_24XX_SDMA_IRQ0 }, | |
4436 | { 0, OMAP_INT_24XX_SDMA_IRQ1 }, | |
4437 | { 0, OMAP_INT_24XX_SDMA_IRQ2 }, | |
4438 | { 0, OMAP_INT_24XX_SDMA_IRQ3 }, | |
4439 | }; | |
4440 | ||
4441 | struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, | |
4442 | DisplayState *ds, const char *core) | |
4443 | { | |
4444 | struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) | |
4445 | qemu_mallocz(sizeof(struct omap_mpu_state_s)); | |
7e7c5e4c | 4446 | ram_addr_t sram_base, q2_base; |
827df9f3 AZ |
4447 | qemu_irq *cpu_irq; |
4448 | qemu_irq dma_irqs[4]; | |
4449 | omap_clk gpio_clks[4]; | |
4450 | int sdindex; | |
4451 | int i; | |
4452 | ||
4453 | /* Core */ | |
4454 | s->mpu_model = omap2420; | |
4455 | s->env = cpu_init(core ?: "arm1136-r2"); | |
4456 | if (!s->env) { | |
4457 | fprintf(stderr, "Unable to find CPU definition\n"); | |
4458 | exit(1); | |
4459 | } | |
4460 | s->sdram_size = sdram_size; | |
4461 | s->sram_size = OMAP242X_SRAM_SIZE; | |
4462 | ||
4463 | s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; | |
4464 | ||
4465 | /* Clocks */ | |
4466 | omap_clk_init(s); | |
4467 | ||
4468 | /* Memory-mapped stuff */ | |
4469 | cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size, | |
7e7c5e4c | 4470 | (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM); |
827df9f3 AZ |
4471 | cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size, |
4472 | (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM); | |
4473 | ||
4474 | s->l4 = omap_l4_init(OMAP2_L4_BASE, 54); | |
4475 | ||
4476 | /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */ | |
4477 | cpu_irq = arm_pic_init_cpu(s->env); | |
4478 | s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0], | |
4479 | cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ], | |
4480 | omap_findclk(s, "mpu_intc_fclk"), | |
4481 | omap_findclk(s, "mpu_intc_iclk")); | |
4482 | ||
4483 | s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3), | |
4484 | s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s); | |
4485 | ||
4486 | s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1), | |
4487 | omap_findclk(s, "omapctrl_iclk"), s); | |
4488 | ||
4489 | for (i = 0; i < 4; i ++) | |
4490 | dma_irqs[i] = | |
4491 | s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr]; | |
4492 | s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32, | |
4493 | omap_findclk(s, "sdma_iclk"), | |
4494 | omap_findclk(s, "sdma_fclk")); | |
4495 | s->port->addr_valid = omap2_validate_addr; | |
4496 | ||
afbb5194 AZ |
4497 | /* Register SDRAM and SRAM ports for fast DMA transfers. */ |
4498 | soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size); | |
4499 | soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size); | |
4500 | ||
827df9f3 AZ |
4501 | s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19), |
4502 | s->irq[0][OMAP_INT_24XX_UART1_IRQ], | |
4503 | omap_findclk(s, "uart1_fclk"), | |
4504 | omap_findclk(s, "uart1_iclk"), | |
4505 | s->drq[OMAP24XX_DMA_UART1_TX], | |
4506 | s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]); | |
4507 | s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20), | |
4508 | s->irq[0][OMAP_INT_24XX_UART2_IRQ], | |
4509 | omap_findclk(s, "uart2_fclk"), | |
4510 | omap_findclk(s, "uart2_iclk"), | |
4511 | s->drq[OMAP24XX_DMA_UART2_TX], | |
4512 | s->drq[OMAP24XX_DMA_UART2_RX], | |
4513 | serial_hds[0] ? serial_hds[1] : 0); | |
4514 | s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21), | |
4515 | s->irq[0][OMAP_INT_24XX_UART3_IRQ], | |
4516 | omap_findclk(s, "uart3_fclk"), | |
4517 | omap_findclk(s, "uart3_iclk"), | |
4518 | s->drq[OMAP24XX_DMA_UART3_TX], | |
4519 | s->drq[OMAP24XX_DMA_UART3_RX], | |
4520 | serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0); | |
4521 | ||
4522 | s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7), | |
4523 | s->irq[0][OMAP_INT_24XX_GPTIMER1], | |
4524 | omap_findclk(s, "wu_gpt1_clk"), | |
4525 | omap_findclk(s, "wu_l4_iclk")); | |
4526 | s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8), | |
4527 | s->irq[0][OMAP_INT_24XX_GPTIMER2], | |
4528 | omap_findclk(s, "core_gpt2_clk"), | |
4529 | omap_findclk(s, "core_l4_iclk")); | |
4530 | s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22), | |
4531 | s->irq[0][OMAP_INT_24XX_GPTIMER3], | |
4532 | omap_findclk(s, "core_gpt3_clk"), | |
4533 | omap_findclk(s, "core_l4_iclk")); | |
4534 | s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23), | |
4535 | s->irq[0][OMAP_INT_24XX_GPTIMER4], | |
4536 | omap_findclk(s, "core_gpt4_clk"), | |
4537 | omap_findclk(s, "core_l4_iclk")); | |
4538 | s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24), | |
4539 | s->irq[0][OMAP_INT_24XX_GPTIMER5], | |
4540 | omap_findclk(s, "core_gpt5_clk"), | |
4541 | omap_findclk(s, "core_l4_iclk")); | |
4542 | s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25), | |
4543 | s->irq[0][OMAP_INT_24XX_GPTIMER6], | |
4544 | omap_findclk(s, "core_gpt6_clk"), | |
4545 | omap_findclk(s, "core_l4_iclk")); | |
4546 | s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26), | |
4547 | s->irq[0][OMAP_INT_24XX_GPTIMER7], | |
4548 | omap_findclk(s, "core_gpt7_clk"), | |
4549 | omap_findclk(s, "core_l4_iclk")); | |
4550 | s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27), | |
4551 | s->irq[0][OMAP_INT_24XX_GPTIMER8], | |
4552 | omap_findclk(s, "core_gpt8_clk"), | |
4553 | omap_findclk(s, "core_l4_iclk")); | |
4554 | s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28), | |
4555 | s->irq[0][OMAP_INT_24XX_GPTIMER9], | |
4556 | omap_findclk(s, "core_gpt9_clk"), | |
4557 | omap_findclk(s, "core_l4_iclk")); | |
4558 | s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29), | |
4559 | s->irq[0][OMAP_INT_24XX_GPTIMER10], | |
4560 | omap_findclk(s, "core_gpt10_clk"), | |
4561 | omap_findclk(s, "core_l4_iclk")); | |
4562 | s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30), | |
4563 | s->irq[0][OMAP_INT_24XX_GPTIMER11], | |
4564 | omap_findclk(s, "core_gpt11_clk"), | |
4565 | omap_findclk(s, "core_l4_iclk")); | |
4566 | s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31), | |
4567 | s->irq[0][OMAP_INT_24XX_GPTIMER12], | |
4568 | omap_findclk(s, "core_gpt12_clk"), | |
4569 | omap_findclk(s, "core_l4_iclk")); | |
4570 | ||
4571 | omap_tap_init(omap_l4ta(s->l4, 2), s); | |
4572 | ||
4573 | omap_synctimer_init(omap_l4tao(s->l4, 2), s, | |
4574 | omap_findclk(s, "clk32-kHz"), | |
4575 | omap_findclk(s, "core_l4_iclk")); | |
4576 | ||
4577 | s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5), | |
4578 | s->irq[0][OMAP_INT_24XX_I2C1_IRQ], | |
4579 | &s->drq[OMAP24XX_DMA_I2C1_TX], | |
4580 | omap_findclk(s, "i2c1.fclk"), | |
4581 | omap_findclk(s, "i2c1.iclk")); | |
4582 | s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6), | |
4583 | s->irq[0][OMAP_INT_24XX_I2C2_IRQ], | |
4584 | &s->drq[OMAP24XX_DMA_I2C2_TX], | |
4585 | omap_findclk(s, "i2c2.fclk"), | |
4586 | omap_findclk(s, "i2c2.iclk")); | |
4587 | ||
4588 | gpio_clks[0] = omap_findclk(s, "gpio1_dbclk"); | |
4589 | gpio_clks[1] = omap_findclk(s, "gpio2_dbclk"); | |
4590 | gpio_clks[2] = omap_findclk(s, "gpio3_dbclk"); | |
4591 | gpio_clks[3] = omap_findclk(s, "gpio4_dbclk"); | |
4592 | s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3), | |
4593 | &s->irq[0][OMAP_INT_24XX_GPIO_BANK1], | |
4594 | gpio_clks, omap_findclk(s, "gpio_iclk"), 4); | |
4595 | ||
4596 | s->sdrc = omap_sdrc_init(0x68009000); | |
4597 | s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]); | |
4598 | ||
4599 | sdindex = drive_get_index(IF_SD, 0, 0); | |
4600 | if (sdindex == -1) { | |
4601 | fprintf(stderr, "qemu: missing SecureDigital device\n"); | |
4602 | exit(1); | |
4603 | } | |
4604 | s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), drives_table[sdindex].bdrv, | |
4605 | s->irq[0][OMAP_INT_24XX_MMC_IRQ], | |
4606 | &s->drq[OMAP24XX_DMA_MMC1_TX], | |
4607 | omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk")); | |
4608 | ||
4609 | s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4, | |
99570a40 | 4610 | s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ], |
827df9f3 AZ |
4611 | &s->drq[OMAP24XX_DMA_SPI1_TX0], |
4612 | omap_findclk(s, "spi1_fclk"), | |
4613 | omap_findclk(s, "spi1_iclk")); | |
4614 | s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2, | |
99570a40 | 4615 | s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ], |
827df9f3 AZ |
4616 | &s->drq[OMAP24XX_DMA_SPI2_TX0], |
4617 | omap_findclk(s, "spi2_fclk"), | |
4618 | omap_findclk(s, "spi2_iclk")); | |
4619 | ||
4620 | s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800, ds, | |
4621 | /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */ | |
4622 | s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS], | |
4623 | omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"), | |
4624 | omap_findclk(s, "dss_54m_clk"), | |
4625 | omap_findclk(s, "dss_l3_iclk"), | |
4626 | omap_findclk(s, "dss_l4_iclk")); | |
4627 | ||
54585ffe AZ |
4628 | omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000, |
4629 | s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"), | |
4630 | serial_hds[0] && serial_hds[1] && serial_hds[2] ? | |
4631 | serial_hds[3] : 0); | |
4632 | ||
99570a40 AZ |
4633 | s->eac = omap_eac_init(omap_l4ta(s->l4, 32), |
4634 | s->irq[0][OMAP_INT_24XX_EAC_IRQ], | |
4635 | /* Ten consecutive lines */ | |
4636 | &s->drq[OMAP24XX_DMA_EAC_AC_RD], | |
4637 | omap_findclk(s, "func_96m_clk"), | |
4638 | omap_findclk(s, "core_l4_iclk")); | |
4639 | ||
827df9f3 AZ |
4640 | /* All register mappings (includin those not currenlty implemented): |
4641 | * SystemControlMod 48000000 - 48000fff | |
4642 | * SystemControlL4 48001000 - 48001fff | |
4643 | * 32kHz Timer Mod 48004000 - 48004fff | |
4644 | * 32kHz Timer L4 48005000 - 48005fff | |
4645 | * PRCM ModA 48008000 - 480087ff | |
4646 | * PRCM ModB 48008800 - 48008fff | |
4647 | * PRCM L4 48009000 - 48009fff | |
4648 | * TEST-BCM Mod 48012000 - 48012fff | |
4649 | * TEST-BCM L4 48013000 - 48013fff | |
4650 | * TEST-TAP Mod 48014000 - 48014fff | |
4651 | * TEST-TAP L4 48015000 - 48015fff | |
4652 | * GPIO1 Mod 48018000 - 48018fff | |
4653 | * GPIO Top 48019000 - 48019fff | |
4654 | * GPIO2 Mod 4801a000 - 4801afff | |
4655 | * GPIO L4 4801b000 - 4801bfff | |
4656 | * GPIO3 Mod 4801c000 - 4801cfff | |
4657 | * GPIO4 Mod 4801e000 - 4801efff | |
4658 | * WDTIMER1 Mod 48020000 - 48010fff | |
4659 | * WDTIMER Top 48021000 - 48011fff | |
4660 | * WDTIMER2 Mod 48022000 - 48012fff | |
4661 | * WDTIMER L4 48023000 - 48013fff | |
4662 | * WDTIMER3 Mod 48024000 - 48014fff | |
4663 | * WDTIMER3 L4 48025000 - 48015fff | |
4664 | * WDTIMER4 Mod 48026000 - 48016fff | |
4665 | * WDTIMER4 L4 48027000 - 48017fff | |
4666 | * GPTIMER1 Mod 48028000 - 48018fff | |
4667 | * GPTIMER1 L4 48029000 - 48019fff | |
4668 | * GPTIMER2 Mod 4802a000 - 4801afff | |
4669 | * GPTIMER2 L4 4802b000 - 4801bfff | |
4670 | * L4-Config AP 48040000 - 480407ff | |
4671 | * L4-Config IP 48040800 - 48040fff | |
4672 | * L4-Config LA 48041000 - 48041fff | |
4673 | * ARM11ETB Mod 48048000 - 48049fff | |
4674 | * ARM11ETB L4 4804a000 - 4804afff | |
4675 | * DISPLAY Top 48050000 - 480503ff | |
4676 | * DISPLAY DISPC 48050400 - 480507ff | |
4677 | * DISPLAY RFBI 48050800 - 48050bff | |
4678 | * DISPLAY VENC 48050c00 - 48050fff | |
4679 | * DISPLAY L4 48051000 - 48051fff | |
4680 | * CAMERA Top 48052000 - 480523ff | |
4681 | * CAMERA core 48052400 - 480527ff | |
4682 | * CAMERA DMA 48052800 - 48052bff | |
4683 | * CAMERA MMU 48052c00 - 48052fff | |
4684 | * CAMERA L4 48053000 - 48053fff | |
4685 | * SDMA Mod 48056000 - 48056fff | |
4686 | * SDMA L4 48057000 - 48057fff | |
4687 | * SSI Top 48058000 - 48058fff | |
4688 | * SSI GDD 48059000 - 48059fff | |
4689 | * SSI Port1 4805a000 - 4805afff | |
4690 | * SSI Port2 4805b000 - 4805bfff | |
4691 | * SSI L4 4805c000 - 4805cfff | |
4692 | * USB Mod 4805e000 - 480fefff | |
4693 | * USB L4 4805f000 - 480fffff | |
4694 | * WIN_TRACER1 Mod 48060000 - 48060fff | |
4695 | * WIN_TRACER1 L4 48061000 - 48061fff | |
4696 | * WIN_TRACER2 Mod 48062000 - 48062fff | |
4697 | * WIN_TRACER2 L4 48063000 - 48063fff | |
4698 | * WIN_TRACER3 Mod 48064000 - 48064fff | |
4699 | * WIN_TRACER3 L4 48065000 - 48065fff | |
4700 | * WIN_TRACER4 Top 48066000 - 480660ff | |
4701 | * WIN_TRACER4 ETT 48066100 - 480661ff | |
4702 | * WIN_TRACER4 WT 48066200 - 480662ff | |
4703 | * WIN_TRACER4 L4 48067000 - 48067fff | |
4704 | * XTI Mod 48068000 - 48068fff | |
4705 | * XTI L4 48069000 - 48069fff | |
4706 | * UART1 Mod 4806a000 - 4806afff | |
4707 | * UART1 L4 4806b000 - 4806bfff | |
4708 | * UART2 Mod 4806c000 - 4806cfff | |
4709 | * UART2 L4 4806d000 - 4806dfff | |
4710 | * UART3 Mod 4806e000 - 4806efff | |
4711 | * UART3 L4 4806f000 - 4806ffff | |
4712 | * I2C1 Mod 48070000 - 48070fff | |
4713 | * I2C1 L4 48071000 - 48071fff | |
4714 | * I2C2 Mod 48072000 - 48072fff | |
4715 | * I2C2 L4 48073000 - 48073fff | |
4716 | * McBSP1 Mod 48074000 - 48074fff | |
4717 | * McBSP1 L4 48075000 - 48075fff | |
4718 | * McBSP2 Mod 48076000 - 48076fff | |
4719 | * McBSP2 L4 48077000 - 48077fff | |
4720 | * GPTIMER3 Mod 48078000 - 48078fff | |
4721 | * GPTIMER3 L4 48079000 - 48079fff | |
4722 | * GPTIMER4 Mod 4807a000 - 4807afff | |
4723 | * GPTIMER4 L4 4807b000 - 4807bfff | |
4724 | * GPTIMER5 Mod 4807c000 - 4807cfff | |
4725 | * GPTIMER5 L4 4807d000 - 4807dfff | |
4726 | * GPTIMER6 Mod 4807e000 - 4807efff | |
4727 | * GPTIMER6 L4 4807f000 - 4807ffff | |
4728 | * GPTIMER7 Mod 48080000 - 48080fff | |
4729 | * GPTIMER7 L4 48081000 - 48081fff | |
4730 | * GPTIMER8 Mod 48082000 - 48082fff | |
4731 | * GPTIMER8 L4 48083000 - 48083fff | |
4732 | * GPTIMER9 Mod 48084000 - 48084fff | |
4733 | * GPTIMER9 L4 48085000 - 48085fff | |
4734 | * GPTIMER10 Mod 48086000 - 48086fff | |
4735 | * GPTIMER10 L4 48087000 - 48087fff | |
4736 | * GPTIMER11 Mod 48088000 - 48088fff | |
4737 | * GPTIMER11 L4 48089000 - 48089fff | |
4738 | * GPTIMER12 Mod 4808a000 - 4808afff | |
4739 | * GPTIMER12 L4 4808b000 - 4808bfff | |
4740 | * EAC Mod 48090000 - 48090fff | |
4741 | * EAC L4 48091000 - 48091fff | |
4742 | * FAC Mod 48092000 - 48092fff | |
4743 | * FAC L4 48093000 - 48093fff | |
4744 | * MAILBOX Mod 48094000 - 48094fff | |
4745 | * MAILBOX L4 48095000 - 48095fff | |
4746 | * SPI1 Mod 48098000 - 48098fff | |
4747 | * SPI1 L4 48099000 - 48099fff | |
4748 | * SPI2 Mod 4809a000 - 4809afff | |
4749 | * SPI2 L4 4809b000 - 4809bfff | |
4750 | * MMC/SDIO Mod 4809c000 - 4809cfff | |
4751 | * MMC/SDIO L4 4809d000 - 4809dfff | |
4752 | * MS_PRO Mod 4809e000 - 4809efff | |
4753 | * MS_PRO L4 4809f000 - 4809ffff | |
4754 | * RNG Mod 480a0000 - 480a0fff | |
4755 | * RNG L4 480a1000 - 480a1fff | |
4756 | * DES3DES Mod 480a2000 - 480a2fff | |
4757 | * DES3DES L4 480a3000 - 480a3fff | |
4758 | * SHA1MD5 Mod 480a4000 - 480a4fff | |
4759 | * SHA1MD5 L4 480a5000 - 480a5fff | |
4760 | * AES Mod 480a6000 - 480a6fff | |
4761 | * AES L4 480a7000 - 480a7fff | |
4762 | * PKA Mod 480a8000 - 480a9fff | |
4763 | * PKA L4 480aa000 - 480aafff | |
4764 | * MG Mod 480b0000 - 480b0fff | |
4765 | * MG L4 480b1000 - 480b1fff | |
4766 | * HDQ/1-wire Mod 480b2000 - 480b2fff | |
4767 | * HDQ/1-wire L4 480b3000 - 480b3fff | |
4768 | * MPU interrupt 480fe000 - 480fefff | |
54585ffe | 4769 | * STI channel base 54000000 - 5400ffff |
827df9f3 AZ |
4770 | * IVA RAM 5c000000 - 5c01ffff |
4771 | * IVA ROM 5c020000 - 5c027fff | |
4772 | * IMG_BUF_A 5c040000 - 5c040fff | |
4773 | * IMG_BUF_B 5c042000 - 5c042fff | |
4774 | * VLCDS 5c048000 - 5c0487ff | |
4775 | * IMX_COEF 5c049000 - 5c04afff | |
4776 | * IMX_CMD 5c051000 - 5c051fff | |
4777 | * VLCDQ 5c053000 - 5c0533ff | |
4778 | * VLCDH 5c054000 - 5c054fff | |
4779 | * SEQ_CMD 5c055000 - 5c055fff | |
4780 | * IMX_REG 5c056000 - 5c0560ff | |
4781 | * VLCD_REG 5c056100 - 5c0561ff | |
4782 | * SEQ_REG 5c056200 - 5c0562ff | |
4783 | * IMG_BUF_REG 5c056300 - 5c0563ff | |
4784 | * SEQIRQ_REG 5c056400 - 5c0564ff | |
4785 | * OCP_REG 5c060000 - 5c060fff | |
4786 | * SYSC_REG 5c070000 - 5c070fff | |
4787 | * MMU_REG 5d000000 - 5d000fff | |
4788 | * sDMA R 68000400 - 680005ff | |
4789 | * sDMA W 68000600 - 680007ff | |
4790 | * Display Control 68000800 - 680009ff | |
4791 | * DSP subsystem 68000a00 - 68000bff | |
4792 | * MPU subsystem 68000c00 - 68000dff | |
4793 | * IVA subsystem 68001000 - 680011ff | |
4794 | * USB 68001200 - 680013ff | |
4795 | * Camera 68001400 - 680015ff | |
4796 | * VLYNQ (firewall) 68001800 - 68001bff | |
4797 | * VLYNQ 68001e00 - 68001fff | |
4798 | * SSI 68002000 - 680021ff | |
4799 | * L4 68002400 - 680025ff | |
4800 | * DSP (firewall) 68002800 - 68002bff | |
4801 | * DSP subsystem 68002e00 - 68002fff | |
4802 | * IVA (firewall) 68003000 - 680033ff | |
4803 | * IVA 68003600 - 680037ff | |
4804 | * GFX 68003a00 - 68003bff | |
4805 | * CMDWR emulation 68003c00 - 68003dff | |
4806 | * SMS 68004000 - 680041ff | |
4807 | * OCM 68004200 - 680043ff | |
4808 | * GPMC 68004400 - 680045ff | |
4809 | * RAM (firewall) 68005000 - 680053ff | |
4810 | * RAM (err login) 68005400 - 680057ff | |
4811 | * ROM (firewall) 68005800 - 68005bff | |
4812 | * ROM (err login) 68005c00 - 68005fff | |
4813 | * GPMC (firewall) 68006000 - 680063ff | |
4814 | * GPMC (err login) 68006400 - 680067ff | |
4815 | * SMS (err login) 68006c00 - 68006fff | |
4816 | * SMS registers 68008000 - 68008fff | |
4817 | * SDRC registers 68009000 - 68009fff | |
4818 | * GPMC registers 6800a000 6800afff | |
4819 | */ | |
4820 | ||
4821 | qemu_register_reset(omap2_mpu_reset, s); | |
4822 | ||
4823 | return s; | |
4824 | } |