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Use MMU globals for some MMU traps
[qemu.git] / hw / omap2.c
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827df9f3
AZ		 1/*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22#include "hw.h"
23#include "arm-misc.h"
24#include "omap.h"
25#include "sysemu.h"
26#include "qemu-timer.h"
27#include "qemu-char.h"
28#include "flash.h"
99570a40 29#include "audio/audio.h"
827df9f3
AZ		 30
31/* GP timers */
32struct omap_gp_timer_s {
33 qemu_irq irq;
34 qemu_irq wkup;
35 qemu_irq in;
36 qemu_irq out;
37 omap_clk clk;
38 target_phys_addr_t base;
39 QEMUTimer *timer;
40 QEMUTimer *match;
41 struct omap_target_agent_s *ta;
42
43 int in_val;
44 int out_val;
45 int64_t time;
46 int64_t rate;
47 int64_t ticks_per_sec;
48
49 int16_t config;
50 int status;
51 int it_ena;
52 int wu_ena;
53 int enable;
54 int inout;
55 int capt2;
56 int pt;
57 enum {
58 gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both
59 } trigger;
60 enum {
61 gpt_capture_none, gpt_capture_rising,
62 gpt_capture_falling, gpt_capture_both
63 } capture;
64 int scpwm;
65 int ce;
66 int pre;
67 int ptv;
68 int ar;
69 int st;
70 int posted;
71 uint32_t val;
72 uint32_t load_val;
73 uint32_t capture_val[2];
74 uint32_t match_val;
75 int capt_num;
76
77 uint16_t writeh; /* LSB */
78 uint16_t readh; /* MSB */
79};
80
81#define GPT_TCAR_IT (1 << 2)
82#define GPT_OVF_IT (1 << 1)
83#define GPT_MAT_IT (1 << 0)
84
85static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it)
86{
87 if (timer->it_ena & it) {
88 if (!timer->status)
89 qemu_irq_raise(timer->irq);
90
91 timer->status |= it;
92 /* Or are the status bits set even when masked?
93 * i.e. is masking applied before or after the status register? */
94 }
95
96 if (timer->wu_ena & it)
97 qemu_irq_pulse(timer->wkup);
98}
99
100static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level)
101{
102 if (!timer->inout && timer->out_val != level) {
103 timer->out_val = level;
104 qemu_set_irq(timer->out, level);
105 }
106}
107
108static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer)
109{
110 uint64_t distance;
111
112 if (timer->st && timer->rate) {
113 distance = qemu_get_clock(vm_clock) - timer->time;
114 distance = muldiv64(distance, timer->rate, timer->ticks_per_sec);
115
116 if (distance >= 0xffffffff - timer->val)
117 return 0xffffffff;
118 else
119 return timer->val + distance;
120 } else
121 return timer->val;
122}
123
124static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer)
125{
126 if (timer->st) {
127 timer->val = omap_gp_timer_read(timer);
128 timer->time = qemu_get_clock(vm_clock);
129 }
130}
131
132static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer)
133{
134 int64_t expires, matches;
135
136 if (timer->st && timer->rate) {
137 expires = muldiv64(0x100000000ll - timer->val,
138 timer->ticks_per_sec, timer->rate);
139 qemu_mod_timer(timer->timer, timer->time + expires);
140
141 if (timer->ce && timer->match_val >= timer->val) {
142 matches = muldiv64(timer->match_val - timer->val,
143 timer->ticks_per_sec, timer->rate);
144 qemu_mod_timer(timer->match, timer->time + matches);
145 } else
146 qemu_del_timer(timer->match);
147 } else {
148 qemu_del_timer(timer->timer);
149 qemu_del_timer(timer->match);
150 omap_gp_timer_out(timer, timer->scpwm);
151 }
152}
153
154static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)
155{
156 if (timer->pt)
157 /* TODO in overflow-and-match mode if the first event to
158 * occurs is the match, don't toggle. */
159 omap_gp_timer_out(timer, !timer->out_val);
160 else
161 /* TODO inverted pulse on timer->out_val == 1? */
162 qemu_irq_pulse(timer->out);
163}
164
165static void omap_gp_timer_tick(void *opaque)
166{
167 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
168
169 if (!timer->ar) {
170 timer->st = 0;
171 timer->val = 0;
172 } else {
173 timer->val = timer->load_val;
174 timer->time = qemu_get_clock(vm_clock);
175 }
176
177 if (timer->trigger == gpt_trigger_overflow ||
178 timer->trigger == gpt_trigger_both)
179 omap_gp_timer_trigger(timer);
180
181 omap_gp_timer_intr(timer, GPT_OVF_IT);
182 omap_gp_timer_update(timer);
183}
184
185static void omap_gp_timer_match(void *opaque)
186{
187 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
188
189 if (timer->trigger == gpt_trigger_both)
190 omap_gp_timer_trigger(timer);
191
192 omap_gp_timer_intr(timer, GPT_MAT_IT);
193}
194
195static void omap_gp_timer_input(void *opaque, int line, int on)
196{
197 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
198 int trigger;
199
200 switch (s->capture) {
201 default:
202 case gpt_capture_none:
203 trigger = 0;
204 break;
205 case gpt_capture_rising:
206 trigger = !s->in_val && on;
207 break;
208 case gpt_capture_falling:
209 trigger = s->in_val && !on;
210 break;
211 case gpt_capture_both:
212 trigger = (s->in_val == !on);
213 break;
214 }
215 s->in_val = on;
216
217 if (s->inout && trigger && s->capt_num < 2) {
218 s->capture_val[s->capt_num] = omap_gp_timer_read(s);
219
220 if (s->capt2 == s->capt_num ++)
221 omap_gp_timer_intr(s, GPT_TCAR_IT);
222 }
223}
224
225static void omap_gp_timer_clk_update(void *opaque, int line, int on)
226{
227 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
228
229 omap_gp_timer_sync(timer);
230 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
231 omap_gp_timer_update(timer);
232}
233
234static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer)
235{
236 omap_clk_adduser(timer->clk,
237 qemu_allocate_irqs(omap_gp_timer_clk_update, timer, 1)[0]);
238 timer->rate = omap_clk_getrate(timer->clk);
239}
240
241static void omap_gp_timer_reset(struct omap_gp_timer_s *s)
242{
243 s->config = 0x000;
244 s->status = 0;
245 s->it_ena = 0;
246 s->wu_ena = 0;
247 s->inout = 0;
248 s->capt2 = 0;
249 s->capt_num = 0;
250 s->pt = 0;
251 s->trigger = gpt_trigger_none;
252 s->capture = gpt_capture_none;
253 s->scpwm = 0;
254 s->ce = 0;
255 s->pre = 0;
256 s->ptv = 0;
257 s->ar = 0;
258 s->st = 0;
259 s->posted = 1;
260 s->val = 0x00000000;
261 s->load_val = 0x00000000;
262 s->capture_val[0] = 0x00000000;
263 s->capture_val[1] = 0x00000000;
264 s->match_val = 0x00000000;
265 omap_gp_timer_update(s);
266}
267
268static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
269{
270 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
271 int offset = addr - s->base;
272
273 switch (offset) {
274 case 0x00: /* TIDR */
275 return 0x21;
276
277 case 0x10: /* TIOCP_CFG */
278 return s->config;
279
280 case 0x14: /* TISTAT */
281 /* ??? When's this bit reset? */
282 return 1; /* RESETDONE */
283
284 case 0x18: /* TISR */
285 return s->status;
286
287 case 0x1c: /* TIER */
288 return s->it_ena;
289
290 case 0x20: /* TWER */
291 return s->wu_ena;
292
293 case 0x24: /* TCLR */
294 return (s->inout << 14) |
295 (s->capt2 << 13) |
296 (s->pt << 12) |
297 (s->trigger << 10) |
298 (s->capture << 8) |
299 (s->scpwm << 7) |
300 (s->ce << 6) |
301 (s->pre << 5) |
302 (s->ptv << 2) |
303 (s->ar << 1) |
304 (s->st << 0);
305
306 case 0x28: /* TCRR */
307 return omap_gp_timer_read(s);
308
309 case 0x2c: /* TLDR */
310 return s->load_val;
311
312 case 0x30: /* TTGR */
313 return 0xffffffff;
314
315 case 0x34: /* TWPS */
316 return 0x00000000; /* No posted writes pending. */
317
318 case 0x38: /* TMAR */
319 return s->match_val;
320
321 case 0x3c: /* TCAR1 */
322 return s->capture_val[0];
323
324 case 0x40: /* TSICR */
325 return s->posted << 2;
326
327 case 0x44: /* TCAR2 */
328 return s->capture_val[1];
329 }
330
331 OMAP_BAD_REG(addr);
332 return 0;
333}
334
335static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
336{
337 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
338 uint32_t ret;
339
340 if (addr & 2)
341 return s->readh;
342 else {
343 ret = omap_gp_timer_readw(opaque, addr);
344 s->readh = ret >> 16;
345 return ret & 0xffff;
346 }
347}
348
349static CPUReadMemoryFunc *omap_gp_timer_readfn[] = {
350 omap_badwidth_read32,
351 omap_gp_timer_readh,
352 omap_gp_timer_readw,
353};
354
355static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
356 uint32_t value)
357{
358 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
359 int offset = addr - s->base;
360
361 switch (offset) {
362 case 0x00: /* TIDR */
363 case 0x14: /* TISTAT */
364 case 0x34: /* TWPS */
365 case 0x3c: /* TCAR1 */
366 case 0x44: /* TCAR2 */
367 OMAP_RO_REG(addr);
368 break;
369
370 case 0x10: /* TIOCP_CFG */
371 s->config = value & 0x33d;
372 if (((value >> 3) & 3) == 3) /* IDLEMODE */
373 fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n",
374 __FUNCTION__);
375 if (value & 2) /* SOFTRESET */
376 omap_gp_timer_reset(s);
377 break;
378
379 case 0x18: /* TISR */
380 if (value & GPT_TCAR_IT)
381 s->capt_num = 0;
382 if (s->status && !(s->status &= ~value))
383 qemu_irq_lower(s->irq);
384 break;
385
386 case 0x1c: /* TIER */
387 s->it_ena = value & 7;
388 break;
389
390 case 0x20: /* TWER */
391 s->wu_ena = value & 7;
392 break;
393
394 case 0x24: /* TCLR */
395 omap_gp_timer_sync(s);
396 s->inout = (value >> 14) & 1;
397 s->capt2 = (value >> 13) & 1;
398 s->pt = (value >> 12) & 1;
399 s->trigger = (value >> 10) & 3;
400 if (s->capture == gpt_capture_none &&
401 ((value >> 8) & 3) != gpt_capture_none)
402 s->capt_num = 0;
403 s->capture = (value >> 8) & 3;
404 s->scpwm = (value >> 7) & 1;
405 s->ce = (value >> 6) & 1;
406 s->pre = (value >> 5) & 1;
407 s->ptv = (value >> 2) & 7;
408 s->ar = (value >> 1) & 1;
409 s->st = (value >> 0) & 1;
410 if (s->inout && s->trigger != gpt_trigger_none)
411 fprintf(stderr, "%s: GP timer pin must be an output "
412 "for this trigger mode\n", __FUNCTION__);
413 if (!s->inout && s->capture != gpt_capture_none)
414 fprintf(stderr, "%s: GP timer pin must be an input "
415 "for this capture mode\n", __FUNCTION__);
416 if (s->trigger == gpt_trigger_none)
417 omap_gp_timer_out(s, s->scpwm);
418 /* TODO: make sure this doesn't overflow 32-bits */
419 s->ticks_per_sec = ticks_per_sec << (s->pre ? s->ptv + 1 : 0);
420 omap_gp_timer_update(s);
421 break;
422
423 case 0x28: /* TCRR */
424 s->time = qemu_get_clock(vm_clock);
425 s->val = value;
426 omap_gp_timer_update(s);
427 break;
428
429 case 0x2c: /* TLDR */
430 s->load_val = value;
431 break;
432
433 case 0x30: /* TTGR */
434 s->time = qemu_get_clock(vm_clock);
435 s->val = s->load_val;
436 omap_gp_timer_update(s);
437 break;
438
439 case 0x38: /* TMAR */
440 omap_gp_timer_sync(s);
441 s->match_val = value;
442 omap_gp_timer_update(s);
443 break;
444
445 case 0x40: /* TSICR */
446 s->posted = (value >> 2) & 1;
447 if (value & 2) /* How much exactly are we supposed to reset? */
448 omap_gp_timer_reset(s);
449 break;
450
451 default:
452 OMAP_BAD_REG(addr);
453 }
454}
455
456static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
457 uint32_t value)
458{
459 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
460
461 if (addr & 2)
462 return omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
463 else
464 s->writeh = (uint16_t) value;
465}
466
467static CPUWriteMemoryFunc *omap_gp_timer_writefn[] = {
468 omap_badwidth_write32,
469 omap_gp_timer_writeh,
470 omap_gp_timer_write,
471};
472
473struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
474 qemu_irq irq, omap_clk fclk, omap_clk iclk)
475{
476 int iomemtype;
477 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *)
478 qemu_mallocz(sizeof(struct omap_gp_timer_s));
479
480 s->ta = ta;
481 s->irq = irq;
482 s->clk = fclk;
483 s->timer = qemu_new_timer(vm_clock, omap_gp_timer_tick, s);
484 s->match = qemu_new_timer(vm_clock, omap_gp_timer_match, s);
485 s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0];
486 omap_gp_timer_reset(s);
487 omap_gp_timer_clk_setup(s);
488
c66fb5bc 489 iomemtype = l4_register_io_memory(0, omap_gp_timer_readfn,
827df9f3
AZ		 490 omap_gp_timer_writefn, s);
491 s->base = omap_l4_attach(ta, 0, iomemtype);
492
493 return s;
494}
495
496/* 32-kHz Sync Timer of the OMAP2 */
497static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) {
498 return muldiv64(qemu_get_clock(vm_clock), 0x8000, ticks_per_sec);
499}
500
501static void omap_synctimer_reset(struct omap_synctimer_s *s)
502{
503 s->val = omap_synctimer_read(s);
504}
505
506static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
507{
508 struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
509 int offset = addr - s->base;
510
511 switch (offset) {
512 case 0x00: /* 32KSYNCNT_REV */
513 return 0x21;
514
515 case 0x10: /* CR */
516 return omap_synctimer_read(s) - s->val;
517 }
518
519 OMAP_BAD_REG(addr);
520 return 0;
521}
522
523static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
524{
525 struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
526 uint32_t ret;
527
528 if (addr & 2)
529 return s->readh;
530 else {
531 ret = omap_synctimer_readw(opaque, addr);
532 s->readh = ret >> 16;
533 return ret & 0xffff;
534 }
535}
536
537static CPUReadMemoryFunc *omap_synctimer_readfn[] = {
538 omap_badwidth_read32,
539 omap_synctimer_readh,
540 omap_synctimer_readw,
541};
542
543static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
544 uint32_t value)
545{
546 OMAP_BAD_REG(addr);
547}
548
549static CPUWriteMemoryFunc *omap_synctimer_writefn[] = {
550 omap_badwidth_write32,
551 omap_synctimer_write,
552 omap_synctimer_write,
553};
554
555void omap_synctimer_init(struct omap_target_agent_s *ta,
556 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk)
557{
558 struct omap_synctimer_s *s = &mpu->synctimer;
559
560 omap_synctimer_reset(s);
c66fb5bc 561 s->base = omap_l4_attach(ta, 0, l4_register_io_memory(0,
827df9f3
AZ		 562 omap_synctimer_readfn, omap_synctimer_writefn, s));
563}
564
565/* General-Purpose Interface of OMAP2 */
566struct omap2_gpio_s {
567 target_phys_addr_t base;
568 qemu_irq irq[2];
569 qemu_irq wkup;
570 qemu_irq *in;
571 qemu_irq handler[32];
572
573 uint8_t config[2];
574 uint32_t inputs;
575 uint32_t outputs;
576 uint32_t dir;
577 uint32_t level[2];
578 uint32_t edge[2];
579 uint32_t mask[2];
580 uint32_t wumask;
581 uint32_t ints[2];
582 uint32_t debounce;
583 uint8_t delay;
584};
585
586static inline void omap_gpio_module_int_update(struct omap2_gpio_s *s,
587 int line)
588{
589 qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
590}
591
592static void omap_gpio_module_wake(struct omap2_gpio_s *s, int line)
593{
594 if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */
595 return;
596 if (!(s->config[0] & (3 << 3))) /* Force Idle */
597 return;
598 if (!(s->wumask & (1 << line)))
599 return;
600
601 qemu_irq_raise(s->wkup);
602}
603
604static inline void omap_gpio_module_out_update(struct omap2_gpio_s *s,
605 uint32_t diff)
606{
607 int ln;
608
609 s->outputs ^= diff;
610 diff &= ~s->dir;
611 while ((ln = ffs(diff))) {
612 ln --;
613 qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
614 diff &= ~(1 << ln);
615 }
616}
617
618static void omap_gpio_module_level_update(struct omap2_gpio_s *s, int line)
619{
620 s->ints[line] |= s->dir &
621 ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
622 omap_gpio_module_int_update(s, line);
623}
624
625static inline void omap_gpio_module_int(struct omap2_gpio_s *s, int line)
626{
627 s->ints[0] |= 1 << line;
628 omap_gpio_module_int_update(s, 0);
629 s->ints[1] |= 1 << line;
630 omap_gpio_module_int_update(s, 1);
631 omap_gpio_module_wake(s, line);
632}
633
634static void omap_gpio_module_set(void *opaque, int line, int level)
635{
636 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
637
638 if (level) {
639 if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
640 omap_gpio_module_int(s, line);
641 s->inputs |= 1 << line;
642 } else {
643 if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
644 omap_gpio_module_int(s, line);
645 s->inputs &= ~(1 << line);
646 }
647}
648
649static void omap_gpio_module_reset(struct omap2_gpio_s *s)
650{
651 s->config[0] = 0;
652 s->config[1] = 2;
653 s->ints[0] = 0;
654 s->ints[1] = 0;
655 s->mask[0] = 0;
656 s->mask[1] = 0;
657 s->wumask = 0;
658 s->dir = ~0;
659 s->level[0] = 0;
660 s->level[1] = 0;
661 s->edge[0] = 0;
662 s->edge[1] = 0;
663 s->debounce = 0;
664 s->delay = 0;
665}
666
667static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr)
668{
669 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
670 int offset = addr - s->base;
671
672 switch (offset) {
673 case 0x00: /* GPIO_REVISION */
674 return 0x18;
675
676 case 0x10: /* GPIO_SYSCONFIG */
677 return s->config[0];
678
679 case 0x14: /* GPIO_SYSSTATUS */
680 return 0x01;
681
682 case 0x18: /* GPIO_IRQSTATUS1 */
683 return s->ints[0];
684
685 case 0x1c: /* GPIO_IRQENABLE1 */
686 case 0x60: /* GPIO_CLEARIRQENABLE1 */
687 case 0x64: /* GPIO_SETIRQENABLE1 */
688 return s->mask[0];
689
690 case 0x20: /* GPIO_WAKEUPENABLE */
691 case 0x80: /* GPIO_CLEARWKUENA */
692 case 0x84: /* GPIO_SETWKUENA */
693 return s->wumask;
694
695 case 0x28: /* GPIO_IRQSTATUS2 */
696 return s->ints[1];
697
698 case 0x2c: /* GPIO_IRQENABLE2 */
699 case 0x70: /* GPIO_CLEARIRQENABLE2 */
700 case 0x74: /* GPIO_SETIREQNEABLE2 */
701 return s->mask[1];
702
703 case 0x30: /* GPIO_CTRL */
704 return s->config[1];
705
706 case 0x34: /* GPIO_OE */
707 return s->dir;
708
709 case 0x38: /* GPIO_DATAIN */
710 return s->inputs;
711
712 case 0x3c: /* GPIO_DATAOUT */
713 case 0x90: /* GPIO_CLEARDATAOUT */
714 case 0x94: /* GPIO_SETDATAOUT */
715 return s->outputs;
716
717 case 0x40: /* GPIO_LEVELDETECT0 */
718 return s->level[0];
719
720 case 0x44: /* GPIO_LEVELDETECT1 */
721 return s->level[1];
722
723 case 0x48: /* GPIO_RISINGDETECT */
724 return s->edge[0];
725
726 case 0x4c: /* GPIO_FALLINGDETECT */
727 return s->edge[1];
728
729 case 0x50: /* GPIO_DEBOUNCENABLE */
730 return s->debounce;
731
732 case 0x54: /* GPIO_DEBOUNCINGTIME */
733 return s->delay;
734 }
735
736 OMAP_BAD_REG(addr);
737 return 0;
738}
739
740static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr,
741 uint32_t value)
742{
743 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
744 int offset = addr - s->base;
745 uint32_t diff;
746 int ln;
747
748 switch (offset) {
749 case 0x00: /* GPIO_REVISION */
750 case 0x14: /* GPIO_SYSSTATUS */
751 case 0x38: /* GPIO_DATAIN */
752 OMAP_RO_REG(addr);
753 break;
754
755 case 0x10: /* GPIO_SYSCONFIG */
756 if (((value >> 3) & 3) == 3)
757 fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
758 if (value & 2)
759 omap_gpio_module_reset(s);
760 s->config[0] = value & 0x1d;
761 break;
762
763 case 0x18: /* GPIO_IRQSTATUS1 */
764 if (s->ints[0] & value) {
765 s->ints[0] &= ~value;
766 omap_gpio_module_level_update(s, 0);
767 }
768 break;
769
770 case 0x1c: /* GPIO_IRQENABLE1 */
771 s->mask[0] = value;
772 omap_gpio_module_int_update(s, 0);
773 break;
774
775 case 0x20: /* GPIO_WAKEUPENABLE */
776 s->wumask = value;
777 break;
778
779 case 0x28: /* GPIO_IRQSTATUS2 */
780 if (s->ints[1] & value) {
781 s->ints[1] &= ~value;
782 omap_gpio_module_level_update(s, 1);
783 }
784 break;
785
786 case 0x2c: /* GPIO_IRQENABLE2 */
787 s->mask[1] = value;
788 omap_gpio_module_int_update(s, 1);
789 break;
790
791 case 0x30: /* GPIO_CTRL */
792 s->config[1] = value & 7;
793 break;
794
795 case 0x34: /* GPIO_OE */
796 diff = s->outputs & (s->dir ^ value);
797 s->dir = value;
798
799 value = s->outputs & ~s->dir;
800 while ((ln = ffs(diff))) {
801 diff &= ~(1 <<-- ln);
802 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
803 }
804
805 omap_gpio_module_level_update(s, 0);
806 omap_gpio_module_level_update(s, 1);
807 break;
808
809 case 0x3c: /* GPIO_DATAOUT */
810 omap_gpio_module_out_update(s, s->outputs ^ value);
811 break;
812
813 case 0x40: /* GPIO_LEVELDETECT0 */
814 s->level[0] = value;
815 omap_gpio_module_level_update(s, 0);
816 omap_gpio_module_level_update(s, 1);
817 break;
818
819 case 0x44: /* GPIO_LEVELDETECT1 */
820 s->level[1] = value;
821 omap_gpio_module_level_update(s, 0);
822 omap_gpio_module_level_update(s, 1);
823 break;
824
825 case 0x48: /* GPIO_RISINGDETECT */
826 s->edge[0] = value;
827 break;
828
829 case 0x4c: /* GPIO_FALLINGDETECT */
830 s->edge[1] = value;
831 break;
832
833 case 0x50: /* GPIO_DEBOUNCENABLE */
834 s->debounce = value;
835 break;
836
837 case 0x54: /* GPIO_DEBOUNCINGTIME */
838 s->delay = value;
839 break;
840
841 case 0x60: /* GPIO_CLEARIRQENABLE1 */
842 s->mask[0] &= ~value;
843 omap_gpio_module_int_update(s, 0);
844 break;
845
846 case 0x64: /* GPIO_SETIRQENABLE1 */
847 s->mask[0] |= value;
848 omap_gpio_module_int_update(s, 0);
849 break;
850
851 case 0x70: /* GPIO_CLEARIRQENABLE2 */
852 s->mask[1] &= ~value;
853 omap_gpio_module_int_update(s, 1);
854 break;
855
856 case 0x74: /* GPIO_SETIREQNEABLE2 */
857 s->mask[1] |= value;
858 omap_gpio_module_int_update(s, 1);
859 break;
860
861 case 0x80: /* GPIO_CLEARWKUENA */
862 s->wumask &= ~value;
863 break;
864
865 case 0x84: /* GPIO_SETWKUENA */
866 s->wumask |= value;
867 break;
868
869 case 0x90: /* GPIO_CLEARDATAOUT */
870 omap_gpio_module_out_update(s, s->outputs & value);
871 break;
872
873 case 0x94: /* GPIO_SETDATAOUT */
874 omap_gpio_module_out_update(s, ~s->outputs & value);
875 break;
876
877 default:
878 OMAP_BAD_REG(addr);
879 return;
880 }
881}
882
883static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr)
884{
885 return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3);
886}
887
888static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr,
889 uint32_t value)
890{
891 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
892 int offset = addr - s->base;
893 uint32_t cur = 0;
894 uint32_t mask = 0xffff;
895
896 switch (offset & ~3) {
897 case 0x00: /* GPIO_REVISION */
898 case 0x14: /* GPIO_SYSSTATUS */
899 case 0x38: /* GPIO_DATAIN */
900 OMAP_RO_REG(addr);
901 break;
902
903 case 0x10: /* GPIO_SYSCONFIG */
904 case 0x1c: /* GPIO_IRQENABLE1 */
905 case 0x20: /* GPIO_WAKEUPENABLE */
906 case 0x2c: /* GPIO_IRQENABLE2 */
907 case 0x30: /* GPIO_CTRL */
908 case 0x34: /* GPIO_OE */
909 case 0x3c: /* GPIO_DATAOUT */
910 case 0x40: /* GPIO_LEVELDETECT0 */
911 case 0x44: /* GPIO_LEVELDETECT1 */
912 case 0x48: /* GPIO_RISINGDETECT */
913 case 0x4c: /* GPIO_FALLINGDETECT */
914 case 0x50: /* GPIO_DEBOUNCENABLE */
915 case 0x54: /* GPIO_DEBOUNCINGTIME */
916 cur = omap_gpio_module_read(opaque, addr & ~3) &
917 ~(mask << ((addr & 3) << 3));
918
919 /* Fall through. */
920 case 0x18: /* GPIO_IRQSTATUS1 */
921 case 0x28: /* GPIO_IRQSTATUS2 */
922 case 0x60: /* GPIO_CLEARIRQENABLE1 */
923 case 0x64: /* GPIO_SETIRQENABLE1 */
924 case 0x70: /* GPIO_CLEARIRQENABLE2 */
925 case 0x74: /* GPIO_SETIREQNEABLE2 */
926 case 0x80: /* GPIO_CLEARWKUENA */
927 case 0x84: /* GPIO_SETWKUENA */
928 case 0x90: /* GPIO_CLEARDATAOUT */
929 case 0x94: /* GPIO_SETDATAOUT */
930 value <<= (addr & 3) << 3;
931 omap_gpio_module_write(opaque, addr, cur | value);
932 break;
933
934 default:
935 OMAP_BAD_REG(addr);
936 return;
937 }
938}
939
940static CPUReadMemoryFunc *omap_gpio_module_readfn[] = {
941 omap_gpio_module_readp,
942 omap_gpio_module_readp,
943 omap_gpio_module_read,
944};
945
946static CPUWriteMemoryFunc *omap_gpio_module_writefn[] = {
947 omap_gpio_module_writep,
948 omap_gpio_module_writep,
949 omap_gpio_module_write,
950};
951
952static void omap_gpio_module_init(struct omap2_gpio_s *s,
953 struct omap_target_agent_s *ta, int region,
954 qemu_irq mpu, qemu_irq dsp, qemu_irq wkup,
955 omap_clk fclk, omap_clk iclk)
956{
957 int iomemtype;
958
959 s->irq[0] = mpu;
960 s->irq[1] = dsp;
961 s->wkup = wkup;
962 s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32);
963
c66fb5bc 964 iomemtype = l4_register_io_memory(0, omap_gpio_module_readfn,
827df9f3
AZ		 965 omap_gpio_module_writefn, s);
966 s->base = omap_l4_attach(ta, region, iomemtype);
967}
968
969struct omap_gpif_s {
970 struct omap2_gpio_s module[5];
971 int modules;
972
973 target_phys_addr_t topbase;
974 int autoidle;
975 int gpo;
976};
977
978static void omap_gpif_reset(struct omap_gpif_s *s)
979{
980 int i;
981
982 for (i = 0; i < s->modules; i ++)
983 omap_gpio_module_reset(s->module + i);
984
985 s->autoidle = 0;
986 s->gpo = 0;
987}
988
989static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)
990{
991 struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
992 int offset = addr - s->topbase;
993
994 switch (offset) {
995 case 0x00: /* IPGENERICOCPSPL_REVISION */
996 return 0x18;
997
998 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
999 return s->autoidle;
1000
1001 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
1002 return 0x01;
1003
1004 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
1005 return 0x00;
1006
1007 case 0x40: /* IPGENERICOCPSPL_GPO */
1008 return s->gpo;
1009
1010 case 0x50: /* IPGENERICOCPSPL_GPI */
1011 return 0x00;
1012 }
1013
1014 OMAP_BAD_REG(addr);
1015 return 0;
1016}
1017
1018static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr,
1019 uint32_t value)
1020{
1021 struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
1022 int offset = addr - s->topbase;
1023
1024 switch (offset) {
1025 case 0x00: /* IPGENERICOCPSPL_REVISION */
1026 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
1027 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
1028 case 0x50: /* IPGENERICOCPSPL_GPI */
1029 OMAP_RO_REG(addr);
1030 break;
1031
1032 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
1033 if (value & (1 << 1)) /* SOFTRESET */
1034 omap_gpif_reset(s);
1035 s->autoidle = value & 1;
1036 break;
1037
1038 case 0x40: /* IPGENERICOCPSPL_GPO */
1039 s->gpo = value & 1;
1040 break;
1041
1042 default:
1043 OMAP_BAD_REG(addr);
1044 return;
1045 }
1046}
1047
1048static CPUReadMemoryFunc *omap_gpif_top_readfn[] = {
1049 omap_gpif_top_read,
1050 omap_gpif_top_read,
1051 omap_gpif_top_read,
1052};
1053
1054static CPUWriteMemoryFunc *omap_gpif_top_writefn[] = {
1055 omap_gpif_top_write,
1056 omap_gpif_top_write,
1057 omap_gpif_top_write,
1058};
1059
1060struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
1061 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules)
1062{
1063 int iomemtype, i;
1064 struct omap_gpif_s *s = (struct omap_gpif_s *)
1065 qemu_mallocz(sizeof(struct omap_gpif_s));
1066 int region[4] = { 0, 2, 4, 5 };
1067
1068 s->modules = modules;
1069 for (i = 0; i < modules; i ++)
1070 omap_gpio_module_init(s->module + i, ta, region[i],
1071 irq[i], 0, 0, fclk[i], iclk);
1072
1073 omap_gpif_reset(s);
1074
c66fb5bc 1075 iomemtype = l4_register_io_memory(0, omap_gpif_top_readfn,
827df9f3
AZ		 1076 omap_gpif_top_writefn, s);
1077 s->topbase = omap_l4_attach(ta, 1, iomemtype);
1078
1079 return s;
1080}
1081
1082qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start)
1083{
1084 if (start >= s->modules * 32 || start < 0)
1085 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",
1086 __FUNCTION__, start);
1087 return s->module[start >> 5].in + (start & 31);
1088}
1089
1090void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler)
1091{
1092 if (line >= s->modules * 32 || line < 0)
1093 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
1094 s->module[line >> 5].handler[line & 31] = handler;
1095}
1096
1097/* Multichannel SPI */
1098struct omap_mcspi_s {
1099 target_phys_addr_t base;
1100 qemu_irq irq;
1101 int chnum;
1102
1103 uint32_t sysconfig;
1104 uint32_t systest;
1105 uint32_t irqst;
1106 uint32_t irqen;
1107 uint32_t wken;
1108 uint32_t control;
1109
1110 struct omap_mcspi_ch_s {
1111 qemu_irq txdrq;
1112 qemu_irq rxdrq;
e927bb00 1113 uint32_t (*txrx)(void *opaque, uint32_t, int);
827df9f3
AZ		 1114 void *opaque;
1115
1116 uint32_t tx;
1117 uint32_t rx;
1118
1119 uint32_t config;
1120 uint32_t status;
1121 uint32_t control;
1122 } ch[4];
1123};
1124
1125static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
1126{
1127 qemu_set_irq(s->irq, s->irqst & s->irqen);
1128}
1129
1130static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
1131{
1132 qemu_set_irq(ch->txdrq,
1133 (ch->control & 1) && /* EN */
1134 (ch->config & (1 << 14)) && /* DMAW */
1135 (ch->status & (1 << 1)) && /* TXS */
1136 ((ch->config >> 12) & 3) != 1); /* TRM */
1137 qemu_set_irq(ch->rxdrq,
1138 (ch->control & 1) && /* EN */
1139 (ch->config & (1 << 15)) && /* DMAW */
1140 (ch->status & (1 << 0)) && /* RXS */
1141 ((ch->config >> 12) & 3) != 2); /* TRM */
1142}
1143
1144static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
1145{
1146 struct omap_mcspi_ch_s *ch = s->ch + chnum;
1147
1148 if (!(ch->control & 1)) /* EN */
1149 return;
1150 if ((ch->status & (1 << 0)) && /* RXS */
1151 ((ch->config >> 12) & 3) != 2 && /* TRM */
1152 !(ch->config & (1 << 19))) /* TURBO */
1153 goto intr_update;
1154 if ((ch->status & (1 << 1)) && /* TXS */
1155 ((ch->config >> 12) & 3) != 1) /* TRM */
1156 goto intr_update;
1157
1158 if (!(s->control & 1) || /* SINGLE */
1159 (ch->config & (1 << 20))) { /* FORCE */
1160 if (ch->txrx)
e927bb00
AZ		 1161 ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
1162 1 + (0x1f & (ch->config >> 7)));
827df9f3
AZ		 1163 }
1164
1165 ch->tx = 0;
1166 ch->status |= 1 << 2; /* EOT */
1167 ch->status |= 1 << 1; /* TXS */
1168 if (((ch->config >> 12) & 3) != 2) /* TRM */
1169 ch->status |= 1 << 0; /* RXS */
1170
1171intr_update:
1172 if ((ch->status & (1 << 0)) && /* RXS */
1173 ((ch->config >> 12) & 3) != 2 && /* TRM */
1174 !(ch->config & (1 << 19))) /* TURBO */
1175 s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */
1176 if ((ch->status & (1 << 1)) && /* TXS */
1177 ((ch->config >> 12) & 3) != 1) /* TRM */
1178 s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */
1179 omap_mcspi_interrupt_update(s);
1180 omap_mcspi_dmarequest_update(ch);
1181}
1182
1183static void omap_mcspi_reset(struct omap_mcspi_s *s)
1184{
1185 int ch;
1186
1187 s->sysconfig = 0;
1188 s->systest = 0;
1189 s->irqst = 0;
1190 s->irqen = 0;
1191 s->wken = 0;
1192 s->control = 4;
1193
1194 for (ch = 0; ch < 4; ch ++) {
1195 s->ch[ch].config = 0x060000;
1196 s->ch[ch].status = 2; /* TXS */
1197 s->ch[ch].control = 0;
1198
1199 omap_mcspi_dmarequest_update(s->ch + ch);
1200 }
1201
1202 omap_mcspi_interrupt_update(s);
1203}
1204
1205static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
1206{
1207 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1208 int offset = addr - s->base;
1209 int ch = 0;
1210 uint32_t ret;
1211
1212 switch (offset) {
1213 case 0x00: /* MCSPI_REVISION */
1214 return 0x91;
1215
1216 case 0x10: /* MCSPI_SYSCONFIG */
1217 return s->sysconfig;
1218
1219 case 0x14: /* MCSPI_SYSSTATUS */
1220 return 1; /* RESETDONE */
1221
1222 case 0x18: /* MCSPI_IRQSTATUS */
1223 return s->irqst;
1224
1225 case 0x1c: /* MCSPI_IRQENABLE */
1226 return s->irqen;
1227
1228 case 0x20: /* MCSPI_WAKEUPENABLE */
1229 return s->wken;
1230
1231 case 0x24: /* MCSPI_SYST */
1232 return s->systest;
1233
1234 case 0x28: /* MCSPI_MODULCTRL */
1235 return s->control;
1236
1237 case 0x68: ch ++;
1238 case 0x54: ch ++;
1239 case 0x40: ch ++;
1240 case 0x2c: /* MCSPI_CHCONF */
1241 return s->ch[ch].config;
1242
1243 case 0x6c: ch ++;
1244 case 0x58: ch ++;
1245 case 0x44: ch ++;
1246 case 0x30: /* MCSPI_CHSTAT */
1247 return s->ch[ch].status;
1248
1249 case 0x70: ch ++;
1250 case 0x5c: ch ++;
1251 case 0x48: ch ++;
1252 case 0x34: /* MCSPI_CHCTRL */
1253 return s->ch[ch].control;
1254
1255 case 0x74: ch ++;
1256 case 0x60: ch ++;
1257 case 0x4c: ch ++;
1258 case 0x38: /* MCSPI_TX */
1259 return s->ch[ch].tx;
1260
1261 case 0x78: ch ++;
1262 case 0x64: ch ++;
1263 case 0x50: ch ++;
1264 case 0x3c: /* MCSPI_RX */
1265 s->ch[ch].status &= ~(1 << 0); /* RXS */
1266 ret = s->ch[ch].rx;
1267 omap_mcspi_transfer_run(s, ch);
1268 return ret;
1269 }
1270
1271 OMAP_BAD_REG(addr);
1272 return 0;
1273}
1274
1275static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
1276 uint32_t value)
1277{
1278 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1279 int offset = addr - s->base;
1280 int ch = 0;
1281
1282 switch (offset) {
1283 case 0x00: /* MCSPI_REVISION */
1284 case 0x14: /* MCSPI_SYSSTATUS */
1285 case 0x30: /* MCSPI_CHSTAT0 */
1286 case 0x3c: /* MCSPI_RX0 */
1287 case 0x44: /* MCSPI_CHSTAT1 */
1288 case 0x50: /* MCSPI_RX1 */
1289 case 0x58: /* MCSPI_CHSTAT2 */
1290 case 0x64: /* MCSPI_RX2 */
1291 case 0x6c: /* MCSPI_CHSTAT3 */
1292 case 0x78: /* MCSPI_RX3 */
1293 OMAP_RO_REG(addr);
1294 return;
1295
1296 case 0x10: /* MCSPI_SYSCONFIG */
1297 if (value & (1 << 1)) /* SOFTRESET */
1298 omap_mcspi_reset(s);
1299 s->sysconfig = value & 0x31d;
1300 break;
1301
1302 case 0x18: /* MCSPI_IRQSTATUS */
1303 if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
1304 s->irqst &= ~value;
1305 omap_mcspi_interrupt_update(s);
1306 }
1307 break;
1308
1309 case 0x1c: /* MCSPI_IRQENABLE */
1310 s->irqen = value & 0x1777f;
1311 omap_mcspi_interrupt_update(s);
1312 break;
1313
1314 case 0x20: /* MCSPI_WAKEUPENABLE */
1315 s->wken = value & 1;
1316 break;
1317
1318 case 0x24: /* MCSPI_SYST */
1319 if (s->control & (1 << 3)) /* SYSTEM_TEST */
1320 if (value & (1 << 11)) { /* SSB */
1321 s->irqst |= 0x1777f;
1322 omap_mcspi_interrupt_update(s);
1323 }
1324 s->systest = value & 0xfff;
1325 break;
1326
1327 case 0x28: /* MCSPI_MODULCTRL */
1328 if (value & (1 << 3)) /* SYSTEM_TEST */
1329 if (s->systest & (1 << 11)) { /* SSB */
1330 s->irqst |= 0x1777f;
1331 omap_mcspi_interrupt_update(s);
1332 }
1333 s->control = value & 0xf;
1334 break;
1335
1336 case 0x68: ch ++;
1337 case 0x54: ch ++;
1338 case 0x40: ch ++;
1339 case 0x2c: /* MCSPI_CHCONF */
1340 if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */
1341 omap_mcspi_dmarequest_update(s->ch + ch);
1342 if (((value >> 12) & 3) == 3) /* TRM */
1343 fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
1344 if (((value >> 7) & 0x1f) < 3) /* WL */
1345 fprintf(stderr, "%s: invalid WL value (%i)\n",
1346 __FUNCTION__, (value >> 7) & 0x1f);
1347 s->ch[ch].config = value & 0x7fffff;
1348 break;
1349
1350 case 0x70: ch ++;
1351 case 0x5c: ch ++;
1352 case 0x48: ch ++;
1353 case 0x34: /* MCSPI_CHCTRL */
1354 if (value & ~s->ch[ch].control & 1) { /* EN */
1355 s->ch[ch].control |= 1;
1356 omap_mcspi_transfer_run(s, ch);
1357 } else
1358 s->ch[ch].control = value & 1;
1359 break;
1360
1361 case 0x74: ch ++;
1362 case 0x60: ch ++;
1363 case 0x4c: ch ++;
1364 case 0x38: /* MCSPI_TX */
1365 s->ch[ch].tx = value;
1366 s->ch[ch].status &= ~(1 << 1); /* TXS */
1367 omap_mcspi_transfer_run(s, ch);
1368 break;
1369
1370 default:
1371 OMAP_BAD_REG(addr);
1372 return;
1373 }
1374}
1375
1376static CPUReadMemoryFunc *omap_mcspi_readfn[] = {
1377 omap_badwidth_read32,
1378 omap_badwidth_read32,
1379 omap_mcspi_read,
1380};
1381
1382static CPUWriteMemoryFunc *omap_mcspi_writefn[] = {
1383 omap_badwidth_write32,
1384 omap_badwidth_write32,
1385 omap_mcspi_write,
1386};
1387
1388struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
1389 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
1390{
1391 int iomemtype;
1392 struct omap_mcspi_s *s = (struct omap_mcspi_s *)
1393 qemu_mallocz(sizeof(struct omap_mcspi_s));
1394 struct omap_mcspi_ch_s *ch = s->ch;
1395
1396 s->irq = irq;
1397 s->chnum = chnum;
1398 while (chnum --) {
1399 ch->txdrq = *drq ++;
1400 ch->rxdrq = *drq ++;
1401 ch ++;
1402 }
1403 omap_mcspi_reset(s);
1404
c66fb5bc 1405 iomemtype = l4_register_io_memory(0, omap_mcspi_readfn,
827df9f3
AZ		 1406 omap_mcspi_writefn, s);
1407 s->base = omap_l4_attach(ta, 0, iomemtype);
1408
1409 return s;
1410}
1411
1412void omap_mcspi_attach(struct omap_mcspi_s *s,
e927bb00 1413 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
827df9f3
AZ		 1414 int chipselect)
1415{
1416 if (chipselect < 0 || chipselect >= s->chnum)
1417 cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n",
1418 __FUNCTION__, chipselect);
1419
1420 s->ch[chipselect].txrx = txrx;
1421 s->ch[chipselect].opaque = opaque;
1422}
1423
99570a40
AZ		 1424/* Enhanced Audio Controller (CODEC only) */
1425struct omap_eac_s {
1426 target_phys_addr_t base;
1427 qemu_irq irq;
1428
1429 uint16_t sysconfig;
1430 uint8_t config[4];
1431 uint8_t control;
1432 uint8_t address;
1433 uint16_t data;
1434 uint8_t vtol;
1435 uint8_t vtsl;
1436 uint16_t mixer;
1437 uint16_t gain[4];
1438 uint8_t att;
1439 uint16_t max[7];
1440
1441 struct {
1442 qemu_irq txdrq;
1443 qemu_irq rxdrq;
1444 uint32_t (*txrx)(void *opaque, uint32_t, int);
1445 void *opaque;
1446
1447#define EAC_BUF_LEN 1024
1448 uint32_t rxbuf[EAC_BUF_LEN];
1449 int rxlen;
1450 int rxavail;
1451 uint32_t txbuf[EAC_BUF_LEN];
1452 int txlen;
1453 int txavail;
1454
1455 int enable;
1456 int rate;
1457
1458 uint16_t config[4];
1459
1460 /* These need to be moved to the actual codec */
1461 QEMUSoundCard card;
1462 SWVoiceIn *in_voice;
1463 SWVoiceOut *out_voice;
1464 int hw_enable;
1465 } codec;
1466
1467 struct {
1468 uint8_t control;
1469 uint16_t config;
1470 } modem, bt;
1471};
1472
1473static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
1474{
1475 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
1476}
1477
1478static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
1479{
1480 qemu_set_irq(s->codec.rxdrq, s->codec.rxavail + s->codec.rxlen &&
1481 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
1482}
1483
1484static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
1485{
1486 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
1487 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
1488}
1489
1490static inline void omap_eac_in_refill(struct omap_eac_s *s)
1491{
1492 int left, start = 0;
1493
1494 s->codec.rxlen = MIN(s->codec.rxavail, EAC_BUF_LEN);
1495 s->codec.rxavail -= s->codec.rxlen;
1496
1497 for (left = s->codec.rxlen << 2; left; start = (EAC_BUF_LEN << 2) - left)
1498 left -= AUD_read(s->codec.in_voice,
1499 (uint8_t *) s->codec.rxbuf + start, left);
1500}
1501
1502static inline void omap_eac_out_empty(struct omap_eac_s *s)
1503{
1504 int left, start = 0;
1505
1506 for (left = s->codec.txlen << 2; left; start = (s->codec.txlen << 2) - left)
1507 left -= AUD_write(s->codec.out_voice,
1508 (uint8_t *) s->codec.txbuf + start, left);
1509
1510 s->codec.txavail -= s->codec.txlen;
1511 s->codec.txlen = 0;
1512}
1513
1514static void omap_eac_in_cb(void *opaque, int avail_b)
1515{
1516 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1517
1518 s->codec.rxavail = avail_b >> 2;
1519 omap_eac_in_dmarequest_update(s);
1520 /* TODO: possibly discard current buffer if overrun */
1521}
1522
1523static void omap_eac_out_cb(void *opaque, int free_b)
1524{
1525 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1526
1527 s->codec.txavail = free_b >> 2;
1528 if (s->codec.txlen > s->codec.txavail)
1529 s->codec.txlen = s->codec.txavail;
1530 omap_eac_out_empty(s);
1531 omap_eac_out_dmarequest_update(s);
1532}
1533
1534static void omap_eac_enable_update(struct omap_eac_s *s)
1535{
1536 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
1537 (s->codec.config[1] & 2) && /* AUDEN */
1538 s->codec.hw_enable;
1539}
1540
1541static const int omap_eac_fsint[4] = {
1542 8000,
1543 11025,
1544 22050,
1545 44100,
1546};
1547
1548static const int omap_eac_fsint2[8] = {
1549 8000,
1550 11025,
1551 22050,
1552 44100,
1553 48000,
1554 0, 0, 0,
1555};
1556
1557static const int omap_eac_fsint3[16] = {
1558 8000,
1559 11025,
1560 16000,
1561 22050,
1562 24000,
1563 32000,
1564 44100,
1565 48000,
1566 0, 0, 0, 0, 0, 0, 0, 0,
1567};
1568
1569static void omap_eac_rate_update(struct omap_eac_s *s)
1570{
1571 int fsint[3];
1572
1573 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
1574 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
1575 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
1576 if (fsint[2] < 0xf)
1577 s->codec.rate = omap_eac_fsint3[fsint[2]];
1578 else if (fsint[1] < 0x7)
1579 s->codec.rate = omap_eac_fsint2[fsint[1]];
1580 else
1581 s->codec.rate = omap_eac_fsint[fsint[0]];
1582}
1583
1584static void omap_eac_volume_update(struct omap_eac_s *s)
1585{
1586 /* TODO */
1587}
1588
1589static void omap_eac_format_update(struct omap_eac_s *s)
1590{
1591 audsettings_t fmt;
1592
1593 omap_eac_out_empty(s);
1594
1595 if (s->codec.in_voice) {
1596 AUD_set_active_in(s->codec.in_voice, 0);
1597 AUD_close_in(&s->codec.card, s->codec.in_voice);
1598 s->codec.in_voice = 0;
1599 }
1600 if (s->codec.out_voice) {
1601 AUD_set_active_out(s->codec.out_voice, 0);
1602 AUD_close_out(&s->codec.card, s->codec.out_voice);
1603 s->codec.out_voice = 0;
1604 }
1605
1606 omap_eac_enable_update(s);
1607 if (!s->codec.enable)
1608 return;
1609
1610 omap_eac_rate_update(s);
1611 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
1612 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
1613 fmt.freq = s->codec.rate;
1614 /* TODO: signedness possibly depends on the CODEC hardware - or
1615 * does I2S specify it? */
1616 /* All register writes are 16 bits so we we store 16-bit samples
1617 * in the buffers regardless of AGCFR[B8_16] value. */
1618 fmt.fmt = AUD_FMT_U16;
1619
1620 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
1621 "eac.codec.in", s, omap_eac_in_cb, &fmt);
1622 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
1623 "eac.codec.out", s, omap_eac_out_cb, &fmt);
1624
1625 omap_eac_volume_update(s);
1626
1627 AUD_set_active_in(s->codec.in_voice, 1);
1628 AUD_set_active_out(s->codec.out_voice, 1);
1629}
1630
1631static void omap_eac_reset(struct omap_eac_s *s)
1632{
1633 s->sysconfig = 0;
1634 s->config[0] = 0x0c;
1635 s->config[1] = 0x09;
1636 s->config[2] = 0xab;
1637 s->config[3] = 0x03;
1638 s->control = 0x00;
1639 s->address = 0x00;
1640 s->data = 0x0000;
1641 s->vtol = 0x00;
1642 s->vtsl = 0x00;
1643 s->mixer = 0x0000;
1644 s->gain[0] = 0xe7e7;
1645 s->gain[1] = 0x6767;
1646 s->gain[2] = 0x6767;
1647 s->gain[3] = 0x6767;
1648 s->att = 0xce;
1649 s->max[0] = 0;
1650 s->max[1] = 0;
1651 s->max[2] = 0;
1652 s->max[3] = 0;
1653 s->max[4] = 0;
1654 s->max[5] = 0;
1655 s->max[6] = 0;
1656
1657 s->modem.control = 0x00;
1658 s->modem.config = 0x0000;
1659 s->bt.control = 0x00;
1660 s->bt.config = 0x0000;
1661 s->codec.config[0] = 0x0649;
1662 s->codec.config[1] = 0x0000;
1663 s->codec.config[2] = 0x0007;
1664 s->codec.config[3] = 0x1ffc;
1665 s->codec.rxlen = 0;
1666 s->codec.txlen = 0;
1667 s->codec.rxavail = 0;
1668 s->codec.txavail = 0;
1669
1670 omap_eac_format_update(s);
1671 omap_eac_interrupt_update(s);
1672}
1673
1674static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
1675{
1676 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1677 int offset = addr - s->base;
1678
1679 switch (offset) {
1680 case 0x000: /* CPCFR1 */
1681 return s->config[0];
1682 case 0x004: /* CPCFR2 */
1683 return s->config[1];
1684 case 0x008: /* CPCFR3 */
1685 return s->config[2];
1686 case 0x00c: /* CPCFR4 */
1687 return s->config[3];
1688
1689 case 0x010: /* CPTCTL */
1690 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
1691 ((s->codec.txlen < s->codec.txavail) << 5);
1692
1693 case 0x014: /* CPTTADR */
1694 return s->address;
1695 case 0x018: /* CPTDATL */
1696 return s->data & 0xff;
1697 case 0x01c: /* CPTDATH */
1698 return s->data >> 8;
1699 case 0x020: /* CPTVSLL */
1700 return s->vtol;
1701 case 0x024: /* CPTVSLH */
1702 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
1703 case 0x040: /* MPCTR */
1704 return s->modem.control;
1705 case 0x044: /* MPMCCFR */
1706 return s->modem.config;
1707 case 0x060: /* BPCTR */
1708 return s->bt.control;
1709 case 0x064: /* BPMCCFR */
1710 return s->bt.config;
1711 case 0x080: /* AMSCFR */
1712 return s->mixer;
1713 case 0x084: /* AMVCTR */
1714 return s->gain[0];
1715 case 0x088: /* AM1VCTR */
1716 return s->gain[1];
1717 case 0x08c: /* AM2VCTR */
1718 return s->gain[2];
1719 case 0x090: /* AM3VCTR */
1720 return s->gain[3];
1721 case 0x094: /* ASTCTR */
1722 return s->att;
1723 case 0x098: /* APD1LCR */
1724 return s->max[0];
1725 case 0x09c: /* APD1RCR */
1726 return s->max[1];
1727 case 0x0a0: /* APD2LCR */
1728 return s->max[2];
1729 case 0x0a4: /* APD2RCR */
1730 return s->max[3];
1731 case 0x0a8: /* APD3LCR */
1732 return s->max[4];
1733 case 0x0ac: /* APD3RCR */
1734 return s->max[5];
1735 case 0x0b0: /* APD4R */
1736 return s->max[6];
1737 case 0x0b4: /* ADWR */
1738 /* This should be write-only? Docs list it as read-only. */
1739 return 0x0000;
1740 case 0x0b8: /* ADRDR */
1741 if (likely(s->codec.rxlen > 1))
1742 return s->codec.rxbuf[EAC_BUF_LEN - s->codec.rxlen --];
1743 else if (s->codec.rxlen) {
1744 if (s->codec.rxavail)
1745 omap_eac_in_refill(s);
1746 else {
1747 s->codec.rxlen = 0;
1748 omap_eac_in_dmarequest_update(s);
1749 }
1750 return s->codec.rxbuf[EAC_BUF_LEN - 1];
1751 }
1752 return 0x0000;
1753 case 0x0bc: /* AGCFR */
1754 return s->codec.config[0];
1755 case 0x0c0: /* AGCTR */
1756 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
1757 case 0x0c4: /* AGCFR2 */
1758 return s->codec.config[2];
1759 case 0x0c8: /* AGCFR3 */
1760 return s->codec.config[3];
1761 case 0x0cc: /* MBPDMACTR */
1762 case 0x0d0: /* MPDDMARR */
1763 case 0x0d8: /* MPUDMARR */
1764 case 0x0e4: /* BPDDMARR */
1765 case 0x0ec: /* BPUDMARR */
1766 return 0x0000;
1767
1768 case 0x100: /* VERSION_NUMBER */
1769 return 0x0010;
1770
1771 case 0x104: /* SYSCONFIG */
1772 return s->sysconfig;
1773
1774 case 0x108: /* SYSSTATUS */
1775 return 1 | 0xe; /* RESETDONE | stuff */
1776 }
1777
1778 OMAP_BAD_REG(addr);
1779 return 0;
1780}
1781
1782static void omap_eac_write(void *opaque, target_phys_addr_t addr,
1783 uint32_t value)
1784{
1785 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1786 int offset = addr - s->base;
1787
1788 switch (offset) {
1789 case 0x098: /* APD1LCR */
1790 case 0x09c: /* APD1RCR */
1791 case 0x0a0: /* APD2LCR */
1792 case 0x0a4: /* APD2RCR */
1793 case 0x0a8: /* APD3LCR */
1794 case 0x0ac: /* APD3RCR */
1795 case 0x0b0: /* APD4R */
1796 case 0x0b8: /* ADRDR */
1797 case 0x0d0: /* MPDDMARR */
1798 case 0x0d8: /* MPUDMARR */
1799 case 0x0e4: /* BPDDMARR */
1800 case 0x0ec: /* BPUDMARR */
1801 case 0x100: /* VERSION_NUMBER */
1802 case 0x108: /* SYSSTATUS */
1803 OMAP_RO_REG(addr);
1804 return;
1805
1806 case 0x000: /* CPCFR1 */
1807 s->config[0] = value & 0xff;
1808 omap_eac_format_update(s);
1809 break;
1810 case 0x004: /* CPCFR2 */
1811 s->config[1] = value & 0xff;
1812 omap_eac_format_update(s);
1813 break;
1814 case 0x008: /* CPCFR3 */
1815 s->config[2] = value & 0xff;
1816 omap_eac_format_update(s);
1817 break;
1818 case 0x00c: /* CPCFR4 */
1819 s->config[3] = value & 0xff;
1820 omap_eac_format_update(s);
1821 break;
1822
1823 case 0x010: /* CPTCTL */
1824 /* Assuming TXF and TXE bits are read-only... */
1825 s->control = value & 0x5f;
1826 omap_eac_interrupt_update(s);
1827 break;
1828
1829 case 0x014: /* CPTTADR */
1830 s->address = value & 0xff;
1831 break;
1832 case 0x018: /* CPTDATL */
1833 s->data &= 0xff00;
1834 s->data |= value & 0xff;
1835 break;
1836 case 0x01c: /* CPTDATH */
1837 s->data &= 0x00ff;
1838 s->data |= value << 8;
1839 break;
1840 case 0x020: /* CPTVSLL */
1841 s->vtol = value & 0xf8;
1842 break;
1843 case 0x024: /* CPTVSLH */
1844 s->vtsl = value & 0x9f;
1845 break;
1846 case 0x040: /* MPCTR */
1847 s->modem.control = value & 0x8f;
1848 break;
1849 case 0x044: /* MPMCCFR */
1850 s->modem.config = value & 0x7fff;
1851 break;
1852 case 0x060: /* BPCTR */
1853 s->bt.control = value & 0x8f;
1854 break;
1855 case 0x064: /* BPMCCFR */
1856 s->bt.config = value & 0x7fff;
1857 break;
1858 case 0x080: /* AMSCFR */
1859 s->mixer = value & 0x0fff;
1860 break;
1861 case 0x084: /* AMVCTR */
1862 s->gain[0] = value & 0xffff;
1863 break;
1864 case 0x088: /* AM1VCTR */
1865 s->gain[1] = value & 0xff7f;
1866 break;
1867 case 0x08c: /* AM2VCTR */
1868 s->gain[2] = value & 0xff7f;
1869 break;
1870 case 0x090: /* AM3VCTR */
1871 s->gain[3] = value & 0xff7f;
1872 break;
1873 case 0x094: /* ASTCTR */
1874 s->att = value & 0xff;
1875 break;
1876
1877 case 0x0b4: /* ADWR */
1878 s->codec.txbuf[s->codec.txlen ++] = value;
1879 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
1880 s->codec.txlen == s->codec.txavail)) {
1881 if (s->codec.txavail)
1882 omap_eac_out_empty(s);
1883 else
1884 s->codec.txlen = 0;
1885 }
1886 break;
1887
1888 case 0x0bc: /* AGCFR */
1889 s->codec.config[0] = value & 0x07ff;
1890 omap_eac_format_update(s);
1891 break;
1892 case 0x0c0: /* AGCTR */
1893 s->codec.config[1] = value & 0x780f;
1894 omap_eac_format_update(s);
1895 break;
1896 case 0x0c4: /* AGCFR2 */
1897 s->codec.config[2] = value & 0x003f;
1898 omap_eac_format_update(s);
1899 break;
1900 case 0x0c8: /* AGCFR3 */
1901 s->codec.config[3] = value & 0xffff;
1902 omap_eac_format_update(s);
1903 break;
1904 case 0x0cc: /* MBPDMACTR */
1905 case 0x0d4: /* MPDDMAWR */
1906 case 0x0e0: /* MPUDMAWR */
1907 case 0x0e8: /* BPDDMAWR */
1908 case 0x0f0: /* BPUDMAWR */
1909 break;
1910
1911 case 0x104: /* SYSCONFIG */
1912 if (value & (1 << 1)) /* SOFTRESET */
1913 omap_eac_reset(s);
1914 s->sysconfig = value & 0x31d;
1915 break;
1916
1917 default:
1918 OMAP_BAD_REG(addr);
1919 return;
1920 }
1921}
1922
1923static CPUReadMemoryFunc *omap_eac_readfn[] = {
1924 omap_badwidth_read16,
1925 omap_eac_read,
1926 omap_badwidth_read16,
1927};
1928
1929static CPUWriteMemoryFunc *omap_eac_writefn[] = {
1930 omap_badwidth_write16,
1931 omap_eac_write,
1932 omap_badwidth_write16,
1933};
1934
1935struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
1936 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
1937{
1938 int iomemtype;
1939 struct omap_eac_s *s = (struct omap_eac_s *)
1940 qemu_mallocz(sizeof(struct omap_eac_s));
1941
1942 s->irq = irq;
1943 s->codec.rxdrq = *drq ++;
1944 s->codec.txdrq = *drq ++;
1945 omap_eac_reset(s);
1946
1947#ifdef HAS_AUDIO
1948 /* TODO: do AUD_init globally for machine */
1949 AUD_register_card(AUD_init(), "OMAP EAC", &s->codec.card);
1950
1951 iomemtype = cpu_register_io_memory(0, omap_eac_readfn,
1952 omap_eac_writefn, s);
1953 s->base = omap_l4_attach(ta, 0, iomemtype);
1954#endif
1955
1956 return s;
1957}
1958
54585ffe
AZ		 1959/* STI/XTI (emulation interface) console - reverse engineered only */
1960struct omap_sti_s {
1961 target_phys_addr_t base;
1962 target_phys_addr_t channel_base;
1963 qemu_irq irq;
1964 CharDriverState *chr;
1965
1966 uint32_t sysconfig;
1967 uint32_t systest;
1968 uint32_t irqst;
1969 uint32_t irqen;
1970 uint32_t clkcontrol;
1971 uint32_t serial_config;
1972};
1973
1974#define STI_TRACE_CONSOLE_CHANNEL 239
1975#define STI_TRACE_CONTROL_CHANNEL 253
1976
1977static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
1978{
1979 qemu_set_irq(s->irq, s->irqst & s->irqen);
1980}
1981
1982static void omap_sti_reset(struct omap_sti_s *s)
1983{
1984 s->sysconfig = 0;
1985 s->irqst = 0;
1986 s->irqen = 0;
1987 s->clkcontrol = 0;
1988 s->serial_config = 0;
1989
1990 omap_sti_interrupt_update(s);
1991}
1992
1993static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
1994{
1995 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
1996 int offset = addr - s->base;
1997
1998 switch (offset) {
1999 case 0x00: /* STI_REVISION */
2000 return 0x10;
2001
2002 case 0x10: /* STI_SYSCONFIG */
2003 return s->sysconfig;
2004
2005 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
2006 return 0x00;
2007
2008 case 0x18: /* STI_IRQSTATUS */
2009 return s->irqst;
2010
2011 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
2012 return s->irqen;
2013
2014 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
2015 case 0x28: /* STI_RX_DR / XTI_RXDATA */
e927bb00
AZ		 2016 /* TODO */
2017 return 0;
54585ffe
AZ		 2018
2019 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
2020 return s->clkcontrol;
2021
2022 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
2023 return s->serial_config;
2024 }
2025
2026 OMAP_BAD_REG(addr);
2027 return 0;
2028}
2029
2030static void omap_sti_write(void *opaque, target_phys_addr_t addr,
2031 uint32_t value)
2032{
2033 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
2034 int offset = addr - s->base;
2035
2036 switch (offset) {
2037 case 0x00: /* STI_REVISION */
2038 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
2039 OMAP_RO_REG(addr);
2040 return;
2041
2042 case 0x10: /* STI_SYSCONFIG */
2043 if (value & (1 << 1)) /* SOFTRESET */
2044 omap_sti_reset(s);
2045 s->sysconfig = value & 0xfe;
2046 break;
2047
2048 case 0x18: /* STI_IRQSTATUS */
2049 s->irqst &= ~value;
2050 omap_sti_interrupt_update(s);
2051 break;
2052
2053 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
2054 s->irqen = value & 0xffff;
2055 omap_sti_interrupt_update(s);
2056 break;
2057
2058 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
2059 s->clkcontrol = value & 0xff;
2060 break;
2061
2062 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
2063 s->serial_config = value & 0xff;
2064 break;
2065
2066 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
2067 case 0x28: /* STI_RX_DR / XTI_RXDATA */
e927bb00
AZ		 2068 /* TODO */
2069 return;
2070
54585ffe
AZ		 2071 default:
2072 OMAP_BAD_REG(addr);
2073 return;
2074 }
2075}
2076
2077static CPUReadMemoryFunc *omap_sti_readfn[] = {
2078 omap_badwidth_read32,
2079 omap_badwidth_read32,
2080 omap_sti_read,
2081};
2082
2083static CPUWriteMemoryFunc *omap_sti_writefn[] = {
2084 omap_badwidth_write32,
2085 omap_badwidth_write32,
2086 omap_sti_write,
2087};
2088
2089static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
2090{
2091 OMAP_BAD_REG(addr);
2092 return 0;
2093}
2094
2095static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
2096 uint32_t value)
2097{
2098 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
2099 int offset = addr - s->channel_base;
2100 int ch = offset >> 6;
2101 uint8_t byte = value;
2102
2103 if (ch == STI_TRACE_CONTROL_CHANNEL) {
2104 /* Flush channel <i>value</i>. */
2105 qemu_chr_write(s->chr, "\r", 1);
2106 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
2107 if (value == 0xc0 || value == 0xc3) {
2108 /* Open channel <i>ch</i>. */
2109 } else if (value == 0x00)
2110 qemu_chr_write(s->chr, "\n", 1);
2111 else
2112 qemu_chr_write(s->chr, &byte, 1);
2113 }
2114}
2115
2116static CPUReadMemoryFunc *omap_sti_fifo_readfn[] = {
2117 omap_sti_fifo_read,
2118 omap_badwidth_read8,
2119 omap_badwidth_read8,
2120};
2121
2122static CPUWriteMemoryFunc *omap_sti_fifo_writefn[] = {
2123 omap_sti_fifo_write,
2124 omap_badwidth_write8,
2125 omap_badwidth_write8,
2126};
2127
2128struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
2129 target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
2130 CharDriverState *chr)
2131{
2132 int iomemtype;
2133 struct omap_sti_s *s = (struct omap_sti_s *)
2134 qemu_mallocz(sizeof(struct omap_sti_s));
2135
2136 s->irq = irq;
2137 omap_sti_reset(s);
2138
2139 s->chr = chr ?: qemu_chr_open("null");
2140
c66fb5bc 2141 iomemtype = l4_register_io_memory(0, omap_sti_readfn,
54585ffe
AZ		 2142 omap_sti_writefn, s);
2143 s->base = omap_l4_attach(ta, 0, iomemtype);
2144
2145 iomemtype = cpu_register_io_memory(0, omap_sti_fifo_readfn,
2146 omap_sti_fifo_writefn, s);
2147 s->channel_base = channel_base;
2148 cpu_register_physical_memory(s->channel_base, 0x10000, iomemtype);
2149
2150 return s;
2151}
2152
827df9f3
AZ		 2153/* L4 Interconnect */
2154struct omap_target_agent_s {
2155 struct omap_l4_s *bus;
2156 int regions;
2157 struct omap_l4_region_s *start;
2158 target_phys_addr_t base;
2159 uint32_t component;
2160 uint32_t control;
2161 uint32_t status;
2162};
2163
2164struct omap_l4_s {
2165 target_phys_addr_t base;
2166 int ta_num;
2167 struct omap_target_agent_s ta[0];
2168};
2169
c66fb5bc
AZ		 2170#ifdef L4_MUX_HACK
2171static int omap_l4_io_entries;
2172static int omap_cpu_io_entry;
2173static struct omap_l4_entry {
2174 CPUReadMemoryFunc **mem_read;
2175 CPUWriteMemoryFunc **mem_write;
2176 void *opaque;
2177} *omap_l4_io_entry;
2178static CPUReadMemoryFunc **omap_l4_io_readb_fn;
2179static CPUReadMemoryFunc **omap_l4_io_readh_fn;
2180static CPUReadMemoryFunc **omap_l4_io_readw_fn;
2181static CPUWriteMemoryFunc **omap_l4_io_writeb_fn;
2182static CPUWriteMemoryFunc **omap_l4_io_writeh_fn;
2183static CPUWriteMemoryFunc **omap_l4_io_writew_fn;
2184static void **omap_l4_io_opaque;
2185
2186int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
2187 CPUWriteMemoryFunc **mem_write, void *opaque)
2188{
2189 omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
2190 omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write;
2191 omap_l4_io_entry[omap_l4_io_entries].opaque = opaque;
2192
2193 return omap_l4_io_entries ++;
2194}
2195
2196static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
2197{
2198 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2199
2200 return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
2201}
2202
2203static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
2204{
2205 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2206
2207 return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
2208}
2209
2210static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
2211{
2212 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2213
2214 return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
2215}
2216
2217static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
2218 uint32_t value)
2219{
2220 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2221
2222 return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
2223}
2224
2225static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
2226 uint32_t value)
2227{
2228 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2229
2230 return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
2231}
2232
2233static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
2234 uint32_t value)
2235{
2236 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2237
2238 return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
2239}
2240
2241static CPUReadMemoryFunc *omap_l4_io_readfn[] = {
2242 omap_l4_io_readb,
2243 omap_l4_io_readh,
2244 omap_l4_io_readw,
2245};
2246
2247static CPUWriteMemoryFunc *omap_l4_io_writefn[] = {
2248 omap_l4_io_writeb,
2249 omap_l4_io_writeh,
2250 omap_l4_io_writew,
2251};
2252#endif
2253
827df9f3
AZ		 2254struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
2255{
2256 struct omap_l4_s *bus = qemu_mallocz(
2257 sizeof(*bus) + ta_num * sizeof(*bus->ta));
2258
2259 bus->ta_num = ta_num;
2260 bus->base = base;
2261
c66fb5bc
AZ		 2262#ifdef L4_MUX_HACK
2263 omap_l4_io_entries = 1;
2264 omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry));
2265
2266 omap_cpu_io_entry =
2267 cpu_register_io_memory(0, omap_l4_io_readfn,
2268 omap_l4_io_writefn, bus);
2269# define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
2270 omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2271 omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2272 omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2273 omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2274 omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2275 omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2276 omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES);
2277#endif
2278
827df9f3
AZ		 2279 return bus;
2280}
2281
2282static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
2283{
2284 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
2285 target_phys_addr_t reg = addr - s->base;
2286
2287 switch (reg) {
2288 case 0x00: /* COMPONENT */
2289 return s->component;
2290
2291 case 0x20: /* AGENT_CONTROL */
2292 return s->control;
2293
2294 case 0x28: /* AGENT_STATUS */
2295 return s->status;
2296 }
2297
2298 OMAP_BAD_REG(addr);
2299 return 0;
2300}
2301
2302static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
2303 uint32_t value)
2304{
2305 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
2306 target_phys_addr_t reg = addr - s->base;
2307
2308 switch (reg) {
2309 case 0x00: /* COMPONENT */
2310 case 0x28: /* AGENT_STATUS */
2311 OMAP_RO_REG(addr);
2312 break;
2313
2314 case 0x20: /* AGENT_CONTROL */
2315 s->control = value & 0x01000700;
2316 if (value & 1) /* OCP_RESET */
2317 s->status &= ~1; /* REQ_TIMEOUT */
2318 break;
2319
2320 default:
2321 OMAP_BAD_REG(addr);
2322 }
2323}
2324
2325static CPUReadMemoryFunc *omap_l4ta_readfn[] = {
2326 omap_badwidth_read16,
2327 omap_l4ta_read,
2328 omap_badwidth_read16,
2329};
2330
2331static CPUWriteMemoryFunc *omap_l4ta_writefn[] = {
2332 omap_badwidth_write32,
2333 omap_badwidth_write32,
2334 omap_l4ta_write,
2335};
2336
2337#define L4TA(n) (n)
2338#define L4TAO(n) ((n) + 39)
2339
2340static struct omap_l4_region_s {
2341 target_phys_addr_t offset;
2342 size_t size;
2343 int access;
2344} omap_l4_region[125] = {
2345 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
2346 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
2347 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
2348 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
2349 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
2350 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
2351 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
2352 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
2353 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
2354 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
2355 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
2356 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
2357 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
2358 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
2359 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
2360 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
2361 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
2362 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
2363 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
2364 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
2365 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
2366 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
2367 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
2368 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
2369 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
2370 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
2371 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
2372 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
2373 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
2374 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
2375 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
2376 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
2377 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
2378 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
2379 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
2380 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
2381 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
2382 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
2383 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
2384 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
2385 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
2386 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
2387 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
2388 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
2389 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
2390 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
2391 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
2392 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
2393 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
2394 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
2395 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
2396 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
2397 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
2398 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
2399 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
2400 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
2401 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
2402 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
2403 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
2404 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
2405 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
2406 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
2407 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
2408 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
2409 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
2410 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
2411 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
2412 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
2413 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
2414 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
2415 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
2416 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
2417 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
2418 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
2419 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
2420 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
2421 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
2422 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
2423 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
2424 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
2425 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
2426 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
2427 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
2428 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
2429 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
2430 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
2431 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
2432 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
2433 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
2434 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
2435 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
2436 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
2437 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
2438 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
2439 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
2440 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
2441 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
2442 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
2443 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
2444 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
2445 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
2446 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
2447 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
2448 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
2449 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
2450 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
2451 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
2452 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
2453 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
2454 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
2455 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
2456 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
2457 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
2458 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
2459 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
2460 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
2461 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
2462 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
2463 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
2464 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
2465 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
2466 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
2467 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
2468 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
2469 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
2470};
2471
2472static struct omap_l4_agent_info_s {
2473 int ta;
2474 int region;
2475 int regions;
2476 int ta_region;
2477} omap_l4_agent_info[54] = {
2478 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
2479 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
2480 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
2481 { L4TAO(3), 7, 3, 2 }, /* PRCM */
2482 { L4TA(1), 10, 2, 1 }, /* BCM */
2483 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
2484 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
2485 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
2486 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
2487 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
2488 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
2489 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
2490 { L4TA(12), 38, 2, 1 }, /* sDMA */
2491 { L4TA(13), 40, 5, 4 }, /* SSI */
2492 { L4TAO(4), 45, 2, 1 }, /* USB */
2493 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
2494 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
2495 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
2496 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
2497 { L4TA(18), 55, 2, 1 }, /* XTI */
2498 { L4TA(19), 57, 2, 1 }, /* UART1 */
2499 { L4TA(20), 59, 2, 1 }, /* UART2 */
2500 { L4TA(21), 61, 2, 1 }, /* UART3 */
2501 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
2502 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
2503 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
2504 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
2505 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
2506 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
2507 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
2508 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
2509 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
2510 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
2511 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
2512 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
2513 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
2514 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
2515 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
2516 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
2517 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
2518 { L4TA(32), 97, 2, 1 }, /* EAC */
2519 { L4TA(33), 99, 2, 1 }, /* FAC */
2520 { L4TA(34), 101, 2, 1 }, /* IPC */
2521 { L4TA(35), 103, 2, 1 }, /* SPI1 */
2522 { L4TA(36), 105, 2, 1 }, /* SPI2 */
2523 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
2524 { L4TAO(10), 109, 2, 1 },
2525 { L4TAO(11), 111, 2, 1 }, /* RNG */
2526 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
2527 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
2528 { L4TA(37), 117, 2, 1 }, /* AES */
2529 { L4TA(38), 119, 2, 1 }, /* PKA */
2530 { -1, 121, 2, 1 },
2531 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
2532};
2533
2534#define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs))
2535#define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs))
2536
2537struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
2538{
2539 int i, iomemtype;
2540 struct omap_target_agent_s *ta = 0;
2541 struct omap_l4_agent_info_s *info = 0;
2542
2543 for (i = 0; i < bus->ta_num; i ++)
2544 if (omap_l4_agent_info[i].ta == cs) {
2545 ta = &bus->ta[i];
2546 info = &omap_l4_agent_info[i];
2547 break;
2548 }
2549 if (!ta) {
2550 fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
2551 exit(-1);
2552 }
2553
2554 ta->bus = bus;
2555 ta->start = &omap_l4_region[info->region];
2556 ta->regions = info->regions;
827df9f3
AZ		 2557
2558 ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2559 ta->status = 0x00000000;
2560 ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
2561
c66fb5bc 2562 iomemtype = l4_register_io_memory(0, omap_l4ta_readfn,
827df9f3 2563 omap_l4ta_writefn, ta);
c66fb5bc 2564 ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
827df9f3
AZ		 2565
2566 return ta;
2567}
2568
2569target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
2570 int iotype)
2571{
2572 target_phys_addr_t base;
c66fb5bc
AZ		 2573 ssize_t size;
2574#ifdef L4_MUX_HACK
2575 int i;
2576#endif
827df9f3
AZ		 2577
2578 if (region < 0 || region >= ta->regions) {
2579 fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
2580 exit(-1);
2581 }
2582
2583 base = ta->bus->base + ta->start[region].offset;
2584 size = ta->start[region].size;
c66fb5bc
AZ		 2585 if (iotype) {
2586#ifndef L4_MUX_HACK
827df9f3 2587 cpu_register_physical_memory(base, size, iotype);
c66fb5bc
AZ		 2588#else
2589 cpu_register_physical_memory(base, size, omap_cpu_io_entry);
2590 i = (base - ta->bus->base) / TARGET_PAGE_SIZE;
2591 for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) {
2592 omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
2593 omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
2594 omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
2595 omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
2596 omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
2597 omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
2598 omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque;
2599 }
2600#endif
2601 }
827df9f3
AZ		 2602
2603 return base;
2604}
2605
2606/* TEST-Chip-level TAP */
2607static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
2608{
2609 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2610 target_phys_addr_t reg = addr - s->tap_base;
2611
2612 switch (reg) {
2613 case 0x204: /* IDCODE_reg */
2614 switch (s->mpu_model) {
2615 case omap2420:
2616 case omap2422:
2617 case omap2423:
2618 return 0x5b5d902f; /* ES 2.2 */
2619 case omap2430:
2620 return 0x5b68a02f; /* ES 2.2 */
2621 case omap3430:
2622 return 0x1b7ae02f; /* ES 2 */
2623 default:
2624 cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
2625 }
2626
2627 case 0x208: /* PRODUCTION_ID_reg for OMAP2 */
2628 case 0x210: /* PRODUCTION_ID_reg for OMAP3 */
2629 switch (s->mpu_model) {
2630 case omap2420:
2631 return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */
2632 case omap2422:
2633 return 0x000400f0;
2634 case omap2423:
2635 return 0x000800f0;
2636 case omap2430:
2637 return 0x000000f0;
2638 case omap3430:
2639 return 0x000000f0;
2640 default:
2641 cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
2642 }
2643
2644 case 0x20c:
2645 switch (s->mpu_model) {
2646 case omap2420:
2647 case omap2422:
2648 case omap2423:
2649 return 0xcafeb5d9; /* ES 2.2 */
2650 case omap2430:
2651 return 0xcafeb68a; /* ES 2.2 */
2652 case omap3430:
2653 return 0xcafeb7ae; /* ES 2 */
2654 default:
2655 cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
2656 }
2657
2658 case 0x218: /* DIE_ID_reg */
2659 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2660 case 0x21c: /* DIE_ID_reg */
2661 return 0x54 << 24;
2662 case 0x220: /* DIE_ID_reg */
2663 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2664 case 0x224: /* DIE_ID_reg */
2665 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2666 }
2667
2668 OMAP_BAD_REG(addr);
2669 return 0;
2670}
2671
2672static void omap_tap_write(void *opaque, target_phys_addr_t addr,
2673 uint32_t value)
2674{
2675 OMAP_BAD_REG(addr);
2676}
2677
2678static CPUReadMemoryFunc *omap_tap_readfn[] = {
2679 omap_badwidth_read32,
2680 omap_badwidth_read32,
2681 omap_tap_read,
2682};
2683
2684static CPUWriteMemoryFunc *omap_tap_writefn[] = {
2685 omap_badwidth_write32,
2686 omap_badwidth_write32,
2687 omap_tap_write,
2688};
2689
2690void omap_tap_init(struct omap_target_agent_s *ta,
2691 struct omap_mpu_state_s *mpu)
2692{
c66fb5bc 2693 mpu->tap_base = omap_l4_attach(ta, 0, l4_register_io_memory(0,
827df9f3
AZ		 2694 omap_tap_readfn, omap_tap_writefn, mpu));
2695}
2696
2697/* Power, Reset, and Clock Management */
2698struct omap_prcm_s {
2699 target_phys_addr_t base;
2700 qemu_irq irq[3];
2701 struct omap_mpu_state_s *mpu;
2702
2703 uint32_t irqst[3];
2704 uint32_t irqen[3];
2705
2706 uint32_t sysconfig;
2707 uint32_t voltctrl;
2708 uint32_t scratch[20];
2709
2710 uint32_t clksrc[1];
2711 uint32_t clkout[1];
2712 uint32_t clkemul[1];
2713 uint32_t clkpol[1];
2714 uint32_t clksel[8];
2715 uint32_t clken[12];
2716 uint32_t clkctrl[4];
2717 uint32_t clkidle[7];
2718 uint32_t setuptime[2];
2719
2720 uint32_t wkup[3];
2721 uint32_t wken[3];
2722 uint32_t wkst[3];
2723 uint32_t rst[4];
2724 uint32_t rstctrl[1];
2725 uint32_t power[4];
2726 uint32_t rsttime_wkup;
2727
2728 uint32_t ev;
2729 uint32_t evtime[2];
2730};
2731
2732static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
2733{
2734 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
2735 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
2736}
2737
2738static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
2739{
2740 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
2741 int offset = addr - s->base;
2742
2743 switch (offset) {
2744 case 0x000: /* PRCM_REVISION */
2745 return 0x10;
2746
2747 case 0x010: /* PRCM_SYSCONFIG */
2748 return s->sysconfig;
2749
2750 case 0x018: /* PRCM_IRQSTATUS_MPU */
2751 return s->irqst[0];
2752
2753 case 0x01c: /* PRCM_IRQENABLE_MPU */
2754 return s->irqen[0];
2755
2756 case 0x050: /* PRCM_VOLTCTRL */
2757 return s->voltctrl;
2758 case 0x054: /* PRCM_VOLTST */
2759 return s->voltctrl & 3;
2760
2761 case 0x060: /* PRCM_CLKSRC_CTRL */
2762 return s->clksrc[0];
2763 case 0x070: /* PRCM_CLKOUT_CTRL */
2764 return s->clkout[0];
2765 case 0x078: /* PRCM_CLKEMUL_CTRL */
2766 return s->clkemul[0];
2767 case 0x080: /* PRCM_CLKCFG_CTRL */
2768 case 0x084: /* PRCM_CLKCFG_STATUS */
2769 return 0;
2770
2771 case 0x090: /* PRCM_VOLTSETUP */
2772 return s->setuptime[0];
2773
2774 case 0x094: /* PRCM_CLKSSETUP */
2775 return s->setuptime[1];
2776
2777 case 0x098: /* PRCM_POLCTRL */
2778 return s->clkpol[0];
2779
2780 case 0x0b0: /* GENERAL_PURPOSE1 */
2781 case 0x0b4: /* GENERAL_PURPOSE2 */
2782 case 0x0b8: /* GENERAL_PURPOSE3 */
2783 case 0x0bc: /* GENERAL_PURPOSE4 */
2784 case 0x0c0: /* GENERAL_PURPOSE5 */
2785 case 0x0c4: /* GENERAL_PURPOSE6 */
2786 case 0x0c8: /* GENERAL_PURPOSE7 */
2787 case 0x0cc: /* GENERAL_PURPOSE8 */
2788 case 0x0d0: /* GENERAL_PURPOSE9 */
2789 case 0x0d4: /* GENERAL_PURPOSE10 */
2790 case 0x0d8: /* GENERAL_PURPOSE11 */
2791 case 0x0dc: /* GENERAL_PURPOSE12 */
2792 case 0x0e0: /* GENERAL_PURPOSE13 */
2793 case 0x0e4: /* GENERAL_PURPOSE14 */
2794 case 0x0e8: /* GENERAL_PURPOSE15 */
2795 case 0x0ec: /* GENERAL_PURPOSE16 */
2796 case 0x0f0: /* GENERAL_PURPOSE17 */
2797 case 0x0f4: /* GENERAL_PURPOSE18 */
2798 case 0x0f8: /* GENERAL_PURPOSE19 */
2799 case 0x0fc: /* GENERAL_PURPOSE20 */
2800 return s->scratch[(offset - 0xb0) >> 2];
2801
2802 case 0x140: /* CM_CLKSEL_MPU */
2803 return s->clksel[0];
2804 case 0x148: /* CM_CLKSTCTRL_MPU */
2805 return s->clkctrl[0];
2806
2807 case 0x158: /* RM_RSTST_MPU */
2808 return s->rst[0];
2809 case 0x1c8: /* PM_WKDEP_MPU */
2810 return s->wkup[0];
2811 case 0x1d4: /* PM_EVGENCTRL_MPU */
2812 return s->ev;
2813 case 0x1d8: /* PM_EVEGENONTIM_MPU */
2814 return s->evtime[0];
2815 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
2816 return s->evtime[1];
2817 case 0x1e0: /* PM_PWSTCTRL_MPU */
2818 return s->power[0];
2819 case 0x1e4: /* PM_PWSTST_MPU */
2820 return 0;
2821
2822 case 0x200: /* CM_FCLKEN1_CORE */
2823 return s->clken[0];
2824 case 0x204: /* CM_FCLKEN2_CORE */
2825 return s->clken[1];
2826 case 0x210: /* CM_ICLKEN1_CORE */
2827 return s->clken[2];
2828 case 0x214: /* CM_ICLKEN2_CORE */
2829 return s->clken[3];
2830 case 0x21c: /* CM_ICLKEN4_CORE */
2831 return s->clken[4];
2832
2833 case 0x220: /* CM_IDLEST1_CORE */
2834 /* TODO: check the actual iclk status */
2835 return 0x7ffffff9;
2836 case 0x224: /* CM_IDLEST2_CORE */
2837 /* TODO: check the actual iclk status */
2838 return 0x00000007;
2839 case 0x22c: /* CM_IDLEST4_CORE */
2840 /* TODO: check the actual iclk status */
2841 return 0x0000001f;
2842
2843 case 0x230: /* CM_AUTOIDLE1_CORE */
2844 return s->clkidle[0];
2845 case 0x234: /* CM_AUTOIDLE2_CORE */
2846 return s->clkidle[1];
2847 case 0x238: /* CM_AUTOIDLE3_CORE */
2848 return s->clkidle[2];
2849 case 0x23c: /* CM_AUTOIDLE4_CORE */
2850 return s->clkidle[3];
2851
2852 case 0x240: /* CM_CLKSEL1_CORE */
2853 return s->clksel[1];
2854 case 0x244: /* CM_CLKSEL2_CORE */
2855 return s->clksel[2];
2856
2857 case 0x248: /* CM_CLKSTCTRL_CORE */
2858 return s->clkctrl[1];
2859
2860 case 0x2a0: /* PM_WKEN1_CORE */
2861 return s->wken[0];
2862 case 0x2a4: /* PM_WKEN2_CORE */
2863 return s->wken[1];
2864
2865 case 0x2b0: /* PM_WKST1_CORE */
2866 return s->wkst[0];
2867 case 0x2b4: /* PM_WKST2_CORE */
2868 return s->wkst[1];
2869 case 0x2c8: /* PM_WKDEP_CORE */
2870 return 0x1e;
2871
2872 case 0x2e0: /* PM_PWSTCTRL_CORE */
2873 return s->power[1];
2874 case 0x2e4: /* PM_PWSTST_CORE */
2875 return 0x000030 | (s->power[1] & 0xfc00);
2876
2877 case 0x300: /* CM_FCLKEN_GFX */
2878 return s->clken[5];
2879 case 0x310: /* CM_ICLKEN_GFX */
2880 return s->clken[6];
2881 case 0x320: /* CM_IDLEST_GFX */
2882 /* TODO: check the actual iclk status */
2883 return 0x00000001;
2884 case 0x340: /* CM_CLKSEL_GFX */
2885 return s->clksel[3];
2886 case 0x348: /* CM_CLKSTCTRL_GFX */
2887 return s->clkctrl[2];
2888 case 0x350: /* RM_RSTCTRL_GFX */
2889 return s->rstctrl[0];
2890 case 0x358: /* RM_RSTST_GFX */
2891 return s->rst[1];
2892 case 0x3c8: /* PM_WKDEP_GFX */
2893 return s->wkup[1];
2894
2895 case 0x3e0: /* PM_PWSTCTRL_GFX */
2896 return s->power[2];
2897 case 0x3e4: /* PM_PWSTST_GFX */
2898 return s->power[2] & 3;
2899
2900 case 0x400: /* CM_FCLKEN_WKUP */
2901 return s->clken[7];
2902 case 0x410: /* CM_ICLKEN_WKUP */
2903 return s->clken[8];
2904 case 0x420: /* CM_IDLEST_WKUP */
2905 /* TODO: check the actual iclk status */
2906 return 0x0000003f;
2907 case 0x430: /* CM_AUTOIDLE_WKUP */
2908 return s->clkidle[4];
2909 case 0x440: /* CM_CLKSEL_WKUP */
2910 return s->clksel[4];
2911 case 0x450: /* RM_RSTCTRL_WKUP */
2912 return 0;
2913 case 0x454: /* RM_RSTTIME_WKUP */
2914 return s->rsttime_wkup;
2915 case 0x458: /* RM_RSTST_WKUP */
2916 return s->rst[2];
2917 case 0x4a0: /* PM_WKEN_WKUP */
2918 return s->wken[2];
2919 case 0x4b0: /* PM_WKST_WKUP */
2920 return s->wkst[2];
2921
2922 case 0x500: /* CM_CLKEN_PLL */
2923 return s->clken[9];
2924 case 0x520: /* CM_IDLEST_CKGEN */
2925 /* Core uses 32-kHz clock */
2926 if (!(s->clksel[6] & 3))
2927 return 0x00000377;
2928 /* DPLL not in lock mode, core uses ref_clk */
2929 if ((s->clken[9] & 3) != 3)
2930 return 0x00000375;
2931 /* Core uses DPLL */
2932 return 0x00000376;
2933 case 0x530: /* CM_AUTOIDLE_PLL */
2934 return s->clkidle[5];
2935 case 0x540: /* CM_CLKSEL1_PLL */
2936 return s->clksel[5];
2937 case 0x544: /* CM_CLKSEL2_PLL */
2938 return s->clksel[6];
2939
2940 case 0x800: /* CM_FCLKEN_DSP */
2941 return s->clken[10];
2942 case 0x810: /* CM_ICLKEN_DSP */
2943 return s->clken[11];
2944 case 0x820: /* CM_IDLEST_DSP */
2945 /* TODO: check the actual iclk status */
2946 return 0x00000103;
2947 case 0x830: /* CM_AUTOIDLE_DSP */
2948 return s->clkidle[6];
2949 case 0x840: /* CM_CLKSEL_DSP */
2950 return s->clksel[7];
2951 case 0x848: /* CM_CLKSTCTRL_DSP */
2952 return s->clkctrl[3];
2953 case 0x850: /* RM_RSTCTRL_DSP */
2954 return 0;
2955 case 0x858: /* RM_RSTST_DSP */
2956 return s->rst[3];
2957 case 0x8c8: /* PM_WKDEP_DSP */
2958 return s->wkup[2];
2959 case 0x8e0: /* PM_PWSTCTRL_DSP */
2960 return s->power[3];
2961 case 0x8e4: /* PM_PWSTST_DSP */
2962 return 0x008030 | (s->power[3] & 0x3003);
2963
2964 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
2965 return s->irqst[1];
2966 case 0x8f4: /* PRCM_IRQENABLE_DSP */
2967 return s->irqen[1];
2968
2969 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
2970 return s->irqst[2];
2971 case 0x8fc: /* PRCM_IRQENABLE_IVA */
2972 return s->irqen[2];
2973 }
2974
2975 OMAP_BAD_REG(addr);
2976 return 0;
2977}
2978
2979static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
2980 uint32_t value)
2981{
2982 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
2983 int offset = addr - s->base;
2984
2985 switch (offset) {
2986 case 0x000: /* PRCM_REVISION */
2987 case 0x054: /* PRCM_VOLTST */
2988 case 0x084: /* PRCM_CLKCFG_STATUS */
2989 case 0x1e4: /* PM_PWSTST_MPU */
2990 case 0x220: /* CM_IDLEST1_CORE */
2991 case 0x224: /* CM_IDLEST2_CORE */
2992 case 0x22c: /* CM_IDLEST4_CORE */
2993 case 0x2c8: /* PM_WKDEP_CORE */
2994 case 0x2e4: /* PM_PWSTST_CORE */
2995 case 0x320: /* CM_IDLEST_GFX */
2996 case 0x3e4: /* PM_PWSTST_GFX */
2997 case 0x420: /* CM_IDLEST_WKUP */
2998 case 0x520: /* CM_IDLEST_CKGEN */
2999 case 0x820: /* CM_IDLEST_DSP */
3000 case 0x8e4: /* PM_PWSTST_DSP */
3001 OMAP_RO_REG(addr);
3002 return;
3003
3004 case 0x010: /* PRCM_SYSCONFIG */
3005 s->sysconfig = value & 1;
3006 break;
3007
3008 case 0x018: /* PRCM_IRQSTATUS_MPU */
3009 s->irqst[0] &= ~value;
3010 omap_prcm_int_update(s, 0);
3011 break;
3012 case 0x01c: /* PRCM_IRQENABLE_MPU */
3013 s->irqen[0] = value & 0x3f;
3014 omap_prcm_int_update(s, 0);
3015 break;
3016
3017 case 0x050: /* PRCM_VOLTCTRL */
3018 s->voltctrl = value & 0xf1c3;
3019 break;
3020
3021 case 0x060: /* PRCM_CLKSRC_CTRL */
3022 s->clksrc[0] = value & 0xdb;
3023 /* TODO update clocks */
3024 break;
3025
3026 case 0x070: /* PRCM_CLKOUT_CTRL */
3027 s->clkout[0] = value & 0xbbbb;
3028 /* TODO update clocks */
3029 break;
3030
3031 case 0x078: /* PRCM_CLKEMUL_CTRL */
3032 s->clkemul[0] = value & 1;
3033 /* TODO update clocks */
3034 break;
3035
3036 case 0x080: /* PRCM_CLKCFG_CTRL */
3037 break;
3038
3039 case 0x090: /* PRCM_VOLTSETUP */
3040 s->setuptime[0] = value & 0xffff;
3041 break;
3042 case 0x094: /* PRCM_CLKSSETUP */
3043 s->setuptime[1] = value & 0xffff;
3044 break;
3045
3046 case 0x098: /* PRCM_POLCTRL */
3047 s->clkpol[0] = value & 0x701;
3048 break;
3049
3050 case 0x0b0: /* GENERAL_PURPOSE1 */
3051 case 0x0b4: /* GENERAL_PURPOSE2 */
3052 case 0x0b8: /* GENERAL_PURPOSE3 */
3053 case 0x0bc: /* GENERAL_PURPOSE4 */
3054 case 0x0c0: /* GENERAL_PURPOSE5 */
3055 case 0x0c4: /* GENERAL_PURPOSE6 */
3056 case 0x0c8: /* GENERAL_PURPOSE7 */
3057 case 0x0cc: /* GENERAL_PURPOSE8 */
3058 case 0x0d0: /* GENERAL_PURPOSE9 */
3059 case 0x0d4: /* GENERAL_PURPOSE10 */
3060 case 0x0d8: /* GENERAL_PURPOSE11 */
3061 case 0x0dc: /* GENERAL_PURPOSE12 */
3062 case 0x0e0: /* GENERAL_PURPOSE13 */
3063 case 0x0e4: /* GENERAL_PURPOSE14 */
3064 case 0x0e8: /* GENERAL_PURPOSE15 */
3065 case 0x0ec: /* GENERAL_PURPOSE16 */
3066 case 0x0f0: /* GENERAL_PURPOSE17 */
3067 case 0x0f4: /* GENERAL_PURPOSE18 */
3068 case 0x0f8: /* GENERAL_PURPOSE19 */
3069 case 0x0fc: /* GENERAL_PURPOSE20 */
3070 s->scratch[(offset - 0xb0) >> 2] = value;
3071 break;
3072
3073 case 0x140: /* CM_CLKSEL_MPU */
3074 s->clksel[0] = value & 0x1f;
3075 /* TODO update clocks */
3076 break;
3077 case 0x148: /* CM_CLKSTCTRL_MPU */
3078 s->clkctrl[0] = value & 0x1f;
3079 break;
3080
3081 case 0x158: /* RM_RSTST_MPU */
3082 s->rst[0] &= ~value;
3083 break;
3084 case 0x1c8: /* PM_WKDEP_MPU */
3085 s->wkup[0] = value & 0x15;
3086 break;
3087
3088 case 0x1d4: /* PM_EVGENCTRL_MPU */
3089 s->ev = value & 0x1f;
3090 break;
3091 case 0x1d8: /* PM_EVEGENONTIM_MPU */
3092 s->evtime[0] = value;
3093 break;
3094 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
3095 s->evtime[1] = value;
3096 break;
3097
3098 case 0x1e0: /* PM_PWSTCTRL_MPU */
3099 s->power[0] = value & 0xc0f;
3100 break;
3101
3102 case 0x200: /* CM_FCLKEN1_CORE */
3103 s->clken[0] = value & 0xbfffffff;
3104 /* TODO update clocks */
99570a40 3105 /* The EN_EAC bit only gets/puts func_96m_clk. */
827df9f3
AZ		 3106 break;
3107 case 0x204: /* CM_FCLKEN2_CORE */
3108 s->clken[1] = value & 0x00000007;
3109 /* TODO update clocks */
3110 break;
3111 case 0x210: /* CM_ICLKEN1_CORE */
3112 s->clken[2] = value & 0xfffffff9;
3113 /* TODO update clocks */
99570a40 3114 /* The EN_EAC bit only gets/puts core_l4_iclk. */
827df9f3
AZ		 3115 break;
3116 case 0x214: /* CM_ICLKEN2_CORE */
3117 s->clken[3] = value & 0x00000007;
3118 /* TODO update clocks */
3119 break;
3120 case 0x21c: /* CM_ICLKEN4_CORE */
3121 s->clken[4] = value & 0x0000001f;
3122 /* TODO update clocks */
3123 break;
3124
3125 case 0x230: /* CM_AUTOIDLE1_CORE */
3126 s->clkidle[0] = value & 0xfffffff9;
3127 /* TODO update clocks */
3128 break;
3129 case 0x234: /* CM_AUTOIDLE2_CORE */
3130 s->clkidle[1] = value & 0x00000007;
3131 /* TODO update clocks */
3132 break;
3133 case 0x238: /* CM_AUTOIDLE3_CORE */
3134 s->clkidle[2] = value & 0x00000007;
3135 /* TODO update clocks */
3136 break;
3137 case 0x23c: /* CM_AUTOIDLE4_CORE */
3138 s->clkidle[3] = value & 0x0000001f;
3139 /* TODO update clocks */
3140 break;
3141
3142 case 0x240: /* CM_CLKSEL1_CORE */
3143 s->clksel[1] = value & 0x0fffbf7f;
3144 /* TODO update clocks */
3145 break;
3146
3147 case 0x244: /* CM_CLKSEL2_CORE */
3148 s->clksel[2] = value & 0x00fffffc;
3149 /* TODO update clocks */
3150 break;
3151
3152 case 0x248: /* CM_CLKSTCTRL_CORE */
3153 s->clkctrl[1] = value & 0x7;
3154 break;
3155
3156 case 0x2a0: /* PM_WKEN1_CORE */
3157 s->wken[0] = value & 0x04667ff8;
3158 break;
3159 case 0x2a4: /* PM_WKEN2_CORE */
3160 s->wken[1] = value & 0x00000005;
3161 break;
3162
3163 case 0x2b0: /* PM_WKST1_CORE */
3164 s->wkst[0] &= ~value;
3165 break;
3166 case 0x2b4: /* PM_WKST2_CORE */
3167 s->wkst[1] &= ~value;
3168 break;
3169
3170 case 0x2e0: /* PM_PWSTCTRL_CORE */
3171 s->power[1] = (value & 0x00fc3f) | (1 << 2);
3172 break;
3173
3174 case 0x300: /* CM_FCLKEN_GFX */
3175 s->clken[5] = value & 6;
3176 /* TODO update clocks */
3177 break;
3178 case 0x310: /* CM_ICLKEN_GFX */
3179 s->clken[6] = value & 1;
3180 /* TODO update clocks */
3181 break;
3182 case 0x340: /* CM_CLKSEL_GFX */
3183 s->clksel[3] = value & 7;
3184 /* TODO update clocks */
3185 break;
3186 case 0x348: /* CM_CLKSTCTRL_GFX */
3187 s->clkctrl[2] = value & 1;
3188 break;
3189 case 0x350: /* RM_RSTCTRL_GFX */
3190 s->rstctrl[0] = value & 1;
3191 /* TODO: reset */
3192 break;
3193 case 0x358: /* RM_RSTST_GFX */
3194 s->rst[1] &= ~value;
3195 break;
3196 case 0x3c8: /* PM_WKDEP_GFX */
3197 s->wkup[1] = value & 0x13;
3198 break;
3199 case 0x3e0: /* PM_PWSTCTRL_GFX */
3200 s->power[2] = (value & 0x00c0f) | (3 << 2);
3201 break;
3202
3203 case 0x400: /* CM_FCLKEN_WKUP */
3204 s->clken[7] = value & 0xd;
3205 /* TODO update clocks */
3206 break;
3207 case 0x410: /* CM_ICLKEN_WKUP */
3208 s->clken[8] = value & 0x3f;
3209 /* TODO update clocks */
3210 break;
3211 case 0x430: /* CM_AUTOIDLE_WKUP */
3212 s->clkidle[4] = value & 0x0000003f;
3213 /* TODO update clocks */
3214 break;
3215 case 0x440: /* CM_CLKSEL_WKUP */
3216 s->clksel[4] = value & 3;
3217 /* TODO update clocks */
3218 break;
3219 case 0x450: /* RM_RSTCTRL_WKUP */
3220 /* TODO: reset */
3221 if (value & 2)
3222 qemu_system_reset_request();
3223 break;
3224 case 0x454: /* RM_RSTTIME_WKUP */
3225 s->rsttime_wkup = value & 0x1fff;
3226 break;
3227 case 0x458: /* RM_RSTST_WKUP */
3228 s->rst[2] &= ~value;
3229 break;
3230 case 0x4a0: /* PM_WKEN_WKUP */
3231 s->wken[2] = value & 0x00000005;
3232 break;
3233 case 0x4b0: /* PM_WKST_WKUP */
3234 s->wkst[2] &= ~value;
3235 break;
3236
3237 case 0x500: /* CM_CLKEN_PLL */
3238 s->clken[9] = value & 0xcf;
3239 /* TODO update clocks */
3240 break;
3241 case 0x530: /* CM_AUTOIDLE_PLL */
3242 s->clkidle[5] = value & 0x000000cf;
3243 /* TODO update clocks */
3244 break;
3245 case 0x540: /* CM_CLKSEL1_PLL */
3246 s->clksel[5] = value & 0x03bfff28;
3247 /* TODO update clocks */
3248 break;
3249 case 0x544: /* CM_CLKSEL2_PLL */
3250 s->clksel[6] = value & 3;
3251 /* TODO update clocks */
3252 break;
3253
3254 case 0x800: /* CM_FCLKEN_DSP */
3255 s->clken[10] = value & 0x501;
3256 /* TODO update clocks */
3257 break;
3258 case 0x810: /* CM_ICLKEN_DSP */
3259 s->clken[11] = value & 0x2;
3260 /* TODO update clocks */
3261 break;
3262 case 0x830: /* CM_AUTOIDLE_DSP */
3263 s->clkidle[6] = value & 0x2;
3264 /* TODO update clocks */
3265 break;
3266 case 0x840: /* CM_CLKSEL_DSP */
3267 s->clksel[7] = value & 0x3fff;
3268 /* TODO update clocks */
3269 break;
3270 case 0x848: /* CM_CLKSTCTRL_DSP */
3271 s->clkctrl[3] = value & 0x101;
3272 break;
3273 case 0x850: /* RM_RSTCTRL_DSP */
3274 /* TODO: reset */
3275 break;
3276 case 0x858: /* RM_RSTST_DSP */
3277 s->rst[3] &= ~value;
3278 break;
3279 case 0x8c8: /* PM_WKDEP_DSP */
3280 s->wkup[2] = value & 0x13;
3281 break;
3282 case 0x8e0: /* PM_PWSTCTRL_DSP */
3283 s->power[3] = (value & 0x03017) | (3 << 2);
3284 break;
3285
3286 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
3287 s->irqst[1] &= ~value;
3288 omap_prcm_int_update(s, 1);
3289 break;
3290 case 0x8f4: /* PRCM_IRQENABLE_DSP */
3291 s->irqen[1] = value & 0x7;
3292 omap_prcm_int_update(s, 1);
3293 break;
3294
3295 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
3296 s->irqst[2] &= ~value;
3297 omap_prcm_int_update(s, 2);
3298 break;
3299 case 0x8fc: /* PRCM_IRQENABLE_IVA */
3300 s->irqen[2] = value & 0x7;
3301 omap_prcm_int_update(s, 2);
3302 break;
3303
3304 default:
3305 OMAP_BAD_REG(addr);
3306 return;
3307 }
3308}
3309
3310static CPUReadMemoryFunc *omap_prcm_readfn[] = {
3311 omap_badwidth_read32,
3312 omap_badwidth_read32,
3313 omap_prcm_read,
3314};
3315
3316static CPUWriteMemoryFunc *omap_prcm_writefn[] = {
3317 omap_badwidth_write32,
3318 omap_badwidth_write32,
3319 omap_prcm_write,
3320};
3321
3322static void omap_prcm_reset(struct omap_prcm_s *s)
3323{
3324 s->sysconfig = 0;
3325 s->irqst[0] = 0;
3326 s->irqst[1] = 0;
3327 s->irqst[2] = 0;
3328 s->irqen[0] = 0;
3329 s->irqen[1] = 0;
3330 s->irqen[2] = 0;
3331 s->voltctrl = 0x1040;
3332 s->ev = 0x14;
3333 s->evtime[0] = 0;
3334 s->evtime[1] = 0;
3335 s->clkctrl[0] = 0;
3336 s->clkctrl[1] = 0;
3337 s->clkctrl[2] = 0;
3338 s->clkctrl[3] = 0;
3339 s->clken[1] = 7;
3340 s->clken[3] = 7;
3341 s->clken[4] = 0;
3342 s->clken[5] = 0;
3343 s->clken[6] = 0;
3344 s->clken[7] = 0xc;
3345 s->clken[8] = 0x3e;
3346 s->clken[9] = 0x0d;
3347 s->clken[10] = 0;
3348 s->clken[11] = 0;
3349 s->clkidle[0] = 0;
3350 s->clkidle[2] = 7;
3351 s->clkidle[3] = 0;
3352 s->clkidle[4] = 0;
3353 s->clkidle[5] = 0x0c;
3354 s->clkidle[6] = 0;
3355 s->clksel[0] = 0x01;
3356 s->clksel[1] = 0x02100121;
3357 s->clksel[2] = 0x00000000;
3358 s->clksel[3] = 0x01;
3359 s->clksel[4] = 0;
3360 s->clksel[7] = 0x0121;
3361 s->wkup[0] = 0x15;
3362 s->wkup[1] = 0x13;
3363 s->wkup[2] = 0x13;
3364 s->wken[0] = 0x04667ff8;
3365 s->wken[1] = 0x00000005;
3366 s->wken[2] = 5;
3367 s->wkst[0] = 0;
3368 s->wkst[1] = 0;
3369 s->wkst[2] = 0;
3370 s->power[0] = 0x00c;
3371 s->power[1] = 4;
3372 s->power[2] = 0x0000c;
3373 s->power[3] = 0x14;
3374 s->rstctrl[0] = 1;
3375 s->rst[3] = 1;
3376}
3377
3378static void omap_prcm_coldreset(struct omap_prcm_s *s)
3379{
3380 s->setuptime[0] = 0;
3381 s->setuptime[1] = 0;
3382 memset(&s->scratch, 0, sizeof(s->scratch));
3383 s->rst[0] = 0x01;
3384 s->rst[1] = 0x00;
3385 s->rst[2] = 0x01;
3386 s->clken[0] = 0;
3387 s->clken[2] = 0;
3388 s->clkidle[1] = 0;
3389 s->clksel[5] = 0;
3390 s->clksel[6] = 2;
3391 s->clksrc[0] = 0x43;
3392 s->clkout[0] = 0x0303;
3393 s->clkemul[0] = 0;
3394 s->clkpol[0] = 0x100;
3395 s->rsttime_wkup = 0x1002;
3396
3397 omap_prcm_reset(s);
3398}
3399
3400struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
3401 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
3402 struct omap_mpu_state_s *mpu)
3403{
3404 int iomemtype;
3405 struct omap_prcm_s *s = (struct omap_prcm_s *)
3406 qemu_mallocz(sizeof(struct omap_prcm_s));
3407
3408 s->irq[0] = mpu_int;
3409 s->irq[1] = dsp_int;
3410 s->irq[2] = iva_int;
3411 s->mpu = mpu;
3412 omap_prcm_coldreset(s);
3413
c66fb5bc 3414 iomemtype = l4_register_io_memory(0, omap_prcm_readfn,
827df9f3
AZ		 3415 omap_prcm_writefn, s);
3416 s->base = omap_l4_attach(ta, 0, iomemtype);
3417 omap_l4_attach(ta, 1, iomemtype);
3418
3419 return s;
3420}
3421
3422/* System and Pinout control */
3423struct omap_sysctl_s {
3424 target_phys_addr_t base;
3425 struct omap_mpu_state_s *mpu;
3426
3427 uint32_t sysconfig;
3428 uint32_t devconfig;
3429 uint32_t psaconfig;
3430 uint32_t padconf[0x45];
3431 uint8_t obs;
3432 uint32_t msuspendmux[5];
3433};
3434
3435static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
3436{
3437 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3438 int offset = addr - s->base;
3439
3440 switch (offset) {
3441 case 0x000: /* CONTROL_REVISION */
3442 return 0x20;
3443
3444 case 0x010: /* CONTROL_SYSCONFIG */
3445 return s->sysconfig;
3446
3447 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3448 return s->padconf[(offset - 0x30) >> 2];
3449
3450 case 0x270: /* CONTROL_DEBOBS */
3451 return s->obs;
3452
3453 case 0x274: /* CONTROL_DEVCONF */
3454 return s->devconfig;
3455
3456 case 0x28c: /* CONTROL_EMU_SUPPORT */
3457 return 0;
3458
3459 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
3460 return s->msuspendmux[0];
3461 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
3462 return s->msuspendmux[1];
3463 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
3464 return s->msuspendmux[2];
3465 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
3466 return s->msuspendmux[3];
3467 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
3468 return s->msuspendmux[4];
3469 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
3470 return 0;
3471
3472 case 0x2b8: /* CONTROL_PSA_CTRL */
3473 return s->psaconfig;
3474 case 0x2bc: /* CONTROL_PSA_CMD */
3475 case 0x2c0: /* CONTROL_PSA_VALUE */
3476 return 0;
3477
3478 case 0x2b0: /* CONTROL_SEC_CTRL */
3479 return 0x800000f1;
3480 case 0x2d0: /* CONTROL_SEC_EMU */
3481 return 0x80000015;
3482 case 0x2d4: /* CONTROL_SEC_TAP */
3483 return 0x8000007f;
3484 case 0x2b4: /* CONTROL_SEC_TEST */
3485 case 0x2f0: /* CONTROL_SEC_STATUS */
3486 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
3487 /* Secure mode is not present on general-pusrpose device. Outside
3488 * secure mode these values cannot be read or written. */
3489 return 0;
3490
3491 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
3492 return 0xff;
3493 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
3494 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
3495 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
3496 /* No secure mode so no Extended Secure RAM present. */
3497 return 0;
3498
3499 case 0x2f8: /* CONTROL_STATUS */
3500 /* Device Type => General-purpose */
3501 return 0x0300;
3502 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
3503
3504 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
3505 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
3506 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
3507 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
3508 return 0xdecafbad;
3509
3510 case 0x310: /* CONTROL_RAND_KEY_0 */
3511 case 0x314: /* CONTROL_RAND_KEY_1 */
3512 case 0x318: /* CONTROL_RAND_KEY_2 */
3513 case 0x31c: /* CONTROL_RAND_KEY_3 */
3514 case 0x320: /* CONTROL_CUST_KEY_0 */
3515 case 0x324: /* CONTROL_CUST_KEY_1 */
3516 case 0x330: /* CONTROL_TEST_KEY_0 */
3517 case 0x334: /* CONTROL_TEST_KEY_1 */
3518 case 0x338: /* CONTROL_TEST_KEY_2 */
3519 case 0x33c: /* CONTROL_TEST_KEY_3 */
3520 case 0x340: /* CONTROL_TEST_KEY_4 */
3521 case 0x344: /* CONTROL_TEST_KEY_5 */
3522 case 0x348: /* CONTROL_TEST_KEY_6 */
3523 case 0x34c: /* CONTROL_TEST_KEY_7 */
3524 case 0x350: /* CONTROL_TEST_KEY_8 */
3525 case 0x354: /* CONTROL_TEST_KEY_9 */
3526 /* Can only be accessed in secure mode and when C_FieldAccEnable
3527 * bit is set in CONTROL_SEC_CTRL.
3528 * TODO: otherwise an interconnect access error is generated. */
3529 return 0;
3530 }
3531
3532 OMAP_BAD_REG(addr);
3533 return 0;
3534}
3535
3536static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
3537 uint32_t value)
3538{
3539 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3540 int offset = addr - s->base;
3541
3542 switch (offset) {
3543 case 0x000: /* CONTROL_REVISION */
3544 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
3545 case 0x2c0: /* CONTROL_PSA_VALUE */
3546 case 0x2f8: /* CONTROL_STATUS */
3547 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
3548 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
3549 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
3550 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
3551 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
3552 case 0x310: /* CONTROL_RAND_KEY_0 */
3553 case 0x314: /* CONTROL_RAND_KEY_1 */
3554 case 0x318: /* CONTROL_RAND_KEY_2 */
3555 case 0x31c: /* CONTROL_RAND_KEY_3 */
3556 case 0x320: /* CONTROL_CUST_KEY_0 */
3557 case 0x324: /* CONTROL_CUST_KEY_1 */
3558 case 0x330: /* CONTROL_TEST_KEY_0 */
3559 case 0x334: /* CONTROL_TEST_KEY_1 */
3560 case 0x338: /* CONTROL_TEST_KEY_2 */
3561 case 0x33c: /* CONTROL_TEST_KEY_3 */
3562 case 0x340: /* CONTROL_TEST_KEY_4 */
3563 case 0x344: /* CONTROL_TEST_KEY_5 */
3564 case 0x348: /* CONTROL_TEST_KEY_6 */
3565 case 0x34c: /* CONTROL_TEST_KEY_7 */
3566 case 0x350: /* CONTROL_TEST_KEY_8 */
3567 case 0x354: /* CONTROL_TEST_KEY_9 */
3568 OMAP_RO_REG(addr);
3569 return;
3570
3571 case 0x010: /* CONTROL_SYSCONFIG */
3572 s->sysconfig = value & 0x1e;
3573 break;
3574
3575 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3576 /* XXX: should check constant bits */
3577 s->padconf[(offset - 0x30) >> 2] = value & 0x1f1f1f1f;
3578 break;
3579
3580 case 0x270: /* CONTROL_DEBOBS */
3581 s->obs = value & 0xff;
3582 break;
3583
3584 case 0x274: /* CONTROL_DEVCONF */
3585 s->devconfig = value & 0xffffc7ff;
3586 break;
3587
3588 case 0x28c: /* CONTROL_EMU_SUPPORT */
3589 break;
3590
3591 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
3592 s->msuspendmux[0] = value & 0x3fffffff;
3593 break;
3594 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
3595 s->msuspendmux[1] = value & 0x3fffffff;
3596 break;
3597 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
3598 s->msuspendmux[2] = value & 0x3fffffff;
3599 break;
3600 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
3601 s->msuspendmux[3] = value & 0x3fffffff;
3602 break;
3603 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
3604 s->msuspendmux[4] = value & 0x3fffffff;
3605 break;
3606
3607 case 0x2b8: /* CONTROL_PSA_CTRL */
3608 s->psaconfig = value & 0x1c;
3609 s->psaconfig |= (value & 0x20) ? 2 : 1;
3610 break;
3611 case 0x2bc: /* CONTROL_PSA_CMD */
3612 break;
3613
3614 case 0x2b0: /* CONTROL_SEC_CTRL */
3615 case 0x2b4: /* CONTROL_SEC_TEST */
3616 case 0x2d0: /* CONTROL_SEC_EMU */
3617 case 0x2d4: /* CONTROL_SEC_TAP */
3618 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
3619 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
3620 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
3621 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
3622 case 0x2f0: /* CONTROL_SEC_STATUS */
3623 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
3624 break;
3625
3626 default:
3627 OMAP_BAD_REG(addr);
3628 return;
3629 }
3630}
3631
3632static CPUReadMemoryFunc *omap_sysctl_readfn[] = {
3633 omap_badwidth_read32, /* TODO */
3634 omap_badwidth_read32, /* TODO */
3635 omap_sysctl_read,
3636};
3637
3638static CPUWriteMemoryFunc *omap_sysctl_writefn[] = {
3639 omap_badwidth_write32, /* TODO */
3640 omap_badwidth_write32, /* TODO */
3641 omap_sysctl_write,
3642};
3643
3644static void omap_sysctl_reset(struct omap_sysctl_s *s)
3645{
3646 /* (power-on reset) */
3647 s->sysconfig = 0;
3648 s->obs = 0;
3649 s->devconfig = 0x0c000000;
3650 s->msuspendmux[0] = 0x00000000;
3651 s->msuspendmux[1] = 0x00000000;
3652 s->msuspendmux[2] = 0x00000000;
3653 s->msuspendmux[3] = 0x00000000;
3654 s->msuspendmux[4] = 0x00000000;
3655 s->psaconfig = 1;
3656
3657 s->padconf[0x00] = 0x000f0f0f;
3658 s->padconf[0x01] = 0x00000000;
3659 s->padconf[0x02] = 0x00000000;
3660 s->padconf[0x03] = 0x00000000;
3661 s->padconf[0x04] = 0x00000000;
3662 s->padconf[0x05] = 0x00000000;
3663 s->padconf[0x06] = 0x00000000;
3664 s->padconf[0x07] = 0x00000000;
3665 s->padconf[0x08] = 0x08080800;
3666 s->padconf[0x09] = 0x08080808;
3667 s->padconf[0x0a] = 0x08080808;
3668 s->padconf[0x0b] = 0x08080808;
3669 s->padconf[0x0c] = 0x08080808;
3670 s->padconf[0x0d] = 0x08080800;
3671 s->padconf[0x0e] = 0x08080808;
3672 s->padconf[0x0f] = 0x08080808;
3673 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
3674 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
3675 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
3676 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
3677 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
3678 s->padconf[0x15] = 0x18181818;
3679 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
3680 s->padconf[0x17] = 0x1f001f00;
3681 s->padconf[0x18] = 0x1f1f1f1f;
3682 s->padconf[0x19] = 0x00000000;
3683 s->padconf[0x1a] = 0x1f180000;
3684 s->padconf[0x1b] = 0x00001f1f;
3685 s->padconf[0x1c] = 0x1f001f00;
3686 s->padconf[0x1d] = 0x00000000;
3687 s->padconf[0x1e] = 0x00000000;
3688 s->padconf[0x1f] = 0x08000000;
3689 s->padconf[0x20] = 0x08080808;
3690 s->padconf[0x21] = 0x08080808;
3691 s->padconf[0x22] = 0x0f080808;
3692 s->padconf[0x23] = 0x0f0f0f0f;
3693 s->padconf[0x24] = 0x000f0f0f;
3694 s->padconf[0x25] = 0x1f1f1f0f;
3695 s->padconf[0x26] = 0x080f0f1f;
3696 s->padconf[0x27] = 0x070f1808;
3697 s->padconf[0x28] = 0x0f070707;
3698 s->padconf[0x29] = 0x000f0f1f;
3699 s->padconf[0x2a] = 0x0f0f0f1f;
3700 s->padconf[0x2b] = 0x08000000;
3701 s->padconf[0x2c] = 0x0000001f;
3702 s->padconf[0x2d] = 0x0f0f1f00;
3703 s->padconf[0x2e] = 0x1f1f0f0f;
3704 s->padconf[0x2f] = 0x0f1f1f1f;
3705 s->padconf[0x30] = 0x0f0f0f0f;
3706 s->padconf[0x31] = 0x0f1f0f1f;
3707 s->padconf[0x32] = 0x0f0f0f0f;
3708 s->padconf[0x33] = 0x0f1f0f1f;
3709 s->padconf[0x34] = 0x1f1f0f0f;
3710 s->padconf[0x35] = 0x0f0f1f1f;
3711 s->padconf[0x36] = 0x0f0f1f0f;
3712 s->padconf[0x37] = 0x0f0f0f0f;
3713 s->padconf[0x38] = 0x1f18180f;
3714 s->padconf[0x39] = 0x1f1f1f1f;
3715 s->padconf[0x3a] = 0x00001f1f;
3716 s->padconf[0x3b] = 0x00000000;
3717 s->padconf[0x3c] = 0x00000000;
3718 s->padconf[0x3d] = 0x0f0f0f0f;
3719 s->padconf[0x3e] = 0x18000f0f;
3720 s->padconf[0x3f] = 0x00070000;
3721 s->padconf[0x40] = 0x00000707;
3722 s->padconf[0x41] = 0x0f1f0700;
3723 s->padconf[0x42] = 0x1f1f070f;
3724 s->padconf[0x43] = 0x0008081f;
3725 s->padconf[0x44] = 0x00000800;
3726}
3727
3728struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
3729 omap_clk iclk, struct omap_mpu_state_s *mpu)
3730{
3731 int iomemtype;
3732 struct omap_sysctl_s *s = (struct omap_sysctl_s *)
3733 qemu_mallocz(sizeof(struct omap_sysctl_s));
3734
3735 s->mpu = mpu;
3736 omap_sysctl_reset(s);
3737
c66fb5bc 3738 iomemtype = l4_register_io_memory(0, omap_sysctl_readfn,
827df9f3
AZ		 3739 omap_sysctl_writefn, s);
3740 s->base = omap_l4_attach(ta, 0, iomemtype);
3741 omap_l4_attach(ta, 0, iomemtype);
3742
3743 return s;
3744}
3745
3746/* SDRAM Controller Subsystem */
3747struct omap_sdrc_s {
3748 target_phys_addr_t base;
3749
3750 uint8_t config;
3751};
3752
3753static void omap_sdrc_reset(struct omap_sdrc_s *s)
3754{
3755 s->config = 0x10;
3756}
3757
3758static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
3759{
3760 struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
3761 int offset = addr - s->base;
3762
3763 switch (offset) {
3764 case 0x00: /* SDRC_REVISION */
3765 return 0x20;
3766
3767 case 0x10: /* SDRC_SYSCONFIG */
3768 return s->config;
3769
3770 case 0x14: /* SDRC_SYSSTATUS */
3771 return 1; /* RESETDONE */
3772
3773 case 0x40: /* SDRC_CS_CFG */
3774 case 0x44: /* SDRC_SHARING */
3775 case 0x48: /* SDRC_ERR_ADDR */
3776 case 0x4c: /* SDRC_ERR_TYPE */
3777 case 0x60: /* SDRC_DLLA_SCTRL */
3778 case 0x64: /* SDRC_DLLA_STATUS */
3779 case 0x68: /* SDRC_DLLB_CTRL */
3780 case 0x6c: /* SDRC_DLLB_STATUS */
3781 case 0x70: /* SDRC_POWER */
3782 case 0x80: /* SDRC_MCFG_0 */
3783 case 0x84: /* SDRC_MR_0 */
3784 case 0x88: /* SDRC_EMR1_0 */
3785 case 0x8c: /* SDRC_EMR2_0 */
3786 case 0x90: /* SDRC_EMR3_0 */
3787 case 0x94: /* SDRC_DCDL1_CTRL */
3788 case 0x98: /* SDRC_DCDL2_CTRL */
3789 case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
3790 case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
3791 case 0xa4: /* SDRC_RFR_CTRL_0 */
3792 case 0xa8: /* SDRC_MANUAL_0 */
3793 case 0xb0: /* SDRC_MCFG_1 */
3794 case 0xb4: /* SDRC_MR_1 */
3795 case 0xb8: /* SDRC_EMR1_1 */
3796 case 0xbc: /* SDRC_EMR2_1 */
3797 case 0xc0: /* SDRC_EMR3_1 */
3798 case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
3799 case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
3800 case 0xd4: /* SDRC_RFR_CTRL_1 */
3801 case 0xd8: /* SDRC_MANUAL_1 */
3802 return 0x00;
3803 }
3804
3805 OMAP_BAD_REG(addr);
3806 return 0;
3807}
3808
3809static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
3810 uint32_t value)
3811{
3812 struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
3813 int offset = addr - s->base;
3814
3815 switch (offset) {
3816 case 0x00: /* SDRC_REVISION */
3817 case 0x14: /* SDRC_SYSSTATUS */
3818 case 0x48: /* SDRC_ERR_ADDR */
3819 case 0x64: /* SDRC_DLLA_STATUS */
3820 case 0x6c: /* SDRC_DLLB_STATUS */
3821 OMAP_RO_REG(addr);
3822 return;
3823
3824 case 0x10: /* SDRC_SYSCONFIG */
3825 if ((value >> 3) != 0x2)
3826 fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
3827 __FUNCTION__, value >> 3);
3828 if (value & 2)
3829 omap_sdrc_reset(s);
3830 s->config = value & 0x18;
3831 break;
3832
3833 case 0x40: /* SDRC_CS_CFG */
3834 case 0x44: /* SDRC_SHARING */
3835 case 0x4c: /* SDRC_ERR_TYPE */
3836 case 0x60: /* SDRC_DLLA_SCTRL */
3837 case 0x68: /* SDRC_DLLB_CTRL */
3838 case 0x70: /* SDRC_POWER */
3839 case 0x80: /* SDRC_MCFG_0 */
3840 case 0x84: /* SDRC_MR_0 */
3841 case 0x88: /* SDRC_EMR1_0 */
3842 case 0x8c: /* SDRC_EMR2_0 */
3843 case 0x90: /* SDRC_EMR3_0 */
3844 case 0x94: /* SDRC_DCDL1_CTRL */
3845 case 0x98: /* SDRC_DCDL2_CTRL */
3846 case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
3847 case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
3848 case 0xa4: /* SDRC_RFR_CTRL_0 */
3849 case 0xa8: /* SDRC_MANUAL_0 */
3850 case 0xb0: /* SDRC_MCFG_1 */
3851 case 0xb4: /* SDRC_MR_1 */
3852 case 0xb8: /* SDRC_EMR1_1 */
3853 case 0xbc: /* SDRC_EMR2_1 */
3854 case 0xc0: /* SDRC_EMR3_1 */
3855 case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
3856 case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
3857 case 0xd4: /* SDRC_RFR_CTRL_1 */
3858 case 0xd8: /* SDRC_MANUAL_1 */
3859 break;
3860
3861 default:
3862 OMAP_BAD_REG(addr);
3863 return;
3864 }
3865}
3866
3867static CPUReadMemoryFunc *omap_sdrc_readfn[] = {
3868 omap_badwidth_read32,
3869 omap_badwidth_read32,
3870 omap_sdrc_read,
3871};
3872
3873static CPUWriteMemoryFunc *omap_sdrc_writefn[] = {
3874 omap_badwidth_write32,
3875 omap_badwidth_write32,
3876 omap_sdrc_write,
3877};
3878
3879struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
3880{
3881 int iomemtype;
3882 struct omap_sdrc_s *s = (struct omap_sdrc_s *)
3883 qemu_mallocz(sizeof(struct omap_sdrc_s));
3884
3885 s->base = base;
3886 omap_sdrc_reset(s);
3887
3888 iomemtype = cpu_register_io_memory(0, omap_sdrc_readfn,
3889 omap_sdrc_writefn, s);
3890 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
3891
3892 return s;
3893}
3894
3895/* General-Purpose Memory Controller */
3896struct omap_gpmc_s {
3897 target_phys_addr_t base;
3898 qemu_irq irq;
3899
3900 uint8_t sysconfig;
3901 uint16_t irqst;
3902 uint16_t irqen;
3903 uint16_t timeout;
3904 uint16_t config;
3905 uint32_t prefconfig[2];
3906 int prefcontrol;
3907 int preffifo;
3908 int prefcount;
3909 struct omap_gpmc_cs_file_s {
3910 uint32_t config[7];
3911 target_phys_addr_t base;
3912 size_t size;
3913 int iomemtype;
3914 void (*base_update)(void *opaque, target_phys_addr_t new);
3915 void (*unmap)(void *opaque);
3916 void *opaque;
3917 } cs_file[8];
3918 int ecc_cs;
3919 int ecc_ptr;
3920 uint32_t ecc_cfg;
3921 struct ecc_state_s ecc[9];
3922};
3923
3924static void omap_gpmc_int_update(struct omap_gpmc_s *s)
3925{
3926 qemu_set_irq(s->irq, s->irqen & s->irqst);
3927}
3928
3929static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
3930{
3931 /* TODO: check for overlapping regions and report access errors */
3932 if ((mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf) ||
3933 (base < 0 || base >= 0x40) ||
3934 (base & 0x0f & ~mask)) {
3935 fprintf(stderr, "%s: wrong cs address mapping/decoding!\n",
3936 __FUNCTION__);
3937 return;
3938 }
3939
3940 if (!f->opaque)
3941 return;
3942
3943 f->base = base << 24;
3944 f->size = (0x0fffffff & ~(mask << 24)) + 1;
3945 /* TODO: rather than setting the size of the mapping (which should be
3946 * constant), the mask should cause wrapping of the address space, so
3947 * that the same memory becomes accessible at every <i>size</i> bytes
3948 * starting from <i>base</i>. */
3949 if (f->iomemtype)
3950 cpu_register_physical_memory(f->base, f->size, f->iomemtype);
3951
3952 if (f->base_update)
3953 f->base_update(f->opaque, f->base);
3954}
3955
3956static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
3957{
3958 if (f->size) {
3959 if (f->unmap)
3960 f->unmap(f->opaque);
3961 if (f->iomemtype)
3962 cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
3963 f->base = 0;
3964 f->size = 0;
3965 }
3966}
3967
3968static void omap_gpmc_reset(struct omap_gpmc_s *s)
3969{
3970 int i;
3971
3972 s->sysconfig = 0;
3973 s->irqst = 0;
3974 s->irqen = 0;
3975 omap_gpmc_int_update(s);
3976 s->timeout = 0;
3977 s->config = 0xa00;
3978 s->prefconfig[0] = 0x00004000;
3979 s->prefconfig[1] = 0x00000000;
3980 s->prefcontrol = 0;
3981 s->preffifo = 0;
3982 s->prefcount = 0;
3983 for (i = 0; i < 8; i ++) {
3984 if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
3985 omap_gpmc_cs_unmap(s->cs_file + i);
3986 s->cs_file[i].config[0] = i ? 1 << 12 : 0;
3987 s->cs_file[i].config[1] = 0x101001;
3988 s->cs_file[i].config[2] = 0x020201;
3989 s->cs_file[i].config[3] = 0x10031003;
3990 s->cs_file[i].config[4] = 0x10f1111;
3991 s->cs_file[i].config[5] = 0;
3992 s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
3993 if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
3994 omap_gpmc_cs_map(&s->cs_file[i],
3995 s->cs_file[i].config[6] & 0x1f, /* MASKADDR */
3996 (s->cs_file[i].config[6] >> 8 & 0xf)); /* BASEADDR */
3997 }
3998 omap_gpmc_cs_map(s->cs_file, 0, 0xf);
3999 s->ecc_cs = 0;
4000 s->ecc_ptr = 0;
4001 s->ecc_cfg = 0x3fcff000;
4002 for (i = 0; i < 9; i ++)
4003 ecc_reset(&s->ecc[i]);
4004}
4005
4006static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
4007{
4008 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
4009 int offset = addr - s->base;
4010 int cs;
4011 struct omap_gpmc_cs_file_s *f;
4012
4013 switch (offset) {
4014 case 0x000: /* GPMC_REVISION */
4015 return 0x20;
4016
4017 case 0x010: /* GPMC_SYSCONFIG */
4018 return s->sysconfig;
4019
4020 case 0x014: /* GPMC_SYSSTATUS */
4021 return 1; /* RESETDONE */
4022
4023 case 0x018: /* GPMC_IRQSTATUS */
4024 return s->irqst;
4025
4026 case 0x01c: /* GPMC_IRQENABLE */
4027 return s->irqen;
4028
4029 case 0x040: /* GPMC_TIMEOUT_CONTROL */
4030 return s->timeout;
4031
4032 case 0x044: /* GPMC_ERR_ADDRESS */
4033 case 0x048: /* GPMC_ERR_TYPE */
4034 return 0;
4035
4036 case 0x050: /* GPMC_CONFIG */
4037 return s->config;
4038
4039 case 0x054: /* GPMC_STATUS */
4040 return 0x001;
4041
4042 case 0x060 ... 0x1d4:
4043 cs = (offset - 0x060) / 0x30;
4044 offset -= cs * 0x30;
4045 f = s->cs_file + cs;
4046 switch (offset - cs * 0x30) {
4047 case 0x60: /* GPMC_CONFIG1 */
4048 return f->config[0];
4049 case 0x64: /* GPMC_CONFIG2 */
4050 return f->config[1];
4051 case 0x68: /* GPMC_CONFIG3 */
4052 return f->config[2];
4053 case 0x6c: /* GPMC_CONFIG4 */
4054 return f->config[3];
4055 case 0x70: /* GPMC_CONFIG5 */
4056 return f->config[4];
4057 case 0x74: /* GPMC_CONFIG6 */
4058 return f->config[5];
4059 case 0x78: /* GPMC_CONFIG7 */
4060 return f->config[6];
4061 case 0x84: /* GPMC_NAND_DATA */
4062 return 0;
4063 }
4064 break;
4065
4066 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
4067 return s->prefconfig[0];
4068 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
4069 return s->prefconfig[1];
4070 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
4071 return s->prefcontrol;
4072 case 0x1f0: /* GPMC_PREFETCH_STATUS */
4073 return (s->preffifo << 24) |
4074 ((s->preffifo >
4075 ((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) |
4076 s->prefcount;
4077
4078 case 0x1f4: /* GPMC_ECC_CONFIG */
4079 return s->ecc_cs;
4080 case 0x1f8: /* GPMC_ECC_CONTROL */
4081 return s->ecc_ptr;
4082 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
4083 return s->ecc_cfg;
4084 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
4085 cs = (offset & 0x1f) >> 2;
4086 /* TODO: check correctness */
4087 return
4088 ((s->ecc[cs].cp & 0x07) << 0) |
4089 ((s->ecc[cs].cp & 0x38) << 13) |
4090 ((s->ecc[cs].lp[0] & 0x1ff) << 3) |
4091 ((s->ecc[cs].lp[1] & 0x1ff) << 19);
4092
4093 case 0x230: /* GPMC_TESTMODE_CTRL */
4094 return 0;
4095 case 0x234: /* GPMC_PSA_LSB */
4096 case 0x238: /* GPMC_PSA_MSB */
4097 return 0x00000000;
4098 }
4099
4100 OMAP_BAD_REG(addr);
4101 return 0;
4102}
4103
4104static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
4105 uint32_t value)
4106{
4107 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
4108 int offset = addr - s->base;
4109 int cs;
4110 struct omap_gpmc_cs_file_s *f;
4111
4112 switch (offset) {
4113 case 0x000: /* GPMC_REVISION */
4114 case 0x014: /* GPMC_SYSSTATUS */
4115 case 0x054: /* GPMC_STATUS */
4116 case 0x1f0: /* GPMC_PREFETCH_STATUS */
4117 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
4118 case 0x234: /* GPMC_PSA_LSB */
4119 case 0x238: /* GPMC_PSA_MSB */
4120 OMAP_RO_REG(addr);
4121 break;
4122
4123 case 0x010: /* GPMC_SYSCONFIG */
4124 if ((value >> 3) == 0x3)
4125 fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
4126 __FUNCTION__, value >> 3);
4127 if (value & 2)
4128 omap_gpmc_reset(s);
4129 s->sysconfig = value & 0x19;
4130 break;
4131
4132 case 0x018: /* GPMC_IRQSTATUS */
4133 s->irqen = ~value;
4134 omap_gpmc_int_update(s);
4135 break;
4136
4137 case 0x01c: /* GPMC_IRQENABLE */
4138 s->irqen = value & 0xf03;
4139 omap_gpmc_int_update(s);
4140 break;
4141
4142 case 0x040: /* GPMC_TIMEOUT_CONTROL */
4143 s->timeout = value & 0x1ff1;
4144 break;
4145
4146 case 0x044: /* GPMC_ERR_ADDRESS */
4147 case 0x048: /* GPMC_ERR_TYPE */
4148 break;
4149
4150 case 0x050: /* GPMC_CONFIG */
4151 s->config = value & 0xf13;
4152 break;
4153
4154 case 0x060 ... 0x1d4:
4155 cs = (offset - 0x060) / 0x30;
4156 offset -= cs * 0x30;
4157 f = s->cs_file + cs;
4158 switch (offset) {
4159 case 0x60: /* GPMC_CONFIG1 */
4160 f->config[0] = value & 0xffef3e13;
4161 break;
4162 case 0x64: /* GPMC_CONFIG2 */
4163 f->config[1] = value & 0x001f1f8f;
4164 break;
4165 case 0x68: /* GPMC_CONFIG3 */
4166 f->config[2] = value & 0x001f1f8f;
4167 break;
4168 case 0x6c: /* GPMC_CONFIG4 */
4169 f->config[3] = value & 0x1f8f1f8f;
4170 break;
4171 case 0x70: /* GPMC_CONFIG5 */
4172 f->config[4] = value & 0x0f1f1f1f;
4173 break;
4174 case 0x74: /* GPMC_CONFIG6 */
4175 f->config[5] = value & 0x00000fcf;
4176 break;
4177 case 0x78: /* GPMC_CONFIG7 */
4178 if ((f->config[6] ^ value) & 0xf7f) {
4179 if (f->config[6] & (1 << 6)) /* CSVALID */
4180 omap_gpmc_cs_unmap(f);
4181 if (value & (1 << 6)) /* CSVALID */
4182 omap_gpmc_cs_map(f, value & 0x1f, /* MASKADDR */
4183 (value >> 8 & 0xf)); /* BASEADDR */
4184 }
4185 f->config[6] = value & 0x00000f7f;
4186 break;
4187 case 0x7c: /* GPMC_NAND_COMMAND */
4188 case 0x80: /* GPMC_NAND_ADDRESS */
4189 case 0x84: /* GPMC_NAND_DATA */
4190 break;
4191
4192 default:
4193 goto bad_reg;
4194 }
4195 break;
4196
4197 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
4198 s->prefconfig[0] = value & 0x7f8f7fbf;
4199 /* TODO: update interrupts, fifos, dmas */
4200 break;
4201
4202 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
4203 s->prefconfig[1] = value & 0x3fff;
4204 break;
4205
4206 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
4207 s->prefcontrol = value & 1;
4208 if (s->prefcontrol) {
4209 if (s->prefconfig[0] & 1)
4210 s->preffifo = 0x40;
4211 else
4212 s->preffifo = 0x00;
4213 }
4214 /* TODO: start */
4215 break;
4216
4217 case 0x1f4: /* GPMC_ECC_CONFIG */
4218 s->ecc_cs = 0x8f;
4219 break;
4220 case 0x1f8: /* GPMC_ECC_CONTROL */
4221 if (value & (1 << 8))
4222 for (cs = 0; cs < 9; cs ++)
4223 ecc_reset(&s->ecc[cs]);
4224 s->ecc_ptr = value & 0xf;
4225 if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
4226 s->ecc_ptr = 0;
4227 s->ecc_cs &= ~1;
4228 }
4229 break;
4230 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
4231 s->ecc_cfg = value & 0x3fcff1ff;
4232 break;
4233 case 0x230: /* GPMC_TESTMODE_CTRL */
4234 if (value & 7)
4235 fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
4236 break;
4237
4238 default:
4239 bad_reg:
4240 OMAP_BAD_REG(addr);
4241 return;
4242 }
4243}
4244
4245static CPUReadMemoryFunc *omap_gpmc_readfn[] = {
4246 omap_badwidth_read32, /* TODO */
4247 omap_badwidth_read32, /* TODO */
4248 omap_gpmc_read,
4249};
4250
4251static CPUWriteMemoryFunc *omap_gpmc_writefn[] = {
4252 omap_badwidth_write32, /* TODO */
4253 omap_badwidth_write32, /* TODO */
4254 omap_gpmc_write,
4255};
4256
4257struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
4258{
4259 int iomemtype;
4260 struct omap_gpmc_s *s = (struct omap_gpmc_s *)
4261 qemu_mallocz(sizeof(struct omap_gpmc_s));
4262
4263 s->base = base;
4264 omap_gpmc_reset(s);
4265
4266 iomemtype = cpu_register_io_memory(0, omap_gpmc_readfn,
4267 omap_gpmc_writefn, s);
4268 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
4269
4270 return s;
4271}
4272
4273void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
4274 void (*base_upd)(void *opaque, target_phys_addr_t new),
4275 void (*unmap)(void *opaque), void *opaque)
4276{
4277 struct omap_gpmc_cs_file_s *f;
4278
4279 if (cs < 0 || cs >= 8) {
4280 fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
4281 exit(-1);
4282 }
4283 f = &s->cs_file[cs];
4284
4285 f->iomemtype = iomemtype;
4286 f->base_update = base_upd;
4287 f->unmap = unmap;
4288 f->opaque = opaque;
4289
4290 if (f->config[6] & (1 << 6)) /* CSVALID */
4291 omap_gpmc_cs_map(f, f->config[6] & 0x1f, /* MASKADDR */
4292 (f->config[6] >> 8 & 0xf)); /* BASEADDR */
4293}
4294
4295/* General chip reset */
4296static void omap2_mpu_reset(void *opaque)
4297{
4298 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4299
4300 omap_inth_reset(mpu->ih[0]);
4301 omap_dma_reset(mpu->dma);
4302 omap_prcm_reset(mpu->prcm);
4303 omap_sysctl_reset(mpu->sysc);
4304 omap_gp_timer_reset(mpu->gptimer[0]);
4305 omap_gp_timer_reset(mpu->gptimer[1]);
4306 omap_gp_timer_reset(mpu->gptimer[2]);
4307 omap_gp_timer_reset(mpu->gptimer[3]);
4308 omap_gp_timer_reset(mpu->gptimer[4]);
4309 omap_gp_timer_reset(mpu->gptimer[5]);
4310 omap_gp_timer_reset(mpu->gptimer[6]);
4311 omap_gp_timer_reset(mpu->gptimer[7]);
4312 omap_gp_timer_reset(mpu->gptimer[8]);
4313 omap_gp_timer_reset(mpu->gptimer[9]);
4314 omap_gp_timer_reset(mpu->gptimer[10]);
4315 omap_gp_timer_reset(mpu->gptimer[11]);
4316 omap_synctimer_reset(&mpu->synctimer);
4317 omap_sdrc_reset(mpu->sdrc);
4318 omap_gpmc_reset(mpu->gpmc);
4319 omap_dss_reset(mpu->dss);
4320 omap_uart_reset(mpu->uart[0]);
4321 omap_uart_reset(mpu->uart[1]);
4322 omap_uart_reset(mpu->uart[2]);
4323 omap_mmc_reset(mpu->mmc);
4324 omap_gpif_reset(mpu->gpif);
4325 omap_mcspi_reset(mpu->mcspi[0]);
4326 omap_mcspi_reset(mpu->mcspi[1]);
4327 omap_i2c_reset(mpu->i2c[0]);
4328 omap_i2c_reset(mpu->i2c[1]);
4329 cpu_reset(mpu->env);
4330}
4331
4332static int omap2_validate_addr(struct omap_mpu_state_s *s,
4333 target_phys_addr_t addr)
4334{
4335 return 1;
4336}
4337
4338static const struct dma_irq_map omap2_dma_irq_map[] = {
4339 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
4340 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
4341 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
4342 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
4343};
4344
4345struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
4346 DisplayState *ds, const char *core)
4347{
4348 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4349 qemu_mallocz(sizeof(struct omap_mpu_state_s));
7e7c5e4c 4350 ram_addr_t sram_base, q2_base;
827df9f3
AZ		 4351 qemu_irq *cpu_irq;
4352 qemu_irq dma_irqs[4];
4353 omap_clk gpio_clks[4];
4354 int sdindex;
4355 int i;
4356
4357 /* Core */
4358 s->mpu_model = omap2420;
4359 s->env = cpu_init(core ?: "arm1136-r2");
4360 if (!s->env) {
4361 fprintf(stderr, "Unable to find CPU definition\n");
4362 exit(1);
4363 }
4364 s->sdram_size = sdram_size;
4365 s->sram_size = OMAP242X_SRAM_SIZE;
4366
4367 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
4368
4369 /* Clocks */
4370 omap_clk_init(s);
4371
4372 /* Memory-mapped stuff */
4373 cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
7e7c5e4c 4374 (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
827df9f3
AZ		 4375 cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
4376 (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
4377
4378 s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
4379
4380 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
4381 cpu_irq = arm_pic_init_cpu(s->env);
4382 s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
4383 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
4384 omap_findclk(s, "mpu_intc_fclk"),
4385 omap_findclk(s, "mpu_intc_iclk"));
4386
4387 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
4388 s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
4389
4390 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
4391 omap_findclk(s, "omapctrl_iclk"), s);
4392
4393 for (i = 0; i < 4; i ++)
4394 dma_irqs[i] =
4395 s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
4396 s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
4397 omap_findclk(s, "sdma_iclk"),
4398 omap_findclk(s, "sdma_fclk"));
4399 s->port->addr_valid = omap2_validate_addr;
4400
4401 s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
4402 s->irq[0][OMAP_INT_24XX_UART1_IRQ],
4403 omap_findclk(s, "uart1_fclk"),
4404 omap_findclk(s, "uart1_iclk"),
4405 s->drq[OMAP24XX_DMA_UART1_TX],
4406 s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]);
4407 s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
4408 s->irq[0][OMAP_INT_24XX_UART2_IRQ],
4409 omap_findclk(s, "uart2_fclk"),
4410 omap_findclk(s, "uart2_iclk"),
4411 s->drq[OMAP24XX_DMA_UART2_TX],
4412 s->drq[OMAP24XX_DMA_UART2_RX],
4413 serial_hds[0] ? serial_hds[1] : 0);
4414 s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
4415 s->irq[0][OMAP_INT_24XX_UART3_IRQ],
4416 omap_findclk(s, "uart3_fclk"),
4417 omap_findclk(s, "uart3_iclk"),
4418 s->drq[OMAP24XX_DMA_UART3_TX],
4419 s->drq[OMAP24XX_DMA_UART3_RX],
4420 serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
4421
4422 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
4423 s->irq[0][OMAP_INT_24XX_GPTIMER1],
4424 omap_findclk(s, "wu_gpt1_clk"),
4425 omap_findclk(s, "wu_l4_iclk"));
4426 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
4427 s->irq[0][OMAP_INT_24XX_GPTIMER2],
4428 omap_findclk(s, "core_gpt2_clk"),
4429 omap_findclk(s, "core_l4_iclk"));
4430 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
4431 s->irq[0][OMAP_INT_24XX_GPTIMER3],
4432 omap_findclk(s, "core_gpt3_clk"),
4433 omap_findclk(s, "core_l4_iclk"));
4434 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
4435 s->irq[0][OMAP_INT_24XX_GPTIMER4],
4436 omap_findclk(s, "core_gpt4_clk"),
4437 omap_findclk(s, "core_l4_iclk"));
4438 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
4439 s->irq[0][OMAP_INT_24XX_GPTIMER5],
4440 omap_findclk(s, "core_gpt5_clk"),
4441 omap_findclk(s, "core_l4_iclk"));
4442 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
4443 s->irq[0][OMAP_INT_24XX_GPTIMER6],
4444 omap_findclk(s, "core_gpt6_clk"),
4445 omap_findclk(s, "core_l4_iclk"));
4446 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
4447 s->irq[0][OMAP_INT_24XX_GPTIMER7],
4448 omap_findclk(s, "core_gpt7_clk"),
4449 omap_findclk(s, "core_l4_iclk"));
4450 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
4451 s->irq[0][OMAP_INT_24XX_GPTIMER8],
4452 omap_findclk(s, "core_gpt8_clk"),
4453 omap_findclk(s, "core_l4_iclk"));
4454 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
4455 s->irq[0][OMAP_INT_24XX_GPTIMER9],
4456 omap_findclk(s, "core_gpt9_clk"),
4457 omap_findclk(s, "core_l4_iclk"));
4458 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
4459 s->irq[0][OMAP_INT_24XX_GPTIMER10],
4460 omap_findclk(s, "core_gpt10_clk"),
4461 omap_findclk(s, "core_l4_iclk"));
4462 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
4463 s->irq[0][OMAP_INT_24XX_GPTIMER11],
4464 omap_findclk(s, "core_gpt11_clk"),
4465 omap_findclk(s, "core_l4_iclk"));
4466 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
4467 s->irq[0][OMAP_INT_24XX_GPTIMER12],
4468 omap_findclk(s, "core_gpt12_clk"),
4469 omap_findclk(s, "core_l4_iclk"));
4470
4471 omap_tap_init(omap_l4ta(s->l4, 2), s);
4472
4473 omap_synctimer_init(omap_l4tao(s->l4, 2), s,
4474 omap_findclk(s, "clk32-kHz"),
4475 omap_findclk(s, "core_l4_iclk"));
4476
4477 s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
4478 s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
4479 &s->drq[OMAP24XX_DMA_I2C1_TX],
4480 omap_findclk(s, "i2c1.fclk"),
4481 omap_findclk(s, "i2c1.iclk"));
4482 s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
4483 s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
4484 &s->drq[OMAP24XX_DMA_I2C2_TX],
4485 omap_findclk(s, "i2c2.fclk"),
4486 omap_findclk(s, "i2c2.iclk"));
4487
4488 gpio_clks[0] = omap_findclk(s, "gpio1_dbclk");
4489 gpio_clks[1] = omap_findclk(s, "gpio2_dbclk");
4490 gpio_clks[2] = omap_findclk(s, "gpio3_dbclk");
4491 gpio_clks[3] = omap_findclk(s, "gpio4_dbclk");
4492 s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3),
4493 &s->irq[0][OMAP_INT_24XX_GPIO_BANK1],
4494 gpio_clks, omap_findclk(s, "gpio_iclk"), 4);
4495
4496 s->sdrc = omap_sdrc_init(0x68009000);
4497 s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]);
4498
4499 sdindex = drive_get_index(IF_SD, 0, 0);
4500 if (sdindex == -1) {
4501 fprintf(stderr, "qemu: missing SecureDigital device\n");
4502 exit(1);
4503 }
4504 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), drives_table[sdindex].bdrv,
4505 s->irq[0][OMAP_INT_24XX_MMC_IRQ],
4506 &s->drq[OMAP24XX_DMA_MMC1_TX],
4507 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
4508
4509 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
99570a40 4510 s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
827df9f3
AZ		 4511 &s->drq[OMAP24XX_DMA_SPI1_TX0],
4512 omap_findclk(s, "spi1_fclk"),
4513 omap_findclk(s, "spi1_iclk"));
4514 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
99570a40 4515 s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
827df9f3
AZ		 4516 &s->drq[OMAP24XX_DMA_SPI2_TX0],
4517 omap_findclk(s, "spi2_fclk"),
4518 omap_findclk(s, "spi2_iclk"));
4519
4520 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800, ds,
4521 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
4522 s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
4523 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
4524 omap_findclk(s, "dss_54m_clk"),
4525 omap_findclk(s, "dss_l3_iclk"),
4526 omap_findclk(s, "dss_l4_iclk"));
4527
54585ffe
AZ		 4528 omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
4529 s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
4530 serial_hds[0] && serial_hds[1] && serial_hds[2] ?
4531 serial_hds[3] : 0);
4532
99570a40
AZ		 4533 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
4534 s->irq[0][OMAP_INT_24XX_EAC_IRQ],
4535 /* Ten consecutive lines */
4536 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
4537 omap_findclk(s, "func_96m_clk"),
4538 omap_findclk(s, "core_l4_iclk"));
4539
827df9f3
AZ		 4540 /* All register mappings (includin those not currenlty implemented):
4541 * SystemControlMod 48000000 - 48000fff
4542 * SystemControlL4 48001000 - 48001fff
4543 * 32kHz Timer Mod 48004000 - 48004fff
4544 * 32kHz Timer L4 48005000 - 48005fff
4545 * PRCM ModA 48008000 - 480087ff
4546 * PRCM ModB 48008800 - 48008fff
4547 * PRCM L4 48009000 - 48009fff
4548 * TEST-BCM Mod 48012000 - 48012fff
4549 * TEST-BCM L4 48013000 - 48013fff
4550 * TEST-TAP Mod 48014000 - 48014fff
4551 * TEST-TAP L4 48015000 - 48015fff
4552 * GPIO1 Mod 48018000 - 48018fff
4553 * GPIO Top 48019000 - 48019fff
4554 * GPIO2 Mod 4801a000 - 4801afff
4555 * GPIO L4 4801b000 - 4801bfff
4556 * GPIO3 Mod 4801c000 - 4801cfff
4557 * GPIO4 Mod 4801e000 - 4801efff
4558 * WDTIMER1 Mod 48020000 - 48010fff
4559 * WDTIMER Top 48021000 - 48011fff
4560 * WDTIMER2 Mod 48022000 - 48012fff
4561 * WDTIMER L4 48023000 - 48013fff
4562 * WDTIMER3 Mod 48024000 - 48014fff
4563 * WDTIMER3 L4 48025000 - 48015fff
4564 * WDTIMER4 Mod 48026000 - 48016fff
4565 * WDTIMER4 L4 48027000 - 48017fff
4566 * GPTIMER1 Mod 48028000 - 48018fff
4567 * GPTIMER1 L4 48029000 - 48019fff
4568 * GPTIMER2 Mod 4802a000 - 4801afff
4569 * GPTIMER2 L4 4802b000 - 4801bfff
4570 * L4-Config AP 48040000 - 480407ff
4571 * L4-Config IP 48040800 - 48040fff
4572 * L4-Config LA 48041000 - 48041fff
4573 * ARM11ETB Mod 48048000 - 48049fff
4574 * ARM11ETB L4 4804a000 - 4804afff
4575 * DISPLAY Top 48050000 - 480503ff
4576 * DISPLAY DISPC 48050400 - 480507ff
4577 * DISPLAY RFBI 48050800 - 48050bff
4578 * DISPLAY VENC 48050c00 - 48050fff
4579 * DISPLAY L4 48051000 - 48051fff
4580 * CAMERA Top 48052000 - 480523ff
4581 * CAMERA core 48052400 - 480527ff
4582 * CAMERA DMA 48052800 - 48052bff
4583 * CAMERA MMU 48052c00 - 48052fff
4584 * CAMERA L4 48053000 - 48053fff
4585 * SDMA Mod 48056000 - 48056fff
4586 * SDMA L4 48057000 - 48057fff
4587 * SSI Top 48058000 - 48058fff
4588 * SSI GDD 48059000 - 48059fff
4589 * SSI Port1 4805a000 - 4805afff
4590 * SSI Port2 4805b000 - 4805bfff
4591 * SSI L4 4805c000 - 4805cfff
4592 * USB Mod 4805e000 - 480fefff
4593 * USB L4 4805f000 - 480fffff
4594 * WIN_TRACER1 Mod 48060000 - 48060fff
4595 * WIN_TRACER1 L4 48061000 - 48061fff
4596 * WIN_TRACER2 Mod 48062000 - 48062fff
4597 * WIN_TRACER2 L4 48063000 - 48063fff
4598 * WIN_TRACER3 Mod 48064000 - 48064fff
4599 * WIN_TRACER3 L4 48065000 - 48065fff
4600 * WIN_TRACER4 Top 48066000 - 480660ff
4601 * WIN_TRACER4 ETT 48066100 - 480661ff
4602 * WIN_TRACER4 WT 48066200 - 480662ff
4603 * WIN_TRACER4 L4 48067000 - 48067fff
4604 * XTI Mod 48068000 - 48068fff
4605 * XTI L4 48069000 - 48069fff
4606 * UART1 Mod 4806a000 - 4806afff
4607 * UART1 L4 4806b000 - 4806bfff
4608 * UART2 Mod 4806c000 - 4806cfff
4609 * UART2 L4 4806d000 - 4806dfff
4610 * UART3 Mod 4806e000 - 4806efff
4611 * UART3 L4 4806f000 - 4806ffff
4612 * I2C1 Mod 48070000 - 48070fff
4613 * I2C1 L4 48071000 - 48071fff
4614 * I2C2 Mod 48072000 - 48072fff
4615 * I2C2 L4 48073000 - 48073fff
4616 * McBSP1 Mod 48074000 - 48074fff
4617 * McBSP1 L4 48075000 - 48075fff
4618 * McBSP2 Mod 48076000 - 48076fff
4619 * McBSP2 L4 48077000 - 48077fff
4620 * GPTIMER3 Mod 48078000 - 48078fff
4621 * GPTIMER3 L4 48079000 - 48079fff
4622 * GPTIMER4 Mod 4807a000 - 4807afff
4623 * GPTIMER4 L4 4807b000 - 4807bfff
4624 * GPTIMER5 Mod 4807c000 - 4807cfff
4625 * GPTIMER5 L4 4807d000 - 4807dfff
4626 * GPTIMER6 Mod 4807e000 - 4807efff
4627 * GPTIMER6 L4 4807f000 - 4807ffff
4628 * GPTIMER7 Mod 48080000 - 48080fff
4629 * GPTIMER7 L4 48081000 - 48081fff
4630 * GPTIMER8 Mod 48082000 - 48082fff
4631 * GPTIMER8 L4 48083000 - 48083fff
4632 * GPTIMER9 Mod 48084000 - 48084fff
4633 * GPTIMER9 L4 48085000 - 48085fff
4634 * GPTIMER10 Mod 48086000 - 48086fff
4635 * GPTIMER10 L4 48087000 - 48087fff
4636 * GPTIMER11 Mod 48088000 - 48088fff
4637 * GPTIMER11 L4 48089000 - 48089fff
4638 * GPTIMER12 Mod 4808a000 - 4808afff
4639 * GPTIMER12 L4 4808b000 - 4808bfff
4640 * EAC Mod 48090000 - 48090fff
4641 * EAC L4 48091000 - 48091fff
4642 * FAC Mod 48092000 - 48092fff
4643 * FAC L4 48093000 - 48093fff
4644 * MAILBOX Mod 48094000 - 48094fff
4645 * MAILBOX L4 48095000 - 48095fff
4646 * SPI1 Mod 48098000 - 48098fff
4647 * SPI1 L4 48099000 - 48099fff
4648 * SPI2 Mod 4809a000 - 4809afff
4649 * SPI2 L4 4809b000 - 4809bfff
4650 * MMC/SDIO Mod 4809c000 - 4809cfff
4651 * MMC/SDIO L4 4809d000 - 4809dfff
4652 * MS_PRO Mod 4809e000 - 4809efff
4653 * MS_PRO L4 4809f000 - 4809ffff
4654 * RNG Mod 480a0000 - 480a0fff
4655 * RNG L4 480a1000 - 480a1fff
4656 * DES3DES Mod 480a2000 - 480a2fff
4657 * DES3DES L4 480a3000 - 480a3fff
4658 * SHA1MD5 Mod 480a4000 - 480a4fff
4659 * SHA1MD5 L4 480a5000 - 480a5fff
4660 * AES Mod 480a6000 - 480a6fff
4661 * AES L4 480a7000 - 480a7fff
4662 * PKA Mod 480a8000 - 480a9fff
4663 * PKA L4 480aa000 - 480aafff
4664 * MG Mod 480b0000 - 480b0fff
4665 * MG L4 480b1000 - 480b1fff
4666 * HDQ/1-wire Mod 480b2000 - 480b2fff
4667 * HDQ/1-wire L4 480b3000 - 480b3fff
4668 * MPU interrupt 480fe000 - 480fefff
54585ffe 4669 * STI channel base 54000000 - 5400ffff
827df9f3
AZ		 4670 * IVA RAM 5c000000 - 5c01ffff
4671 * IVA ROM 5c020000 - 5c027fff
4672 * IMG_BUF_A 5c040000 - 5c040fff
4673 * IMG_BUF_B 5c042000 - 5c042fff
4674 * VLCDS 5c048000 - 5c0487ff
4675 * IMX_COEF 5c049000 - 5c04afff
4676 * IMX_CMD 5c051000 - 5c051fff
4677 * VLCDQ 5c053000 - 5c0533ff
4678 * VLCDH 5c054000 - 5c054fff
4679 * SEQ_CMD 5c055000 - 5c055fff
4680 * IMX_REG 5c056000 - 5c0560ff
4681 * VLCD_REG 5c056100 - 5c0561ff
4682 * SEQ_REG 5c056200 - 5c0562ff
4683 * IMG_BUF_REG 5c056300 - 5c0563ff
4684 * SEQIRQ_REG 5c056400 - 5c0564ff
4685 * OCP_REG 5c060000 - 5c060fff
4686 * SYSC_REG 5c070000 - 5c070fff
4687 * MMU_REG 5d000000 - 5d000fff
4688 * sDMA R 68000400 - 680005ff
4689 * sDMA W 68000600 - 680007ff
4690 * Display Control 68000800 - 680009ff
4691 * DSP subsystem 68000a00 - 68000bff
4692 * MPU subsystem 68000c00 - 68000dff
4693 * IVA subsystem 68001000 - 680011ff
4694 * USB 68001200 - 680013ff
4695 * Camera 68001400 - 680015ff
4696 * VLYNQ (firewall) 68001800 - 68001bff
4697 * VLYNQ 68001e00 - 68001fff
4698 * SSI 68002000 - 680021ff
4699 * L4 68002400 - 680025ff
4700 * DSP (firewall) 68002800 - 68002bff
4701 * DSP subsystem 68002e00 - 68002fff
4702 * IVA (firewall) 68003000 - 680033ff
4703 * IVA 68003600 - 680037ff
4704 * GFX 68003a00 - 68003bff
4705 * CMDWR emulation 68003c00 - 68003dff
4706 * SMS 68004000 - 680041ff
4707 * OCM 68004200 - 680043ff
4708 * GPMC 68004400 - 680045ff
4709 * RAM (firewall) 68005000 - 680053ff
4710 * RAM (err login) 68005400 - 680057ff
4711 * ROM (firewall) 68005800 - 68005bff
4712 * ROM (err login) 68005c00 - 68005fff
4713 * GPMC (firewall) 68006000 - 680063ff
4714 * GPMC (err login) 68006400 - 680067ff
4715 * SMS (err login) 68006c00 - 68006fff
4716 * SMS registers 68008000 - 68008fff
4717 * SDRC registers 68009000 - 68009fff
4718 * GPMC registers 6800a000 6800afff
4719 */
4720
4721 qemu_register_reset(omap2_mpu_reset, s);
4722
4723 return s;
4724}
Qemu copy for testing