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b4e3104b AZ |
1 | /* |
2 | * TI OMAP DMA gigacell. | |
3 | * | |
4 | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> | |
5 | * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | #include "qemu-common.h" | |
23 | #include "qemu-timer.h" | |
24 | #include "omap.h" | |
25 | #include "irq.h" | |
afbb5194 | 26 | #include "soc_dma.h" |
b4e3104b AZ |
27 | |
28 | struct omap_dma_channel_s { | |
29 | /* transfer data */ | |
30 | int burst[2]; | |
31 | int pack[2]; | |
827df9f3 AZ |
32 | int endian[2]; |
33 | int endian_lock[2]; | |
34 | int translate[2]; | |
b4e3104b AZ |
35 | enum omap_dma_port port[2]; |
36 | target_phys_addr_t addr[2]; | |
37 | omap_dma_addressing_t mode[2]; | |
827df9f3 | 38 | uint32_t elements; |
b4e3104b | 39 | uint16_t frames; |
827df9f3 | 40 | int32_t frame_index[2]; |
b4e3104b AZ |
41 | int16_t element_index[2]; |
42 | int data_type; | |
43 | ||
44 | /* transfer type */ | |
45 | int transparent_copy; | |
46 | int constant_fill; | |
47 | uint32_t color; | |
827df9f3 | 48 | int prefetch; |
b4e3104b AZ |
49 | |
50 | /* auto init and linked channel data */ | |
51 | int end_prog; | |
52 | int repeat; | |
53 | int auto_init; | |
54 | int link_enabled; | |
55 | int link_next_ch; | |
56 | ||
57 | /* interruption data */ | |
58 | int interrupts; | |
59 | int status; | |
827df9f3 | 60 | int cstatus; |
b4e3104b AZ |
61 | |
62 | /* state data */ | |
63 | int active; | |
64 | int enable; | |
65 | int sync; | |
827df9f3 | 66 | int src_sync; |
b4e3104b AZ |
67 | int pending_request; |
68 | int waiting_end_prog; | |
69 | uint16_t cpc; | |
afbb5194 | 70 | int set_update; |
b4e3104b AZ |
71 | |
72 | /* sync type */ | |
73 | int fs; | |
74 | int bs; | |
75 | ||
76 | /* compatibility */ | |
77 | int omap_3_1_compatible_disable; | |
78 | ||
79 | qemu_irq irq; | |
80 | struct omap_dma_channel_s *sibling; | |
81 | ||
82 | struct omap_dma_reg_set_s { | |
83 | target_phys_addr_t src, dest; | |
84 | int frame; | |
85 | int element; | |
827df9f3 | 86 | int pck_element; |
b4e3104b AZ |
87 | int frame_delta[2]; |
88 | int elem_delta[2]; | |
89 | int frames; | |
90 | int elements; | |
827df9f3 | 91 | int pck_elements; |
b4e3104b AZ |
92 | } active_set; |
93 | ||
afbb5194 AZ |
94 | struct soc_dma_ch_s *dma; |
95 | ||
b4e3104b | 96 | /* unused parameters */ |
827df9f3 | 97 | int write_mode; |
b4e3104b AZ |
98 | int priority; |
99 | int interleave_disabled; | |
100 | int type; | |
827df9f3 AZ |
101 | int suspend; |
102 | int buf_disable; | |
b4e3104b AZ |
103 | }; |
104 | ||
105 | struct omap_dma_s { | |
afbb5194 AZ |
106 | struct soc_dma_s *dma; |
107 | ||
b4e3104b AZ |
108 | struct omap_mpu_state_s *mpu; |
109 | target_phys_addr_t base; | |
110 | omap_clk clk; | |
827df9f3 AZ |
111 | qemu_irq irq[4]; |
112 | void (*intr_update)(struct omap_dma_s *s); | |
b4e3104b AZ |
113 | enum omap_dma_model model; |
114 | int omap_3_1_mapping_disabled; | |
115 | ||
827df9f3 AZ |
116 | uint32_t gcr; |
117 | uint32_t ocp; | |
118 | uint32_t caps[5]; | |
119 | uint32_t irqen[4]; | |
120 | uint32_t irqstat[4]; | |
b4e3104b AZ |
121 | |
122 | int chans; | |
827df9f3 | 123 | struct omap_dma_channel_s ch[32]; |
b4e3104b AZ |
124 | struct omap_dma_lcd_channel_s lcd_ch; |
125 | }; | |
126 | ||
127 | /* Interrupts */ | |
128 | #define TIMEOUT_INTR (1 << 0) | |
129 | #define EVENT_DROP_INTR (1 << 1) | |
130 | #define HALF_FRAME_INTR (1 << 2) | |
131 | #define END_FRAME_INTR (1 << 3) | |
132 | #define LAST_FRAME_INTR (1 << 4) | |
133 | #define END_BLOCK_INTR (1 << 5) | |
134 | #define SYNC (1 << 6) | |
827df9f3 AZ |
135 | #define END_PKT_INTR (1 << 7) |
136 | #define TRANS_ERR_INTR (1 << 8) | |
137 | #define MISALIGN_INTR (1 << 11) | |
b4e3104b | 138 | |
827df9f3 | 139 | static inline void omap_dma_interrupts_update(struct omap_dma_s *s) |
b4e3104b | 140 | { |
827df9f3 | 141 | return s->intr_update(s); |
b4e3104b AZ |
142 | } |
143 | ||
afbb5194 | 144 | static void omap_dma_channel_load(struct omap_dma_channel_s *ch) |
b4e3104b AZ |
145 | { |
146 | struct omap_dma_reg_set_s *a = &ch->active_set; | |
afbb5194 | 147 | int i, normal; |
b4e3104b AZ |
148 | int omap_3_1 = !ch->omap_3_1_compatible_disable; |
149 | ||
150 | /* | |
151 | * TODO: verify address ranges and alignment | |
152 | * TODO: port endianness | |
153 | */ | |
154 | ||
155 | a->src = ch->addr[0]; | |
156 | a->dest = ch->addr[1]; | |
157 | a->frames = ch->frames; | |
158 | a->elements = ch->elements; | |
827df9f3 | 159 | a->pck_elements = ch->frame_index[!ch->src_sync]; |
b4e3104b AZ |
160 | a->frame = 0; |
161 | a->element = 0; | |
827df9f3 | 162 | a->pck_element = 0; |
b4e3104b AZ |
163 | |
164 | if (unlikely(!ch->elements || !ch->frames)) { | |
165 | printf("%s: bad DMA request\n", __FUNCTION__); | |
166 | return; | |
167 | } | |
168 | ||
169 | for (i = 0; i < 2; i ++) | |
170 | switch (ch->mode[i]) { | |
171 | case constant: | |
172 | a->elem_delta[i] = 0; | |
173 | a->frame_delta[i] = 0; | |
174 | break; | |
175 | case post_incremented: | |
176 | a->elem_delta[i] = ch->data_type; | |
177 | a->frame_delta[i] = 0; | |
178 | break; | |
179 | case single_index: | |
180 | a->elem_delta[i] = ch->data_type + | |
181 | ch->element_index[omap_3_1 ? 0 : i] - 1; | |
182 | a->frame_delta[i] = 0; | |
183 | break; | |
184 | case double_index: | |
185 | a->elem_delta[i] = ch->data_type + | |
186 | ch->element_index[omap_3_1 ? 0 : i] - 1; | |
187 | a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] - | |
188 | ch->element_index[omap_3_1 ? 0 : i]; | |
189 | break; | |
190 | default: | |
191 | break; | |
192 | } | |
afbb5194 AZ |
193 | |
194 | normal = !ch->transparent_copy && !ch->constant_fill && | |
195 | /* FIFO is big-endian so either (ch->endian[n] == 1) OR | |
196 | * (ch->endian_lock[n] == 1) mean no endianism conversion. */ | |
197 | (ch->endian[0] | ch->endian_lock[0]) == | |
198 | (ch->endian[1] | ch->endian_lock[1]); | |
199 | for (i = 0; i < 2; i ++) { | |
200 | /* TODO: for a->frame_delta[i] > 0 still use the fast path, just | |
201 | * limit min_elems in omap_dma_transfer_setup to the nearest frame | |
202 | * end. */ | |
203 | if (!a->elem_delta[i] && normal && | |
204 | (a->frames == 1 || !a->frame_delta[i])) | |
205 | ch->dma->type[i] = soc_dma_access_const; | |
206 | else if (a->elem_delta[i] == ch->data_type && normal && | |
207 | (a->frames == 1 || !a->frame_delta[i])) | |
208 | ch->dma->type[i] = soc_dma_access_linear; | |
209 | else | |
210 | ch->dma->type[i] = soc_dma_access_other; | |
211 | ||
212 | ch->dma->vaddr[i] = ch->addr[i]; | |
213 | } | |
214 | soc_dma_ch_update(ch->dma); | |
b4e3104b AZ |
215 | } |
216 | ||
217 | static void omap_dma_activate_channel(struct omap_dma_s *s, | |
218 | struct omap_dma_channel_s *ch) | |
219 | { | |
220 | if (!ch->active) { | |
afbb5194 AZ |
221 | if (ch->set_update) { |
222 | /* It's not clear when the active set is supposed to be | |
223 | * loaded from registers. We're already loading it when the | |
224 | * channel is enabled, and for some guests this is not enough | |
225 | * but that may be also because of a race condition (no | |
226 | * delays in qemu) in the guest code, which we're just | |
227 | * working around here. */ | |
228 | omap_dma_channel_load(ch); | |
229 | ch->set_update = 0; | |
230 | } | |
231 | ||
b4e3104b | 232 | ch->active = 1; |
afbb5194 | 233 | soc_dma_set_request(ch->dma, 1); |
b4e3104b AZ |
234 | if (ch->sync) |
235 | ch->status |= SYNC; | |
b4e3104b | 236 | } |
b4e3104b AZ |
237 | } |
238 | ||
239 | static void omap_dma_deactivate_channel(struct omap_dma_s *s, | |
240 | struct omap_dma_channel_s *ch) | |
241 | { | |
242 | /* Update cpc */ | |
243 | ch->cpc = ch->active_set.dest & 0xffff; | |
244 | ||
827df9f3 | 245 | if (ch->pending_request && !ch->waiting_end_prog && ch->enable) { |
b4e3104b AZ |
246 | /* Don't deactivate the channel */ |
247 | ch->pending_request = 0; | |
827df9f3 | 248 | return; |
b4e3104b AZ |
249 | } |
250 | ||
251 | /* Don't deactive the channel if it is synchronized and the DMA request is | |
252 | active */ | |
afbb5194 | 253 | if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync))) |
b4e3104b AZ |
254 | return; |
255 | ||
256 | if (ch->active) { | |
257 | ch->active = 0; | |
258 | ch->status &= ~SYNC; | |
afbb5194 | 259 | soc_dma_set_request(ch->dma, 0); |
b4e3104b | 260 | } |
b4e3104b AZ |
261 | } |
262 | ||
263 | static void omap_dma_enable_channel(struct omap_dma_s *s, | |
264 | struct omap_dma_channel_s *ch) | |
265 | { | |
266 | if (!ch->enable) { | |
267 | ch->enable = 1; | |
268 | ch->waiting_end_prog = 0; | |
afbb5194 | 269 | omap_dma_channel_load(ch); |
827df9f3 | 270 | /* TODO: theoretically if ch->sync && ch->prefetch && |
afbb5194 AZ |
271 | * !s->dma->drqbmp[ch->sync], we should also activate and fetch |
272 | * from source and then stall until signalled. */ | |
273 | if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync))) | |
b4e3104b AZ |
274 | omap_dma_activate_channel(s, ch); |
275 | } | |
276 | } | |
277 | ||
278 | static void omap_dma_disable_channel(struct omap_dma_s *s, | |
279 | struct omap_dma_channel_s *ch) | |
280 | { | |
281 | if (ch->enable) { | |
282 | ch->enable = 0; | |
283 | /* Discard any pending request */ | |
284 | ch->pending_request = 0; | |
285 | omap_dma_deactivate_channel(s, ch); | |
286 | } | |
287 | } | |
288 | ||
289 | static void omap_dma_channel_end_prog(struct omap_dma_s *s, | |
290 | struct omap_dma_channel_s *ch) | |
291 | { | |
292 | if (ch->waiting_end_prog) { | |
293 | ch->waiting_end_prog = 0; | |
294 | if (!ch->sync || ch->pending_request) { | |
295 | ch->pending_request = 0; | |
296 | omap_dma_activate_channel(s, ch); | |
297 | } | |
298 | } | |
299 | } | |
300 | ||
827df9f3 AZ |
301 | static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s) |
302 | { | |
303 | struct omap_dma_channel_s *ch = s->ch; | |
304 | ||
305 | /* First three interrupts are shared between two channels each. */ | |
306 | if (ch[0].status | ch[6].status) | |
307 | qemu_irq_raise(ch[0].irq); | |
308 | if (ch[1].status | ch[7].status) | |
309 | qemu_irq_raise(ch[1].irq); | |
310 | if (ch[2].status | ch[8].status) | |
311 | qemu_irq_raise(ch[2].irq); | |
312 | if (ch[3].status) | |
313 | qemu_irq_raise(ch[3].irq); | |
314 | if (ch[4].status) | |
315 | qemu_irq_raise(ch[4].irq); | |
316 | if (ch[5].status) | |
317 | qemu_irq_raise(ch[5].irq); | |
318 | } | |
319 | ||
320 | static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s) | |
321 | { | |
322 | struct omap_dma_channel_s *ch = s->ch; | |
323 | int i; | |
324 | ||
325 | for (i = s->chans; i; ch ++, i --) | |
326 | if (ch->status) | |
327 | qemu_irq_raise(ch->irq); | |
328 | } | |
329 | ||
b4e3104b AZ |
330 | static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s) |
331 | { | |
332 | s->omap_3_1_mapping_disabled = 0; | |
333 | s->chans = 9; | |
827df9f3 | 334 | s->intr_update = omap_dma_interrupts_3_1_update; |
b4e3104b AZ |
335 | } |
336 | ||
337 | static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s) | |
338 | { | |
339 | s->omap_3_1_mapping_disabled = 1; | |
340 | s->chans = 16; | |
827df9f3 | 341 | s->intr_update = omap_dma_interrupts_3_2_update; |
b4e3104b AZ |
342 | } |
343 | ||
344 | static void omap_dma_process_request(struct omap_dma_s *s, int request) | |
345 | { | |
346 | int channel; | |
347 | int drop_event = 0; | |
348 | struct omap_dma_channel_s *ch = s->ch; | |
349 | ||
350 | for (channel = 0; channel < s->chans; channel ++, ch ++) { | |
351 | if (ch->enable && ch->sync == request) { | |
352 | if (!ch->active) | |
353 | omap_dma_activate_channel(s, ch); | |
354 | else if (!ch->pending_request) | |
355 | ch->pending_request = 1; | |
356 | else { | |
357 | /* Request collision */ | |
358 | /* Second request received while processing other request */ | |
359 | ch->status |= EVENT_DROP_INTR; | |
360 | drop_event = 1; | |
361 | } | |
362 | } | |
363 | } | |
364 | ||
365 | if (drop_event) | |
366 | omap_dma_interrupts_update(s); | |
367 | } | |
368 | ||
afbb5194 | 369 | static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma) |
b4e3104b | 370 | { |
b4e3104b | 371 | uint8_t value[4]; |
afbb5194 AZ |
372 | struct omap_dma_channel_s *ch = dma->opaque; |
373 | struct omap_dma_reg_set_s *a = &ch->active_set; | |
374 | int bytes = dma->bytes; | |
375 | #ifdef MULTI_REQ | |
376 | uint16_t status = ch->status; | |
377 | #endif | |
b4e3104b | 378 | |
afbb5194 AZ |
379 | do { |
380 | /* Transfer a single element */ | |
381 | /* FIXME: check the endianness */ | |
382 | if (!ch->constant_fill) | |
383 | cpu_physical_memory_read(a->src, value, ch->data_type); | |
384 | else | |
385 | *(uint32_t *) value = ch->color; | |
386 | ||
387 | if (!ch->transparent_copy || *(uint32_t *) value != ch->color) | |
388 | cpu_physical_memory_write(a->dest, value, ch->data_type); | |
389 | ||
390 | a->src += a->elem_delta[0]; | |
391 | a->dest += a->elem_delta[1]; | |
392 | a->element ++; | |
393 | ||
394 | #ifndef MULTI_REQ | |
395 | if (a->element == a->elements) { | |
396 | /* End of Frame */ | |
397 | a->element = 0; | |
398 | a->src += a->frame_delta[0]; | |
399 | a->dest += a->frame_delta[1]; | |
400 | a->frame ++; | |
401 | ||
402 | /* If the channel is async, update cpc */ | |
403 | if (!ch->sync) | |
404 | ch->cpc = a->dest & 0xffff; | |
405 | } | |
406 | } while ((bytes -= ch->data_type)); | |
407 | #else | |
408 | /* If the channel is element synchronized, deactivate it */ | |
409 | if (ch->sync && !ch->fs && !ch->bs) | |
b4e3104b | 410 | omap_dma_deactivate_channel(s, ch); |
afbb5194 AZ |
411 | |
412 | /* If it is the last frame, set the LAST_FRAME interrupt */ | |
413 | if (a->element == 1 && a->frame == a->frames - 1) | |
414 | if (ch->interrupts & LAST_FRAME_INTR) | |
415 | ch->status |= LAST_FRAME_INTR; | |
416 | ||
417 | /* If the half of the frame was reached, set the HALF_FRAME | |
418 | interrupt */ | |
419 | if (a->element == (a->elements >> 1)) | |
420 | if (ch->interrupts & HALF_FRAME_INTR) | |
421 | ch->status |= HALF_FRAME_INTR; | |
422 | ||
423 | if (ch->fs && ch->bs) { | |
424 | a->pck_element ++; | |
425 | /* Check if a full packet has beed transferred. */ | |
426 | if (a->pck_element == a->pck_elements) { | |
427 | a->pck_element = 0; | |
428 | ||
429 | /* Set the END_PKT interrupt */ | |
430 | if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync) | |
431 | ch->status |= END_PKT_INTR; | |
432 | ||
433 | /* If the channel is packet-synchronized, deactivate it */ | |
434 | if (ch->sync) | |
435 | omap_dma_deactivate_channel(s, ch); | |
436 | } | |
b4e3104b AZ |
437 | } |
438 | ||
afbb5194 AZ |
439 | if (a->element == a->elements) { |
440 | /* End of Frame */ | |
441 | a->element = 0; | |
442 | a->src += a->frame_delta[0]; | |
443 | a->dest += a->frame_delta[1]; | |
444 | a->frame ++; | |
445 | ||
446 | /* If the channel is frame synchronized, deactivate it */ | |
447 | if (ch->sync && ch->fs && !ch->bs) | |
b4e3104b AZ |
448 | omap_dma_deactivate_channel(s, ch); |
449 | ||
afbb5194 AZ |
450 | /* If the channel is async, update cpc */ |
451 | if (!ch->sync) | |
452 | ch->cpc = a->dest & 0xffff; | |
453 | ||
454 | /* Set the END_FRAME interrupt */ | |
455 | if (ch->interrupts & END_FRAME_INTR) | |
456 | ch->status |= END_FRAME_INTR; | |
457 | ||
458 | if (a->frame == a->frames) { | |
459 | /* End of Block */ | |
460 | /* Disable the channel */ | |
461 | ||
462 | if (ch->omap_3_1_compatible_disable) { | |
463 | omap_dma_disable_channel(s, ch); | |
464 | if (ch->link_enabled) | |
465 | omap_dma_enable_channel(s, | |
466 | &s->ch[ch->link_next_ch]); | |
467 | } else { | |
468 | if (!ch->auto_init) | |
469 | omap_dma_disable_channel(s, ch); | |
470 | else if (ch->repeat || ch->end_prog) | |
471 | omap_dma_channel_load(ch); | |
472 | else { | |
473 | ch->waiting_end_prog = 1; | |
827df9f3 | 474 | omap_dma_deactivate_channel(s, ch); |
afbb5194 | 475 | } |
827df9f3 | 476 | } |
afbb5194 AZ |
477 | |
478 | if (ch->interrupts & END_BLOCK_INTR) | |
479 | ch->status |= END_BLOCK_INTR; | |
827df9f3 | 480 | } |
afbb5194 AZ |
481 | } |
482 | } while (status == ch->status && ch->active); | |
827df9f3 | 483 | |
afbb5194 AZ |
484 | omap_dma_interrupts_update(s); |
485 | #endif | |
486 | } | |
b4e3104b | 487 | |
afbb5194 AZ |
488 | enum { |
489 | omap_dma_intr_element_sync, | |
490 | omap_dma_intr_last_frame, | |
491 | omap_dma_intr_half_frame, | |
492 | omap_dma_intr_frame, | |
493 | omap_dma_intr_frame_sync, | |
494 | omap_dma_intr_packet, | |
495 | omap_dma_intr_packet_sync, | |
496 | omap_dma_intr_block, | |
497 | __omap_dma_intr_last, | |
498 | }; | |
b4e3104b | 499 | |
afbb5194 AZ |
500 | static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma) |
501 | { | |
502 | struct omap_dma_port_if_s *src_p, *dest_p; | |
503 | struct omap_dma_reg_set_s *a; | |
504 | struct omap_dma_channel_s *ch = dma->opaque; | |
505 | struct omap_dma_s *s = dma->dma->opaque; | |
506 | int frames, min_elems, elements[__omap_dma_intr_last]; | |
b4e3104b | 507 | |
afbb5194 | 508 | a = &ch->active_set; |
b4e3104b | 509 | |
afbb5194 AZ |
510 | src_p = &s->mpu->port[ch->port[0]]; |
511 | dest_p = &s->mpu->port[ch->port[1]]; | |
512 | if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) || | |
513 | (!dest_p->addr_valid(s->mpu, a->dest))) { | |
514 | #if 0 | |
515 | /* Bus time-out */ | |
516 | if (ch->interrupts & TIMEOUT_INTR) | |
517 | ch->status |= TIMEOUT_INTR; | |
518 | omap_dma_deactivate_channel(s, ch); | |
519 | continue; | |
520 | #endif | |
521 | printf("%s: Bus time-out in DMA%i operation\n", | |
522 | __FUNCTION__, dma->num); | |
523 | } | |
b4e3104b | 524 | |
afbb5194 AZ |
525 | min_elems = INT_MAX; |
526 | ||
527 | /* Check all the conditions that terminate the transfer starting | |
528 | * with those that can occur the soonest. */ | |
529 | #define INTR_CHECK(cond, id, nelements) \ | |
530 | if (cond) { \ | |
531 | elements[id] = nelements; \ | |
532 | if (elements[id] < min_elems) \ | |
533 | min_elems = elements[id]; \ | |
534 | } else \ | |
535 | elements[id] = INT_MAX; | |
536 | ||
537 | /* Elements */ | |
538 | INTR_CHECK( | |
539 | ch->sync && !ch->fs && !ch->bs, | |
540 | omap_dma_intr_element_sync, | |
541 | 1) | |
542 | ||
543 | /* Frames */ | |
544 | /* TODO: for transfers where entire frames can be read and written | |
545 | * using memcpy() but a->frame_delta is non-zero, try to still do | |
546 | * transfers using soc_dma but limit min_elems to a->elements - ... | |
547 | * See also the TODO in omap_dma_channel_load. */ | |
548 | INTR_CHECK( | |
549 | (ch->interrupts & LAST_FRAME_INTR) && | |
550 | ((a->frame < a->frames - 1) || !a->element), | |
551 | omap_dma_intr_last_frame, | |
552 | (a->frames - a->frame - 2) * a->elements + | |
553 | (a->elements - a->element + 1)) | |
554 | INTR_CHECK( | |
555 | ch->interrupts & HALF_FRAME_INTR, | |
556 | omap_dma_intr_half_frame, | |
557 | (a->elements >> 1) + | |
558 | (a->element >= (a->elements >> 1) ? a->elements : 0) - | |
559 | a->element) | |
560 | INTR_CHECK( | |
561 | ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR), | |
562 | omap_dma_intr_frame, | |
563 | a->elements - a->element) | |
564 | INTR_CHECK( | |
565 | ch->sync && ch->fs && !ch->bs, | |
566 | omap_dma_intr_frame_sync, | |
567 | a->elements - a->element) | |
568 | ||
569 | /* Packets */ | |
570 | INTR_CHECK( | |
571 | ch->fs && ch->bs && | |
572 | (ch->interrupts & END_PKT_INTR) && !ch->src_sync, | |
573 | omap_dma_intr_packet, | |
574 | a->pck_elements - a->pck_element) | |
575 | INTR_CHECK( | |
576 | ch->fs && ch->bs && ch->sync, | |
577 | omap_dma_intr_packet_sync, | |
578 | a->pck_elements - a->pck_element) | |
579 | ||
580 | /* Blocks */ | |
581 | INTR_CHECK( | |
582 | 1, | |
583 | omap_dma_intr_block, | |
584 | (a->frames - a->frame - 1) * a->elements + | |
585 | (a->elements - a->element)) | |
586 | ||
587 | dma->bytes = min_elems * ch->data_type; | |
588 | ||
589 | /* Set appropriate interrupts and/or deactivate channels */ | |
590 | ||
591 | #ifdef MULTI_REQ | |
592 | /* TODO: should all of this only be done if dma->update, and otherwise | |
593 | * inside omap_dma_transfer_generic below - check what's faster. */ | |
594 | if (dma->update) { | |
595 | #endif | |
b4e3104b | 596 | |
afbb5194 AZ |
597 | /* If the channel is element synchronized, deactivate it */ |
598 | if (min_elems == elements[omap_dma_intr_element_sync]) | |
599 | omap_dma_deactivate_channel(s, ch); | |
600 | ||
601 | /* If it is the last frame, set the LAST_FRAME interrupt */ | |
602 | if (min_elems == elements[omap_dma_intr_last_frame]) | |
603 | ch->status |= LAST_FRAME_INTR; | |
604 | ||
605 | /* If exactly half of the frame was reached, set the HALF_FRAME | |
606 | interrupt */ | |
607 | if (min_elems == elements[omap_dma_intr_half_frame]) | |
608 | ch->status |= HALF_FRAME_INTR; | |
609 | ||
610 | /* If a full packet has been transferred, set the END_PKT interrupt */ | |
611 | if (min_elems == elements[omap_dma_intr_packet]) | |
612 | ch->status |= END_PKT_INTR; | |
613 | ||
614 | /* If the channel is packet-synchronized, deactivate it */ | |
615 | if (min_elems == elements[omap_dma_intr_packet_sync]) | |
616 | omap_dma_deactivate_channel(s, ch); | |
617 | ||
618 | /* If the channel is frame synchronized, deactivate it */ | |
619 | if (min_elems == elements[omap_dma_intr_frame_sync]) | |
620 | omap_dma_deactivate_channel(s, ch); | |
621 | ||
622 | /* Set the END_FRAME interrupt */ | |
623 | if (min_elems == elements[omap_dma_intr_frame]) | |
624 | ch->status |= END_FRAME_INTR; | |
625 | ||
626 | if (min_elems == elements[omap_dma_intr_block]) { | |
627 | /* End of Block */ | |
628 | /* Disable the channel */ | |
629 | ||
630 | if (ch->omap_3_1_compatible_disable) { | |
631 | omap_dma_disable_channel(s, ch); | |
632 | if (ch->link_enabled) | |
633 | omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]); | |
634 | } else { | |
635 | if (!ch->auto_init) | |
636 | omap_dma_disable_channel(s, ch); | |
637 | else if (ch->repeat || ch->end_prog) | |
638 | omap_dma_channel_load(ch); | |
639 | else { | |
640 | ch->waiting_end_prog = 1; | |
641 | omap_dma_deactivate_channel(s, ch); | |
b4e3104b AZ |
642 | } |
643 | } | |
afbb5194 AZ |
644 | |
645 | if (ch->interrupts & END_BLOCK_INTR) | |
646 | ch->status |= END_BLOCK_INTR; | |
647 | } | |
648 | ||
649 | /* Update packet number */ | |
650 | if (ch->fs && ch->bs) { | |
651 | a->pck_element += min_elems; | |
652 | a->pck_element %= a->pck_elements; | |
653 | } | |
654 | ||
655 | /* TODO: check if we really need to update anything here or perhaps we | |
656 | * can skip part of this. */ | |
657 | #ifndef MULTI_REQ | |
658 | if (dma->update) { | |
659 | #endif | |
660 | a->element += min_elems; | |
661 | ||
662 | frames = a->element / a->elements; | |
663 | a->element = a->element % a->elements; | |
664 | a->frame += frames; | |
665 | a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0]; | |
666 | a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1]; | |
667 | ||
668 | /* If the channel is async, update cpc */ | |
669 | if (!ch->sync && frames) | |
670 | ch->cpc = a->dest & 0xffff; | |
d4066479 AZ |
671 | |
672 | /* TODO: if the destination port is IMIF or EMIFF, set the dirty | |
673 | * bits on it. */ | |
b4e3104b AZ |
674 | } |
675 | ||
676 | omap_dma_interrupts_update(s); | |
b4e3104b AZ |
677 | } |
678 | ||
afbb5194 | 679 | void omap_dma_reset(struct soc_dma_s *dma) |
b4e3104b AZ |
680 | { |
681 | int i; | |
afbb5194 | 682 | struct omap_dma_s *s = dma->opaque; |
b4e3104b | 683 | |
afbb5194 | 684 | soc_dma_reset(s->dma); |
827df9f3 AZ |
685 | if (s->model < omap_dma_4) |
686 | s->gcr = 0x0004; | |
687 | else | |
688 | s->gcr = 0x00010010; | |
689 | s->ocp = 0x00000000; | |
690 | memset(&s->irqstat, 0, sizeof(s->irqstat)); | |
691 | memset(&s->irqen, 0, sizeof(s->irqen)); | |
b4e3104b AZ |
692 | s->lcd_ch.src = emiff; |
693 | s->lcd_ch.condition = 0; | |
694 | s->lcd_ch.interrupts = 0; | |
695 | s->lcd_ch.dual = 0; | |
827df9f3 AZ |
696 | if (s->model < omap_dma_4) |
697 | omap_dma_enable_3_1_mapping(s); | |
b4e3104b | 698 | for (i = 0; i < s->chans; i ++) { |
827df9f3 AZ |
699 | s->ch[i].suspend = 0; |
700 | s->ch[i].prefetch = 0; | |
701 | s->ch[i].buf_disable = 0; | |
702 | s->ch[i].src_sync = 0; | |
b4e3104b AZ |
703 | memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst)); |
704 | memset(&s->ch[i].port, 0, sizeof(s->ch[i].port)); | |
705 | memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode)); | |
b4e3104b AZ |
706 | memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index)); |
707 | memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index)); | |
827df9f3 AZ |
708 | memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian)); |
709 | memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock)); | |
710 | memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate)); | |
711 | s->ch[i].write_mode = 0; | |
712 | s->ch[i].data_type = 0; | |
713 | s->ch[i].transparent_copy = 0; | |
714 | s->ch[i].constant_fill = 0; | |
715 | s->ch[i].color = 0x00000000; | |
716 | s->ch[i].end_prog = 0; | |
717 | s->ch[i].repeat = 0; | |
718 | s->ch[i].auto_init = 0; | |
719 | s->ch[i].link_enabled = 0; | |
720 | if (s->model < omap_dma_4) | |
721 | s->ch[i].interrupts = 0x0003; | |
722 | else | |
723 | s->ch[i].interrupts = 0x0000; | |
724 | s->ch[i].status = 0; | |
725 | s->ch[i].cstatus = 0; | |
726 | s->ch[i].active = 0; | |
727 | s->ch[i].enable = 0; | |
728 | s->ch[i].sync = 0; | |
729 | s->ch[i].pending_request = 0; | |
730 | s->ch[i].waiting_end_prog = 0; | |
731 | s->ch[i].cpc = 0x0000; | |
732 | s->ch[i].fs = 0; | |
733 | s->ch[i].bs = 0; | |
734 | s->ch[i].omap_3_1_compatible_disable = 0; | |
b4e3104b | 735 | memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set)); |
827df9f3 AZ |
736 | s->ch[i].priority = 0; |
737 | s->ch[i].interleave_disabled = 0; | |
738 | s->ch[i].type = 0; | |
b4e3104b AZ |
739 | } |
740 | } | |
741 | ||
742 | static int omap_dma_ch_reg_read(struct omap_dma_s *s, | |
743 | struct omap_dma_channel_s *ch, int reg, uint16_t *value) | |
744 | { | |
745 | switch (reg) { | |
746 | case 0x00: /* SYS_DMA_CSDP_CH0 */ | |
747 | *value = (ch->burst[1] << 14) | | |
748 | (ch->pack[1] << 13) | | |
749 | (ch->port[1] << 9) | | |
750 | (ch->burst[0] << 7) | | |
751 | (ch->pack[0] << 6) | | |
752 | (ch->port[0] << 2) | | |
753 | (ch->data_type >> 1); | |
754 | break; | |
755 | ||
756 | case 0x02: /* SYS_DMA_CCR_CH0 */ | |
827df9f3 | 757 | if (s->model <= omap_dma_3_1) |
b4e3104b AZ |
758 | *value = 0 << 10; /* FIFO_FLUSH reads as 0 */ |
759 | else | |
760 | *value = ch->omap_3_1_compatible_disable << 10; | |
761 | *value |= (ch->mode[1] << 14) | | |
762 | (ch->mode[0] << 12) | | |
763 | (ch->end_prog << 11) | | |
764 | (ch->repeat << 9) | | |
765 | (ch->auto_init << 8) | | |
766 | (ch->enable << 7) | | |
767 | (ch->priority << 6) | | |
768 | (ch->fs << 5) | ch->sync; | |
769 | break; | |
770 | ||
771 | case 0x04: /* SYS_DMA_CICR_CH0 */ | |
772 | *value = ch->interrupts; | |
773 | break; | |
774 | ||
775 | case 0x06: /* SYS_DMA_CSR_CH0 */ | |
776 | *value = ch->status; | |
777 | ch->status &= SYNC; | |
778 | if (!ch->omap_3_1_compatible_disable && ch->sibling) { | |
779 | *value |= (ch->sibling->status & 0x3f) << 6; | |
780 | ch->sibling->status &= SYNC; | |
781 | } | |
782 | qemu_irq_lower(ch->irq); | |
783 | break; | |
784 | ||
785 | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ | |
786 | *value = ch->addr[0] & 0x0000ffff; | |
787 | break; | |
788 | ||
789 | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ | |
790 | *value = ch->addr[0] >> 16; | |
791 | break; | |
792 | ||
793 | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ | |
794 | *value = ch->addr[1] & 0x0000ffff; | |
795 | break; | |
796 | ||
797 | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ | |
798 | *value = ch->addr[1] >> 16; | |
799 | break; | |
800 | ||
801 | case 0x10: /* SYS_DMA_CEN_CH0 */ | |
802 | *value = ch->elements; | |
803 | break; | |
804 | ||
805 | case 0x12: /* SYS_DMA_CFN_CH0 */ | |
806 | *value = ch->frames; | |
807 | break; | |
808 | ||
809 | case 0x14: /* SYS_DMA_CFI_CH0 */ | |
810 | *value = ch->frame_index[0]; | |
811 | break; | |
812 | ||
813 | case 0x16: /* SYS_DMA_CEI_CH0 */ | |
814 | *value = ch->element_index[0]; | |
815 | break; | |
816 | ||
817 | case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ | |
818 | if (ch->omap_3_1_compatible_disable) | |
819 | *value = ch->active_set.src & 0xffff; /* CSAC */ | |
820 | else | |
821 | *value = ch->cpc; | |
822 | break; | |
823 | ||
824 | case 0x1a: /* DMA_CDAC */ | |
825 | *value = ch->active_set.dest & 0xffff; /* CDAC */ | |
826 | break; | |
827 | ||
828 | case 0x1c: /* DMA_CDEI */ | |
829 | *value = ch->element_index[1]; | |
830 | break; | |
831 | ||
832 | case 0x1e: /* DMA_CDFI */ | |
833 | *value = ch->frame_index[1]; | |
834 | break; | |
835 | ||
836 | case 0x20: /* DMA_COLOR_L */ | |
837 | *value = ch->color & 0xffff; | |
838 | break; | |
839 | ||
840 | case 0x22: /* DMA_COLOR_U */ | |
841 | *value = ch->color >> 16; | |
842 | break; | |
843 | ||
844 | case 0x24: /* DMA_CCR2 */ | |
845 | *value = (ch->bs << 2) | | |
846 | (ch->transparent_copy << 1) | | |
847 | ch->constant_fill; | |
848 | break; | |
849 | ||
850 | case 0x28: /* DMA_CLNK_CTRL */ | |
851 | *value = (ch->link_enabled << 15) | | |
852 | (ch->link_next_ch & 0xf); | |
853 | break; | |
854 | ||
855 | case 0x2a: /* DMA_LCH_CTRL */ | |
856 | *value = (ch->interleave_disabled << 15) | | |
857 | ch->type; | |
858 | break; | |
859 | ||
860 | default: | |
861 | return 1; | |
862 | } | |
863 | return 0; | |
864 | } | |
865 | ||
866 | static int omap_dma_ch_reg_write(struct omap_dma_s *s, | |
867 | struct omap_dma_channel_s *ch, int reg, uint16_t value) | |
868 | { | |
869 | switch (reg) { | |
870 | case 0x00: /* SYS_DMA_CSDP_CH0 */ | |
871 | ch->burst[1] = (value & 0xc000) >> 14; | |
872 | ch->pack[1] = (value & 0x2000) >> 13; | |
873 | ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9); | |
874 | ch->burst[0] = (value & 0x0180) >> 7; | |
875 | ch->pack[0] = (value & 0x0040) >> 6; | |
876 | ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); | |
827df9f3 AZ |
877 | ch->data_type = 1 << (value & 3); |
878 | if (ch->port[0] >= __omap_dma_port_last) | |
b4e3104b AZ |
879 | printf("%s: invalid DMA port %i\n", __FUNCTION__, |
880 | ch->port[0]); | |
827df9f3 | 881 | if (ch->port[1] >= __omap_dma_port_last) |
b4e3104b AZ |
882 | printf("%s: invalid DMA port %i\n", __FUNCTION__, |
883 | ch->port[1]); | |
884 | if ((value & 3) == 3) | |
885 | printf("%s: bad data_type for DMA channel\n", __FUNCTION__); | |
886 | break; | |
887 | ||
888 | case 0x02: /* SYS_DMA_CCR_CH0 */ | |
889 | ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); | |
890 | ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); | |
891 | ch->end_prog = (value & 0x0800) >> 11; | |
827df9f3 | 892 | if (s->model >= omap_dma_3_2) |
b4e3104b AZ |
893 | ch->omap_3_1_compatible_disable = (value >> 10) & 0x1; |
894 | ch->repeat = (value & 0x0200) >> 9; | |
895 | ch->auto_init = (value & 0x0100) >> 8; | |
896 | ch->priority = (value & 0x0040) >> 6; | |
897 | ch->fs = (value & 0x0020) >> 5; | |
898 | ch->sync = value & 0x001f; | |
899 | ||
900 | if (value & 0x0080) | |
901 | omap_dma_enable_channel(s, ch); | |
902 | else | |
903 | omap_dma_disable_channel(s, ch); | |
904 | ||
905 | if (ch->end_prog) | |
906 | omap_dma_channel_end_prog(s, ch); | |
907 | ||
908 | break; | |
909 | ||
910 | case 0x04: /* SYS_DMA_CICR_CH0 */ | |
827df9f3 | 911 | ch->interrupts = value & 0x3f; |
b4e3104b AZ |
912 | break; |
913 | ||
914 | case 0x06: /* SYS_DMA_CSR_CH0 */ | |
915 | OMAP_RO_REG((target_phys_addr_t) reg); | |
916 | break; | |
917 | ||
918 | case 0x08: /* SYS_DMA_CSSA_L_CH0 */ | |
919 | ch->addr[0] &= 0xffff0000; | |
920 | ch->addr[0] |= value; | |
921 | break; | |
922 | ||
923 | case 0x0a: /* SYS_DMA_CSSA_U_CH0 */ | |
924 | ch->addr[0] &= 0x0000ffff; | |
925 | ch->addr[0] |= (uint32_t) value << 16; | |
926 | break; | |
927 | ||
928 | case 0x0c: /* SYS_DMA_CDSA_L_CH0 */ | |
929 | ch->addr[1] &= 0xffff0000; | |
930 | ch->addr[1] |= value; | |
931 | break; | |
932 | ||
933 | case 0x0e: /* SYS_DMA_CDSA_U_CH0 */ | |
934 | ch->addr[1] &= 0x0000ffff; | |
935 | ch->addr[1] |= (uint32_t) value << 16; | |
936 | break; | |
937 | ||
938 | case 0x10: /* SYS_DMA_CEN_CH0 */ | |
939 | ch->elements = value; | |
940 | break; | |
941 | ||
942 | case 0x12: /* SYS_DMA_CFN_CH0 */ | |
943 | ch->frames = value; | |
944 | break; | |
945 | ||
946 | case 0x14: /* SYS_DMA_CFI_CH0 */ | |
947 | ch->frame_index[0] = (int16_t) value; | |
948 | break; | |
949 | ||
950 | case 0x16: /* SYS_DMA_CEI_CH0 */ | |
951 | ch->element_index[0] = (int16_t) value; | |
952 | break; | |
953 | ||
954 | case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */ | |
955 | OMAP_RO_REG((target_phys_addr_t) reg); | |
956 | break; | |
957 | ||
958 | case 0x1c: /* DMA_CDEI */ | |
959 | ch->element_index[1] = (int16_t) value; | |
960 | break; | |
961 | ||
962 | case 0x1e: /* DMA_CDFI */ | |
963 | ch->frame_index[1] = (int16_t) value; | |
964 | break; | |
965 | ||
966 | case 0x20: /* DMA_COLOR_L */ | |
967 | ch->color &= 0xffff0000; | |
968 | ch->color |= value; | |
969 | break; | |
970 | ||
971 | case 0x22: /* DMA_COLOR_U */ | |
972 | ch->color &= 0xffff; | |
973 | ch->color |= value << 16; | |
974 | break; | |
975 | ||
976 | case 0x24: /* DMA_CCR2 */ | |
827df9f3 | 977 | ch->bs = (value >> 2) & 0x1; |
b4e3104b AZ |
978 | ch->transparent_copy = (value >> 1) & 0x1; |
979 | ch->constant_fill = value & 0x1; | |
980 | break; | |
981 | ||
982 | case 0x28: /* DMA_CLNK_CTRL */ | |
983 | ch->link_enabled = (value >> 15) & 0x1; | |
984 | if (value & (1 << 14)) { /* Stop_Lnk */ | |
985 | ch->link_enabled = 0; | |
986 | omap_dma_disable_channel(s, ch); | |
987 | } | |
988 | ch->link_next_ch = value & 0x1f; | |
989 | break; | |
990 | ||
991 | case 0x2a: /* DMA_LCH_CTRL */ | |
992 | ch->interleave_disabled = (value >> 15) & 0x1; | |
993 | ch->type = value & 0xf; | |
994 | break; | |
995 | ||
996 | default: | |
997 | return 1; | |
998 | } | |
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, | |
1003 | uint16_t value) | |
1004 | { | |
1005 | switch (offset) { | |
1006 | case 0xbc0: /* DMA_LCD_CSDP */ | |
1007 | s->brust_f2 = (value >> 14) & 0x3; | |
1008 | s->pack_f2 = (value >> 13) & 0x1; | |
1009 | s->data_type_f2 = (1 << ((value >> 11) & 0x3)); | |
1010 | s->brust_f1 = (value >> 7) & 0x3; | |
1011 | s->pack_f1 = (value >> 6) & 0x1; | |
1012 | s->data_type_f1 = (1 << ((value >> 0) & 0x3)); | |
1013 | break; | |
1014 | ||
1015 | case 0xbc2: /* DMA_LCD_CCR */ | |
1016 | s->mode_f2 = (value >> 14) & 0x3; | |
1017 | s->mode_f1 = (value >> 12) & 0x3; | |
1018 | s->end_prog = (value >> 11) & 0x1; | |
1019 | s->omap_3_1_compatible_disable = (value >> 10) & 0x1; | |
1020 | s->repeat = (value >> 9) & 0x1; | |
1021 | s->auto_init = (value >> 8) & 0x1; | |
1022 | s->running = (value >> 7) & 0x1; | |
1023 | s->priority = (value >> 6) & 0x1; | |
1024 | s->bs = (value >> 4) & 0x1; | |
1025 | break; | |
1026 | ||
1027 | case 0xbc4: /* DMA_LCD_CTRL */ | |
1028 | s->dst = (value >> 8) & 0x1; | |
1029 | s->src = ((value >> 6) & 0x3) << 1; | |
1030 | s->condition = 0; | |
1031 | /* Assume no bus errors and thus no BUS_ERROR irq bits. */ | |
1032 | s->interrupts = (value >> 1) & 1; | |
1033 | s->dual = value & 1; | |
1034 | break; | |
1035 | ||
1036 | case 0xbc8: /* TOP_B1_L */ | |
1037 | s->src_f1_top &= 0xffff0000; | |
1038 | s->src_f1_top |= 0x0000ffff & value; | |
1039 | break; | |
1040 | ||
1041 | case 0xbca: /* TOP_B1_U */ | |
1042 | s->src_f1_top &= 0x0000ffff; | |
1043 | s->src_f1_top |= value << 16; | |
1044 | break; | |
1045 | ||
1046 | case 0xbcc: /* BOT_B1_L */ | |
1047 | s->src_f1_bottom &= 0xffff0000; | |
1048 | s->src_f1_bottom |= 0x0000ffff & value; | |
1049 | break; | |
1050 | ||
1051 | case 0xbce: /* BOT_B1_U */ | |
1052 | s->src_f1_bottom &= 0x0000ffff; | |
1053 | s->src_f1_bottom |= (uint32_t) value << 16; | |
1054 | break; | |
1055 | ||
1056 | case 0xbd0: /* TOP_B2_L */ | |
1057 | s->src_f2_top &= 0xffff0000; | |
1058 | s->src_f2_top |= 0x0000ffff & value; | |
1059 | break; | |
1060 | ||
1061 | case 0xbd2: /* TOP_B2_U */ | |
1062 | s->src_f2_top &= 0x0000ffff; | |
1063 | s->src_f2_top |= (uint32_t) value << 16; | |
1064 | break; | |
1065 | ||
1066 | case 0xbd4: /* BOT_B2_L */ | |
1067 | s->src_f2_bottom &= 0xffff0000; | |
1068 | s->src_f2_bottom |= 0x0000ffff & value; | |
1069 | break; | |
1070 | ||
1071 | case 0xbd6: /* BOT_B2_U */ | |
1072 | s->src_f2_bottom &= 0x0000ffff; | |
1073 | s->src_f2_bottom |= (uint32_t) value << 16; | |
1074 | break; | |
1075 | ||
1076 | case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ | |
1077 | s->element_index_f1 = value; | |
1078 | break; | |
1079 | ||
1080 | case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ | |
1081 | s->frame_index_f1 &= 0xffff0000; | |
1082 | s->frame_index_f1 |= 0x0000ffff & value; | |
1083 | break; | |
1084 | ||
1085 | case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ | |
1086 | s->frame_index_f1 &= 0x0000ffff; | |
1087 | s->frame_index_f1 |= (uint32_t) value << 16; | |
1088 | break; | |
1089 | ||
1090 | case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ | |
1091 | s->element_index_f2 = value; | |
1092 | break; | |
1093 | ||
1094 | case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ | |
1095 | s->frame_index_f2 &= 0xffff0000; | |
1096 | s->frame_index_f2 |= 0x0000ffff & value; | |
1097 | break; | |
1098 | ||
1099 | case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ | |
1100 | s->frame_index_f2 &= 0x0000ffff; | |
1101 | s->frame_index_f2 |= (uint32_t) value << 16; | |
1102 | break; | |
1103 | ||
1104 | case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ | |
1105 | s->elements_f1 = value; | |
1106 | break; | |
1107 | ||
1108 | case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ | |
1109 | s->frames_f1 = value; | |
1110 | break; | |
1111 | ||
1112 | case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ | |
1113 | s->elements_f2 = value; | |
1114 | break; | |
1115 | ||
1116 | case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ | |
1117 | s->frames_f2 = value; | |
1118 | break; | |
1119 | ||
1120 | case 0xbea: /* DMA_LCD_LCH_CTRL */ | |
1121 | s->lch_type = value & 0xf; | |
1122 | break; | |
1123 | ||
1124 | default: | |
1125 | return 1; | |
1126 | } | |
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, | |
1131 | uint16_t *ret) | |
1132 | { | |
1133 | switch (offset) { | |
1134 | case 0xbc0: /* DMA_LCD_CSDP */ | |
1135 | *ret = (s->brust_f2 << 14) | | |
1136 | (s->pack_f2 << 13) | | |
1137 | ((s->data_type_f2 >> 1) << 11) | | |
1138 | (s->brust_f1 << 7) | | |
1139 | (s->pack_f1 << 6) | | |
1140 | ((s->data_type_f1 >> 1) << 0); | |
1141 | break; | |
1142 | ||
1143 | case 0xbc2: /* DMA_LCD_CCR */ | |
1144 | *ret = (s->mode_f2 << 14) | | |
1145 | (s->mode_f1 << 12) | | |
1146 | (s->end_prog << 11) | | |
1147 | (s->omap_3_1_compatible_disable << 10) | | |
1148 | (s->repeat << 9) | | |
1149 | (s->auto_init << 8) | | |
1150 | (s->running << 7) | | |
1151 | (s->priority << 6) | | |
1152 | (s->bs << 4); | |
1153 | break; | |
1154 | ||
1155 | case 0xbc4: /* DMA_LCD_CTRL */ | |
1156 | qemu_irq_lower(s->irq); | |
1157 | *ret = (s->dst << 8) | | |
1158 | ((s->src & 0x6) << 5) | | |
1159 | (s->condition << 3) | | |
1160 | (s->interrupts << 1) | | |
1161 | s->dual; | |
1162 | break; | |
1163 | ||
1164 | case 0xbc8: /* TOP_B1_L */ | |
1165 | *ret = s->src_f1_top & 0xffff; | |
1166 | break; | |
1167 | ||
1168 | case 0xbca: /* TOP_B1_U */ | |
1169 | *ret = s->src_f1_top >> 16; | |
1170 | break; | |
1171 | ||
1172 | case 0xbcc: /* BOT_B1_L */ | |
1173 | *ret = s->src_f1_bottom & 0xffff; | |
1174 | break; | |
1175 | ||
1176 | case 0xbce: /* BOT_B1_U */ | |
1177 | *ret = s->src_f1_bottom >> 16; | |
1178 | break; | |
1179 | ||
1180 | case 0xbd0: /* TOP_B2_L */ | |
1181 | *ret = s->src_f2_top & 0xffff; | |
1182 | break; | |
1183 | ||
1184 | case 0xbd2: /* TOP_B2_U */ | |
1185 | *ret = s->src_f2_top >> 16; | |
1186 | break; | |
1187 | ||
1188 | case 0xbd4: /* BOT_B2_L */ | |
1189 | *ret = s->src_f2_bottom & 0xffff; | |
1190 | break; | |
1191 | ||
1192 | case 0xbd6: /* BOT_B2_U */ | |
1193 | *ret = s->src_f2_bottom >> 16; | |
1194 | break; | |
1195 | ||
1196 | case 0xbd8: /* DMA_LCD_SRC_EI_B1 */ | |
1197 | *ret = s->element_index_f1; | |
1198 | break; | |
1199 | ||
1200 | case 0xbda: /* DMA_LCD_SRC_FI_B1_L */ | |
1201 | *ret = s->frame_index_f1 & 0xffff; | |
1202 | break; | |
1203 | ||
1204 | case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */ | |
1205 | *ret = s->frame_index_f1 >> 16; | |
1206 | break; | |
1207 | ||
1208 | case 0xbdc: /* DMA_LCD_SRC_EI_B2 */ | |
1209 | *ret = s->element_index_f2; | |
1210 | break; | |
1211 | ||
1212 | case 0xbde: /* DMA_LCD_SRC_FI_B2_L */ | |
1213 | *ret = s->frame_index_f2 & 0xffff; | |
1214 | break; | |
1215 | ||
1216 | case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */ | |
1217 | *ret = s->frame_index_f2 >> 16; | |
1218 | break; | |
1219 | ||
1220 | case 0xbe0: /* DMA_LCD_SRC_EN_B1 */ | |
1221 | *ret = s->elements_f1; | |
1222 | break; | |
1223 | ||
1224 | case 0xbe4: /* DMA_LCD_SRC_FN_B1 */ | |
1225 | *ret = s->frames_f1; | |
1226 | break; | |
1227 | ||
1228 | case 0xbe2: /* DMA_LCD_SRC_EN_B2 */ | |
1229 | *ret = s->elements_f2; | |
1230 | break; | |
1231 | ||
1232 | case 0xbe6: /* DMA_LCD_SRC_FN_B2 */ | |
1233 | *ret = s->frames_f2; | |
1234 | break; | |
1235 | ||
1236 | case 0xbea: /* DMA_LCD_LCH_CTRL */ | |
1237 | *ret = s->lch_type; | |
1238 | break; | |
1239 | ||
1240 | default: | |
1241 | return 1; | |
1242 | } | |
1243 | return 0; | |
1244 | } | |
1245 | ||
1246 | static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset, | |
1247 | uint16_t value) | |
1248 | { | |
1249 | switch (offset) { | |
1250 | case 0x300: /* SYS_DMA_LCD_CTRL */ | |
1251 | s->src = (value & 0x40) ? imif : emiff; | |
1252 | s->condition = 0; | |
1253 | /* Assume no bus errors and thus no BUS_ERROR irq bits. */ | |
1254 | s->interrupts = (value >> 1) & 1; | |
1255 | s->dual = value & 1; | |
1256 | break; | |
1257 | ||
1258 | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ | |
1259 | s->src_f1_top &= 0xffff0000; | |
1260 | s->src_f1_top |= 0x0000ffff & value; | |
1261 | break; | |
1262 | ||
1263 | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ | |
1264 | s->src_f1_top &= 0x0000ffff; | |
1265 | s->src_f1_top |= value << 16; | |
1266 | break; | |
1267 | ||
1268 | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ | |
1269 | s->src_f1_bottom &= 0xffff0000; | |
1270 | s->src_f1_bottom |= 0x0000ffff & value; | |
1271 | break; | |
1272 | ||
1273 | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ | |
1274 | s->src_f1_bottom &= 0x0000ffff; | |
1275 | s->src_f1_bottom |= value << 16; | |
1276 | break; | |
1277 | ||
1278 | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ | |
1279 | s->src_f2_top &= 0xffff0000; | |
1280 | s->src_f2_top |= 0x0000ffff & value; | |
1281 | break; | |
1282 | ||
1283 | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ | |
1284 | s->src_f2_top &= 0x0000ffff; | |
1285 | s->src_f2_top |= value << 16; | |
1286 | break; | |
1287 | ||
1288 | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ | |
1289 | s->src_f2_bottom &= 0xffff0000; | |
1290 | s->src_f2_bottom |= 0x0000ffff & value; | |
1291 | break; | |
1292 | ||
1293 | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ | |
1294 | s->src_f2_bottom &= 0x0000ffff; | |
1295 | s->src_f2_bottom |= value << 16; | |
1296 | break; | |
1297 | ||
1298 | default: | |
1299 | return 1; | |
1300 | } | |
1301 | return 0; | |
1302 | } | |
1303 | ||
1304 | static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset, | |
1305 | uint16_t *ret) | |
1306 | { | |
1307 | int i; | |
1308 | ||
1309 | switch (offset) { | |
1310 | case 0x300: /* SYS_DMA_LCD_CTRL */ | |
1311 | i = s->condition; | |
1312 | s->condition = 0; | |
1313 | qemu_irq_lower(s->irq); | |
1314 | *ret = ((s->src == imif) << 6) | (i << 3) | | |
1315 | (s->interrupts << 1) | s->dual; | |
1316 | break; | |
1317 | ||
1318 | case 0x302: /* SYS_DMA_LCD_TOP_F1_L */ | |
1319 | *ret = s->src_f1_top & 0xffff; | |
1320 | break; | |
1321 | ||
1322 | case 0x304: /* SYS_DMA_LCD_TOP_F1_U */ | |
1323 | *ret = s->src_f1_top >> 16; | |
1324 | break; | |
1325 | ||
1326 | case 0x306: /* SYS_DMA_LCD_BOT_F1_L */ | |
1327 | *ret = s->src_f1_bottom & 0xffff; | |
1328 | break; | |
1329 | ||
1330 | case 0x308: /* SYS_DMA_LCD_BOT_F1_U */ | |
1331 | *ret = s->src_f1_bottom >> 16; | |
1332 | break; | |
1333 | ||
1334 | case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */ | |
1335 | *ret = s->src_f2_top & 0xffff; | |
1336 | break; | |
1337 | ||
1338 | case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */ | |
1339 | *ret = s->src_f2_top >> 16; | |
1340 | break; | |
1341 | ||
1342 | case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */ | |
1343 | *ret = s->src_f2_bottom & 0xffff; | |
1344 | break; | |
1345 | ||
1346 | case 0x310: /* SYS_DMA_LCD_BOT_F2_U */ | |
1347 | *ret = s->src_f2_bottom >> 16; | |
1348 | break; | |
1349 | ||
1350 | default: | |
1351 | return 1; | |
1352 | } | |
1353 | return 0; | |
1354 | } | |
1355 | ||
1356 | static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value) | |
1357 | { | |
1358 | switch (offset) { | |
1359 | case 0x400: /* SYS_DMA_GCR */ | |
1360 | s->gcr = value; | |
1361 | break; | |
1362 | ||
1363 | case 0x404: /* DMA_GSCR */ | |
1364 | if (value & 0x8) | |
1365 | omap_dma_disable_3_1_mapping(s); | |
1366 | else | |
1367 | omap_dma_enable_3_1_mapping(s); | |
1368 | break; | |
1369 | ||
1370 | case 0x408: /* DMA_GRST */ | |
1371 | if (value & 0x1) | |
afbb5194 | 1372 | omap_dma_reset(s->dma); |
b4e3104b AZ |
1373 | break; |
1374 | ||
1375 | default: | |
1376 | return 1; | |
1377 | } | |
1378 | return 0; | |
1379 | } | |
1380 | ||
1381 | static int omap_dma_sys_read(struct omap_dma_s *s, int offset, | |
1382 | uint16_t *ret) | |
1383 | { | |
1384 | switch (offset) { | |
1385 | case 0x400: /* SYS_DMA_GCR */ | |
1386 | *ret = s->gcr; | |
1387 | break; | |
1388 | ||
1389 | case 0x404: /* DMA_GSCR */ | |
1390 | *ret = s->omap_3_1_mapping_disabled << 3; | |
1391 | break; | |
1392 | ||
1393 | case 0x408: /* DMA_GRST */ | |
1394 | *ret = 0; | |
1395 | break; | |
1396 | ||
1397 | case 0x442: /* DMA_HW_ID */ | |
1398 | case 0x444: /* DMA_PCh2_ID */ | |
1399 | case 0x446: /* DMA_PCh0_ID */ | |
1400 | case 0x448: /* DMA_PCh1_ID */ | |
1401 | case 0x44a: /* DMA_PChG_ID */ | |
1402 | case 0x44c: /* DMA_PChD_ID */ | |
1403 | *ret = 1; | |
1404 | break; | |
1405 | ||
1406 | case 0x44e: /* DMA_CAPS_0_U */ | |
827df9f3 | 1407 | *ret = (s->caps[0] >> 16) & 0xffff; |
b4e3104b | 1408 | break; |
b4e3104b | 1409 | case 0x450: /* DMA_CAPS_0_L */ |
827df9f3 | 1410 | *ret = (s->caps[0] >> 0) & 0xffff; |
b4e3104b AZ |
1411 | break; |
1412 | ||
827df9f3 AZ |
1413 | case 0x452: /* DMA_CAPS_1_U */ |
1414 | *ret = (s->caps[1] >> 16) & 0xffff; | |
1415 | break; | |
b4e3104b | 1416 | case 0x454: /* DMA_CAPS_1_L */ |
827df9f3 | 1417 | *ret = (s->caps[1] >> 0) & 0xffff; |
b4e3104b AZ |
1418 | break; |
1419 | ||
1420 | case 0x456: /* DMA_CAPS_2 */ | |
827df9f3 | 1421 | *ret = s->caps[2]; |
b4e3104b AZ |
1422 | break; |
1423 | ||
1424 | case 0x458: /* DMA_CAPS_3 */ | |
827df9f3 | 1425 | *ret = s->caps[3]; |
b4e3104b AZ |
1426 | break; |
1427 | ||
1428 | case 0x45a: /* DMA_CAPS_4 */ | |
827df9f3 | 1429 | *ret = s->caps[4]; |
b4e3104b AZ |
1430 | break; |
1431 | ||
1432 | case 0x460: /* DMA_PCh2_SR */ | |
1433 | case 0x480: /* DMA_PCh0_SR */ | |
1434 | case 0x482: /* DMA_PCh1_SR */ | |
1435 | case 0x4c0: /* DMA_PChD_SR_0 */ | |
1436 | printf("%s: Physical Channel Status Registers not implemented.\n", | |
1437 | __FUNCTION__); | |
1438 | *ret = 0xff; | |
1439 | break; | |
1440 | ||
1441 | default: | |
1442 | return 1; | |
1443 | } | |
1444 | return 0; | |
1445 | } | |
1446 | ||
1447 | static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr) | |
1448 | { | |
1449 | struct omap_dma_s *s = (struct omap_dma_s *) opaque; | |
1450 | int reg, ch, offset = addr - s->base; | |
1451 | uint16_t ret; | |
1452 | ||
1453 | switch (offset) { | |
1454 | case 0x300 ... 0x3fe: | |
827df9f3 | 1455 | if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { |
b4e3104b AZ |
1456 | if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret)) |
1457 | break; | |
1458 | return ret; | |
1459 | } | |
1460 | /* Fall through. */ | |
1461 | case 0x000 ... 0x2fe: | |
1462 | reg = offset & 0x3f; | |
1463 | ch = (offset >> 6) & 0x0f; | |
1464 | if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret)) | |
1465 | break; | |
1466 | return ret; | |
1467 | ||
1468 | case 0x404 ... 0x4fe: | |
827df9f3 | 1469 | if (s->model <= omap_dma_3_1) |
b4e3104b AZ |
1470 | break; |
1471 | /* Fall through. */ | |
1472 | case 0x400: | |
1473 | if (omap_dma_sys_read(s, offset, &ret)) | |
1474 | break; | |
1475 | return ret; | |
1476 | ||
1477 | case 0xb00 ... 0xbfe: | |
1478 | if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { | |
1479 | if (omap_dma_3_2_lcd_read(&s->lcd_ch, offset, &ret)) | |
1480 | break; | |
1481 | return ret; | |
1482 | } | |
1483 | break; | |
1484 | } | |
1485 | ||
1486 | OMAP_BAD_REG(addr); | |
1487 | return 0; | |
1488 | } | |
1489 | ||
1490 | static void omap_dma_write(void *opaque, target_phys_addr_t addr, | |
1491 | uint32_t value) | |
1492 | { | |
1493 | struct omap_dma_s *s = (struct omap_dma_s *) opaque; | |
1494 | int reg, ch, offset = addr - s->base; | |
1495 | ||
1496 | switch (offset) { | |
1497 | case 0x300 ... 0x3fe: | |
827df9f3 | 1498 | if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) { |
b4e3104b AZ |
1499 | if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value)) |
1500 | break; | |
1501 | return; | |
1502 | } | |
1503 | /* Fall through. */ | |
1504 | case 0x000 ... 0x2fe: | |
1505 | reg = offset & 0x3f; | |
1506 | ch = (offset >> 6) & 0x0f; | |
1507 | if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value)) | |
1508 | break; | |
1509 | return; | |
1510 | ||
1511 | case 0x404 ... 0x4fe: | |
827df9f3 | 1512 | if (s->model <= omap_dma_3_1) |
b4e3104b AZ |
1513 | break; |
1514 | case 0x400: | |
1515 | /* Fall through. */ | |
1516 | if (omap_dma_sys_write(s, offset, value)) | |
1517 | break; | |
1518 | return; | |
1519 | ||
1520 | case 0xb00 ... 0xbfe: | |
1521 | if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) { | |
1522 | if (omap_dma_3_2_lcd_write(&s->lcd_ch, offset, value)) | |
1523 | break; | |
1524 | return; | |
1525 | } | |
1526 | break; | |
1527 | } | |
1528 | ||
1529 | OMAP_BAD_REG(addr); | |
1530 | } | |
1531 | ||
1532 | static CPUReadMemoryFunc *omap_dma_readfn[] = { | |
1533 | omap_badwidth_read16, | |
1534 | omap_dma_read, | |
1535 | omap_badwidth_read16, | |
1536 | }; | |
1537 | ||
1538 | static CPUWriteMemoryFunc *omap_dma_writefn[] = { | |
1539 | omap_badwidth_write16, | |
1540 | omap_dma_write, | |
1541 | omap_badwidth_write16, | |
1542 | }; | |
1543 | ||
1544 | static void omap_dma_request(void *opaque, int drq, int req) | |
1545 | { | |
1546 | struct omap_dma_s *s = (struct omap_dma_s *) opaque; | |
827df9f3 | 1547 | /* The request pins are level triggered in QEMU. */ |
b4e3104b | 1548 | if (req) { |
afbb5194 AZ |
1549 | if (~s->dma->drqbmp & (1 << drq)) { |
1550 | s->dma->drqbmp |= 1 << drq; | |
b4e3104b AZ |
1551 | omap_dma_process_request(s, drq); |
1552 | } | |
1553 | } else | |
afbb5194 | 1554 | s->dma->drqbmp &= ~(1 << drq); |
b4e3104b AZ |
1555 | } |
1556 | ||
afbb5194 | 1557 | /* XXX: this won't be needed once soc_dma knows about clocks. */ |
b4e3104b AZ |
1558 | static void omap_dma_clk_update(void *opaque, int line, int on) |
1559 | { | |
1560 | struct omap_dma_s *s = (struct omap_dma_s *) opaque; | |
afbb5194 | 1561 | int i; |
b4e3104b | 1562 | |
afbb5194 AZ |
1563 | s->dma->freq = omap_clk_getrate(s->clk); |
1564 | ||
1565 | for (i = 0; i < s->chans; i ++) | |
1566 | if (s->ch[i].active) | |
1567 | soc_dma_set_request(s->ch[i].dma, on); | |
b4e3104b AZ |
1568 | } |
1569 | ||
827df9f3 AZ |
1570 | static void omap_dma_setcaps(struct omap_dma_s *s) |
1571 | { | |
1572 | switch (s->model) { | |
1573 | default: | |
1574 | case omap_dma_3_1: | |
1575 | break; | |
1576 | case omap_dma_3_2: | |
1577 | case omap_dma_4: | |
1578 | /* XXX Only available for sDMA */ | |
1579 | s->caps[0] = | |
1580 | (1 << 19) | /* Constant Fill Capability */ | |
1581 | (1 << 18); /* Transparent BLT Capability */ | |
1582 | s->caps[1] = | |
1583 | (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */ | |
1584 | s->caps[2] = | |
1585 | (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */ | |
1586 | (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */ | |
1587 | (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */ | |
1588 | (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */ | |
1589 | (1 << 4) | /* DST_CONST_ADRS_CPBLTY */ | |
1590 | (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */ | |
1591 | (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */ | |
1592 | (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */ | |
1593 | (1 << 0); /* SRC_CONST_ADRS_CPBLTY */ | |
1594 | s->caps[3] = | |
1595 | (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */ | |
1596 | (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */ | |
1597 | (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */ | |
1598 | (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */ | |
1599 | (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */ | |
1600 | (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */ | |
1601 | (1 << 1) | /* FRAME_SYNCHR_CPBLTY */ | |
1602 | (1 << 0); /* ELMNT_SYNCHR_CPBLTY */ | |
1603 | s->caps[4] = | |
1604 | (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */ | |
1605 | (1 << 6) | /* SYNC_STATUS_CPBLTY */ | |
1606 | (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */ | |
1607 | (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */ | |
1608 | (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */ | |
1609 | (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */ | |
1610 | (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */ | |
1611 | (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */ | |
1612 | break; | |
1613 | } | |
1614 | } | |
1615 | ||
afbb5194 | 1616 | struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs, |
b4e3104b AZ |
1617 | qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, |
1618 | enum omap_dma_model model) | |
1619 | { | |
1620 | int iomemtype, num_irqs, memsize, i; | |
1621 | struct omap_dma_s *s = (struct omap_dma_s *) | |
1622 | qemu_mallocz(sizeof(struct omap_dma_s)); | |
1623 | ||
827df9f3 | 1624 | if (model <= omap_dma_3_1) { |
b4e3104b AZ |
1625 | num_irqs = 6; |
1626 | memsize = 0x800; | |
1627 | } else { | |
1628 | num_irqs = 16; | |
1629 | memsize = 0xc00; | |
1630 | } | |
1631 | s->base = base; | |
1632 | s->model = model; | |
1633 | s->mpu = mpu; | |
1634 | s->clk = clk; | |
1635 | s->lcd_ch.irq = lcd_irq; | |
1636 | s->lcd_ch.mpu = mpu; | |
afbb5194 AZ |
1637 | |
1638 | s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16); | |
1639 | s->dma->freq = omap_clk_getrate(clk); | |
1640 | s->dma->transfer_fn = omap_dma_transfer_generic; | |
1641 | s->dma->setup_fn = omap_dma_transfer_setup; | |
1642 | s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32); | |
1643 | s->dma->opaque = s; | |
1644 | ||
b4e3104b AZ |
1645 | while (num_irqs --) |
1646 | s->ch[num_irqs].irq = irqs[num_irqs]; | |
1647 | for (i = 0; i < 3; i ++) { | |
1648 | s->ch[i].sibling = &s->ch[i + 6]; | |
1649 | s->ch[i + 6].sibling = &s->ch[i]; | |
1650 | } | |
afbb5194 AZ |
1651 | for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) { |
1652 | s->ch[i].dma = &s->dma->ch[i]; | |
1653 | s->dma->ch[i].opaque = &s->ch[i]; | |
1654 | } | |
1655 | ||
1656 | omap_dma_setcaps(s); | |
b4e3104b | 1657 | omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
afbb5194 | 1658 | omap_dma_reset(s->dma); |
b4e3104b AZ |
1659 | omap_dma_clk_update(s, 0, 1); |
1660 | ||
1661 | iomemtype = cpu_register_io_memory(0, omap_dma_readfn, | |
1662 | omap_dma_writefn, s); | |
1663 | cpu_register_physical_memory(s->base, memsize, iomemtype); | |
1664 | ||
afbb5194 AZ |
1665 | mpu->drq = s->dma->drq; |
1666 | ||
1667 | return s->dma; | |
b4e3104b AZ |
1668 | } |
1669 | ||
827df9f3 AZ |
1670 | static void omap_dma_interrupts_4_update(struct omap_dma_s *s) |
1671 | { | |
1672 | struct omap_dma_channel_s *ch = s->ch; | |
1673 | uint32_t bmp, bit; | |
1674 | ||
1675 | for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1) | |
1676 | if (ch->status) { | |
1677 | bmp |= bit; | |
1678 | ch->cstatus |= ch->status; | |
1679 | ch->status = 0; | |
1680 | } | |
1681 | if ((s->irqstat[0] |= s->irqen[0] & bmp)) | |
1682 | qemu_irq_raise(s->irq[0]); | |
1683 | if ((s->irqstat[1] |= s->irqen[1] & bmp)) | |
1684 | qemu_irq_raise(s->irq[1]); | |
1685 | if ((s->irqstat[2] |= s->irqen[2] & bmp)) | |
1686 | qemu_irq_raise(s->irq[2]); | |
1687 | if ((s->irqstat[3] |= s->irqen[3] & bmp)) | |
1688 | qemu_irq_raise(s->irq[3]); | |
1689 | } | |
1690 | ||
1691 | static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr) | |
1692 | { | |
1693 | struct omap_dma_s *s = (struct omap_dma_s *) opaque; | |
1694 | int irqn = 0, chnum, offset = addr - s->base; | |
1695 | struct omap_dma_channel_s *ch; | |
1696 | ||
1697 | switch (offset) { | |
1698 | case 0x00: /* DMA4_REVISION */ | |
1699 | return 0x40; | |
1700 | ||
1701 | case 0x14: /* DMA4_IRQSTATUS_L3 */ | |
1702 | irqn ++; | |
1703 | case 0x10: /* DMA4_IRQSTATUS_L2 */ | |
1704 | irqn ++; | |
1705 | case 0x0c: /* DMA4_IRQSTATUS_L1 */ | |
1706 | irqn ++; | |
1707 | case 0x08: /* DMA4_IRQSTATUS_L0 */ | |
1708 | return s->irqstat[irqn]; | |
1709 | ||
1710 | case 0x24: /* DMA4_IRQENABLE_L3 */ | |
1711 | irqn ++; | |
1712 | case 0x20: /* DMA4_IRQENABLE_L2 */ | |
1713 | irqn ++; | |
1714 | case 0x1c: /* DMA4_IRQENABLE_L1 */ | |
1715 | irqn ++; | |
1716 | case 0x18: /* DMA4_IRQENABLE_L0 */ | |
1717 | return s->irqen[irqn]; | |
1718 | ||
1719 | case 0x28: /* DMA4_SYSSTATUS */ | |
1720 | return 1; /* RESETDONE */ | |
1721 | ||
1722 | case 0x2c: /* DMA4_OCP_SYSCONFIG */ | |
1723 | return s->ocp; | |
1724 | ||
1725 | case 0x64: /* DMA4_CAPS_0 */ | |
1726 | return s->caps[0]; | |
1727 | case 0x6c: /* DMA4_CAPS_2 */ | |
1728 | return s->caps[2]; | |
1729 | case 0x70: /* DMA4_CAPS_3 */ | |
1730 | return s->caps[3]; | |
1731 | case 0x74: /* DMA4_CAPS_4 */ | |
1732 | return s->caps[4]; | |
1733 | ||
1734 | case 0x78: /* DMA4_GCR */ | |
1735 | return s->gcr; | |
1736 | ||
1737 | case 0x80 ... 0xfff: | |
1738 | offset -= 0x80; | |
1739 | chnum = offset / 0x60; | |
1740 | ch = s->ch + chnum; | |
1741 | offset -= chnum * 0x60; | |
1742 | break; | |
1743 | ||
1744 | default: | |
1745 | OMAP_BAD_REG(addr); | |
1746 | return 0; | |
1747 | } | |
1748 | ||
1749 | /* Per-channel registers */ | |
1750 | switch (offset) { | |
1751 | case 0x00: /* DMA4_CCR */ | |
1752 | return (ch->buf_disable << 25) | | |
1753 | (ch->src_sync << 24) | | |
1754 | (ch->prefetch << 23) | | |
1755 | ((ch->sync & 0x60) << 14) | | |
1756 | (ch->bs << 18) | | |
1757 | (ch->transparent_copy << 17) | | |
1758 | (ch->constant_fill << 16) | | |
1759 | (ch->mode[1] << 14) | | |
1760 | (ch->mode[0] << 12) | | |
1761 | (0 << 10) | (0 << 9) | | |
1762 | (ch->suspend << 8) | | |
1763 | (ch->enable << 7) | | |
1764 | (ch->priority << 6) | | |
1765 | (ch->fs << 5) | (ch->sync & 0x1f); | |
1766 | ||
1767 | case 0x04: /* DMA4_CLNK_CTRL */ | |
1768 | return (ch->link_enabled << 15) | ch->link_next_ch; | |
1769 | ||
1770 | case 0x08: /* DMA4_CICR */ | |
1771 | return ch->interrupts; | |
1772 | ||
1773 | case 0x0c: /* DMA4_CSR */ | |
1774 | return ch->cstatus; | |
1775 | ||
1776 | case 0x10: /* DMA4_CSDP */ | |
1777 | return (ch->endian[0] << 21) | | |
1778 | (ch->endian_lock[0] << 20) | | |
1779 | (ch->endian[1] << 19) | | |
1780 | (ch->endian_lock[1] << 18) | | |
1781 | (ch->write_mode << 16) | | |
1782 | (ch->burst[1] << 14) | | |
1783 | (ch->pack[1] << 13) | | |
1784 | (ch->translate[1] << 9) | | |
1785 | (ch->burst[0] << 7) | | |
1786 | (ch->pack[0] << 6) | | |
1787 | (ch->translate[0] << 2) | | |
1788 | (ch->data_type >> 1); | |
1789 | ||
1790 | case 0x14: /* DMA4_CEN */ | |
1791 | return ch->elements; | |
1792 | ||
1793 | case 0x18: /* DMA4_CFN */ | |
1794 | return ch->frames; | |
1795 | ||
1796 | case 0x1c: /* DMA4_CSSA */ | |
1797 | return ch->addr[0]; | |
1798 | ||
1799 | case 0x20: /* DMA4_CDSA */ | |
1800 | return ch->addr[1]; | |
1801 | ||
1802 | case 0x24: /* DMA4_CSEI */ | |
1803 | return ch->element_index[0]; | |
1804 | ||
1805 | case 0x28: /* DMA4_CSFI */ | |
1806 | return ch->frame_index[0]; | |
1807 | ||
1808 | case 0x2c: /* DMA4_CDEI */ | |
1809 | return ch->element_index[1]; | |
1810 | ||
1811 | case 0x30: /* DMA4_CDFI */ | |
1812 | return ch->frame_index[1]; | |
1813 | ||
1814 | case 0x34: /* DMA4_CSAC */ | |
1815 | return ch->active_set.src & 0xffff; | |
1816 | ||
1817 | case 0x38: /* DMA4_CDAC */ | |
1818 | return ch->active_set.dest & 0xffff; | |
1819 | ||
1820 | case 0x3c: /* DMA4_CCEN */ | |
1821 | return ch->active_set.element; | |
1822 | ||
1823 | case 0x40: /* DMA4_CCFN */ | |
1824 | return ch->active_set.frame; | |
1825 | ||
1826 | case 0x44: /* DMA4_COLOR */ | |
1827 | /* XXX only in sDMA */ | |
1828 | return ch->color; | |
1829 | ||
1830 | default: | |
1831 | OMAP_BAD_REG(addr); | |
1832 | return 0; | |
1833 | } | |
1834 | } | |
1835 | ||
1836 | static void omap_dma4_write(void *opaque, target_phys_addr_t addr, | |
1837 | uint32_t value) | |
1838 | { | |
1839 | struct omap_dma_s *s = (struct omap_dma_s *) opaque; | |
1840 | int chnum, irqn = 0, offset = addr - s->base; | |
1841 | struct omap_dma_channel_s *ch; | |
1842 | ||
1843 | switch (offset) { | |
1844 | case 0x14: /* DMA4_IRQSTATUS_L3 */ | |
1845 | irqn ++; | |
1846 | case 0x10: /* DMA4_IRQSTATUS_L2 */ | |
1847 | irqn ++; | |
1848 | case 0x0c: /* DMA4_IRQSTATUS_L1 */ | |
1849 | irqn ++; | |
1850 | case 0x08: /* DMA4_IRQSTATUS_L0 */ | |
1851 | s->irqstat[irqn] &= ~value; | |
1852 | if (!s->irqstat[irqn]) | |
1853 | qemu_irq_lower(s->irq[irqn]); | |
1854 | return; | |
1855 | ||
1856 | case 0x24: /* DMA4_IRQENABLE_L3 */ | |
1857 | irqn ++; | |
1858 | case 0x20: /* DMA4_IRQENABLE_L2 */ | |
1859 | irqn ++; | |
1860 | case 0x1c: /* DMA4_IRQENABLE_L1 */ | |
1861 | irqn ++; | |
1862 | case 0x18: /* DMA4_IRQENABLE_L0 */ | |
1863 | s->irqen[irqn] = value; | |
1864 | return; | |
1865 | ||
1866 | case 0x2c: /* DMA4_OCP_SYSCONFIG */ | |
1867 | if (value & 2) /* SOFTRESET */ | |
afbb5194 | 1868 | omap_dma_reset(s->dma); |
827df9f3 AZ |
1869 | s->ocp = value & 0x3321; |
1870 | if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */ | |
1871 | fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__); | |
1872 | return; | |
1873 | ||
1874 | case 0x78: /* DMA4_GCR */ | |
1875 | s->gcr = value & 0x00ff00ff; | |
1876 | if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */ | |
1877 | fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__); | |
1878 | return; | |
1879 | ||
1880 | case 0x80 ... 0xfff: | |
1881 | offset -= 0x80; | |
1882 | chnum = offset / 0x60; | |
1883 | ch = s->ch + chnum; | |
1884 | offset -= chnum * 0x60; | |
1885 | break; | |
1886 | ||
1887 | case 0x00: /* DMA4_REVISION */ | |
1888 | case 0x28: /* DMA4_SYSSTATUS */ | |
1889 | case 0x64: /* DMA4_CAPS_0 */ | |
1890 | case 0x6c: /* DMA4_CAPS_2 */ | |
1891 | case 0x70: /* DMA4_CAPS_3 */ | |
1892 | case 0x74: /* DMA4_CAPS_4 */ | |
1893 | OMAP_RO_REG(addr); | |
1894 | return; | |
1895 | ||
1896 | default: | |
1897 | OMAP_BAD_REG(addr); | |
1898 | return; | |
1899 | } | |
1900 | ||
1901 | /* Per-channel registers */ | |
1902 | switch (offset) { | |
1903 | case 0x00: /* DMA4_CCR */ | |
1904 | ch->buf_disable = (value >> 25) & 1; | |
1905 | ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */ | |
1906 | if (ch->buf_disable && !ch->src_sync) | |
1907 | fprintf(stderr, "%s: Buffering disable is not allowed in " | |
1908 | "destination synchronised mode\n", __FUNCTION__); | |
1909 | ch->prefetch = (value >> 23) & 1; | |
1910 | ch->bs = (value >> 18) & 1; | |
1911 | ch->transparent_copy = (value >> 17) & 1; | |
1912 | ch->constant_fill = (value >> 16) & 1; | |
1913 | ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14); | |
1914 | ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12); | |
1915 | ch->suspend = (value & 0x0100) >> 8; | |
1916 | ch->priority = (value & 0x0040) >> 6; | |
1917 | ch->fs = (value & 0x0020) >> 5; | |
1918 | if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) | |
1919 | fprintf(stderr, "%s: For a packet transfer at least one port " | |
1920 | "must be constant-addressed\n", __FUNCTION__); | |
1921 | ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060); | |
1922 | /* XXX must be 0x01 for CamDMA */ | |
1923 | ||
1924 | if (value & 0x0080) | |
1925 | omap_dma_enable_channel(s, ch); | |
1926 | else | |
1927 | omap_dma_disable_channel(s, ch); | |
1928 | ||
1929 | break; | |
1930 | ||
1931 | case 0x04: /* DMA4_CLNK_CTRL */ | |
1932 | ch->link_enabled = (value >> 15) & 0x1; | |
1933 | ch->link_next_ch = value & 0x1f; | |
1934 | break; | |
1935 | ||
1936 | case 0x08: /* DMA4_CICR */ | |
1937 | ch->interrupts = value & 0x09be; | |
1938 | break; | |
1939 | ||
1940 | case 0x0c: /* DMA4_CSR */ | |
1941 | ch->cstatus &= ~value; | |
1942 | break; | |
1943 | ||
1944 | case 0x10: /* DMA4_CSDP */ | |
1945 | ch->endian[0] =(value >> 21) & 1; | |
1946 | ch->endian_lock[0] =(value >> 20) & 1; | |
1947 | ch->endian[1] =(value >> 19) & 1; | |
1948 | ch->endian_lock[1] =(value >> 18) & 1; | |
1949 | if (ch->endian[0] != ch->endian[1]) | |
afbb5194 | 1950 | fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n", |
827df9f3 AZ |
1951 | __FUNCTION__); |
1952 | ch->write_mode = (value >> 16) & 3; | |
1953 | ch->burst[1] = (value & 0xc000) >> 14; | |
1954 | ch->pack[1] = (value & 0x2000) >> 13; | |
1955 | ch->translate[1] = (value & 0x1e00) >> 9; | |
1956 | ch->burst[0] = (value & 0x0180) >> 7; | |
1957 | ch->pack[0] = (value & 0x0040) >> 6; | |
1958 | ch->translate[0] = (value & 0x003c) >> 2; | |
1959 | if (ch->translate[0] | ch->translate[1]) | |
1960 | fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n", | |
1961 | __FUNCTION__); | |
1962 | ch->data_type = 1 << (value & 3); | |
1963 | if ((value & 3) == 3) | |
1964 | printf("%s: bad data_type for DMA channel\n", __FUNCTION__); | |
1965 | break; | |
1966 | ||
1967 | case 0x14: /* DMA4_CEN */ | |
afbb5194 | 1968 | ch->set_update = 1; |
827df9f3 AZ |
1969 | ch->elements = value & 0xffffff; |
1970 | break; | |
1971 | ||
1972 | case 0x18: /* DMA4_CFN */ | |
1973 | ch->frames = value & 0xffff; | |
afbb5194 | 1974 | ch->set_update = 1; |
827df9f3 AZ |
1975 | break; |
1976 | ||
1977 | case 0x1c: /* DMA4_CSSA */ | |
1978 | ch->addr[0] = (target_phys_addr_t) (uint32_t) value; | |
afbb5194 | 1979 | ch->set_update = 1; |
827df9f3 AZ |
1980 | break; |
1981 | ||
1982 | case 0x20: /* DMA4_CDSA */ | |
1983 | ch->addr[1] = (target_phys_addr_t) (uint32_t) value; | |
afbb5194 | 1984 | ch->set_update = 1; |
827df9f3 AZ |
1985 | break; |
1986 | ||
1987 | case 0x24: /* DMA4_CSEI */ | |
1988 | ch->element_index[0] = (int16_t) value; | |
afbb5194 | 1989 | ch->set_update = 1; |
827df9f3 AZ |
1990 | break; |
1991 | ||
1992 | case 0x28: /* DMA4_CSFI */ | |
1993 | ch->frame_index[0] = (int32_t) value; | |
afbb5194 | 1994 | ch->set_update = 1; |
827df9f3 AZ |
1995 | break; |
1996 | ||
1997 | case 0x2c: /* DMA4_CDEI */ | |
1998 | ch->element_index[1] = (int16_t) value; | |
afbb5194 | 1999 | ch->set_update = 1; |
827df9f3 AZ |
2000 | break; |
2001 | ||
2002 | case 0x30: /* DMA4_CDFI */ | |
2003 | ch->frame_index[1] = (int32_t) value; | |
afbb5194 | 2004 | ch->set_update = 1; |
827df9f3 AZ |
2005 | break; |
2006 | ||
2007 | case 0x44: /* DMA4_COLOR */ | |
2008 | /* XXX only in sDMA */ | |
2009 | ch->color = value; | |
2010 | break; | |
2011 | ||
2012 | case 0x34: /* DMA4_CSAC */ | |
2013 | case 0x38: /* DMA4_CDAC */ | |
2014 | case 0x3c: /* DMA4_CCEN */ | |
2015 | case 0x40: /* DMA4_CCFN */ | |
2016 | OMAP_RO_REG(addr); | |
2017 | break; | |
2018 | ||
2019 | default: | |
2020 | OMAP_BAD_REG(addr); | |
2021 | } | |
2022 | } | |
2023 | ||
2024 | static CPUReadMemoryFunc *omap_dma4_readfn[] = { | |
2025 | omap_badwidth_read16, | |
2026 | omap_dma4_read, | |
2027 | omap_dma4_read, | |
2028 | }; | |
2029 | ||
2030 | static CPUWriteMemoryFunc *omap_dma4_writefn[] = { | |
2031 | omap_badwidth_write16, | |
2032 | omap_dma4_write, | |
2033 | omap_dma4_write, | |
2034 | }; | |
2035 | ||
afbb5194 | 2036 | struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs, |
827df9f3 AZ |
2037 | struct omap_mpu_state_s *mpu, int fifo, |
2038 | int chans, omap_clk iclk, omap_clk fclk) | |
2039 | { | |
afbb5194 | 2040 | int iomemtype, i; |
827df9f3 AZ |
2041 | struct omap_dma_s *s = (struct omap_dma_s *) |
2042 | qemu_mallocz(sizeof(struct omap_dma_s)); | |
2043 | ||
2044 | s->base = base; | |
2045 | s->model = omap_dma_4; | |
2046 | s->chans = chans; | |
2047 | s->mpu = mpu; | |
2048 | s->clk = fclk; | |
afbb5194 AZ |
2049 | |
2050 | s->dma = soc_dma_init(s->chans); | |
2051 | s->dma->freq = omap_clk_getrate(fclk); | |
2052 | s->dma->transfer_fn = omap_dma_transfer_generic; | |
2053 | s->dma->setup_fn = omap_dma_transfer_setup; | |
2054 | s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64); | |
2055 | s->dma->opaque = s; | |
2056 | for (i = 0; i < s->chans; i ++) { | |
2057 | s->ch[i].dma = &s->dma->ch[i]; | |
2058 | s->dma->ch[i].opaque = &s->ch[i]; | |
2059 | } | |
2060 | ||
827df9f3 AZ |
2061 | memcpy(&s->irq, irqs, sizeof(s->irq)); |
2062 | s->intr_update = omap_dma_interrupts_4_update; | |
afbb5194 | 2063 | |
827df9f3 | 2064 | omap_dma_setcaps(s); |
827df9f3 | 2065 | omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]); |
afbb5194 AZ |
2066 | omap_dma_reset(s->dma); |
2067 | omap_dma_clk_update(s, 0, !!s->dma->freq); | |
827df9f3 AZ |
2068 | |
2069 | iomemtype = cpu_register_io_memory(0, omap_dma4_readfn, | |
2070 | omap_dma4_writefn, s); | |
2071 | cpu_register_physical_memory(s->base, 0x1000, iomemtype); | |
2072 | ||
afbb5194 AZ |
2073 | mpu->drq = s->dma->drq; |
2074 | ||
2075 | return s->dma; | |
827df9f3 AZ |
2076 | } |
2077 | ||
afbb5194 | 2078 | struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma) |
b4e3104b | 2079 | { |
afbb5194 AZ |
2080 | struct omap_dma_s *s = dma->opaque; |
2081 | ||
b4e3104b AZ |
2082 | return &s->lcd_ch; |
2083 | } |