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1/* omap_sx1.c Support for the Siemens SX1 smartphone emulation.
2 *
3 * Copyright (C) 2008
4 * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 * Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com>
6 *
7 * based on PalmOne's (TM) PDAs support (palm.c)
8 */
9
10/*
11 * PalmOne's (TM) PDAs.
12 *
13 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
fad6cb1a 25 * You should have received a copy of the GNU General Public License along
8167ee88 26 * with this program; if not, see <http://www.gnu.org/licenses/>.
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27 */
28#include "hw.h"
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29#include "console.h"
30#include "omap.h"
31#include "boards.h"
32#include "arm-misc.h"
33#include "flash.h"
2446333c 34#include "blockdev.h"
4b3fedf3 35#include "exec-memory.h"
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36
37/*****************************************************************************/
38/* Siemens SX1 Cellphone V1 */
39/* - ARM OMAP310 processor
40 * - SRAM 192 kB
41 * - SDRAM 32 MB at 0x10000000
42 * - Boot flash 16 MB at 0x00000000
43 * - Application flash 8 MB at 0x04000000
44 * - 3 serial ports
45 * - 1 SecureDigital
46 * - 1 LCD display
47 * - 1 RTC
48 */
49
50/*****************************************************************************/
51/* Siemens SX1 Cellphone V2 */
52/* - ARM OMAP310 processor
53 * - SRAM 192 kB
54 * - SDRAM 32 MB at 0x10000000
55 * - Boot flash 32 MB at 0x00000000
56 * - 3 serial ports
57 * - 1 SecureDigital
58 * - 1 LCD display
59 * - 1 RTC
60 */
61
c227f099 62static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
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63{
64 uint32_t *val = (uint32_t *) opaque;
65
66 return *val >> ((offset & 3) << 3);
67}
68
c227f099 69static uint32_t static_readh(void *opaque, target_phys_addr_t offset)
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70{
71 uint32_t *val = (uint32_t *) opaque;
72
73 return *val >> ((offset & 1) << 3);
74}
75
c227f099 76static uint32_t static_readw(void *opaque, target_phys_addr_t offset)
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77{
78 uint32_t *val = (uint32_t *) opaque;
79
80 return *val >> ((offset & 0) << 3);
81}
82
c227f099 83static void static_write(void *opaque, target_phys_addr_t offset,
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84 uint32_t value)
85{
86#ifdef SPY
87 printf("%s: value %08lx written at " PA_FMT "\n",
88 __FUNCTION__, value, offset);
89#endif
90}
91
d60efc6b 92static CPUReadMemoryFunc * const static_readfn[] = {
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93 static_readb,
94 static_readh,
95 static_readw,
96};
97
d60efc6b 98static CPUWriteMemoryFunc * const static_writefn[] = {
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99 static_write,
100 static_write,
101 static_write,
102};
103
104#define sdram_size 0x02000000
105#define sector_size (128 * 1024)
106#define flash0_size (16 * 1024 * 1024)
107#define flash1_size ( 8 * 1024 * 1024)
108#define flash2_size (32 * 1024 * 1024)
109#define total_ram_v1 (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE)
110#define total_ram_v2 (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE)
111
112static struct arm_boot_info sx1_binfo = {
113 .loader_start = OMAP_EMIFF_BASE,
114 .ram_size = sdram_size,
115 .board_id = 0x265,
116};
117
c227f099 118static void sx1_init(ram_addr_t ram_size,
5f70aab1 119 const char *boot_device,
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120 const char *kernel_filename, const char *kernel_cmdline,
121 const char *initrd_filename, const char *cpu_model,
122 const int version)
123{
124 struct omap_mpu_state_s *cpu;
4b3fedf3 125 MemoryRegion *address_space = get_system_memory();
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126 int io;
127 static uint32_t cs0val = 0x00213090;
128 static uint32_t cs1val = 0x00215070;
129 static uint32_t cs2val = 0x00001139;
130 static uint32_t cs3val = 0x00001139;
751c6a17 131 DriveInfo *dinfo;
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132 int fl_idx;
133 uint32_t flash_size = flash0_size;
01e0451a 134 int be;
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135
136 if (version == 2) {
137 flash_size = flash2_size;
138 }
139
4b3fedf3 140 cpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model);
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141
142 /* External Flash (EMIFS) */
143 cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
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144 qemu_ram_alloc(NULL, "omap_sx1.flash0-0",
145 flash_size) | IO_MEM_ROM);
997641a8 146
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147 io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val,
148 DEVICE_NATIVE_ENDIAN);
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149 cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,
150 OMAP_CS0_SIZE - flash_size, io);
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151 io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val,
152 DEVICE_NATIVE_ENDIAN);
997641a8 153 cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);
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154 io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val,
155 DEVICE_NATIVE_ENDIAN);
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156 cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);
157
158 fl_idx = 0;
3d08ff69 159#ifdef TARGET_WORDS_BIGENDIAN
01e0451a 160 be = 1;
3d08ff69 161#else
01e0451a 162 be = 0;
3d08ff69 163#endif
997641a8 164
751c6a17 165 if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
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166 if (!pflash_cfi01_register(OMAP_CS0_BASE, NULL,
167 "omap_sx1.flash0-1", flash_size,
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168 dinfo->bdrv, sector_size,
169 flash_size / sector_size,
01e0451a 170 4, 0, 0, 0, 0, be)) {
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171 fprintf(stderr, "qemu: Error registering flash memory %d.\n",
172 fl_idx);
173 }
174 fl_idx++;
175 }
176
177 if ((version == 1) &&
751c6a17 178 (dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
997641a8 179 cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size,
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180 qemu_ram_alloc(NULL, "omap_sx1.flash1-0",
181 flash1_size) | IO_MEM_ROM);
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182 io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,
183 DEVICE_NATIVE_ENDIAN);
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184 cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,
185 OMAP_CS1_SIZE - flash1_size, io);
186
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187 if (!pflash_cfi01_register(OMAP_CS1_BASE, NULL,
188 "omap_sx1.flash1-1", flash1_size,
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189 dinfo->bdrv, sector_size,
190 flash1_size / sector_size,
01e0451a 191 4, 0, 0, 0, 0, be)) {
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192 fprintf(stderr, "qemu: Error registering flash memory %d.\n",
193 fl_idx);
194 }
195 fl_idx++;
196 } else {
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197 io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,
198 DEVICE_NATIVE_ENDIAN);
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199 cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);
200 }
201
202 if (!kernel_filename && !fl_idx) {
203 fprintf(stderr, "Kernel or Flash image must be specified\n");
204 exit(1);
205 }
206
207 /* Load the kernel. */
208 if (kernel_filename) {
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209 sx1_binfo.kernel_filename = kernel_filename;
210 sx1_binfo.kernel_cmdline = kernel_cmdline;
211 sx1_binfo.initrd_filename = initrd_filename;
212 arm_load_kernel(cpu->env, &sx1_binfo);
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213 }
214
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215 /* TODO: fix next line */
216 //~ qemu_console_resize(ds, 640, 480);
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217}
218
c227f099 219static void sx1_init_v1(ram_addr_t ram_size,
5f70aab1 220 const char *boot_device,
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221 const char *kernel_filename, const char *kernel_cmdline,
222 const char *initrd_filename, const char *cpu_model)
223{
fbe1b595 224 sx1_init(ram_size, boot_device, kernel_filename,
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225 kernel_cmdline, initrd_filename, cpu_model, 1);
226}
227
c227f099 228static void sx1_init_v2(ram_addr_t ram_size,
5f70aab1 229 const char *boot_device,
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230 const char *kernel_filename, const char *kernel_cmdline,
231 const char *initrd_filename, const char *cpu_model)
232{
fbe1b595 233 sx1_init(ram_size, boot_device, kernel_filename,
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234 kernel_cmdline, initrd_filename, cpu_model, 2);
235}
236
f80f9ec9 237static QEMUMachine sx1_machine_v2 = {
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238 .name = "sx1",
239 .desc = "Siemens SX1 (OMAP310) V2",
240 .init = sx1_init_v2,
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241};
242
f80f9ec9 243static QEMUMachine sx1_machine_v1 = {
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244 .name = "sx1-v1",
245 .desc = "Siemens SX1 (OMAP310) V1",
246 .init = sx1_init_v1,
997641a8 247};
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248
249static void sx1_machine_init(void)
250{
251 qemu_register_machine(&sx1_machine_v2);
252 qemu_register_machine(&sx1_machine_v1);
253}
254
255machine_init(sx1_machine_init);