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dbda808a FB |
1 | /* |
2 | * OpenPIC emulation | |
5fafdf24 | 3 | * |
dbda808a | 4 | * Copyright (c) 2004 Jocelyn Mayer |
704c7e5d | 5 | * 2011 Alexander Graf |
5fafdf24 | 6 | * |
dbda808a FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | /* | |
26 | * | |
27 | * Based on OpenPic implementations: | |
67b55785 | 28 | * - Intel GW80314 I/O companion chip developer's manual |
dbda808a FB |
29 | * - Motorola MPC8245 & MPC8540 user manuals. |
30 | * - Motorola MCP750 (aka Raven) programmer manual. | |
31 | * - Motorola Harrier programmer manuel | |
32 | * | |
33 | * Serial interrupts, as implemented in Raven chipset are not supported yet. | |
5fafdf24 | 34 | * |
dbda808a | 35 | */ |
87ecb68b PB |
36 | #include "hw.h" |
37 | #include "ppc_mac.h" | |
38 | #include "pci.h" | |
b7169916 | 39 | #include "openpic.h" |
dbda808a | 40 | |
611493d9 | 41 | //#define DEBUG_OPENPIC |
dbda808a FB |
42 | |
43 | #ifdef DEBUG_OPENPIC | |
001faf32 | 44 | #define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
dbda808a | 45 | #else |
001faf32 | 46 | #define DPRINTF(fmt, ...) do { } while (0) |
dbda808a | 47 | #endif |
dbda808a | 48 | |
cdbb912a AG |
49 | #define MAX_CPU 15 |
50 | #define MAX_SRC 256 | |
dbda808a FB |
51 | #define MAX_TMR 4 |
52 | #define VECTOR_BITS 8 | |
53 | #define MAX_IPI 4 | |
cdbb912a | 54 | #define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR) |
dbda808a FB |
55 | #define VID 0x03 /* MPIC version ID */ |
56 | #define VENI 0x00000000 /* Vendor ID */ | |
57 | ||
58 | enum { | |
59 | IRQ_IPVP = 0, | |
60 | IRQ_IDE, | |
61 | }; | |
62 | ||
b7169916 AJ |
63 | /* OpenPIC */ |
64 | #define OPENPIC_MAX_CPU 2 | |
65 | #define OPENPIC_MAX_IRQ 64 | |
66 | #define OPENPIC_EXT_IRQ 48 | |
67 | #define OPENPIC_MAX_TMR MAX_TMR | |
68 | #define OPENPIC_MAX_IPI MAX_IPI | |
dbda808a | 69 | |
b7169916 AJ |
70 | /* Interrupt definitions */ |
71 | #define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */ | |
72 | #define OPENPIC_IRQ_ERR (OPENPIC_EXT_IRQ + 1) /* Error IRQ */ | |
73 | #define OPENPIC_IRQ_TIM0 (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */ | |
74 | #if OPENPIC_MAX_IPI > 0 | |
75 | #define OPENPIC_IRQ_IPI0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */ | |
76 | #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */ | |
dbda808a | 77 | #else |
b7169916 AJ |
78 | #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */ |
79 | #define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */ | |
dbda808a FB |
80 | #endif |
81 | ||
b7169916 AJ |
82 | /* MPIC */ |
83 | #define MPIC_MAX_CPU 1 | |
84 | #define MPIC_MAX_EXT 12 | |
85 | #define MPIC_MAX_INT 64 | |
cdbb912a | 86 | #define MPIC_MAX_IRQ MAX_IRQ |
dbda808a FB |
87 | |
88 | /* Interrupt definitions */ | |
cdbb912a AG |
89 | /* IRQs, accessible through the IRQ region */ |
90 | #define MPIC_EXT_IRQ 0x00 | |
91 | #define MPIC_INT_IRQ 0x10 | |
92 | #define MPIC_MSG_IRQ 0xb0 | |
93 | #define MPIC_MSI_IRQ 0xe0 | |
94 | /* These are available through separate regions, but | |
95 | for simplicity's sake mapped into the same number space */ | |
96 | #define MPIC_TMR_IRQ 0x100 | |
97 | #define MPIC_IPI_IRQ 0x104 | |
b7169916 AJ |
98 | |
99 | #define MPIC_GLB_REG_START 0x0 | |
100 | #define MPIC_GLB_REG_SIZE 0x10F0 | |
101 | #define MPIC_TMR_REG_START 0x10F0 | |
102 | #define MPIC_TMR_REG_SIZE 0x220 | |
cdbb912a AG |
103 | #define MPIC_IRQ_REG_START 0x10000 |
104 | #define MPIC_IRQ_REG_SIZE (MAX_SRC * 0x20) | |
b7169916 | 105 | #define MPIC_CPU_REG_START 0x20000 |
bc59d9c9 | 106 | #define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) |
b7169916 | 107 | |
3e772232 BB |
108 | /* |
109 | * Block Revision Register1 (BRR1): QEMU does not fully emulate | |
110 | * any version on MPIC. So to start with, set the IP version to 0. | |
111 | * | |
112 | * NOTE: This is Freescale MPIC specific register. Keep it here till | |
113 | * this code is refactored for different variants of OPENPIC and MPIC. | |
114 | */ | |
115 | #define FSL_BRR1_IPID (0x0040 << 16) /* 16 bit IP-block ID */ | |
116 | #define FSL_BRR1_IPMJ (0x00 << 8) /* 8 bit IP major number */ | |
117 | #define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */ | |
118 | ||
b7169916 | 119 | enum mpic_ide_bits { |
0d33defb AG |
120 | IDR_EP = 31, |
121 | IDR_CI0 = 30, | |
122 | IDR_CI1 = 29, | |
123 | IDR_P1 = 1, | |
124 | IDR_P0 = 0, | |
b7169916 AJ |
125 | }; |
126 | ||
dbda808a FB |
127 | #define BF_WIDTH(_bits_) \ |
128 | (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8)) | |
129 | ||
130 | static inline void set_bit (uint32_t *field, int bit) | |
131 | { | |
132 | field[bit >> 5] |= 1 << (bit & 0x1F); | |
133 | } | |
134 | ||
135 | static inline void reset_bit (uint32_t *field, int bit) | |
136 | { | |
137 | field[bit >> 5] &= ~(1 << (bit & 0x1F)); | |
138 | } | |
139 | ||
140 | static inline int test_bit (uint32_t *field, int bit) | |
141 | { | |
142 | return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0; | |
143 | } | |
144 | ||
704c7e5d AG |
145 | static int get_current_cpu(void) |
146 | { | |
147 | return cpu_single_env->cpu_index; | |
148 | } | |
149 | ||
a8170e5e | 150 | static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, |
704c7e5d | 151 | int idx); |
a8170e5e | 152 | static void openpic_cpu_write_internal(void *opaque, hwaddr addr, |
704c7e5d AG |
153 | uint32_t val, int idx); |
154 | ||
dbda808a FB |
155 | enum { |
156 | IRQ_EXTERNAL = 0x01, | |
157 | IRQ_INTERNAL = 0x02, | |
158 | IRQ_TIMER = 0x04, | |
159 | IRQ_SPECIAL = 0x08, | |
b1d8e52e | 160 | }; |
dbda808a | 161 | |
c227f099 | 162 | typedef struct IRQ_queue_t { |
dbda808a FB |
163 | uint32_t queue[BF_WIDTH(MAX_IRQ)]; |
164 | int next; | |
165 | int priority; | |
c227f099 | 166 | } IRQ_queue_t; |
dbda808a | 167 | |
c227f099 | 168 | typedef struct IRQ_src_t { |
dbda808a FB |
169 | uint32_t ipvp; /* IRQ vector/priority register */ |
170 | uint32_t ide; /* IRQ destination register */ | |
171 | int type; | |
172 | int last_cpu; | |
611493d9 | 173 | int pending; /* TRUE if IRQ is pending */ |
c227f099 | 174 | } IRQ_src_t; |
dbda808a FB |
175 | |
176 | enum IPVP_bits { | |
177 | IPVP_MASK = 31, | |
178 | IPVP_ACTIVITY = 30, | |
179 | IPVP_MODE = 29, | |
180 | IPVP_POLARITY = 23, | |
181 | IPVP_SENSE = 22, | |
182 | }; | |
183 | #define IPVP_PRIORITY_MASK (0x1F << 16) | |
611493d9 | 184 | #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16)) |
dbda808a FB |
185 | #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1) |
186 | #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK) | |
187 | ||
c227f099 | 188 | typedef struct IRQ_dst_t { |
b7169916 | 189 | uint32_t tfrr; |
dbda808a FB |
190 | uint32_t pctp; /* CPU current task priority */ |
191 | uint32_t pcsr; /* CPU sensitivity register */ | |
c227f099 AL |
192 | IRQ_queue_t raised; |
193 | IRQ_queue_t servicing; | |
e9df014c | 194 | qemu_irq *irqs; |
c227f099 | 195 | } IRQ_dst_t; |
dbda808a | 196 | |
c227f099 | 197 | typedef struct openpic_t { |
dbda808a | 198 | PCIDevice pci_dev; |
23c5e4ca | 199 | MemoryRegion mem; |
71cf9e62 FC |
200 | |
201 | /* Sub-regions */ | |
202 | MemoryRegion sub_io_mem[7]; | |
203 | ||
dbda808a FB |
204 | /* Global registers */ |
205 | uint32_t frep; /* Feature reporting register */ | |
206 | uint32_t glbc; /* Global configuration register */ | |
207 | uint32_t micr; /* MPIC interrupt configuration register */ | |
208 | uint32_t veni; /* Vendor identification register */ | |
e9df014c | 209 | uint32_t pint; /* Processor initialization register */ |
dbda808a FB |
210 | uint32_t spve; /* Spurious vector register */ |
211 | uint32_t tifr; /* Timer frequency reporting register */ | |
212 | /* Source registers */ | |
c227f099 | 213 | IRQ_src_t src[MAX_IRQ]; |
dbda808a | 214 | /* Local registers per output pin */ |
c227f099 | 215 | IRQ_dst_t dst[MAX_CPU]; |
dbda808a FB |
216 | int nb_cpus; |
217 | /* Timer registers */ | |
218 | struct { | |
060fbfe1 AJ |
219 | uint32_t ticc; /* Global timer current count register */ |
220 | uint32_t tibc; /* Global timer base count register */ | |
dbda808a | 221 | } timers[MAX_TMR]; |
e9df014c JM |
222 | /* IRQ out is used when in bypass mode (not implemented) */ |
223 | qemu_irq irq_out; | |
b7169916 AJ |
224 | int max_irq; |
225 | int irq_ipi0; | |
226 | int irq_tim0; | |
b7169916 | 227 | void (*reset) (void *); |
c227f099 AL |
228 | void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *); |
229 | } openpic_t; | |
dbda808a | 230 | |
c227f099 | 231 | static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ) |
dbda808a FB |
232 | { |
233 | set_bit(q->queue, n_IRQ); | |
234 | } | |
235 | ||
c227f099 | 236 | static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ) |
dbda808a FB |
237 | { |
238 | reset_bit(q->queue, n_IRQ); | |
239 | } | |
240 | ||
c227f099 | 241 | static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ) |
dbda808a FB |
242 | { |
243 | return test_bit(q->queue, n_IRQ); | |
244 | } | |
245 | ||
c227f099 | 246 | static void IRQ_check (openpic_t *opp, IRQ_queue_t *q) |
dbda808a FB |
247 | { |
248 | int next, i; | |
249 | int priority; | |
250 | ||
251 | next = -1; | |
252 | priority = -1; | |
b7169916 | 253 | for (i = 0; i < opp->max_irq; i++) { |
060fbfe1 | 254 | if (IRQ_testbit(q, i)) { |
5fafdf24 | 255 | DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n", |
611493d9 | 256 | i, IPVP_PRIORITY(opp->src[i].ipvp), priority); |
060fbfe1 AJ |
257 | if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) { |
258 | next = i; | |
259 | priority = IPVP_PRIORITY(opp->src[i].ipvp); | |
260 | } | |
261 | } | |
dbda808a FB |
262 | } |
263 | q->next = next; | |
264 | q->priority = priority; | |
265 | } | |
266 | ||
c227f099 | 267 | static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q) |
dbda808a FB |
268 | { |
269 | if (q->next == -1) { | |
611493d9 | 270 | /* XXX: optimize */ |
060fbfe1 | 271 | IRQ_check(opp, q); |
dbda808a FB |
272 | } |
273 | ||
274 | return q->next; | |
275 | } | |
276 | ||
c227f099 | 277 | static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ) |
dbda808a | 278 | { |
c227f099 AL |
279 | IRQ_dst_t *dst; |
280 | IRQ_src_t *src; | |
dbda808a FB |
281 | int priority; |
282 | ||
283 | dst = &opp->dst[n_CPU]; | |
284 | src = &opp->src[n_IRQ]; | |
285 | priority = IPVP_PRIORITY(src->ipvp); | |
286 | if (priority <= dst->pctp) { | |
060fbfe1 | 287 | /* Too low priority */ |
e9df014c JM |
288 | DPRINTF("%s: IRQ %d has too low priority on CPU %d\n", |
289 | __func__, n_IRQ, n_CPU); | |
060fbfe1 | 290 | return; |
dbda808a FB |
291 | } |
292 | if (IRQ_testbit(&dst->raised, n_IRQ)) { | |
060fbfe1 | 293 | /* Interrupt miss */ |
e9df014c JM |
294 | DPRINTF("%s: IRQ %d was missed on CPU %d\n", |
295 | __func__, n_IRQ, n_CPU); | |
060fbfe1 | 296 | return; |
dbda808a FB |
297 | } |
298 | set_bit(&src->ipvp, IPVP_ACTIVITY); | |
299 | IRQ_setbit(&dst->raised, n_IRQ); | |
e9df014c JM |
300 | if (priority < dst->raised.priority) { |
301 | /* An higher priority IRQ is already raised */ | |
302 | DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n", | |
303 | __func__, n_IRQ, dst->raised.next, n_CPU); | |
304 | return; | |
305 | } | |
306 | IRQ_get_next(opp, &dst->raised); | |
307 | if (IRQ_get_next(opp, &dst->servicing) != -1 && | |
24865167 | 308 | priority <= dst->servicing.priority) { |
e9df014c JM |
309 | DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n", |
310 | __func__, n_IRQ, dst->servicing.next, n_CPU); | |
311 | /* Already servicing a higher priority IRQ */ | |
312 | return; | |
dbda808a | 313 | } |
e9df014c | 314 | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ); |
b7169916 | 315 | opp->irq_raise(opp, n_CPU, src); |
dbda808a FB |
316 | } |
317 | ||
611493d9 | 318 | /* update pic state because registers for n_IRQ have changed value */ |
c227f099 | 319 | static void openpic_update_irq(openpic_t *opp, int n_IRQ) |
dbda808a | 320 | { |
c227f099 | 321 | IRQ_src_t *src; |
dbda808a FB |
322 | int i; |
323 | ||
324 | src = &opp->src[n_IRQ]; | |
611493d9 FB |
325 | |
326 | if (!src->pending) { | |
327 | /* no irq pending */ | |
e9df014c | 328 | DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ); |
611493d9 FB |
329 | return; |
330 | } | |
331 | if (test_bit(&src->ipvp, IPVP_MASK)) { | |
060fbfe1 | 332 | /* Interrupt source is disabled */ |
e9df014c | 333 | DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ); |
060fbfe1 | 334 | return; |
dbda808a FB |
335 | } |
336 | if (IPVP_PRIORITY(src->ipvp) == 0) { | |
060fbfe1 | 337 | /* Priority set to zero */ |
e9df014c | 338 | DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ); |
060fbfe1 | 339 | return; |
dbda808a | 340 | } |
611493d9 FB |
341 | if (test_bit(&src->ipvp, IPVP_ACTIVITY)) { |
342 | /* IRQ already active */ | |
e9df014c | 343 | DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ); |
611493d9 FB |
344 | return; |
345 | } | |
dbda808a | 346 | if (src->ide == 0x00000000) { |
060fbfe1 | 347 | /* No target */ |
e9df014c | 348 | DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ); |
060fbfe1 | 349 | return; |
dbda808a | 350 | } |
611493d9 | 351 | |
e9df014c JM |
352 | if (src->ide == (1 << src->last_cpu)) { |
353 | /* Only one CPU is allowed to receive this IRQ */ | |
354 | IRQ_local_pipe(opp, src->last_cpu, n_IRQ); | |
355 | } else if (!test_bit(&src->ipvp, IPVP_MODE)) { | |
611493d9 FB |
356 | /* Directed delivery mode */ |
357 | for (i = 0; i < opp->nb_cpus; i++) { | |
358 | if (test_bit(&src->ide, i)) | |
359 | IRQ_local_pipe(opp, i, n_IRQ); | |
360 | } | |
dbda808a | 361 | } else { |
611493d9 | 362 | /* Distributed delivery mode */ |
e9df014c JM |
363 | for (i = src->last_cpu + 1; i != src->last_cpu; i++) { |
364 | if (i == opp->nb_cpus) | |
611493d9 FB |
365 | i = 0; |
366 | if (test_bit(&src->ide, i)) { | |
367 | IRQ_local_pipe(opp, i, n_IRQ); | |
368 | src->last_cpu = i; | |
369 | break; | |
370 | } | |
371 | } | |
372 | } | |
373 | } | |
374 | ||
d537cf6c | 375 | static void openpic_set_irq(void *opaque, int n_IRQ, int level) |
611493d9 | 376 | { |
c227f099 AL |
377 | openpic_t *opp = opaque; |
378 | IRQ_src_t *src; | |
611493d9 FB |
379 | |
380 | src = &opp->src[n_IRQ]; | |
5fafdf24 | 381 | DPRINTF("openpic: set irq %d = %d ipvp=%08x\n", |
611493d9 FB |
382 | n_IRQ, level, src->ipvp); |
383 | if (test_bit(&src->ipvp, IPVP_SENSE)) { | |
384 | /* level-sensitive irq */ | |
385 | src->pending = level; | |
386 | if (!level) | |
387 | reset_bit(&src->ipvp, IPVP_ACTIVITY); | |
388 | } else { | |
389 | /* edge-sensitive irq */ | |
390 | if (level) | |
391 | src->pending = 1; | |
dbda808a | 392 | } |
611493d9 | 393 | openpic_update_irq(opp, n_IRQ); |
dbda808a FB |
394 | } |
395 | ||
67b55785 | 396 | static void openpic_reset (void *opaque) |
dbda808a | 397 | { |
c227f099 | 398 | openpic_t *opp = (openpic_t *)opaque; |
dbda808a FB |
399 | int i; |
400 | ||
401 | opp->glbc = 0x80000000; | |
f8407028 | 402 | /* Initialise controller registers */ |
b7169916 | 403 | opp->frep = ((OPENPIC_EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID; |
dbda808a | 404 | opp->veni = VENI; |
e9df014c | 405 | opp->pint = 0x00000000; |
dbda808a FB |
406 | opp->spve = 0x000000FF; |
407 | opp->tifr = 0x003F7A00; | |
408 | /* ? */ | |
409 | opp->micr = 0x00000000; | |
410 | /* Initialise IRQ sources */ | |
b7169916 | 411 | for (i = 0; i < opp->max_irq; i++) { |
060fbfe1 AJ |
412 | opp->src[i].ipvp = 0xA0000000; |
413 | opp->src[i].ide = 0x00000000; | |
dbda808a FB |
414 | } |
415 | /* Initialise IRQ destinations */ | |
e9df014c | 416 | for (i = 0; i < MAX_CPU; i++) { |
060fbfe1 AJ |
417 | opp->dst[i].pctp = 0x0000000F; |
418 | opp->dst[i].pcsr = 0x00000000; | |
419 | memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t)); | |
d14ed254 | 420 | opp->dst[i].raised.next = -1; |
060fbfe1 | 421 | memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
d14ed254 | 422 | opp->dst[i].servicing.next = -1; |
dbda808a FB |
423 | } |
424 | /* Initialise timers */ | |
425 | for (i = 0; i < MAX_TMR; i++) { | |
060fbfe1 AJ |
426 | opp->timers[i].ticc = 0x00000000; |
427 | opp->timers[i].tibc = 0x80000000; | |
dbda808a | 428 | } |
dbda808a FB |
429 | /* Go out of RESET state */ |
430 | opp->glbc = 0x00000000; | |
431 | } | |
432 | ||
8d3a8c1e | 433 | static inline uint32_t read_IRQreg_ide(openpic_t *opp, int n_IRQ) |
dbda808a | 434 | { |
8d3a8c1e AG |
435 | return opp->src[n_IRQ].ide; |
436 | } | |
dbda808a | 437 | |
8d3a8c1e AG |
438 | static inline uint32_t read_IRQreg_ipvp(openpic_t *opp, int n_IRQ) |
439 | { | |
440 | return opp->src[n_IRQ].ipvp; | |
dbda808a FB |
441 | } |
442 | ||
11de8b71 | 443 | static inline void write_IRQreg_ide(openpic_t *opp, int n_IRQ, uint32_t val) |
dbda808a FB |
444 | { |
445 | uint32_t tmp; | |
446 | ||
11de8b71 AG |
447 | tmp = val & 0xC0000000; |
448 | tmp |= val & ((1ULL << MAX_CPU) - 1); | |
449 | opp->src[n_IRQ].ide = tmp; | |
450 | DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide); | |
451 | } | |
452 | ||
453 | static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val) | |
454 | { | |
455 | /* NOTE: not fully accurate for special IRQs, but simple and sufficient */ | |
456 | /* ACTIVITY bit is read-only */ | |
457 | opp->src[n_IRQ].ipvp = (opp->src[n_IRQ].ipvp & 0x40000000) | |
458 | | (val & 0x800F00FF); | |
459 | openpic_update_irq(opp, n_IRQ); | |
460 | DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", n_IRQ, val, | |
461 | opp->src[n_IRQ].ipvp); | |
dbda808a FB |
462 | } |
463 | ||
b9b2aaa3 AG |
464 | static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, |
465 | unsigned len) | |
dbda808a | 466 | { |
c227f099 AL |
467 | openpic_t *opp = opaque; |
468 | IRQ_dst_t *dst; | |
e9df014c | 469 | int idx; |
dbda808a | 470 | |
0bf9e31a | 471 | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
dbda808a FB |
472 | if (addr & 0xF) |
473 | return; | |
dbda808a | 474 | switch (addr) { |
3e772232 BB |
475 | case 0x00: /* Block Revision Register1 (BRR1) is Readonly */ |
476 | break; | |
704c7e5d AG |
477 | case 0x40: |
478 | case 0x50: | |
479 | case 0x60: | |
480 | case 0x70: | |
481 | case 0x80: | |
482 | case 0x90: | |
483 | case 0xA0: | |
484 | case 0xB0: | |
485 | openpic_cpu_write_internal(opp, addr, val, get_current_cpu()); | |
dbda808a | 486 | break; |
704c7e5d | 487 | case 0x1000: /* FREP */ |
dbda808a | 488 | break; |
704c7e5d | 489 | case 0x1020: /* GLBC */ |
b7169916 AJ |
490 | if (val & 0x80000000 && opp->reset) |
491 | opp->reset(opp); | |
dbda808a | 492 | opp->glbc = val & ~0x80000000; |
060fbfe1 | 493 | break; |
704c7e5d | 494 | case 0x1080: /* VENI */ |
060fbfe1 | 495 | break; |
704c7e5d | 496 | case 0x1090: /* PINT */ |
e9df014c JM |
497 | for (idx = 0; idx < opp->nb_cpus; idx++) { |
498 | if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) { | |
499 | DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx); | |
500 | dst = &opp->dst[idx]; | |
501 | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); | |
502 | } else if (!(val & (1 << idx)) && (opp->pint & (1 << idx))) { | |
503 | DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx); | |
504 | dst = &opp->dst[idx]; | |
505 | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); | |
506 | } | |
dbda808a | 507 | } |
e9df014c | 508 | opp->pint = val; |
060fbfe1 | 509 | break; |
704c7e5d AG |
510 | case 0x10A0: /* IPI_IPVP */ |
511 | case 0x10B0: | |
512 | case 0x10C0: | |
513 | case 0x10D0: | |
dbda808a FB |
514 | { |
515 | int idx; | |
704c7e5d | 516 | idx = (addr - 0x10A0) >> 4; |
11de8b71 | 517 | write_IRQreg_ipvp(opp, opp->irq_ipi0 + idx, val); |
dbda808a FB |
518 | } |
519 | break; | |
704c7e5d | 520 | case 0x10E0: /* SPVE */ |
dbda808a FB |
521 | opp->spve = val & 0x000000FF; |
522 | break; | |
704c7e5d | 523 | case 0x10F0: /* TIFR */ |
dbda808a | 524 | opp->tifr = val; |
060fbfe1 | 525 | break; |
dbda808a FB |
526 | default: |
527 | break; | |
528 | } | |
529 | } | |
530 | ||
b9b2aaa3 | 531 | static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) |
dbda808a | 532 | { |
c227f099 | 533 | openpic_t *opp = opaque; |
dbda808a FB |
534 | uint32_t retval; |
535 | ||
0bf9e31a | 536 | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
dbda808a FB |
537 | retval = 0xFFFFFFFF; |
538 | if (addr & 0xF) | |
539 | return retval; | |
dbda808a | 540 | switch (addr) { |
704c7e5d | 541 | case 0x1000: /* FREP */ |
dbda808a FB |
542 | retval = opp->frep; |
543 | break; | |
704c7e5d | 544 | case 0x1020: /* GLBC */ |
dbda808a | 545 | retval = opp->glbc; |
060fbfe1 | 546 | break; |
704c7e5d | 547 | case 0x1080: /* VENI */ |
dbda808a | 548 | retval = opp->veni; |
060fbfe1 | 549 | break; |
704c7e5d | 550 | case 0x1090: /* PINT */ |
dbda808a | 551 | retval = 0x00000000; |
060fbfe1 | 552 | break; |
3e772232 | 553 | case 0x00: /* Block Revision Register1 (BRR1) */ |
704c7e5d AG |
554 | case 0x40: |
555 | case 0x50: | |
556 | case 0x60: | |
557 | case 0x70: | |
558 | case 0x80: | |
559 | case 0x90: | |
560 | case 0xA0: | |
dbda808a | 561 | case 0xB0: |
704c7e5d AG |
562 | retval = openpic_cpu_read_internal(opp, addr, get_current_cpu()); |
563 | break; | |
564 | case 0x10A0: /* IPI_IPVP */ | |
565 | case 0x10B0: | |
566 | case 0x10C0: | |
567 | case 0x10D0: | |
dbda808a FB |
568 | { |
569 | int idx; | |
704c7e5d | 570 | idx = (addr - 0x10A0) >> 4; |
8d3a8c1e | 571 | retval = read_IRQreg_ipvp(opp, opp->irq_ipi0 + idx); |
dbda808a | 572 | } |
060fbfe1 | 573 | break; |
704c7e5d | 574 | case 0x10E0: /* SPVE */ |
dbda808a FB |
575 | retval = opp->spve; |
576 | break; | |
704c7e5d | 577 | case 0x10F0: /* TIFR */ |
dbda808a | 578 | retval = opp->tifr; |
060fbfe1 | 579 | break; |
dbda808a FB |
580 | default: |
581 | break; | |
582 | } | |
583 | DPRINTF("%s: => %08x\n", __func__, retval); | |
dbda808a FB |
584 | |
585 | return retval; | |
586 | } | |
587 | ||
b9b2aaa3 AG |
588 | static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val, |
589 | unsigned len) | |
dbda808a | 590 | { |
c227f099 | 591 | openpic_t *opp = opaque; |
dbda808a FB |
592 | int idx; |
593 | ||
594 | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val); | |
595 | if (addr & 0xF) | |
596 | return; | |
38ae51a8 | 597 | addr -= 0x10; |
dbda808a FB |
598 | addr &= 0xFFFF; |
599 | idx = (addr & 0xFFF0) >> 6; | |
600 | addr = addr & 0x30; | |
601 | switch (addr) { | |
602 | case 0x00: /* TICC */ | |
603 | break; | |
604 | case 0x10: /* TIBC */ | |
060fbfe1 AJ |
605 | if ((opp->timers[idx].ticc & 0x80000000) != 0 && |
606 | (val & 0x80000000) == 0 && | |
dbda808a | 607 | (opp->timers[idx].tibc & 0x80000000) != 0) |
060fbfe1 AJ |
608 | opp->timers[idx].ticc &= ~0x80000000; |
609 | opp->timers[idx].tibc = val; | |
610 | break; | |
dbda808a | 611 | case 0x20: /* TIVP */ |
11de8b71 | 612 | write_IRQreg_ipvp(opp, opp->irq_tim0 + idx, val); |
060fbfe1 | 613 | break; |
dbda808a | 614 | case 0x30: /* TIDE */ |
11de8b71 | 615 | write_IRQreg_ide(opp, opp->irq_tim0 + idx, val); |
060fbfe1 | 616 | break; |
dbda808a FB |
617 | } |
618 | } | |
619 | ||
b9b2aaa3 | 620 | static uint64_t openpic_timer_read(void *opaque, hwaddr addr, unsigned len) |
dbda808a | 621 | { |
c227f099 | 622 | openpic_t *opp = opaque; |
dbda808a FB |
623 | uint32_t retval; |
624 | int idx; | |
625 | ||
626 | DPRINTF("%s: addr %08x\n", __func__, addr); | |
627 | retval = 0xFFFFFFFF; | |
628 | if (addr & 0xF) | |
629 | return retval; | |
38ae51a8 | 630 | addr -= 0x10; |
dbda808a FB |
631 | addr &= 0xFFFF; |
632 | idx = (addr & 0xFFF0) >> 6; | |
633 | addr = addr & 0x30; | |
634 | switch (addr) { | |
635 | case 0x00: /* TICC */ | |
060fbfe1 | 636 | retval = opp->timers[idx].ticc; |
dbda808a FB |
637 | break; |
638 | case 0x10: /* TIBC */ | |
060fbfe1 AJ |
639 | retval = opp->timers[idx].tibc; |
640 | break; | |
dbda808a | 641 | case 0x20: /* TIPV */ |
8d3a8c1e | 642 | retval = read_IRQreg_ipvp(opp, opp->irq_tim0 + idx); |
060fbfe1 | 643 | break; |
dbda808a | 644 | case 0x30: /* TIDE */ |
8d3a8c1e | 645 | retval = read_IRQreg_ide(opp, opp->irq_tim0 + idx); |
060fbfe1 | 646 | break; |
dbda808a FB |
647 | } |
648 | DPRINTF("%s: => %08x\n", __func__, retval); | |
dbda808a FB |
649 | |
650 | return retval; | |
651 | } | |
652 | ||
b9b2aaa3 AG |
653 | static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val, |
654 | unsigned len) | |
dbda808a | 655 | { |
c227f099 | 656 | openpic_t *opp = opaque; |
dbda808a FB |
657 | int idx; |
658 | ||
659 | DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val); | |
660 | if (addr & 0xF) | |
661 | return; | |
dbda808a FB |
662 | addr = addr & 0xFFF0; |
663 | idx = addr >> 5; | |
664 | if (addr & 0x10) { | |
665 | /* EXDE / IFEDE / IEEDE */ | |
11de8b71 | 666 | write_IRQreg_ide(opp, idx, val); |
dbda808a FB |
667 | } else { |
668 | /* EXVP / IFEVP / IEEVP */ | |
11de8b71 | 669 | write_IRQreg_ipvp(opp, idx, val); |
dbda808a FB |
670 | } |
671 | } | |
672 | ||
b9b2aaa3 | 673 | static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) |
dbda808a | 674 | { |
c227f099 | 675 | openpic_t *opp = opaque; |
dbda808a FB |
676 | uint32_t retval; |
677 | int idx; | |
678 | ||
679 | DPRINTF("%s: addr %08x\n", __func__, addr); | |
680 | retval = 0xFFFFFFFF; | |
681 | if (addr & 0xF) | |
682 | return retval; | |
683 | addr = addr & 0xFFF0; | |
684 | idx = addr >> 5; | |
685 | if (addr & 0x10) { | |
686 | /* EXDE / IFEDE / IEEDE */ | |
8d3a8c1e | 687 | retval = read_IRQreg_ide(opp, idx); |
dbda808a FB |
688 | } else { |
689 | /* EXVP / IFEVP / IEEVP */ | |
8d3a8c1e | 690 | retval = read_IRQreg_ipvp(opp, idx); |
dbda808a FB |
691 | } |
692 | DPRINTF("%s: => %08x\n", __func__, retval); | |
dbda808a FB |
693 | |
694 | return retval; | |
695 | } | |
696 | ||
a8170e5e | 697 | static void openpic_cpu_write_internal(void *opaque, hwaddr addr, |
704c7e5d | 698 | uint32_t val, int idx) |
dbda808a | 699 | { |
c227f099 AL |
700 | openpic_t *opp = opaque; |
701 | IRQ_src_t *src; | |
702 | IRQ_dst_t *dst; | |
704c7e5d | 703 | int s_IRQ, n_IRQ; |
dbda808a | 704 | |
704c7e5d AG |
705 | DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx, |
706 | addr, val); | |
dbda808a FB |
707 | if (addr & 0xF) |
708 | return; | |
dbda808a FB |
709 | dst = &opp->dst[idx]; |
710 | addr &= 0xFF0; | |
711 | switch (addr) { | |
704c7e5d | 712 | case 0x40: /* IPIDR */ |
dbda808a FB |
713 | case 0x50: |
714 | case 0x60: | |
715 | case 0x70: | |
716 | idx = (addr - 0x40) >> 4; | |
a675155e | 717 | /* we use IDE as mask which CPUs to deliver the IPI to still. */ |
11de8b71 AG |
718 | write_IRQreg_ide(opp, opp->irq_ipi0 + idx, |
719 | opp->src[opp->irq_ipi0 + idx].ide | val); | |
b7169916 AJ |
720 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 1); |
721 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 0); | |
dbda808a | 722 | break; |
dbda808a | 723 | case 0x80: /* PCTP */ |
060fbfe1 AJ |
724 | dst->pctp = val & 0x0000000F; |
725 | break; | |
dbda808a | 726 | case 0x90: /* WHOAMI */ |
060fbfe1 AJ |
727 | /* Read-only register */ |
728 | break; | |
dbda808a | 729 | case 0xA0: /* PIAC */ |
060fbfe1 AJ |
730 | /* Read-only register */ |
731 | break; | |
dbda808a FB |
732 | case 0xB0: /* PEOI */ |
733 | DPRINTF("PEOI\n"); | |
060fbfe1 AJ |
734 | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
735 | IRQ_resetbit(&dst->servicing, s_IRQ); | |
736 | dst->servicing.next = -1; | |
737 | /* Set up next servicing IRQ */ | |
738 | s_IRQ = IRQ_get_next(opp, &dst->servicing); | |
e9df014c JM |
739 | /* Check queued interrupts. */ |
740 | n_IRQ = IRQ_get_next(opp, &dst->raised); | |
741 | src = &opp->src[n_IRQ]; | |
742 | if (n_IRQ != -1 && | |
743 | (s_IRQ == -1 || | |
744 | IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) { | |
745 | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", | |
746 | idx, n_IRQ); | |
b7169916 | 747 | opp->irq_raise(opp, idx, src); |
e9df014c | 748 | } |
060fbfe1 | 749 | break; |
dbda808a FB |
750 | default: |
751 | break; | |
752 | } | |
753 | } | |
754 | ||
b9b2aaa3 AG |
755 | static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val, |
756 | unsigned len) | |
704c7e5d AG |
757 | { |
758 | openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12); | |
759 | } | |
760 | ||
a8170e5e | 761 | static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, |
704c7e5d | 762 | int idx) |
dbda808a | 763 | { |
c227f099 AL |
764 | openpic_t *opp = opaque; |
765 | IRQ_src_t *src; | |
766 | IRQ_dst_t *dst; | |
dbda808a | 767 | uint32_t retval; |
704c7e5d | 768 | int n_IRQ; |
3b46e624 | 769 | |
704c7e5d | 770 | DPRINTF("%s: cpu %d addr " TARGET_FMT_plx "\n", __func__, idx, addr); |
dbda808a FB |
771 | retval = 0xFFFFFFFF; |
772 | if (addr & 0xF) | |
773 | return retval; | |
dbda808a FB |
774 | dst = &opp->dst[idx]; |
775 | addr &= 0xFF0; | |
776 | switch (addr) { | |
3e772232 BB |
777 | case 0x00: /* Block Revision Register1 (BRR1) */ |
778 | retval = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN; | |
779 | break; | |
dbda808a | 780 | case 0x80: /* PCTP */ |
060fbfe1 AJ |
781 | retval = dst->pctp; |
782 | break; | |
dbda808a | 783 | case 0x90: /* WHOAMI */ |
060fbfe1 AJ |
784 | retval = idx; |
785 | break; | |
dbda808a | 786 | case 0xA0: /* PIAC */ |
e9df014c JM |
787 | DPRINTF("Lower OpenPIC INT output\n"); |
788 | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); | |
060fbfe1 | 789 | n_IRQ = IRQ_get_next(opp, &dst->raised); |
dbda808a | 790 | DPRINTF("PIAC: irq=%d\n", n_IRQ); |
060fbfe1 AJ |
791 | if (n_IRQ == -1) { |
792 | /* No more interrupt pending */ | |
e9df014c | 793 | retval = IPVP_VECTOR(opp->spve); |
060fbfe1 AJ |
794 | } else { |
795 | src = &opp->src[n_IRQ]; | |
796 | if (!test_bit(&src->ipvp, IPVP_ACTIVITY) || | |
797 | !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) { | |
798 | /* - Spurious level-sensitive IRQ | |
799 | * - Priorities has been changed | |
800 | * and the pending IRQ isn't allowed anymore | |
801 | */ | |
802 | reset_bit(&src->ipvp, IPVP_ACTIVITY); | |
803 | retval = IPVP_VECTOR(opp->spve); | |
804 | } else { | |
805 | /* IRQ enter servicing state */ | |
806 | IRQ_setbit(&dst->servicing, n_IRQ); | |
807 | retval = IPVP_VECTOR(src->ipvp); | |
808 | } | |
809 | IRQ_resetbit(&dst->raised, n_IRQ); | |
810 | dst->raised.next = -1; | |
811 | if (!test_bit(&src->ipvp, IPVP_SENSE)) { | |
611493d9 | 812 | /* edge-sensitive IRQ */ |
060fbfe1 | 813 | reset_bit(&src->ipvp, IPVP_ACTIVITY); |
611493d9 FB |
814 | src->pending = 0; |
815 | } | |
a675155e AG |
816 | |
817 | if ((n_IRQ >= opp->irq_ipi0) && (n_IRQ < (opp->irq_ipi0 + MAX_IPI))) { | |
818 | src->ide &= ~(1 << idx); | |
819 | if (src->ide && !test_bit(&src->ipvp, IPVP_SENSE)) { | |
820 | /* trigger on CPUs that didn't know about it yet */ | |
821 | openpic_set_irq(opp, n_IRQ, 1); | |
822 | openpic_set_irq(opp, n_IRQ, 0); | |
823 | /* if all CPUs knew about it, set active bit again */ | |
824 | set_bit(&src->ipvp, IPVP_ACTIVITY); | |
825 | } | |
826 | } | |
060fbfe1 AJ |
827 | } |
828 | break; | |
dbda808a | 829 | case 0xB0: /* PEOI */ |
060fbfe1 AJ |
830 | retval = 0; |
831 | break; | |
dbda808a FB |
832 | default: |
833 | break; | |
834 | } | |
835 | DPRINTF("%s: => %08x\n", __func__, retval); | |
dbda808a FB |
836 | |
837 | return retval; | |
838 | } | |
839 | ||
b9b2aaa3 | 840 | static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len) |
704c7e5d AG |
841 | { |
842 | return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12); | |
843 | } | |
844 | ||
b9b2aaa3 AG |
845 | static void openpic_write(void *opaque, hwaddr addr, uint64_t val, |
846 | unsigned len) | |
dbda808a | 847 | { |
c227f099 | 848 | openpic_t *opp = opaque; |
dbda808a | 849 | |
611493d9 | 850 | DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val); |
dbda808a FB |
851 | if (addr < 0x1100) { |
852 | /* Global registers */ | |
b9b2aaa3 | 853 | openpic_gbl_write(opp, addr, val, len); |
dbda808a FB |
854 | } else if (addr < 0x10000) { |
855 | /* Timers registers */ | |
b9b2aaa3 | 856 | openpic_timer_write(opp, addr, val, len); |
dbda808a FB |
857 | } else if (addr < 0x20000) { |
858 | /* Source registers */ | |
b9b2aaa3 | 859 | openpic_src_write(opp, addr, val, len); |
dbda808a FB |
860 | } else { |
861 | /* CPU registers */ | |
b9b2aaa3 | 862 | openpic_cpu_write(opp, addr, val, len); |
dbda808a FB |
863 | } |
864 | } | |
865 | ||
b9b2aaa3 | 866 | static uint64_t openpic_read(void *opaque, hwaddr addr, unsigned len) |
dbda808a | 867 | { |
c227f099 | 868 | openpic_t *opp = opaque; |
dbda808a FB |
869 | uint32_t retval; |
870 | ||
611493d9 | 871 | DPRINTF("%s: offset %08x\n", __func__, (int)addr); |
dbda808a FB |
872 | if (addr < 0x1100) { |
873 | /* Global registers */ | |
b9b2aaa3 | 874 | retval = openpic_gbl_read(opp, addr, len); |
dbda808a FB |
875 | } else if (addr < 0x10000) { |
876 | /* Timers registers */ | |
b9b2aaa3 | 877 | retval = openpic_timer_read(opp, addr, len); |
dbda808a FB |
878 | } else if (addr < 0x20000) { |
879 | /* Source registers */ | |
b9b2aaa3 | 880 | retval = openpic_src_read(opp, addr, len); |
dbda808a FB |
881 | } else { |
882 | /* CPU registers */ | |
b9b2aaa3 | 883 | retval = openpic_cpu_read(opp, addr, len); |
dbda808a FB |
884 | } |
885 | ||
886 | return retval; | |
887 | } | |
888 | ||
23c5e4ca AK |
889 | static const MemoryRegionOps openpic_ops = { |
890 | .read = openpic_read, | |
891 | .write = openpic_write, | |
892 | .endianness = DEVICE_LITTLE_ENDIAN, | |
b9b2aaa3 AG |
893 | .impl = { |
894 | .min_access_size = 4, | |
895 | .max_access_size = 4, | |
896 | }, | |
23c5e4ca AK |
897 | }; |
898 | ||
c227f099 | 899 | static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) |
67b55785 BS |
900 | { |
901 | unsigned int i; | |
902 | ||
903 | for (i = 0; i < BF_WIDTH(MAX_IRQ); i++) | |
904 | qemu_put_be32s(f, &q->queue[i]); | |
905 | ||
906 | qemu_put_sbe32s(f, &q->next); | |
907 | qemu_put_sbe32s(f, &q->priority); | |
908 | } | |
909 | ||
910 | static void openpic_save(QEMUFile* f, void *opaque) | |
911 | { | |
c227f099 | 912 | openpic_t *opp = (openpic_t *)opaque; |
67b55785 BS |
913 | unsigned int i; |
914 | ||
915 | qemu_put_be32s(f, &opp->frep); | |
916 | qemu_put_be32s(f, &opp->glbc); | |
917 | qemu_put_be32s(f, &opp->micr); | |
918 | qemu_put_be32s(f, &opp->veni); | |
919 | qemu_put_be32s(f, &opp->pint); | |
920 | qemu_put_be32s(f, &opp->spve); | |
921 | qemu_put_be32s(f, &opp->tifr); | |
922 | ||
b7169916 | 923 | for (i = 0; i < opp->max_irq; i++) { |
67b55785 BS |
924 | qemu_put_be32s(f, &opp->src[i].ipvp); |
925 | qemu_put_be32s(f, &opp->src[i].ide); | |
926 | qemu_put_sbe32s(f, &opp->src[i].type); | |
927 | qemu_put_sbe32s(f, &opp->src[i].last_cpu); | |
928 | qemu_put_sbe32s(f, &opp->src[i].pending); | |
929 | } | |
930 | ||
b7169916 AJ |
931 | qemu_put_sbe32s(f, &opp->nb_cpus); |
932 | ||
933 | for (i = 0; i < opp->nb_cpus; i++) { | |
934 | qemu_put_be32s(f, &opp->dst[i].tfrr); | |
67b55785 BS |
935 | qemu_put_be32s(f, &opp->dst[i].pctp); |
936 | qemu_put_be32s(f, &opp->dst[i].pcsr); | |
937 | openpic_save_IRQ_queue(f, &opp->dst[i].raised); | |
938 | openpic_save_IRQ_queue(f, &opp->dst[i].servicing); | |
939 | } | |
940 | ||
67b55785 BS |
941 | for (i = 0; i < MAX_TMR; i++) { |
942 | qemu_put_be32s(f, &opp->timers[i].ticc); | |
943 | qemu_put_be32s(f, &opp->timers[i].tibc); | |
944 | } | |
945 | ||
67b55785 BS |
946 | pci_device_save(&opp->pci_dev, f); |
947 | } | |
948 | ||
c227f099 | 949 | static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q) |
67b55785 BS |
950 | { |
951 | unsigned int i; | |
952 | ||
953 | for (i = 0; i < BF_WIDTH(MAX_IRQ); i++) | |
954 | qemu_get_be32s(f, &q->queue[i]); | |
955 | ||
956 | qemu_get_sbe32s(f, &q->next); | |
957 | qemu_get_sbe32s(f, &q->priority); | |
958 | } | |
959 | ||
960 | static int openpic_load(QEMUFile* f, void *opaque, int version_id) | |
961 | { | |
c227f099 | 962 | openpic_t *opp = (openpic_t *)opaque; |
67b55785 BS |
963 | unsigned int i; |
964 | ||
965 | if (version_id != 1) | |
966 | return -EINVAL; | |
967 | ||
968 | qemu_get_be32s(f, &opp->frep); | |
969 | qemu_get_be32s(f, &opp->glbc); | |
970 | qemu_get_be32s(f, &opp->micr); | |
971 | qemu_get_be32s(f, &opp->veni); | |
972 | qemu_get_be32s(f, &opp->pint); | |
973 | qemu_get_be32s(f, &opp->spve); | |
974 | qemu_get_be32s(f, &opp->tifr); | |
975 | ||
b7169916 | 976 | for (i = 0; i < opp->max_irq; i++) { |
67b55785 BS |
977 | qemu_get_be32s(f, &opp->src[i].ipvp); |
978 | qemu_get_be32s(f, &opp->src[i].ide); | |
979 | qemu_get_sbe32s(f, &opp->src[i].type); | |
980 | qemu_get_sbe32s(f, &opp->src[i].last_cpu); | |
981 | qemu_get_sbe32s(f, &opp->src[i].pending); | |
982 | } | |
983 | ||
b7169916 AJ |
984 | qemu_get_sbe32s(f, &opp->nb_cpus); |
985 | ||
986 | for (i = 0; i < opp->nb_cpus; i++) { | |
987 | qemu_get_be32s(f, &opp->dst[i].tfrr); | |
67b55785 BS |
988 | qemu_get_be32s(f, &opp->dst[i].pctp); |
989 | qemu_get_be32s(f, &opp->dst[i].pcsr); | |
990 | openpic_load_IRQ_queue(f, &opp->dst[i].raised); | |
991 | openpic_load_IRQ_queue(f, &opp->dst[i].servicing); | |
992 | } | |
993 | ||
67b55785 BS |
994 | for (i = 0; i < MAX_TMR; i++) { |
995 | qemu_get_be32s(f, &opp->timers[i].ticc); | |
996 | qemu_get_be32s(f, &opp->timers[i].tibc); | |
997 | } | |
998 | ||
67b55785 BS |
999 | return pci_device_load(&opp->pci_dev, f); |
1000 | } | |
1001 | ||
c227f099 | 1002 | static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src) |
b7169916 AJ |
1003 | { |
1004 | qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); | |
1005 | } | |
1006 | ||
8a5faa1d | 1007 | qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus, |
e9df014c | 1008 | qemu_irq **irqs, qemu_irq irq_out) |
dbda808a | 1009 | { |
c227f099 | 1010 | openpic_t *opp; |
dbda808a | 1011 | int i, m; |
3b46e624 | 1012 | |
dbda808a FB |
1013 | /* XXX: for now, only one CPU is supported */ |
1014 | if (nb_cpus != 1) | |
1015 | return NULL; | |
8a5faa1d AL |
1016 | opp = g_malloc0(sizeof(openpic_t)); |
1017 | memory_region_init_io(&opp->mem, &openpic_ops, opp, "openpic", 0x40000); | |
3b46e624 | 1018 | |
91d848eb | 1019 | // isu_base &= 0xFFFC0000; |
dbda808a | 1020 | opp->nb_cpus = nb_cpus; |
b7169916 AJ |
1021 | opp->max_irq = OPENPIC_MAX_IRQ; |
1022 | opp->irq_ipi0 = OPENPIC_IRQ_IPI0; | |
1023 | opp->irq_tim0 = OPENPIC_IRQ_TIM0; | |
dbda808a | 1024 | /* Set IRQ types */ |
b7169916 | 1025 | for (i = 0; i < OPENPIC_EXT_IRQ; i++) { |
dbda808a FB |
1026 | opp->src[i].type = IRQ_EXTERNAL; |
1027 | } | |
b7169916 | 1028 | for (; i < OPENPIC_IRQ_TIM0; i++) { |
dbda808a FB |
1029 | opp->src[i].type = IRQ_SPECIAL; |
1030 | } | |
b7169916 | 1031 | m = OPENPIC_IRQ_IPI0; |
dbda808a FB |
1032 | for (; i < m; i++) { |
1033 | opp->src[i].type = IRQ_TIMER; | |
1034 | } | |
b7169916 | 1035 | for (; i < OPENPIC_MAX_IRQ; i++) { |
dbda808a FB |
1036 | opp->src[i].type = IRQ_INTERNAL; |
1037 | } | |
7668a27f | 1038 | for (i = 0; i < nb_cpus; i++) |
e9df014c JM |
1039 | opp->dst[i].irqs = irqs[i]; |
1040 | opp->irq_out = irq_out; | |
67b55785 | 1041 | |
0be71e32 AW |
1042 | register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2, |
1043 | openpic_save, openpic_load, opp); | |
a08d4367 | 1044 | qemu_register_reset(openpic_reset, opp); |
b7169916 AJ |
1045 | |
1046 | opp->irq_raise = openpic_irq_raise; | |
1047 | opp->reset = openpic_reset; | |
1048 | ||
23c5e4ca AK |
1049 | if (pmem) |
1050 | *pmem = &opp->mem; | |
e9df014c | 1051 | |
b7169916 AJ |
1052 | return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq); |
1053 | } | |
1054 | ||
c227f099 | 1055 | static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src) |
b7169916 AJ |
1056 | { |
1057 | int n_ci = IDR_CI0 - n_CPU; | |
0bf9e31a | 1058 | |
b7169916 AJ |
1059 | if(test_bit(&src->ide, n_ci)) { |
1060 | qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]); | |
1061 | } | |
1062 | else { | |
1063 | qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | static void mpic_reset (void *opaque) | |
1068 | { | |
c227f099 | 1069 | openpic_t *mpp = (openpic_t *)opaque; |
b7169916 AJ |
1070 | int i; |
1071 | ||
1072 | mpp->glbc = 0x80000000; | |
1073 | /* Initialise controller registers */ | |
bbc58422 | 1074 | mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1) << 8); |
b7169916 AJ |
1075 | mpp->veni = VENI; |
1076 | mpp->pint = 0x00000000; | |
1077 | mpp->spve = 0x0000FFFF; | |
1078 | /* Initialise IRQ sources */ | |
1079 | for (i = 0; i < mpp->max_irq; i++) { | |
1080 | mpp->src[i].ipvp = 0x80800000; | |
1081 | mpp->src[i].ide = 0x00000001; | |
1082 | } | |
9250fd24 AG |
1083 | /* Set IDE for IPIs to 0 so we don't get spurious interrupts */ |
1084 | for (i = mpp->irq_ipi0; i < (mpp->irq_ipi0 + MAX_IPI); i++) { | |
1085 | mpp->src[i].ide = 0; | |
1086 | } | |
b7169916 AJ |
1087 | /* Initialise IRQ destinations */ |
1088 | for (i = 0; i < MAX_CPU; i++) { | |
1089 | mpp->dst[i].pctp = 0x0000000F; | |
1090 | mpp->dst[i].tfrr = 0x00000000; | |
c227f099 | 1091 | memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t)); |
b7169916 | 1092 | mpp->dst[i].raised.next = -1; |
c227f099 | 1093 | memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
b7169916 AJ |
1094 | mpp->dst[i].servicing.next = -1; |
1095 | } | |
1096 | /* Initialise timers */ | |
1097 | for (i = 0; i < MAX_TMR; i++) { | |
1098 | mpp->timers[i].ticc = 0x00000000; | |
1099 | mpp->timers[i].tibc = 0x80000000; | |
1100 | } | |
1101 | /* Go out of RESET state */ | |
1102 | mpp->glbc = 0x00000000; | |
1103 | } | |
1104 | ||
b9b2aaa3 AG |
1105 | static void mpic_timer_write(void *opaque, hwaddr addr, uint64_t val, |
1106 | unsigned len) | |
b7169916 | 1107 | { |
c227f099 | 1108 | openpic_t *mpp = opaque; |
b7169916 AJ |
1109 | int idx, cpu; |
1110 | ||
0bf9e31a | 1111 | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val); |
b7169916 AJ |
1112 | if (addr & 0xF) |
1113 | return; | |
b7169916 AJ |
1114 | cpu = addr >> 12; |
1115 | idx = (addr >> 6) & 0x3; | |
1116 | switch (addr & 0x30) { | |
1117 | case 0x00: /* gtccr */ | |
1118 | break; | |
1119 | case 0x10: /* gtbcr */ | |
1120 | if ((mpp->timers[idx].ticc & 0x80000000) != 0 && | |
1121 | (val & 0x80000000) == 0 && | |
1122 | (mpp->timers[idx].tibc & 0x80000000) != 0) | |
1123 | mpp->timers[idx].ticc &= ~0x80000000; | |
1124 | mpp->timers[idx].tibc = val; | |
1125 | break; | |
1126 | case 0x20: /* GTIVPR */ | |
11de8b71 | 1127 | write_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx, val); |
b7169916 AJ |
1128 | break; |
1129 | case 0x30: /* GTIDR & TFRR */ | |
1130 | if ((addr & 0xF0) == 0xF0) | |
1131 | mpp->dst[cpu].tfrr = val; | |
1132 | else | |
11de8b71 | 1133 | write_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx, val); |
b7169916 AJ |
1134 | break; |
1135 | } | |
1136 | } | |
1137 | ||
b9b2aaa3 | 1138 | static uint64_t mpic_timer_read(void *opaque, hwaddr addr, unsigned len) |
b7169916 | 1139 | { |
c227f099 | 1140 | openpic_t *mpp = opaque; |
b7169916 AJ |
1141 | uint32_t retval; |
1142 | int idx, cpu; | |
1143 | ||
0bf9e31a | 1144 | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
b7169916 AJ |
1145 | retval = 0xFFFFFFFF; |
1146 | if (addr & 0xF) | |
1147 | return retval; | |
b7169916 AJ |
1148 | cpu = addr >> 12; |
1149 | idx = (addr >> 6) & 0x3; | |
1150 | switch (addr & 0x30) { | |
1151 | case 0x00: /* gtccr */ | |
1152 | retval = mpp->timers[idx].ticc; | |
1153 | break; | |
1154 | case 0x10: /* gtbcr */ | |
1155 | retval = mpp->timers[idx].tibc; | |
1156 | break; | |
1157 | case 0x20: /* TIPV */ | |
8d3a8c1e | 1158 | retval = read_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx); |
b7169916 AJ |
1159 | break; |
1160 | case 0x30: /* TIDR */ | |
1161 | if ((addr &0xF0) == 0XF0) | |
1162 | retval = mpp->dst[cpu].tfrr; | |
1163 | else | |
8d3a8c1e | 1164 | retval = read_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx); |
b7169916 AJ |
1165 | break; |
1166 | } | |
1167 | DPRINTF("%s: => %08x\n", __func__, retval); | |
1168 | ||
1169 | return retval; | |
1170 | } | |
1171 | ||
cdbb912a AG |
1172 | static void mpic_src_irq_write(void *opaque, hwaddr addr, |
1173 | uint64_t val, unsigned len) | |
b7169916 | 1174 | { |
c227f099 | 1175 | openpic_t *mpp = opaque; |
cdbb912a | 1176 | int idx = addr / 0x20; |
b7169916 | 1177 | |
cdbb912a AG |
1178 | DPRINTF("%s: addr " TARGET_FMT_plx " <= %08" PRIx64 "\n", |
1179 | __func__, addr, val); | |
b7169916 AJ |
1180 | if (addr & 0xF) |
1181 | return; | |
1182 | ||
cdbb912a AG |
1183 | if (addr & 0x10) { |
1184 | /* EXDE / IFEDE / IEEDE */ | |
1185 | write_IRQreg_ide(mpp, idx, val); | |
1186 | } else { | |
1187 | /* EXVP / IFEVP / IEEVP */ | |
1188 | write_IRQreg_ipvp(mpp, idx, val); | |
b7169916 | 1189 | } |
b7169916 AJ |
1190 | } |
1191 | ||
cdbb912a | 1192 | static uint64_t mpic_src_irq_read(void *opaque, hwaddr addr, unsigned len) |
b7169916 | 1193 | { |
c227f099 | 1194 | openpic_t *mpp = opaque; |
b7169916 | 1195 | uint32_t retval; |
cdbb912a | 1196 | int idx = addr / 0x20; |
b7169916 | 1197 | |
0bf9e31a | 1198 | DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr); |
b7169916 | 1199 | if (addr & 0xF) |
cdbb912a | 1200 | return -1; |
b7169916 | 1201 | |
cdbb912a AG |
1202 | if (addr & 0x10) { |
1203 | /* EXDE / IFEDE / IEEDE */ | |
1204 | retval = read_IRQreg_ide(mpp, idx); | |
1205 | } else { | |
1206 | /* EXVP / IFEVP / IEEVP */ | |
1207 | retval = read_IRQreg_ipvp(mpp, idx); | |
b7169916 | 1208 | } |
cdbb912a | 1209 | DPRINTF("%s: => %08x\n", __func__, retval); |
b7169916 AJ |
1210 | |
1211 | return retval; | |
1212 | } | |
1213 | ||
71cf9e62 | 1214 | static const MemoryRegionOps mpic_glb_ops = { |
b9b2aaa3 AG |
1215 | .write = openpic_gbl_write, |
1216 | .read = openpic_gbl_read, | |
71cf9e62 | 1217 | .endianness = DEVICE_BIG_ENDIAN, |
b9b2aaa3 AG |
1218 | .impl = { |
1219 | .min_access_size = 4, | |
1220 | .max_access_size = 4, | |
1221 | }, | |
b7169916 AJ |
1222 | }; |
1223 | ||
71cf9e62 | 1224 | static const MemoryRegionOps mpic_tmr_ops = { |
b9b2aaa3 AG |
1225 | .write = mpic_timer_write, |
1226 | .read = mpic_timer_read, | |
71cf9e62 | 1227 | .endianness = DEVICE_BIG_ENDIAN, |
b9b2aaa3 AG |
1228 | .impl = { |
1229 | .min_access_size = 4, | |
1230 | .max_access_size = 4, | |
1231 | }, | |
b7169916 AJ |
1232 | }; |
1233 | ||
71cf9e62 | 1234 | static const MemoryRegionOps mpic_cpu_ops = { |
b9b2aaa3 AG |
1235 | .write = openpic_cpu_write, |
1236 | .read = openpic_cpu_read, | |
71cf9e62 | 1237 | .endianness = DEVICE_BIG_ENDIAN, |
b9b2aaa3 AG |
1238 | .impl = { |
1239 | .min_access_size = 4, | |
1240 | .max_access_size = 4, | |
1241 | }, | |
b7169916 AJ |
1242 | }; |
1243 | ||
cdbb912a AG |
1244 | static const MemoryRegionOps mpic_irq_ops = { |
1245 | .write = mpic_src_irq_write, | |
1246 | .read = mpic_src_irq_read, | |
71cf9e62 | 1247 | .endianness = DEVICE_BIG_ENDIAN, |
cdbb912a AG |
1248 | .impl = { |
1249 | .min_access_size = 4, | |
1250 | .max_access_size = 4, | |
71cf9e62 | 1251 | }, |
b7169916 AJ |
1252 | }; |
1253 | ||
a8170e5e | 1254 | qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base, |
71cf9e62 | 1255 | int nb_cpus, qemu_irq **irqs, qemu_irq irq_out) |
b7169916 | 1256 | { |
71cf9e62 FC |
1257 | openpic_t *mpp; |
1258 | int i; | |
b7169916 | 1259 | struct { |
71cf9e62 FC |
1260 | const char *name; |
1261 | MemoryRegionOps const *ops; | |
a8170e5e | 1262 | hwaddr start_addr; |
71cf9e62 | 1263 | ram_addr_t size; |
dfebf62b | 1264 | } const list[] = { |
71cf9e62 FC |
1265 | {"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE}, |
1266 | {"tmr", &mpic_tmr_ops, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE}, | |
cdbb912a | 1267 | {"irq", &mpic_irq_ops, MPIC_IRQ_REG_START, MPIC_IRQ_REG_SIZE}, |
71cf9e62 | 1268 | {"cpu", &mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE}, |
b7169916 AJ |
1269 | }; |
1270 | ||
7267c094 | 1271 | mpp = g_malloc0(sizeof(openpic_t)); |
b7169916 | 1272 | |
71cf9e62 FC |
1273 | memory_region_init(&mpp->mem, "mpic", 0x40000); |
1274 | memory_region_add_subregion(address_space, base, &mpp->mem); | |
1275 | ||
b7169916 | 1276 | for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) { |
b7169916 | 1277 | |
71cf9e62 FC |
1278 | memory_region_init_io(&mpp->sub_io_mem[i], list[i].ops, mpp, |
1279 | list[i].name, list[i].size); | |
1280 | ||
1281 | memory_region_add_subregion(&mpp->mem, list[i].start_addr, | |
1282 | &mpp->sub_io_mem[i]); | |
b7169916 AJ |
1283 | } |
1284 | ||
1285 | mpp->nb_cpus = nb_cpus; | |
1286 | mpp->max_irq = MPIC_MAX_IRQ; | |
1287 | mpp->irq_ipi0 = MPIC_IPI_IRQ; | |
1288 | mpp->irq_tim0 = MPIC_TMR_IRQ; | |
1289 | ||
1290 | for (i = 0; i < nb_cpus; i++) | |
1291 | mpp->dst[i].irqs = irqs[i]; | |
1292 | mpp->irq_out = irq_out; | |
b7169916 AJ |
1293 | |
1294 | mpp->irq_raise = mpic_irq_raise; | |
1295 | mpp->reset = mpic_reset; | |
1296 | ||
0be71e32 | 1297 | register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp); |
a08d4367 | 1298 | qemu_register_reset(mpic_reset, mpp); |
b7169916 AJ |
1299 | |
1300 | return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq); | |
dbda808a | 1301 | } |