[qemu.git] / hw / parallel.c

/*
 * QEMU Parallel PORT emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2007 Marko Kohtala
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "qemu-char.h"
#include "isa.h"
#include "pc.h"

//#define DEBUG_PARALLEL

#ifdef DEBUG_PARALLEL
#define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
#else
#define pdebug(fmt, arg...) ((void)0)
#endif

#define PARA_REG_DATA 0
#define PARA_REG_STS 1
#define PARA_REG_CTR 2
#define PARA_REG_EPP_ADDR 3
#define PARA_REG_EPP_DATA 4

/*
 * These are the definitions for the Printer Status Register
 */
#define PARA_STS_BUSY	0x80	/* Busy complement */
#define PARA_STS_ACK	0x40	/* Acknowledge */
#define PARA_STS_PAPER	0x20	/* Out of paper */
#define PARA_STS_ONLINE	0x10	/* Online */
#define PARA_STS_ERROR	0x08	/* Error complement */
#define PARA_STS_TMOUT	0x01	/* EPP timeout */

/*
 * These are the definitions for the Printer Control Register
 */
#define PARA_CTR_DIR	0x20	/* Direction (1=read, 0=write) */
#define PARA_CTR_INTEN	0x10	/* IRQ Enable */
#define PARA_CTR_SELECT	0x08	/* Select In complement */
#define PARA_CTR_INIT	0x04	/* Initialize Printer complement */
#define PARA_CTR_AUTOLF	0x02	/* Auto linefeed complement */
#define PARA_CTR_STROBE	0x01	/* Strobe complement */

#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)

struct ParallelState {
    uint8_t dataw;
    uint8_t datar;
    uint8_t status;
    uint8_t control;
    qemu_irq irq;
    int irq_pending;
    CharDriverState *chr;
    int hw_driver;
    int epp_timeout;
    uint32_t last_read_offset; /* For debugging */
    /* Memory-mapped interface */
    target_phys_addr_t base;
    int it_shift;
};

static void parallel_update_irq(ParallelState *s)
{
    if (s->irq_pending)
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void
parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;

    pdebug("write addr=0x%02x val=0x%02x\n", addr, val);

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        s->dataw = val;
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if ((val & PARA_CTR_INIT) == 0 ) {
            s->status = PARA_STS_BUSY;
            s->status |= PARA_STS_ACK;
            s->status |= PARA_STS_ONLINE;
            s->status |= PARA_STS_ERROR;
        }
        else if (val & PARA_CTR_SELECT) {
            if (val & PARA_CTR_STROBE) {
                s->status &= ~PARA_STS_BUSY;
                if ((s->control & PARA_CTR_STROBE) == 0)
                    qemu_chr_write(s->chr, &s->dataw, 1);
            } else {
                if (s->control & PARA_CTR_INTEN) {
                    s->irq_pending = 1;
                }
            }
        }
        parallel_update_irq(s);
        s->control = val;
        break;
    }
}

static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint8_t parm = val;
    int dir;

    /* Sometimes programs do several writes for timing purposes on old
       HW. Take care not to waste time on writes that do nothing. */

    s->last_read_offset = ~0U;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->dataw == val)
            return;
        pdebug("wd%02x\n", val);
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
        s->dataw = val;
        break;
    case PARA_REG_STS:
        pdebug("ws%02x\n", val);
        if (val & PARA_STS_TMOUT)
            s->epp_timeout = 0;
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if (s->control == val)
            return;
        pdebug("wc%02x\n", val);

        if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
            if (val & PARA_CTR_DIR) {
                dir = 1;
            } else {
                dir = 0;
            }
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
            parm &= ~PARA_CTR_DIR;
        }

        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
        s->control = val;
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP address cycle, so do nothing */
            pdebug("wa%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("wa%02x t\n", val);
            }
            else
                pdebug("wa%02x\n", val);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("we%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("we%02x t\n", val);
            }
            else
                pdebug("we%02x\n", val);
        }
        break;
    }
}

static void
parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint16_t eppdata = cpu_to_le16(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%04x s\n", val);
        return;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%04x t\n", val);
    }
    else
        pdebug("we%04x\n", val);
}

static void
parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint32_t eppdata = cpu_to_le32(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%08x s\n", val);
        return;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%08x t\n", val);
    }
    else
        pdebug("we%08x\n", val);
}

static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret = 0xff;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->control & PARA_CTR_DIR)
            ret = s->datar;
        else
            ret = s->dataw;
        break;
    case PARA_REG_STS:
        ret = s->status;
        s->irq_pending = 0;
        if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
            /* XXX Fixme: wait 5 microseconds */
            if (s->status & PARA_STS_ACK)
                s->status &= ~PARA_STS_ACK;
            else {
                /* XXX Fixme: wait 5 microseconds */
                s->status |= PARA_STS_ACK;
                s->status |= PARA_STS_BUSY;
            }
        }
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        ret = s->control;
        break;
    }
    pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
    return ret;
}

static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint8_t ret = 0xff;
    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
        if (s->last_read_offset != addr || s->datar != ret)
            pdebug("rd%02x\n", ret);
        s->datar = ret;
        break;
    case PARA_REG_STS:
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
        ret &= ~PARA_STS_TMOUT;
        if (s->epp_timeout)
            ret |= PARA_STS_TMOUT;
        if (s->last_read_offset != addr || s->status != ret)
            pdebug("rs%02x\n", ret);
        s->status = ret;
        break;
    case PARA_REG_CTR:
        /* s->control has some bits fixed to 1. It is zero only when
           it has not been yet written to.  */
        if (s->control == 0) {
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
            s->control = ret;
        }
        else {
            ret = s->control;
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP addr cycle, so do nothing */
            pdebug("ra%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("ra%02x t\n", ret);
            }
            else
                pdebug("ra%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("re%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("re%02x t\n", ret);
            }
            else
                pdebug("re%02x\n", ret);
        }
        break;
    }
    s->last_read_offset = addr;
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint16_t eppdata = ~0;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%04x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le16_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%04x t\n", ret);
    }
    else
        pdebug("re%04x\n", ret);
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint32_t eppdata = ~0U;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%08x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le32_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%08x t\n", ret);
    }
    else
        pdebug("re%08x\n", ret);
    return ret;
}

static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
{
    addr &= 7;
    pdebug("wecp%d=%02x\n", addr, val);
}

static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
{
    uint8_t ret = 0xff;
    addr &= 7;
    pdebug("recp%d:%02x\n", addr, ret);
    return ret;
}

static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr)
{
    s->datar = ~0;
    s->dataw = ~0;
    s->status = PARA_STS_BUSY;
    s->status |= PARA_STS_ACK;
    s->status |= PARA_STS_ONLINE;
    s->status |= PARA_STS_ERROR;
    s->status |= PARA_STS_TMOUT;
    s->control = PARA_CTR_SELECT;
    s->control |= PARA_CTR_INIT;
    s->control |= 0xc0;
    s->irq = irq;
    s->irq_pending = 0;
    s->chr = chr;
    s->hw_driver = 0;
    s->epp_timeout = 0;
    s->last_read_offset = ~0U;
}

/* If fd is zero, it means that the parallel device uses the console */
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
{
    ParallelState *s;
    uint8_t dummy;

    s = qemu_mallocz(sizeof(ParallelState));
    if (!s)
        return NULL;
    parallel_reset(s, irq, chr);

    if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
        s->hw_driver = 1;
        s->status = dummy;
    }

    if (s->hw_driver) {
        register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
        register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
        register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
        register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
        register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
        register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
        register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
        register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
    }
    else {
        register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
        register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
    }
    return s;
}

/* Memory mapped interface */
static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
}

static void parallel_mm_writeb (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}

static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
}

static void parallel_mm_writew (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}

static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
}

static void parallel_mm_writel (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);
}

static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
    &parallel_mm_readb,
    &parallel_mm_readw,
    &parallel_mm_readl,
};

static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
    &parallel_mm_writeb,
    &parallel_mm_writew,
    &parallel_mm_writel,
};

/* If fd is zero, it means that the parallel device uses the console */
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
{
    ParallelState *s;
    int io_sw;

    s = qemu_mallocz(sizeof(ParallelState));
    if (!s)
        return NULL;
    parallel_reset(s, irq, chr);
    s->base = base;
    s->it_shift = it_shift;

    io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
    cpu_register_physical_memory(base, 8 << it_shift, io_sw);
    return s;
}
Commit	Line	Data
6508fe59 FB	1	/*
6508fe59 FB	2	* QEMU Parallel PORT emulation
5fafdf24	3	*
e57a8c0e	4	* Copyright (c) 2003-2005 Fabrice Bellard
5867c88a	5	* Copyright (c) 2007 Marko Kohtala
5fafdf24	6	*
6508fe59 FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
87ecb68b PB	25	#include "hw.h"
	26	#include "qemu-char.h"
	27	#include "isa.h"
	28	#include "pc.h"
6508fe59 FB	29
	30	//#define DEBUG_PARALLEL
	31
5867c88a TS	32	#ifdef DEBUG_PARALLEL
	33	#define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
	34	#else
	35	#define pdebug(fmt, arg...) ((void)0)
	36	#endif
	37
	38	#define PARA_REG_DATA 0
	39	#define PARA_REG_STS 1
	40	#define PARA_REG_CTR 2
	41	#define PARA_REG_EPP_ADDR 3
	42	#define PARA_REG_EPP_DATA 4
	43
6508fe59 FB	44	/*
	45	* These are the definitions for the Printer Status Register
	46	*/
	47	#define PARA_STS_BUSY 0x80 /* Busy complement */
	48	#define PARA_STS_ACK 0x40 /* Acknowledge */
	49	#define PARA_STS_PAPER 0x20 /* Out of paper */
	50	#define PARA_STS_ONLINE 0x10 /* Online */
	51	#define PARA_STS_ERROR 0x08 /* Error complement */
5867c88a	52	#define PARA_STS_TMOUT 0x01 /* EPP timeout */
6508fe59 FB	53
	54	/*
	55	* These are the definitions for the Printer Control Register
	56	*/
5867c88a	57	#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
6508fe59 FB	58	#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
	59	#define PARA_CTR_SELECT 0x08 /* Select In complement */
	60	#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
	61	#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
	62	#define PARA_CTR_STROBE 0x01 /* Strobe complement */
	63
5867c88a TS	64	#define PARA_CTR_SIGNAL (PARA_CTR_SELECT\|PARA_CTR_INIT\|PARA_CTR_AUTOLF\|PARA_CTR_STROBE)
5867c88a TS	65
6508fe59	66	struct ParallelState {
5867c88a TS	67	uint8_t dataw;
	68	uint8_t datar;
	69	uint8_t status;
6508fe59	70	uint8_t control;
d537cf6c	71	qemu_irq irq;
6508fe59 FB	72	int irq_pending;
6508fe59 FB	73	CharDriverState *chr;
e57a8c0e	74	int hw_driver;
5867c88a TS	75	int epp_timeout;
5867c88a TS	76	uint32_t last_read_offset; /* For debugging */
d60532ca TS	77	/* Memory-mapped interface */
	78	target_phys_addr_t base;
	79	int it_shift;
6508fe59 FB	80	};
	81
	82	static void parallel_update_irq(ParallelState *s)
	83	{
	84	if (s->irq_pending)
d537cf6c	85	qemu_irq_raise(s->irq);
6508fe59	86	else
d537cf6c	87	qemu_irq_lower(s->irq);
6508fe59 FB	88	}
6508fe59 FB	89
5867c88a TS	90	static void
5867c88a TS	91	parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
6508fe59 FB	92	{
6508fe59 FB	93	ParallelState *s = opaque;
3b46e624	94
5867c88a TS	95	pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
	96
	97	addr &= 7;
	98	switch(addr) {
	99	case PARA_REG_DATA:
0fa7f157 TS	100	s->dataw = val;
0fa7f157 TS	101	parallel_update_irq(s);
5867c88a TS	102	break;
5867c88a TS	103	case PARA_REG_CTR:
52ccc5e0	104	val \|= 0xc0;
0fa7f157 TS	105	if ((val & PARA_CTR_INIT) == 0 ) {
	106	s->status = PARA_STS_BUSY;
	107	s->status \|= PARA_STS_ACK;
	108	s->status \|= PARA_STS_ONLINE;
	109	s->status \|= PARA_STS_ERROR;
	110	}
	111	else if (val & PARA_CTR_SELECT) {
	112	if (val & PARA_CTR_STROBE) {
	113	s->status &= ~PARA_STS_BUSY;
	114	if ((s->control & PARA_CTR_STROBE) == 0)
	115	qemu_chr_write(s->chr, &s->dataw, 1);
	116	} else {
	117	if (s->control & PARA_CTR_INTEN) {
	118	s->irq_pending = 1;
	119	}
	120	}
	121	}
	122	parallel_update_irq(s);
	123	s->control = val;
5867c88a TS	124	break;
	125	}
	126	}
	127
	128	static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
	129	{
	130	ParallelState *s = opaque;
	131	uint8_t parm = val;
563e3c6e	132	int dir;
5867c88a TS	133
	134	/* Sometimes programs do several writes for timing purposes on old
	135	HW. Take care not to waste time on writes that do nothing. */
	136
	137	s->last_read_offset = ~0U;
	138
6508fe59	139	addr &= 7;
6508fe59	140	switch(addr) {
5867c88a TS	141	case PARA_REG_DATA:
5867c88a TS	142	if (s->dataw == val)
0fa7f157 TS	143	return;
	144	pdebug("wd%02x\n", val);
	145	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
	146	s->dataw = val;
6508fe59	147	break;
5867c88a	148	case PARA_REG_STS:
0fa7f157 TS	149	pdebug("ws%02x\n", val);
	150	if (val & PARA_STS_TMOUT)
	151	s->epp_timeout = 0;
	152	break;
5867c88a TS	153	case PARA_REG_CTR:
	154	val \|= 0xc0;
	155	if (s->control == val)
0fa7f157 TS	156	return;
0fa7f157 TS	157	pdebug("wc%02x\n", val);
563e3c6e AJ	158
	159	if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
	160	if (val & PARA_CTR_DIR) {
	161	dir = 1;
	162	} else {
	163	dir = 0;
	164	}
	165	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
	166	parm &= ~PARA_CTR_DIR;
	167	}
	168
0fa7f157 TS	169	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
0fa7f157 TS	170	s->control = val;
6508fe59	171	break;
5867c88a	172	case PARA_REG_EPP_ADDR:
0fa7f157 TS	173	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	174	/* Controls not correct for EPP address cycle, so do nothing */
	175	pdebug("wa%02x s\n", val);
	176	else {
	177	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	178	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
	179	s->epp_timeout = 1;
	180	pdebug("wa%02x t\n", val);
	181	}
	182	else
	183	pdebug("wa%02x\n", val);
	184	}
	185	break;
5867c88a	186	case PARA_REG_EPP_DATA:
0fa7f157 TS	187	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	188	/* Controls not correct for EPP data cycle, so do nothing */
	189	pdebug("we%02x s\n", val);
	190	else {
	191	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	192	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
	193	s->epp_timeout = 1;
	194	pdebug("we%02x t\n", val);
	195	}
	196	else
	197	pdebug("we%02x\n", val);
	198	}
	199	break;
5867c88a TS	200	}
	201	}
	202
	203	static void
	204	parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
	205	{
	206	ParallelState *s = opaque;
	207	uint16_t eppdata = cpu_to_le16(val);
	208	int err;
	209	struct ParallelIOArg ioarg = {
0fa7f157	210	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	211	};
5867c88a TS	212	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	213	/* Controls not correct for EPP data cycle, so do nothing */
	214	pdebug("we%04x s\n", val);
	215	return;
5867c88a TS	216	}
	217	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
	218	if (err) {
0fa7f157 TS	219	s->epp_timeout = 1;
0fa7f157 TS	220	pdebug("we%04x t\n", val);
5867c88a TS	221	}
5867c88a TS	222	else
0fa7f157	223	pdebug("we%04x\n", val);
5867c88a TS	224	}
	225
	226	static void
	227	parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
	228	{
	229	ParallelState *s = opaque;
	230	uint32_t eppdata = cpu_to_le32(val);
	231	int err;
	232	struct ParallelIOArg ioarg = {
0fa7f157	233	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	234	};
5867c88a TS	235	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	236	/* Controls not correct for EPP data cycle, so do nothing */
	237	pdebug("we%08x s\n", val);
	238	return;
5867c88a TS	239	}
	240	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
	241	if (err) {
0fa7f157 TS	242	s->epp_timeout = 1;
0fa7f157 TS	243	pdebug("we%08x t\n", val);
6508fe59	244	}
5867c88a	245	else
0fa7f157	246	pdebug("we%08x\n", val);
6508fe59 FB	247	}
6508fe59 FB	248
5867c88a	249	static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
6508fe59 FB	250	{
	251	ParallelState *s = opaque;
	252	uint32_t ret = 0xff;
	253
	254	addr &= 7;
	255	switch(addr) {
5867c88a	256	case PARA_REG_DATA:
0fa7f157 TS	257	if (s->control & PARA_CTR_DIR)
	258	ret = s->datar;
	259	else
	260	ret = s->dataw;
6508fe59	261	break;
5867c88a	262	case PARA_REG_STS:
0fa7f157 TS	263	ret = s->status;
	264	s->irq_pending = 0;
	265	if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
	266	/* XXX Fixme: wait 5 microseconds */
	267	if (s->status & PARA_STS_ACK)
	268	s->status &= ~PARA_STS_ACK;
	269	else {
	270	/* XXX Fixme: wait 5 microseconds */
	271	s->status \|= PARA_STS_ACK;
	272	s->status \|= PARA_STS_BUSY;
	273	}
	274	}
	275	parallel_update_irq(s);
6508fe59	276	break;
5867c88a	277	case PARA_REG_CTR:
6508fe59 FB	278	ret = s->control;
	279	break;
	280	}
5867c88a TS	281	pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
	282	return ret;
	283	}
	284
	285	static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
	286	{
	287	ParallelState *s = opaque;
	288	uint8_t ret = 0xff;
	289	addr &= 7;
	290	switch(addr) {
	291	case PARA_REG_DATA:
0fa7f157 TS	292	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
	293	if (s->last_read_offset != addr \|\| s->datar != ret)
	294	pdebug("rd%02x\n", ret);
5867c88a TS	295	s->datar = ret;
	296	break;
	297	case PARA_REG_STS:
0fa7f157 TS	298	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
	299	ret &= ~PARA_STS_TMOUT;
	300	if (s->epp_timeout)
	301	ret \|= PARA_STS_TMOUT;
	302	if (s->last_read_offset != addr \|\| s->status != ret)
	303	pdebug("rs%02x\n", ret);
	304	s->status = ret;
5867c88a TS	305	break;
	306	case PARA_REG_CTR:
	307	/* s->control has some bits fixed to 1. It is zero only when
0fa7f157 TS	308	it has not been yet written to. */
	309	if (s->control == 0) {
	310	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
	311	if (s->last_read_offset != addr)
	312	pdebug("rc%02x\n", ret);
	313	s->control = ret;
	314	}
	315	else {
	316	ret = s->control;
	317	if (s->last_read_offset != addr)
	318	pdebug("rc%02x\n", ret);
	319	}
5867c88a TS	320	break;
5867c88a TS	321	case PARA_REG_EPP_ADDR:
0fa7f157 TS	322	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	323	/* Controls not correct for EPP addr cycle, so do nothing */
	324	pdebug("ra%02x s\n", ret);
	325	else {
	326	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	327	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
	328	s->epp_timeout = 1;
	329	pdebug("ra%02x t\n", ret);
	330	}
	331	else
	332	pdebug("ra%02x\n", ret);
	333	}
	334	break;
5867c88a	335	case PARA_REG_EPP_DATA:
0fa7f157 TS	336	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	337	/* Controls not correct for EPP data cycle, so do nothing */
	338	pdebug("re%02x s\n", ret);
	339	else {
	340	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	341	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
	342	s->epp_timeout = 1;
	343	pdebug("re%02x t\n", ret);
	344	}
	345	else
	346	pdebug("re%02x\n", ret);
	347	}
	348	break;
5867c88a TS	349	}
	350	s->last_read_offset = addr;
	351	return ret;
	352	}
	353
	354	static uint32_t
	355	parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
	356	{
	357	ParallelState *s = opaque;
	358	uint32_t ret;
	359	uint16_t eppdata = ~0;
	360	int err;
	361	struct ParallelIOArg ioarg = {
0fa7f157	362	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	363	};
5867c88a TS	364	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	365	/* Controls not correct for EPP data cycle, so do nothing */
	366	pdebug("re%04x s\n", eppdata);
	367	return eppdata;
5867c88a TS	368	}
	369	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
	370	ret = le16_to_cpu(eppdata);
	371
	372	if (err) {
0fa7f157 TS	373	s->epp_timeout = 1;
0fa7f157 TS	374	pdebug("re%04x t\n", ret);
5867c88a TS	375	}
5867c88a TS	376	else
0fa7f157	377	pdebug("re%04x\n", ret);
5867c88a TS	378	return ret;
	379	}
	380
	381	static uint32_t
	382	parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
	383	{
	384	ParallelState *s = opaque;
	385	uint32_t ret;
	386	uint32_t eppdata = ~0U;
	387	int err;
	388	struct ParallelIOArg ioarg = {
0fa7f157	389	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	390	};
5867c88a TS	391	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	392	/* Controls not correct for EPP data cycle, so do nothing */
	393	pdebug("re%08x s\n", eppdata);
	394	return eppdata;
5867c88a TS	395	}
	396	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
	397	ret = le32_to_cpu(eppdata);
	398
	399	if (err) {
0fa7f157 TS	400	s->epp_timeout = 1;
0fa7f157 TS	401	pdebug("re%08x t\n", ret);
5867c88a TS	402	}
5867c88a TS	403	else
0fa7f157	404	pdebug("re%08x\n", ret);
5867c88a TS	405	return ret;
	406	}
	407
	408	static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
	409	{
	410	addr &= 7;
	411	pdebug("wecp%d=%02x\n", addr, val);
	412	}
	413
	414	static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
	415	{
	416	uint8_t ret = 0xff;
	417	addr &= 7;
	418	pdebug("recp%d:%02x\n", addr, ret);
6508fe59 FB	419	return ret;
	420	}
	421
d60532ca	422	static void parallel_reset(ParallelState s, qemu_irq irq, CharDriverState chr)
6508fe59	423	{
5867c88a TS	424	s->datar = ~0;
5867c88a TS	425	s->dataw = ~0;
6508fe59 FB	426	s->status = PARA_STS_BUSY;
	427	s->status \|= PARA_STS_ACK;
	428	s->status \|= PARA_STS_ONLINE;
	429	s->status \|= PARA_STS_ERROR;
52ccc5e0	430	s->status \|= PARA_STS_TMOUT;
6508fe59 FB	431	s->control = PARA_CTR_SELECT;
6508fe59 FB	432	s->control \|= PARA_CTR_INIT;
52ccc5e0	433	s->control \|= 0xc0;
5867c88a TS	434	s->irq = irq;
	435	s->irq_pending = 0;
	436	s->chr = chr;
	437	s->hw_driver = 0;
	438	s->epp_timeout = 0;
	439	s->last_read_offset = ~0U;
d60532ca TS	440	}
	441
	442	/* If fd is zero, it means that the parallel device uses the console */
	443	ParallelState parallel_init(int base, qemu_irq irq, CharDriverState chr)
	444	{
	445	ParallelState *s;
	446	uint8_t dummy;
	447
	448	s = qemu_mallocz(sizeof(ParallelState));
	449	if (!s)
	450	return NULL;
	451	parallel_reset(s, irq, chr);
6508fe59	452
5867c88a TS	453	if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
5867c88a TS	454	s->hw_driver = 1;
0fa7f157	455	s->status = dummy;
5867c88a TS	456	}
	457
	458	if (s->hw_driver) {
0fa7f157 TS	459	register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
	460	register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
	461	register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
	462	register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
	463	register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
	464	register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
	465	register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
	466	register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
5867c88a TS	467	}
5867c88a TS	468	else {
0fa7f157 TS	469	register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
0fa7f157 TS	470	register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
5867c88a	471	}
6508fe59 FB	472	return s;
6508fe59 FB	473	}
d60532ca TS	474
d60532ca TS	475	/* Memory mapped interface */
9596ebb7	476	static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
d60532ca TS	477	{
	478	ParallelState *s = opaque;
	479
	480	return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
	481	}
	482
9596ebb7 PB	483	static void parallel_mm_writeb (void *opaque,
9596ebb7 PB	484	target_phys_addr_t addr, uint32_t value)
d60532ca TS	485	{
	486	ParallelState *s = opaque;
	487
	488	parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
	489	}
	490
9596ebb7	491	static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
d60532ca TS	492	{
	493	ParallelState *s = opaque;
	494
	495	return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
	496	}
	497
9596ebb7 PB	498	static void parallel_mm_writew (void *opaque,
9596ebb7 PB	499	target_phys_addr_t addr, uint32_t value)
d60532ca TS	500	{
	501	ParallelState *s = opaque;
	502
	503	parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
	504	}
	505
9596ebb7	506	static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
d60532ca TS	507	{
	508	ParallelState *s = opaque;
	509
	510	return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
	511	}
	512
9596ebb7 PB	513	static void parallel_mm_writel (void *opaque,
9596ebb7 PB	514	target_phys_addr_t addr, uint32_t value)
d60532ca TS	515	{
	516	ParallelState *s = opaque;
	517
	518	parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);
	519	}
	520
	521	static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
	522	&parallel_mm_readb,
	523	&parallel_mm_readw,
	524	&parallel_mm_readl,
	525	};
	526
	527	static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
	528	&parallel_mm_writeb,
	529	&parallel_mm_writew,
	530	&parallel_mm_writel,
	531	};
	532
	533	/* If fd is zero, it means that the parallel device uses the console */
	534	ParallelState parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState chr)
	535	{
	536	ParallelState *s;
	537	int io_sw;
	538
	539	s = qemu_mallocz(sizeof(ParallelState));
	540	if (!s)
	541	return NULL;
	542	parallel_reset(s, irq, chr);
	543	s->base = base;
	544	s->it_shift = it_shift;
	545
	546	io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
	547	cpu_register_physical_memory(base, 8 << it_shift, io_sw);
	548	return s;
	549	}