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CommitLineData
6508fe59
FB
1/*
2 * QEMU Parallel PORT emulation
5fafdf24 3 *
e57a8c0e 4 * Copyright (c) 2003-2005 Fabrice Bellard
5867c88a 5 * Copyright (c) 2007 Marko Kohtala
5fafdf24 6 *
6508fe59
FB
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
87ecb68b
PB
25#include "hw.h"
26#include "qemu-char.h"
27#include "isa.h"
28#include "pc.h"
666daa68 29#include "sysemu.h"
6508fe59
FB
30
31//#define DEBUG_PARALLEL
32
5867c88a 33#ifdef DEBUG_PARALLEL
001faf32 34#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
5867c88a 35#else
001faf32 36#define pdebug(fmt, ...) ((void)0)
5867c88a
TS
37#endif
38
39#define PARA_REG_DATA 0
40#define PARA_REG_STS 1
41#define PARA_REG_CTR 2
42#define PARA_REG_EPP_ADDR 3
43#define PARA_REG_EPP_DATA 4
44
6508fe59
FB
45/*
46 * These are the definitions for the Printer Status Register
47 */
48#define PARA_STS_BUSY 0x80 /* Busy complement */
49#define PARA_STS_ACK 0x40 /* Acknowledge */
50#define PARA_STS_PAPER 0x20 /* Out of paper */
51#define PARA_STS_ONLINE 0x10 /* Online */
52#define PARA_STS_ERROR 0x08 /* Error complement */
5867c88a 53#define PARA_STS_TMOUT 0x01 /* EPP timeout */
6508fe59
FB
54
55/*
56 * These are the definitions for the Printer Control Register
57 */
5867c88a 58#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
6508fe59
FB
59#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
60#define PARA_CTR_SELECT 0x08 /* Select In complement */
61#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
62#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
63#define PARA_CTR_STROBE 0x01 /* Strobe complement */
64
5867c88a
TS
65#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
66
6508fe59 67struct ParallelState {
5867c88a
TS
68 uint8_t dataw;
69 uint8_t datar;
70 uint8_t status;
6508fe59 71 uint8_t control;
d537cf6c 72 qemu_irq irq;
6508fe59
FB
73 int irq_pending;
74 CharDriverState *chr;
e57a8c0e 75 int hw_driver;
5867c88a
TS
76 int epp_timeout;
77 uint32_t last_read_offset; /* For debugging */
d60532ca 78 /* Memory-mapped interface */
d60532ca 79 int it_shift;
6508fe59
FB
80};
81
021f0674
GH
82typedef struct ISAParallelState {
83 ISADevice dev;
e8ee28fb 84 uint32_t index;
021f0674
GH
85 uint32_t iobase;
86 uint32_t isairq;
87 ParallelState state;
88} ISAParallelState;
89
6508fe59
FB
90static void parallel_update_irq(ParallelState *s)
91{
92 if (s->irq_pending)
d537cf6c 93 qemu_irq_raise(s->irq);
6508fe59 94 else
d537cf6c 95 qemu_irq_lower(s->irq);
6508fe59
FB
96}
97
5867c88a
TS
98static void
99parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
6508fe59
FB
100{
101 ParallelState *s = opaque;
3b46e624 102
5867c88a
TS
103 pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
104
105 addr &= 7;
106 switch(addr) {
107 case PARA_REG_DATA:
0fa7f157
TS
108 s->dataw = val;
109 parallel_update_irq(s);
5867c88a
TS
110 break;
111 case PARA_REG_CTR:
52ccc5e0 112 val |= 0xc0;
0fa7f157
TS
113 if ((val & PARA_CTR_INIT) == 0 ) {
114 s->status = PARA_STS_BUSY;
115 s->status |= PARA_STS_ACK;
116 s->status |= PARA_STS_ONLINE;
117 s->status |= PARA_STS_ERROR;
118 }
119 else if (val & PARA_CTR_SELECT) {
120 if (val & PARA_CTR_STROBE) {
121 s->status &= ~PARA_STS_BUSY;
122 if ((s->control & PARA_CTR_STROBE) == 0)
123 qemu_chr_write(s->chr, &s->dataw, 1);
124 } else {
125 if (s->control & PARA_CTR_INTEN) {
126 s->irq_pending = 1;
127 }
128 }
129 }
130 parallel_update_irq(s);
131 s->control = val;
5867c88a
TS
132 break;
133 }
134}
135
136static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
137{
138 ParallelState *s = opaque;
139 uint8_t parm = val;
563e3c6e 140 int dir;
5867c88a
TS
141
142 /* Sometimes programs do several writes for timing purposes on old
143 HW. Take care not to waste time on writes that do nothing. */
144
145 s->last_read_offset = ~0U;
146
6508fe59 147 addr &= 7;
6508fe59 148 switch(addr) {
5867c88a
TS
149 case PARA_REG_DATA:
150 if (s->dataw == val)
0fa7f157
TS
151 return;
152 pdebug("wd%02x\n", val);
153 qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
154 s->dataw = val;
6508fe59 155 break;
5867c88a 156 case PARA_REG_STS:
0fa7f157
TS
157 pdebug("ws%02x\n", val);
158 if (val & PARA_STS_TMOUT)
159 s->epp_timeout = 0;
160 break;
5867c88a
TS
161 case PARA_REG_CTR:
162 val |= 0xc0;
163 if (s->control == val)
0fa7f157
TS
164 return;
165 pdebug("wc%02x\n", val);
563e3c6e
AJ
166
167 if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
168 if (val & PARA_CTR_DIR) {
169 dir = 1;
170 } else {
171 dir = 0;
172 }
173 qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
174 parm &= ~PARA_CTR_DIR;
175 }
176
0fa7f157
TS
177 qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
178 s->control = val;
6508fe59 179 break;
5867c88a 180 case PARA_REG_EPP_ADDR:
0fa7f157
TS
181 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
182 /* Controls not correct for EPP address cycle, so do nothing */
183 pdebug("wa%02x s\n", val);
184 else {
185 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
186 if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
187 s->epp_timeout = 1;
188 pdebug("wa%02x t\n", val);
189 }
190 else
191 pdebug("wa%02x\n", val);
192 }
193 break;
5867c88a 194 case PARA_REG_EPP_DATA:
0fa7f157
TS
195 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
196 /* Controls not correct for EPP data cycle, so do nothing */
197 pdebug("we%02x s\n", val);
198 else {
199 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
200 if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
201 s->epp_timeout = 1;
202 pdebug("we%02x t\n", val);
203 }
204 else
205 pdebug("we%02x\n", val);
206 }
207 break;
5867c88a
TS
208 }
209}
210
211static void
212parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
213{
214 ParallelState *s = opaque;
215 uint16_t eppdata = cpu_to_le16(val);
216 int err;
217 struct ParallelIOArg ioarg = {
0fa7f157 218 .buffer = &eppdata, .count = sizeof(eppdata)
5867c88a
TS
219 };
220 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157
TS
221 /* Controls not correct for EPP data cycle, so do nothing */
222 pdebug("we%04x s\n", val);
223 return;
5867c88a
TS
224 }
225 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
226 if (err) {
0fa7f157
TS
227 s->epp_timeout = 1;
228 pdebug("we%04x t\n", val);
5867c88a
TS
229 }
230 else
0fa7f157 231 pdebug("we%04x\n", val);
5867c88a
TS
232}
233
234static void
235parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
236{
237 ParallelState *s = opaque;
238 uint32_t eppdata = cpu_to_le32(val);
239 int err;
240 struct ParallelIOArg ioarg = {
0fa7f157 241 .buffer = &eppdata, .count = sizeof(eppdata)
5867c88a
TS
242 };
243 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157
TS
244 /* Controls not correct for EPP data cycle, so do nothing */
245 pdebug("we%08x s\n", val);
246 return;
5867c88a
TS
247 }
248 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
249 if (err) {
0fa7f157
TS
250 s->epp_timeout = 1;
251 pdebug("we%08x t\n", val);
6508fe59 252 }
5867c88a 253 else
0fa7f157 254 pdebug("we%08x\n", val);
6508fe59
FB
255}
256
5867c88a 257static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
6508fe59
FB
258{
259 ParallelState *s = opaque;
260 uint32_t ret = 0xff;
261
262 addr &= 7;
263 switch(addr) {
5867c88a 264 case PARA_REG_DATA:
0fa7f157
TS
265 if (s->control & PARA_CTR_DIR)
266 ret = s->datar;
267 else
268 ret = s->dataw;
6508fe59 269 break;
5867c88a 270 case PARA_REG_STS:
0fa7f157
TS
271 ret = s->status;
272 s->irq_pending = 0;
273 if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
274 /* XXX Fixme: wait 5 microseconds */
275 if (s->status & PARA_STS_ACK)
276 s->status &= ~PARA_STS_ACK;
277 else {
278 /* XXX Fixme: wait 5 microseconds */
279 s->status |= PARA_STS_ACK;
280 s->status |= PARA_STS_BUSY;
281 }
282 }
283 parallel_update_irq(s);
6508fe59 284 break;
5867c88a 285 case PARA_REG_CTR:
6508fe59
FB
286 ret = s->control;
287 break;
288 }
5867c88a
TS
289 pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
290 return ret;
291}
292
293static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
294{
295 ParallelState *s = opaque;
296 uint8_t ret = 0xff;
297 addr &= 7;
298 switch(addr) {
299 case PARA_REG_DATA:
0fa7f157
TS
300 qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
301 if (s->last_read_offset != addr || s->datar != ret)
302 pdebug("rd%02x\n", ret);
5867c88a
TS
303 s->datar = ret;
304 break;
305 case PARA_REG_STS:
0fa7f157
TS
306 qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
307 ret &= ~PARA_STS_TMOUT;
308 if (s->epp_timeout)
309 ret |= PARA_STS_TMOUT;
310 if (s->last_read_offset != addr || s->status != ret)
311 pdebug("rs%02x\n", ret);
312 s->status = ret;
5867c88a
TS
313 break;
314 case PARA_REG_CTR:
315 /* s->control has some bits fixed to 1. It is zero only when
0fa7f157
TS
316 it has not been yet written to. */
317 if (s->control == 0) {
318 qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
319 if (s->last_read_offset != addr)
320 pdebug("rc%02x\n", ret);
321 s->control = ret;
322 }
323 else {
324 ret = s->control;
325 if (s->last_read_offset != addr)
326 pdebug("rc%02x\n", ret);
327 }
5867c88a
TS
328 break;
329 case PARA_REG_EPP_ADDR:
0fa7f157
TS
330 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
331 /* Controls not correct for EPP addr cycle, so do nothing */
332 pdebug("ra%02x s\n", ret);
333 else {
334 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
335 if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
336 s->epp_timeout = 1;
337 pdebug("ra%02x t\n", ret);
338 }
339 else
340 pdebug("ra%02x\n", ret);
341 }
342 break;
5867c88a 343 case PARA_REG_EPP_DATA:
0fa7f157
TS
344 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
345 /* Controls not correct for EPP data cycle, so do nothing */
346 pdebug("re%02x s\n", ret);
347 else {
348 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
349 if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
350 s->epp_timeout = 1;
351 pdebug("re%02x t\n", ret);
352 }
353 else
354 pdebug("re%02x\n", ret);
355 }
356 break;
5867c88a
TS
357 }
358 s->last_read_offset = addr;
359 return ret;
360}
361
362static uint32_t
363parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
364{
365 ParallelState *s = opaque;
366 uint32_t ret;
367 uint16_t eppdata = ~0;
368 int err;
369 struct ParallelIOArg ioarg = {
0fa7f157 370 .buffer = &eppdata, .count = sizeof(eppdata)
5867c88a
TS
371 };
372 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
0fa7f157
TS
373 /* Controls not correct for EPP data cycle, so do nothing */
374 pdebug("re%04x s\n", eppdata);
375 return eppdata;
5867c88a
TS
376 }
377 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
378 ret = le16_to_cpu(eppdata);
379
380 if (err) {
0fa7f157
TS
381 s->epp_timeout = 1;
382 pdebug("re%04x t\n", ret);
5867c88a
TS
383 }
384 else
0fa7f157 385 pdebug("re%04x\n", ret);
5867c88a
TS
386 return ret;
387}
388
389static uint32_t
390parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
391{
392 ParallelState *s = opaque;
393 uint32_t ret;
394 uint32_t eppdata = ~0U;
395 int err;
396 struct ParallelIOArg ioarg = {
0fa7f157 397 .buffer = &eppdata, .count = sizeof(eppdata)
5867c88a
TS
398 };
399 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
0fa7f157
TS
400 /* Controls not correct for EPP data cycle, so do nothing */
401 pdebug("re%08x s\n", eppdata);
402 return eppdata;
5867c88a
TS
403 }
404 err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
405 ret = le32_to_cpu(eppdata);
406
407 if (err) {
0fa7f157
TS
408 s->epp_timeout = 1;
409 pdebug("re%08x t\n", ret);
5867c88a
TS
410 }
411 else
0fa7f157 412 pdebug("re%08x\n", ret);
5867c88a
TS
413 return ret;
414}
415
416static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
417{
7f5b7d3e 418 pdebug("wecp%d=%02x\n", addr & 7, val);
5867c88a
TS
419}
420
421static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
422{
423 uint8_t ret = 0xff;
7f5b7d3e
BS
424
425 pdebug("recp%d:%02x\n", addr & 7, ret);
6508fe59
FB
426 return ret;
427}
428
33093a0a 429static void parallel_reset(void *opaque)
6508fe59 430{
33093a0a
AJ
431 ParallelState *s = opaque;
432
5867c88a
TS
433 s->datar = ~0;
434 s->dataw = ~0;
6508fe59
FB
435 s->status = PARA_STS_BUSY;
436 s->status |= PARA_STS_ACK;
437 s->status |= PARA_STS_ONLINE;
438 s->status |= PARA_STS_ERROR;
52ccc5e0 439 s->status |= PARA_STS_TMOUT;
6508fe59
FB
440 s->control = PARA_CTR_SELECT;
441 s->control |= PARA_CTR_INIT;
52ccc5e0 442 s->control |= 0xc0;
5867c88a 443 s->irq_pending = 0;
5867c88a
TS
444 s->hw_driver = 0;
445 s->epp_timeout = 0;
446 s->last_read_offset = ~0U;
d60532ca
TS
447}
448
e8ee28fb
GH
449static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
450
021f0674 451static int parallel_isa_initfn(ISADevice *dev)
d60532ca 452{
e8ee28fb 453 static int index;
021f0674
GH
454 ISAParallelState *isa = DO_UPCAST(ISAParallelState, dev, dev);
455 ParallelState *s = &isa->state;
e8ee28fb 456 int base;
d60532ca
TS
457 uint8_t dummy;
458
021f0674
GH
459 if (!s->chr) {
460 fprintf(stderr, "Can't create parallel device, empty char device\n");
461 exit(1);
462 }
463
e8ee28fb
GH
464 if (isa->index == -1)
465 isa->index = index;
466 if (isa->index >= MAX_PARALLEL_PORTS)
467 return -1;
468 if (isa->iobase == -1)
469 isa->iobase = isa_parallel_io[isa->index];
470 index++;
471
472 base = isa->iobase;
021f0674 473 isa_init_irq(dev, &s->irq, isa->isairq);
a08d4367 474 qemu_register_reset(parallel_reset, s);
6508fe59 475
021f0674 476 if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
5867c88a 477 s->hw_driver = 1;
0fa7f157 478 s->status = dummy;
5867c88a
TS
479 }
480
481 if (s->hw_driver) {
0fa7f157
TS
482 register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
483 register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
484 register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
485 register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
486 register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
487 register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
488 register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
489 register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
5867c88a
TS
490 }
491 else {
0fa7f157
TS
492 register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
493 register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
5867c88a 494 }
021f0674
GH
495 return 0;
496}
497
021f0674
GH
498ParallelState *parallel_init(int index, CharDriverState *chr)
499{
500 ISADevice *dev;
501
502 dev = isa_create("isa-parallel");
e8ee28fb 503 qdev_prop_set_uint32(&dev->qdev, "index", index);
021f0674 504 qdev_prop_set_chr(&dev->qdev, "chardev", chr);
5c17ca25 505 if (qdev_init(&dev->qdev) < 0)
021f0674
GH
506 return NULL;
507 return &DO_UPCAST(ISAParallelState, dev, dev)->state;
6508fe59 508}
d60532ca
TS
509
510/* Memory mapped interface */
c227f099 511static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
d60532ca
TS
512{
513 ParallelState *s = opaque;
514
8da3ff18 515 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
d60532ca
TS
516}
517
9596ebb7 518static void parallel_mm_writeb (void *opaque,
c227f099 519 target_phys_addr_t addr, uint32_t value)
d60532ca
TS
520{
521 ParallelState *s = opaque;
522
8da3ff18 523 parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
d60532ca
TS
524}
525
c227f099 526static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
d60532ca
TS
527{
528 ParallelState *s = opaque;
529
8da3ff18 530 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
d60532ca
TS
531}
532
9596ebb7 533static void parallel_mm_writew (void *opaque,
c227f099 534 target_phys_addr_t addr, uint32_t value)
d60532ca
TS
535{
536 ParallelState *s = opaque;
537
8da3ff18 538 parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
d60532ca
TS
539}
540
c227f099 541static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
d60532ca
TS
542{
543 ParallelState *s = opaque;
544
8da3ff18 545 return parallel_ioport_read_sw(s, addr >> s->it_shift);
d60532ca
TS
546}
547
9596ebb7 548static void parallel_mm_writel (void *opaque,
c227f099 549 target_phys_addr_t addr, uint32_t value)
d60532ca
TS
550{
551 ParallelState *s = opaque;
552
8da3ff18 553 parallel_ioport_write_sw(s, addr >> s->it_shift, value);
d60532ca
TS
554}
555
d60efc6b 556static CPUReadMemoryFunc * const parallel_mm_read_sw[] = {
d60532ca
TS
557 &parallel_mm_readb,
558 &parallel_mm_readw,
559 &parallel_mm_readl,
560};
561
d60efc6b 562static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = {
d60532ca
TS
563 &parallel_mm_writeb,
564 &parallel_mm_writew,
565 &parallel_mm_writel,
566};
567
568/* If fd is zero, it means that the parallel device uses the console */
c227f099 569ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
d60532ca
TS
570{
571 ParallelState *s;
572 int io_sw;
573
574 s = qemu_mallocz(sizeof(ParallelState));
33093a0a
AJ
575 s->irq = irq;
576 s->chr = chr;
d60532ca 577 s->it_shift = it_shift;
a08d4367 578 qemu_register_reset(parallel_reset, s);
d60532ca 579
1eed09cb 580 io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);
d60532ca
TS
581 cpu_register_physical_memory(base, 8 << it_shift, io_sw);
582 return s;
583}
021f0674
GH
584
585static ISADeviceInfo parallel_isa_info = {
586 .qdev.name = "isa-parallel",
587 .qdev.size = sizeof(ISAParallelState),
588 .init = parallel_isa_initfn,
589 .qdev.props = (Property[]) {
51954d56 590 DEFINE_PROP_UINT32("index", ISAParallelState, index, -1),
e8ee28fb 591 DEFINE_PROP_HEX32("iobase", ISAParallelState, iobase, -1),
021f0674
GH
592 DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7),
593 DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
594 DEFINE_PROP_END_OF_LIST(),
595 },
596};
597
598static void parallel_register_devices(void)
599{
600 isa_qdev_register(&parallel_isa_info);
601}
602
603device_init(parallel_register_devices)