[qemu.git] / hw / parallel.c

/*
 * QEMU Parallel PORT emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2007 Marko Kohtala
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_PARALLEL

#ifdef DEBUG_PARALLEL
#define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
#else
#define pdebug(fmt, arg...) ((void)0)
#endif

#define PARA_REG_DATA 0
#define PARA_REG_STS 1
#define PARA_REG_CTR 2
#define PARA_REG_EPP_ADDR 3
#define PARA_REG_EPP_DATA 4

/*
 * These are the definitions for the Printer Status Register
 */
#define PARA_STS_BUSY	0x80	/* Busy complement */
#define PARA_STS_ACK	0x40	/* Acknowledge */
#define PARA_STS_PAPER	0x20	/* Out of paper */
#define PARA_STS_ONLINE	0x10	/* Online */
#define PARA_STS_ERROR	0x08	/* Error complement */
#define PARA_STS_TMOUT	0x01	/* EPP timeout */

/*
 * These are the definitions for the Printer Control Register
 */
#define PARA_CTR_DIR	0x20	/* Direction (1=read, 0=write) */
#define PARA_CTR_INTEN	0x10	/* IRQ Enable */
#define PARA_CTR_SELECT	0x08	/* Select In complement */
#define PARA_CTR_INIT	0x04	/* Initialize Printer complement */
#define PARA_CTR_AUTOLF	0x02	/* Auto linefeed complement */
#define PARA_CTR_STROBE	0x01	/* Strobe complement */

#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)

struct ParallelState {
    uint8_t dataw;
    uint8_t datar;
    uint8_t status;
    uint8_t control;
    qemu_irq irq;
    int irq_pending;
    CharDriverState *chr;
    int hw_driver;
    int epp_timeout;
    uint32_t last_read_offset; /* For debugging */
    /* Memory-mapped interface */
    target_phys_addr_t base;
    int it_shift;
};

static void parallel_update_irq(ParallelState *s)
{
    if (s->irq_pending)
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void
parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
   
    pdebug("write addr=0x%02x val=0x%02x\n", addr, val);

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        s->dataw = val;
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        if ((val & PARA_CTR_INIT) == 0 ) {
            s->status = PARA_STS_BUSY;
            s->status |= PARA_STS_ACK;
            s->status |= PARA_STS_ONLINE;
            s->status |= PARA_STS_ERROR;
        }
        else if (val & PARA_CTR_SELECT) {
            if (val & PARA_CTR_STROBE) {
                s->status &= ~PARA_STS_BUSY;
                if ((s->control & PARA_CTR_STROBE) == 0)
                    qemu_chr_write(s->chr, &s->dataw, 1);
            } else {
                if (s->control & PARA_CTR_INTEN) {
                    s->irq_pending = 1;
                }
            }
        }
        parallel_update_irq(s);
        s->control = val;
        break;
    }
}

static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint8_t parm = val;

    /* Sometimes programs do several writes for timing purposes on old
       HW. Take care not to waste time on writes that do nothing. */

    s->last_read_offset = ~0U;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->dataw == val)
            return;
        pdebug("wd%02x\n", val);
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
        s->dataw = val;
        break;
    case PARA_REG_STS:
        pdebug("ws%02x\n", val);
        if (val & PARA_STS_TMOUT)
            s->epp_timeout = 0;
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if (s->control == val)
            return;
        pdebug("wc%02x\n", val);
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
        s->control = val;
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP address cycle, so do nothing */
            pdebug("wa%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("wa%02x t\n", val);
            }
            else
                pdebug("wa%02x\n", val);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("we%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("we%02x t\n", val);
            }
            else
                pdebug("we%02x\n", val);
        }
        break;
    }
}

static void
parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint16_t eppdata = cpu_to_le16(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%04x s\n", val);
        return;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%04x t\n", val);
    }
    else
        pdebug("we%04x\n", val);
}

static void
parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint32_t eppdata = cpu_to_le32(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%08x s\n", val);
        return;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%08x t\n", val);
    }
    else
        pdebug("we%08x\n", val);
}

static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret = 0xff;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->control & PARA_CTR_DIR)
            ret = s->datar;
        else
            ret = s->dataw;
        break;
    case PARA_REG_STS:
        ret = s->status;
        s->irq_pending = 0;
        if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
            /* XXX Fixme: wait 5 microseconds */
            if (s->status & PARA_STS_ACK)
                s->status &= ~PARA_STS_ACK;
            else {
                /* XXX Fixme: wait 5 microseconds */
                s->status |= PARA_STS_ACK;
                s->status |= PARA_STS_BUSY;
            }
        }
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        ret = s->control;
        break;
    }
    pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
    return ret;
}

static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint8_t ret = 0xff;
    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
        if (s->last_read_offset != addr || s->datar != ret)
            pdebug("rd%02x\n", ret);
        s->datar = ret;
        break;
    case PARA_REG_STS:
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
        ret &= ~PARA_STS_TMOUT;
        if (s->epp_timeout)
            ret |= PARA_STS_TMOUT;
        if (s->last_read_offset != addr || s->status != ret)
            pdebug("rs%02x\n", ret);
        s->status = ret;
        break;
    case PARA_REG_CTR:
        /* s->control has some bits fixed to 1. It is zero only when
           it has not been yet written to.  */
        if (s->control == 0) {
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
            s->control = ret;
        }
        else {
            ret = s->control;
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP addr cycle, so do nothing */
            pdebug("ra%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("ra%02x t\n", ret);
            }
            else
                pdebug("ra%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("re%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("re%02x t\n", ret);
            }
            else
                pdebug("re%02x\n", ret);
        }
        break;
    }
    s->last_read_offset = addr;
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint16_t eppdata = ~0;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%04x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le16_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%04x t\n", ret);
    }
    else
        pdebug("re%04x\n", ret);
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint32_t eppdata = ~0U;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%08x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le32_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%08x t\n", ret);
    }
    else
        pdebug("re%08x\n", ret);
    return ret;
}

static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
{
    addr &= 7;
    pdebug("wecp%d=%02x\n", addr, val);
}

static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
{
    uint8_t ret = 0xff;
    addr &= 7;
    pdebug("recp%d:%02x\n", addr, ret);
    return ret;
}

static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr)
{
    s->datar = ~0;
    s->dataw = ~0;
    s->status = PARA_STS_BUSY;
    s->status |= PARA_STS_ACK;
    s->status |= PARA_STS_ONLINE;
    s->status |= PARA_STS_ERROR;
    s->control = PARA_CTR_SELECT;
    s->control |= PARA_CTR_INIT;
    s->irq = irq;
    s->irq_pending = 0;
    s->chr = chr;
    s->hw_driver = 0;
    s->epp_timeout = 0;
    s->last_read_offset = ~0U;
}

/* If fd is zero, it means that the parallel device uses the console */
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
{
    ParallelState *s;
    uint8_t dummy;

    s = qemu_mallocz(sizeof(ParallelState));
    if (!s)
        return NULL;
    parallel_reset(s, irq, chr);

    if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
        s->hw_driver = 1;
        s->status = dummy;
    }

    if (s->hw_driver) {
        register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
        register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
        register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
        register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
        register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
        register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
        register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
        register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
    }
    else {
        register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
        register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
    }
    return s;
}

/* Memory mapped interface */
uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
}

void parallel_mm_writeb (void *opaque,
                       target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}

uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
}

void parallel_mm_writew (void *opaque,
                       target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}

uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
}

void parallel_mm_writel (void *opaque,
                       target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);
}

static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
    &parallel_mm_readb,
    &parallel_mm_readw,
    &parallel_mm_readl,
};

static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
    &parallel_mm_writeb,
    &parallel_mm_writew,
    &parallel_mm_writel,
};

/* If fd is zero, it means that the parallel device uses the console */
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
{
    ParallelState *s;
    int io_sw;

    s = qemu_mallocz(sizeof(ParallelState));
    if (!s)
        return NULL;
    parallel_reset(s, irq, chr);
    s->base = base;
    s->it_shift = it_shift;

    io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
    cpu_register_physical_memory(base, 8 << it_shift, io_sw);
    return s;
}
Commit	Line	Data
6508fe59 FB	1	/*
6508fe59 FB	2	* QEMU Parallel PORT emulation
5fafdf24	3	*
e57a8c0e	4	* Copyright (c) 2003-2005 Fabrice Bellard
5867c88a	5	* Copyright (c) 2007 Marko Kohtala
5fafdf24	6	*
6508fe59 FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25	#include "vl.h"
	26
	27	//#define DEBUG_PARALLEL
	28
5867c88a TS	29	#ifdef DEBUG_PARALLEL
	30	#define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
	31	#else
	32	#define pdebug(fmt, arg...) ((void)0)
	33	#endif
	34
	35	#define PARA_REG_DATA 0
	36	#define PARA_REG_STS 1
	37	#define PARA_REG_CTR 2
	38	#define PARA_REG_EPP_ADDR 3
	39	#define PARA_REG_EPP_DATA 4
	40
6508fe59 FB	41	/*
	42	* These are the definitions for the Printer Status Register
	43	*/
	44	#define PARA_STS_BUSY 0x80 /* Busy complement */
	45	#define PARA_STS_ACK 0x40 /* Acknowledge */
	46	#define PARA_STS_PAPER 0x20 /* Out of paper */
	47	#define PARA_STS_ONLINE 0x10 /* Online */
	48	#define PARA_STS_ERROR 0x08 /* Error complement */
5867c88a	49	#define PARA_STS_TMOUT 0x01 /* EPP timeout */
6508fe59 FB	50
	51	/*
	52	* These are the definitions for the Printer Control Register
	53	*/
5867c88a	54	#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
6508fe59 FB	55	#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
	56	#define PARA_CTR_SELECT 0x08 /* Select In complement */
	57	#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
	58	#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
	59	#define PARA_CTR_STROBE 0x01 /* Strobe complement */
	60
5867c88a TS	61	#define PARA_CTR_SIGNAL (PARA_CTR_SELECT\|PARA_CTR_INIT\|PARA_CTR_AUTOLF\|PARA_CTR_STROBE)
5867c88a TS	62
6508fe59	63	struct ParallelState {
5867c88a TS	64	uint8_t dataw;
	65	uint8_t datar;
	66	uint8_t status;
6508fe59	67	uint8_t control;
d537cf6c	68	qemu_irq irq;
6508fe59 FB	69	int irq_pending;
6508fe59 FB	70	CharDriverState *chr;
e57a8c0e	71	int hw_driver;
5867c88a TS	72	int epp_timeout;
5867c88a TS	73	uint32_t last_read_offset; /* For debugging */
d60532ca TS	74	/* Memory-mapped interface */
	75	target_phys_addr_t base;
	76	int it_shift;
6508fe59 FB	77	};
	78
	79	static void parallel_update_irq(ParallelState *s)
	80	{
	81	if (s->irq_pending)
d537cf6c	82	qemu_irq_raise(s->irq);
6508fe59	83	else
d537cf6c	84	qemu_irq_lower(s->irq);
6508fe59 FB	85	}
6508fe59 FB	86
5867c88a TS	87	static void
5867c88a TS	88	parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
6508fe59 FB	89	{
6508fe59 FB	90	ParallelState *s = opaque;
5fafdf24	91
5867c88a TS	92	pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
	93
	94	addr &= 7;
	95	switch(addr) {
	96	case PARA_REG_DATA:
0fa7f157 TS	97	s->dataw = val;
0fa7f157 TS	98	parallel_update_irq(s);
5867c88a TS	99	break;
5867c88a TS	100	case PARA_REG_CTR:
0fa7f157 TS	101	if ((val & PARA_CTR_INIT) == 0 ) {
	102	s->status = PARA_STS_BUSY;
	103	s->status \|= PARA_STS_ACK;
	104	s->status \|= PARA_STS_ONLINE;
	105	s->status \|= PARA_STS_ERROR;
	106	}
	107	else if (val & PARA_CTR_SELECT) {
	108	if (val & PARA_CTR_STROBE) {
	109	s->status &= ~PARA_STS_BUSY;
	110	if ((s->control & PARA_CTR_STROBE) == 0)
	111	qemu_chr_write(s->chr, &s->dataw, 1);
	112	} else {
	113	if (s->control & PARA_CTR_INTEN) {
	114	s->irq_pending = 1;
	115	}
	116	}
	117	}
	118	parallel_update_irq(s);
	119	s->control = val;
5867c88a TS	120	break;
	121	}
	122	}
	123
	124	static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
	125	{
	126	ParallelState *s = opaque;
	127	uint8_t parm = val;
	128
	129	/* Sometimes programs do several writes for timing purposes on old
	130	HW. Take care not to waste time on writes that do nothing. */
	131
	132	s->last_read_offset = ~0U;
	133
6508fe59	134	addr &= 7;
6508fe59	135	switch(addr) {
5867c88a TS	136	case PARA_REG_DATA:
5867c88a TS	137	if (s->dataw == val)
0fa7f157 TS	138	return;
	139	pdebug("wd%02x\n", val);
	140	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
	141	s->dataw = val;
6508fe59	142	break;
5867c88a	143	case PARA_REG_STS:
0fa7f157 TS	144	pdebug("ws%02x\n", val);
	145	if (val & PARA_STS_TMOUT)
	146	s->epp_timeout = 0;
	147	break;
5867c88a TS	148	case PARA_REG_CTR:
	149	val \|= 0xc0;
	150	if (s->control == val)
0fa7f157 TS	151	return;
	152	pdebug("wc%02x\n", val);
	153	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
	154	s->control = val;
6508fe59	155	break;
5867c88a	156	case PARA_REG_EPP_ADDR:
0fa7f157 TS	157	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	158	/* Controls not correct for EPP address cycle, so do nothing */
	159	pdebug("wa%02x s\n", val);
	160	else {
	161	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	162	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
	163	s->epp_timeout = 1;
	164	pdebug("wa%02x t\n", val);
	165	}
	166	else
	167	pdebug("wa%02x\n", val);
	168	}
	169	break;
5867c88a	170	case PARA_REG_EPP_DATA:
0fa7f157 TS	171	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	172	/* Controls not correct for EPP data cycle, so do nothing */
	173	pdebug("we%02x s\n", val);
	174	else {
	175	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	176	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
	177	s->epp_timeout = 1;
	178	pdebug("we%02x t\n", val);
	179	}
	180	else
	181	pdebug("we%02x\n", val);
	182	}
	183	break;
5867c88a TS	184	}
	185	}
	186
	187	static void
	188	parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
	189	{
	190	ParallelState *s = opaque;
	191	uint16_t eppdata = cpu_to_le16(val);
	192	int err;
	193	struct ParallelIOArg ioarg = {
0fa7f157	194	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	195	};
5867c88a TS	196	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	197	/* Controls not correct for EPP data cycle, so do nothing */
	198	pdebug("we%04x s\n", val);
	199	return;
5867c88a TS	200	}
	201	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
	202	if (err) {
0fa7f157 TS	203	s->epp_timeout = 1;
0fa7f157 TS	204	pdebug("we%04x t\n", val);
5867c88a TS	205	}
5867c88a TS	206	else
0fa7f157	207	pdebug("we%04x\n", val);
5867c88a TS	208	}
	209
	210	static void
	211	parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
	212	{
	213	ParallelState *s = opaque;
	214	uint32_t eppdata = cpu_to_le32(val);
	215	int err;
	216	struct ParallelIOArg ioarg = {
0fa7f157	217	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	218	};
5867c88a TS	219	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	220	/* Controls not correct for EPP data cycle, so do nothing */
	221	pdebug("we%08x s\n", val);
	222	return;
5867c88a TS	223	}
	224	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
	225	if (err) {
0fa7f157 TS	226	s->epp_timeout = 1;
0fa7f157 TS	227	pdebug("we%08x t\n", val);
6508fe59	228	}
5867c88a	229	else
0fa7f157	230	pdebug("we%08x\n", val);
6508fe59 FB	231	}
6508fe59 FB	232
5867c88a	233	static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
6508fe59 FB	234	{
	235	ParallelState *s = opaque;
	236	uint32_t ret = 0xff;
	237
	238	addr &= 7;
	239	switch(addr) {
5867c88a	240	case PARA_REG_DATA:
0fa7f157 TS	241	if (s->control & PARA_CTR_DIR)
	242	ret = s->datar;
	243	else
	244	ret = s->dataw;
6508fe59	245	break;
5867c88a	246	case PARA_REG_STS:
0fa7f157 TS	247	ret = s->status;
	248	s->irq_pending = 0;
	249	if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
	250	/* XXX Fixme: wait 5 microseconds */
	251	if (s->status & PARA_STS_ACK)
	252	s->status &= ~PARA_STS_ACK;
	253	else {
	254	/* XXX Fixme: wait 5 microseconds */
	255	s->status \|= PARA_STS_ACK;
	256	s->status \|= PARA_STS_BUSY;
	257	}
	258	}
	259	parallel_update_irq(s);
6508fe59	260	break;
5867c88a	261	case PARA_REG_CTR:
6508fe59 FB	262	ret = s->control;
	263	break;
	264	}
5867c88a TS	265	pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
	266	return ret;
	267	}
	268
	269	static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
	270	{
	271	ParallelState *s = opaque;
	272	uint8_t ret = 0xff;
	273	addr &= 7;
	274	switch(addr) {
	275	case PARA_REG_DATA:
0fa7f157 TS	276	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
	277	if (s->last_read_offset != addr \|\| s->datar != ret)
	278	pdebug("rd%02x\n", ret);
5867c88a TS	279	s->datar = ret;
	280	break;
	281	case PARA_REG_STS:
0fa7f157 TS	282	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
	283	ret &= ~PARA_STS_TMOUT;
	284	if (s->epp_timeout)
	285	ret \|= PARA_STS_TMOUT;
	286	if (s->last_read_offset != addr \|\| s->status != ret)
	287	pdebug("rs%02x\n", ret);
	288	s->status = ret;
5867c88a TS	289	break;
	290	case PARA_REG_CTR:
	291	/* s->control has some bits fixed to 1. It is zero only when
0fa7f157 TS	292	it has not been yet written to. */
	293	if (s->control == 0) {
	294	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
	295	if (s->last_read_offset != addr)
	296	pdebug("rc%02x\n", ret);
	297	s->control = ret;
	298	}
	299	else {
	300	ret = s->control;
	301	if (s->last_read_offset != addr)
	302	pdebug("rc%02x\n", ret);
	303	}
5867c88a TS	304	break;
5867c88a TS	305	case PARA_REG_EPP_ADDR:
0fa7f157 TS	306	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	307	/* Controls not correct for EPP addr cycle, so do nothing */
	308	pdebug("ra%02x s\n", ret);
	309	else {
	310	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	311	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
	312	s->epp_timeout = 1;
	313	pdebug("ra%02x t\n", ret);
	314	}
	315	else
	316	pdebug("ra%02x\n", ret);
	317	}
	318	break;
5867c88a	319	case PARA_REG_EPP_DATA:
0fa7f157 TS	320	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	321	/* Controls not correct for EPP data cycle, so do nothing */
	322	pdebug("re%02x s\n", ret);
	323	else {
	324	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	325	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
	326	s->epp_timeout = 1;
	327	pdebug("re%02x t\n", ret);
	328	}
	329	else
	330	pdebug("re%02x\n", ret);
	331	}
	332	break;
5867c88a TS	333	}
	334	s->last_read_offset = addr;
	335	return ret;
	336	}
	337
	338	static uint32_t
	339	parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
	340	{
	341	ParallelState *s = opaque;
	342	uint32_t ret;
	343	uint16_t eppdata = ~0;
	344	int err;
	345	struct ParallelIOArg ioarg = {
0fa7f157	346	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	347	};
5867c88a TS	348	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	349	/* Controls not correct for EPP data cycle, so do nothing */
	350	pdebug("re%04x s\n", eppdata);
	351	return eppdata;
5867c88a TS	352	}
	353	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
	354	ret = le16_to_cpu(eppdata);
	355
	356	if (err) {
0fa7f157 TS	357	s->epp_timeout = 1;
0fa7f157 TS	358	pdebug("re%04x t\n", ret);
5867c88a TS	359	}
5867c88a TS	360	else
0fa7f157	361	pdebug("re%04x\n", ret);
5867c88a TS	362	return ret;
	363	}
	364
	365	static uint32_t
	366	parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
	367	{
	368	ParallelState *s = opaque;
	369	uint32_t ret;
	370	uint32_t eppdata = ~0U;
	371	int err;
	372	struct ParallelIOArg ioarg = {
0fa7f157	373	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	374	};
5867c88a TS	375	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	376	/* Controls not correct for EPP data cycle, so do nothing */
	377	pdebug("re%08x s\n", eppdata);
	378	return eppdata;
5867c88a TS	379	}
	380	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
	381	ret = le32_to_cpu(eppdata);
	382
	383	if (err) {
0fa7f157 TS	384	s->epp_timeout = 1;
0fa7f157 TS	385	pdebug("re%08x t\n", ret);
5867c88a TS	386	}
5867c88a TS	387	else
0fa7f157	388	pdebug("re%08x\n", ret);
5867c88a TS	389	return ret;
	390	}
	391
	392	static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
	393	{
	394	addr &= 7;
	395	pdebug("wecp%d=%02x\n", addr, val);
	396	}
	397
	398	static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
	399	{
	400	uint8_t ret = 0xff;
	401	addr &= 7;
	402	pdebug("recp%d:%02x\n", addr, ret);
6508fe59 FB	403	return ret;
	404	}
	405
d60532ca	406	static void parallel_reset(ParallelState s, qemu_irq irq, CharDriverState chr)
6508fe59	407	{
5867c88a TS	408	s->datar = ~0;
5867c88a TS	409	s->dataw = ~0;
6508fe59 FB	410	s->status = PARA_STS_BUSY;
	411	s->status \|= PARA_STS_ACK;
	412	s->status \|= PARA_STS_ONLINE;
	413	s->status \|= PARA_STS_ERROR;
	414	s->control = PARA_CTR_SELECT;
	415	s->control \|= PARA_CTR_INIT;
5867c88a TS	416	s->irq = irq;
	417	s->irq_pending = 0;
	418	s->chr = chr;
	419	s->hw_driver = 0;
	420	s->epp_timeout = 0;
	421	s->last_read_offset = ~0U;
d60532ca TS	422	}
	423
	424	/* If fd is zero, it means that the parallel device uses the console */
	425	ParallelState parallel_init(int base, qemu_irq irq, CharDriverState chr)
	426	{
	427	ParallelState *s;
	428	uint8_t dummy;
	429
	430	s = qemu_mallocz(sizeof(ParallelState));
	431	if (!s)
	432	return NULL;
	433	parallel_reset(s, irq, chr);
6508fe59	434
5867c88a TS	435	if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
5867c88a TS	436	s->hw_driver = 1;
0fa7f157	437	s->status = dummy;
5867c88a TS	438	}
	439
	440	if (s->hw_driver) {
0fa7f157 TS	441	register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
	442	register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
	443	register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
	444	register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
	445	register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
	446	register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
	447	register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
	448	register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
5867c88a TS	449	}
5867c88a TS	450	else {
0fa7f157 TS	451	register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
0fa7f157 TS	452	register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
5867c88a	453	}
6508fe59 FB	454	return s;
6508fe59 FB	455	}
d60532ca TS	456
	457	/* Memory mapped interface */
	458	uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
	459	{
	460	ParallelState *s = opaque;
	461
	462	return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
	463	}
	464
	465	void parallel_mm_writeb (void *opaque,
	466	target_phys_addr_t addr, uint32_t value)
	467	{
	468	ParallelState *s = opaque;
	469
	470	parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
	471	}
	472
	473	uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
	474	{
	475	ParallelState *s = opaque;
	476
	477	return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
	478	}
	479
	480	void parallel_mm_writew (void *opaque,
	481	target_phys_addr_t addr, uint32_t value)
	482	{
	483	ParallelState *s = opaque;
	484
	485	parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
	486	}
	487
	488	uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
	489	{
	490	ParallelState *s = opaque;
	491
	492	return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
	493	}
	494
	495	void parallel_mm_writel (void *opaque,
	496	target_phys_addr_t addr, uint32_t value)
	497	{
	498	ParallelState *s = opaque;
	499
	500	parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);
	501	}
	502
	503	static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
	504	&parallel_mm_readb,
	505	&parallel_mm_readw,
	506	&parallel_mm_readl,
	507	};
	508
	509	static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
	510	&parallel_mm_writeb,
	511	&parallel_mm_writew,
	512	&parallel_mm_writel,
	513	};
	514
	515	/* If fd is zero, it means that the parallel device uses the console */
	516	ParallelState parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState chr)
	517	{
	518	ParallelState *s;
	519	int io_sw;
520
521	s = qemu_mallocz(sizeof(ParallelState));
522	if (!s)
523	return NULL;
524	parallel_reset(s, irq, chr);
525	s->base = base;
526	s->it_shift = it_shift;
527
528	io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
529	cpu_register_physical_memory(base, 8 << it_shift, io_sw);
530	return s;
531	}